Nonvolatile memory device
Patent Information
- Application Number
- TW113127286
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2020-06-19
- Filing Date
- 2021-06-17
- Publication Date
- 2026-07-21
- Estimated Expiration
- 2041-06-16
Abstract
Description
Non-Volatile Memory Element and Processing Tool Embodiments of the present disclosure relate to the field of electronic components and methods and apparatuses for manufacturing electronic components. More specifically, embodiments of the present disclosure provide methods for forming 3D-NAND die stacks. Semiconductor technology has been developing rapidly, and component sizes have been shrinking with technological advancements to provide faster processing and storage capabilities per unit of space. In NAND components, the string current needs to be high enough to obtain sufficient current to distinguish ON and OFF cells. The string current depends on the carrier mobility, which is enhanced by enlarging the grain size of the silicon channel. Existing 3D-NAND memory stacks with alternating oxide and nitride layers have limited silicon nitride (SiN) charge trapping layers, which are formed by depositing continuous trapping layers. Existing 3D-NAND memory stacks suffer from cell performance degradation in charge-trapping-based memories due to charge diffusion and cell-to-cell interference exacerbated by the reduction in cell-to-cell distance. Therefore, the technology requires 3D-NAND components with limited charge trapping layers that will suppress performance degradation in charge-trapping-based memories. Additionally, the technology requires methods and apparatuses for forming 3D-NAND components. One or more embodiments of the present disclosure relate to methods of forming memory elements. In one embodiment, a method of forming an electronic component includes the steps of: forming an opening in a memory stack including alternating layers of a first material layer and a second material layer, the memory stack being located on a common source line; recessing the second material layer through the opening to form a first recessed region; forming a deposition enabling layer (DEL) on a surface of the first recessed region; recessing the deposition enabling layer (DEL) to form a second recessed region; and selectively depositing a trapping layer in the second recessed region. Additional embodiments of the present disclosure relate to memory elements. In one embodiment, a non-volatile memory element includes: a memory stack including memory cells and memory holes, the memory cells including gates, channel layers, and trapping layers confined between the gates and the channel layers, and the memory holes extending through the memory stack and having a first portion and a second portion, the second portion including a common source layer, wherein the trapping layer is located on sidewalls of the common source layer. A further embodiment of the present disclosure relates to a processing tool. In one embodiment, a processing tool includes: a central transfer station including a robot configured to move wafers; a plurality of processing stations, each processing station being connected to the central transfer station and providing a processing area separated from the processing areas of adjacent processing stations, the processing stations including a capture layer selective deposition chamber; and a controller connected to the central transfer station and the processing stations, the controller being configured to activate the robot to move wafers between the processing stations and to control the processes occurring in each of the processing stations. Before describing several exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the structures or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways. As used in this specification and the appended claims, the terms "precursor", "reactant", "reaction gas" and the like are used interchangeably to represent any gaseous species that can react with the surface of a substrate. In the following description, numerous specific details are set forth, such as specific materials, chemical compositions, element sizes, etc., to provide a thorough understanding of one or more embodiments of the present disclosure. However, it will be apparent to one of ordinary skill in the art that one or more embodiments of the present disclosure may be practiced without these specific details. In other instances, semiconductor manufacturing processes, techniques, materials, equipment, etc. are not described in extreme detail to avoid unnecessarily obscuring this description. One of ordinary skill in the art will be able to implement the appropriate functions based on the description provided without undue experimentation. Although certain exemplary embodiments of the present disclosure are described and illustrated in the accompanying drawings, it should be understood that such embodiments are merely illustrative and not limiting of the present disclosure, and the present disclosure is not limited to the specific structures and configurations shown and described, as modifications may be contemplated by one of ordinary skill in the art. In existing 3D NAND stacks based on charge trapping as a storage layer, the charge trapping is a continuous layer. The continuous charge trapping layer causes two serious problems that prevent the scaling of the wordline (WL) to WL insulator - cell-to-cell interference and lateral charge diffusion. In one or more embodiments, to suppress cell-to-cell interference and lateral charge diffusion, the trapping layer (i.e., trapping cut or confined structure) under the source and drain (S / D) of each cell is eliminated. The problem with existing trapping cut structures is that due to the deposition and removal processes, there is partial use of the gate area and variations in the shape and thickness of the trapping silicon nitride (SiN). Therefore, one or more embodiments provide a novel structure and method for effectively placing the trapping layer for a given wordline thickness and allowing suppression of variations in the trapping layer shape and thickness. One or more embodiments provide for the selective deposition of a silicon nitride (SiN) capture layer. In one or more embodiments, a sacrificial layer is used for selective deposition (also referred to as a deposition-enabling layer, DEL) to allow for the selective capture of SiN deposition. In one or more embodiments, the capture layer is formed by the deposition of a mold including the sacrificial layer, memory hole (MH) patterning, the sacrificial layer recessing from the MH side, forming a deposition-enabling layer (DEL) on one side of the recess, and the selective deposition of the capture layer. In one or more embodiments, a blocking oxide is formed - after removing the sacrificial layer from the slit side, the deposition-enabling layer (DEL) is converted to an oxide to be used as a blocking oxide. In one or more embodiments, a high-k dielectric layer, a barrier layer, and a word line (WL) are then formed. In one or more embodiments, the capture layer is advantageously limited only between the tunnel oxide and the word line. Cell-to-cell interference and lateral diffusion are advantageously inhibited. In one or more embodiments, the selective deposition of the capture layer advantageously inhibits variations in the shape and thickness of the capture layer. In one or more embodiments, metal deposition and other processes can be performed in an isolated environment (e.g., a cluster process tool). Accordingly, some embodiments of the present disclosure provide an integrated tool system with associated process modules to implement these methods. FIG. 1 shows a flowchart of an exemplary method 10 for forming a memory element. Those skilled in the art will recognize that method 10 can include any or all of the illustrated processes. Additionally, for some portions, the order of the individual processes can be different. Without departing from the present disclosure, method 10 can start with any one of the recited processes. Referring to FIG. 1, at operation 15, a memory stack is formed. At operation 20, a word line ladder is formed in the memory stack. At operation 25, memory hole channels are patterned into the word line ladder. At operation 30, depending on circumstances, for example, a first layer such as a nitride layer can be recessed via the memory hole channels. At operation 35, a polysilicon layer is deposited. At operation 40, the polysilicon layer is recessed. At operation 45, a capture layer is deposited. At operation 50, bit line pads are formed. At operation 55, the memory ladder is slit patterned. At operation 60, the sacrificial layer is removed and replaced. At operation 65, a first layer such as a nitride layer is removed. At operation 70, the polysilicon layer is oxidized to form a blocking oxide. At operation 75, word line material is deposited. At operation 80, the slit is filled, and at operation 85, word line contacts are formed. FIGS. 2 - 21 show portions of a memory element 100 following the process flow shown for method 10 in FIG. 1. Figure 2 shows an initial or starting memory stack of the electronic component 100 in accordance with one or more embodiments of the present disclosure. In some embodiments, the electronic component 100 shown in Figure 2 is formed in layers on a bare substrate 102, as shown. The electronic component of Figure 2 consists of the substrate 102, a common source line 120, and a memory stack 112. The substrate 102 can be any suitable material known to those skilled in the art. As used in this specification and the appended claims, the term "substrate" refers to the surface or a portion of the surface on which a process is performed. Those skilled in the art will also understand that, unless the context clearly indicates otherwise, a reference to a substrate may refer only to a portion of the substrate. In addition, a reference to depositing on a substrate may mean a bare substrate and a substrate on which one or more films or features are deposited or formed. As used herein, a "substrate" refers to any substrate or the surface of a material formed on a substrate on which film processing is performed during a manufacturing process. For example, substrate surfaces on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. The substrate can be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to performing film processing directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps can also be performed on underlying layers formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlying layers as indicated by the context. Thus, for example, when a film / layer or a portion of a film / layer is deposited onto a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface. The common source line 120 is located on the substrate 102. The common source as 120 can also be referred to as a semiconductor layer. The common source line 120 can be formed by any suitable technique known to those skilled in the art and can be made of any suitable material including, but not limited to, polysilicon (polycrystalline silicon). In some embodiments, the common source line 120 includes several different conductive or semiconductor materials. For example, in one or more embodiments, as shown in Figure 2, the common source line 120 includes a first polysilicon layer 104 on the substrate 102. An oxide layer 106 can be formed on the first polysilicon layer 104. The sacrificial layer 108 may be formed on the oxide layer 106 and may be made of any suitable material. In some embodiments, the sacrificial layer 108 is removed and replaced in a subsequent process. In some embodiments, the sacrificial layer 108 is not removed and remains within the memory element 100. In this case, the term "sacrificial" has an extended meaning to include a permanent layer and may be referred to as a conductive layer. In the illustrated embodiment, as further described below, the sacrificial layer 108 is removed in operation 60. In one or more embodiments, the sacrificial layer 108 comprises a material that can be selectively removed relative to the adjacent oxide layer 106. A second oxide layer 106 may be formed on the top surface of the sacrificial layer 108, and subsequently a second polysilicon layer 104 may be formed on the second oxide layer 106. A memory stack 130 is formed on the common source line 120. The memory stack 130 in the illustrated embodiment comprises a plurality of alternating first layers 106 and second layers 110. In one or more embodiments, the first layer 106 comprises an oxide layer and the second layer 110 comprises a nitride layer. In some embodiments, the memory stack 130 comprises a non-replaceable gate, such as alternating oxide and polysilicon (poly-Si; OP), or oxide and metal, or oxide and sacrificial layer. The second layer 110 comprises a material that has an etch selectivity relative to the first layer 106 such that the second layer 110 can be removed without substantially affecting the first layer 106. In one or more embodiments, the first layer 106 comprises silicon oxide (SiO x ). In one or more embodiments, the second layer 110 comprises silicon nitride (SiN). In one or more embodiments, the first layer 106 and the second layer 110 are deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD). Individual alternating layers can be formed to any suitable thickness. In some embodiments, the thicknesses of each of the second layers 110 are substantially equal. In one or more embodiments, each of the second layers 110 has a first second-layer thickness. In some embodiments, the thicknesses of each of the first layers 134 are substantially equal. As used in this context, substantially equal thicknesses are within + / - 5% of each other. In some embodiments, a silicon layer (not shown) is formed between the second layer 110 and the first layer 106. The thickness of the silicon layer can be relatively thin compared to the thicknesses of the layers of the second layer 110 or the first layer 106. In one or more embodiments, the first layer 106 has a thickness in the range of from about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm. In one or more embodiments, the first layer 106 has a thickness in the range of from about 0.5 to about 40 nm. In one or more embodiments, the second layer 110 has a thickness in the range of from about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm. In one or more embodiments, the second layer 110 has a thickness in the range of from about 0.5 to about 40 nm. Referring to FIG. 3, at operation 20 of method 10, a stepped structure 131 is generated. A mask layer 140 is deposited on the top surface of the memory stack 130. The mask layer 140 can comprise any suitable material known to those skilled in the art. In one or more embodiments, the mask layer 140 comprises a nitride. In one or more embodiments, the stepped structure 131 exposes the top surface 135 of the first layer 106. The top surface 135 can be used to provide space for the word-line contacts to be formed, as described below. A suitable fill material 137 can be deposited to occupy the space outside the stepped structure 131. Those skilled in the art will understand that the suitable fill material 137 can be any material that prevents electrical short circuits between adjacent word lines. The stepped structure 131, where each word line has a width that is less than the width of the word line below it (shown left to right in the figure). The use of relative terms such as "above" and "below" should not be construed as limiting the scope of the present disclosure to a physical orientation in space. Referring to FIGS. 4A and 4B, at operation 25, the memory hole channel 150 is opened through the memory stack 130. In some embodiments, opening the memory hole channel 150 includes etching through the mask layer 140, the memory stack 130, the common source line 120 and into the substrate 102. Referring to FIG. 4B, which is an expanded view of region 103, the memory hole channel 150 has sidewalls extending through the memory stack 130, and these sidewalls expose the surface 138 of the second layer 110 and the surface 139 of the first layer 106. The sacrificial layer 108 has a surface 122 that is exposed as the sidewall of the memory hole channel 150. The memory channel hole 150 extends into the substrate 102 for a distance such that the sidewall surface 112 and the bottom 114 of the memory hole channel 150 are formed within the substrate 102. The bottom 114 of the memory hole channel 150 can be formed at any point within the thickness of the substrate 102. In some embodiments, the memory hole channel 150 extends into the substrate 102 with a thickness in the range of about 10% to about 90% of the thickness of the substrate 102, or in the range of about 20% to about 80%, or in the range of about 30% to about 70%, or in the range of about 40% to about 60%. In some embodiments, the memory hole channel 150 extends into the substrate 102 a distance greater than or equal to 10%, 20%, 30%, 40%, 50%, 60%, 70% or 80% of the thickness of the substrate 102. FIG. 5A shows operation 30, in which the second layer 110, such as a nitride layer, is selectively recessed through the memory hole channel 150 to form a recessed area 152. FIG. 5B is an expanded view of region 103 of FIG. 5A. In one or more embodiments, the second layer 110, such as a nitride layer, is recessed using reactive species formed through an opening 150 with a process gas including oxygen (O 2 ) and nitrogen trifluoride (NF 3 ). In other embodiments, the second layer 110, such as a nitride layer, is recessed using hot phosphorus (HP) through the opening 150. FIGS. 6A and 6B show operation 35, in which a polysilicon layer 154 is deposited in the memory hole 150 to fill the recessed area 152. FIG. 6B is an expanded view of region 103. The polysilicon layer 154 can be deposited in any suitable manner known to those skilled in the art, including but not limited to atomic layer deposition (ALD) or chemical vapor deposition (CVD). In some embodiments, the polysilicon layer 154 may also be referred to as a deposited enabling layer (DEL). FIGS. 7A and 7B show operation 40, in which the polysilicon layer 154 is recessed to form a recessed area 155. FIG. 7B is an expanded view of region 103. The polysilicon layer 154 is removed from the sidewall surface 112 and the bottom 114 of the memory hole channel 150. Figures 8A and 8B illustrate operation 45, in which a capture layer 156 is selectively deposited on the polysilicon layer 154 in the recessed area 155, on the sidewall surfaces 112 of the sacrificial layer 108 and the oxide layer 104 of the common source line 120, and on the bottom surface 114 of the memory hole 150. Figure 8B is an expanded view of area 103. In one or more embodiments, the capture layer 156 may comprise any suitable material known to those skilled in the art. In some embodiments, the capture layer 156 comprises silicon nitride (SiN). In one or more embodiments, the capture layer 156 is deposited on the hydrogen-terminated polysilicon layer 154 by atomic layer selective deposition. In one or more embodiments, the capture layer 156 is deposited by alternately supplying dichlorosilane (SiH 2 Cl 2 ) and ammonia (NH 3 ). Without wishing to be bound by theory, it is believed that the capture layer 156 is advantageously formed only on the hydrogen-terminated surface of the polysilicon layer 154 and not on the sidewall surfaces of the first layer 106 because there are no Si-H x and N-H y bonds on the surface of the first layer 106. In one or more embodiments, the capture layer 156 has improved film quality compared to a capture layer formed using ammonia (NH 3 ) plasma. Figures 9A and 9B illustrate operation 50, in which a transition layer is conformally deposited into the memory hole channel 150 adjacent to the capture layer 156. Figure 9B is an expanded view of area 103. The transistor layer can be formed by any suitable technique known to those skilled in the art. In some embodiments, the transistor layer is formed by a conformal deposition process. In some embodiments, the transistor layer is formed by one or more of atomic layer deposition or chemical vapor deposition. In one or more embodiments, the deposition of the transistor layer is substantially conformal. As used herein, a "substantially conformal" layer refers to a layer having a thickness that is substantially the same everywhere (e.g., at the top, middle, and bottom of the sidewall and at the bottom of the memory hole channel 150). The thickness variation of a substantially conformal layer is less than or equal to about 5%, 2%, 1%, or 0.5%. Referring to FIG. 9B, which is an expanded view of region 103, in one or more embodiments, the transistor layer includes a tunnel oxide layer 158 in the memory hole channel 150 and a polysilicon channel layer 160 on the tunnel oxide layer 158. In one or more embodiments, the tunnel oxide layer 158 and the polysilicon channel layer 160 are deposited in the memory hole channel 150, on the sidewalls of the memory hole channel 150, or on the capture layer 156. The tunnel oxide layer 158 and the polysilicon channel layer 160 can have any suitable thickness, depending on, for example, the size of the memory hole channel 150. In some embodiments, the polysilicon channel layer 160 has a thickness in the range of about 0.5 nm to about 50 nm, or in the range of about 0.75 nm to about 35 nm, or in the range of about 1 nm to about 20 nm. In some embodiments, the polysilicon channel layer 160 is a continuous film. In one or more embodiments, the polysilicon channel layer 160 is formed by conformal deposition on the tunnel oxide layer 158, and the polysilicon channel layer 160 has a thickness in the range of about 1 nm to about 20 nm. In one or more embodiments, the memory hole channel 150 is subsequently filled with a dielectric material 162. The dielectric material 162 can include any suitable dielectric material known to those skilled in the art. As used herein, the term "dielectric material" refers to an electrical insulator that can be polarized in an electric field. In some embodiments, the dielectric material 162 includes one or more of oxides, carbon-doped oxides, silicon dioxide (SiO), porous silicon dioxide (SiO 2 ), silicon dioxide (SiO), silicon nitride (SiN), silicon dioxide / silicon nitride, carbides, oxycarbides, nitrides, oxynitrides, oxcarbonitrides, polymers, phosphosilicate glass, fluorosilicate (SiOF) glass, or organosilicate glass (SiOCH). FIGS. 10A-10C illustrate operation 55 of method 10, in which bit line pads 164 are formed in the mask layer 140. The bit line pads 164 can be any suitable material known to those skilled in the art, including but not limited to polysilicon. Referring to FIG. 10B, which is an expanded view of region 165, in one or more embodiments, the cell 165 includes a polysilicon layer 154 and a capture layer 156 adjacent to the memory hole 150 filled with the tunnel oxide layer 158, the polysilicon channel layer 160, and the dielectric material 162. Referring to FIG. 10C, which is an expanded view of region 167, in one or more embodiments, the bottom region of the memory hole includes a capture layer 156 lining the bottom of the memory hole 150, the tunnel oxide layer 158 is adjacent to the capture layer 156, the polysilicon channel layer 160 is located on the tunnel oxide layer, and the dielectric material 162 fills the memory hole 150. FIG. 11 illustrates operation 55 of method 10, where an interlayer dielectric 141 is deposited on the top surfaces of the mask layer 140 and the bit line pad 164. The interlayer dielectric (ILD) 141 can be deposited by any suitable technique known to those skilled in the art. The interlayer dielectric 141 can include any suitable material known to those skilled in the art. In one or more embodiments, the interlayer dielectric 141 is a low-k dielectric, including but not limited to materials such as silicon dioxide, silicon oxide, carbon doped oxides (such as carbon doped silicon dioxide, "carbon doped oxide, CDO"), porous silicon dioxide (SiO 2 ), silicon nitride (SiN), or any combination thereof. Although the term "silicon oxide" can be used to describe the interlayer dielectric 141, those skilled in the art will recognize that the present disclosure is not limited to a specific stoichiometry. For example, both the terms "silicon oxide" and "silicon dioxide" can be used to describe materials having any suitable stoichiometric ratio of silicon and oxygen atoms. The same is true for the other materials listed in the present disclosure, such as silicon nitride, oxynitride, aluminum oxide, zirconium oxide, and the like. Referring to FIG. 11, at operation 55 of method 10, the memory stack 130 is slit patterned to form a slit pattern opening 170 extending from the top surface of the interlayer dielectric 141 to the sacrificial layer 108 of the common source line 120. FIG. 12 shows that the spacer material 172 is deposited in the slit pattern opening 170 and then etched back so that the spacer material 172 is formed on the sidewalls of the slit pattern opening 170. The spacer material 172 can include any suitable material known to those skilled in the art. In one or more embodiments, the spacer material 172 includes polysilicon. FIG. 13 illustrates operation 60 of method 10, where the sacrificial layer 108 in the common source line 120 and the oxide layer 106 directly adjacent to the sacrificial layer 108 are removed. The sacrificial layer 108 can be removed by any suitable technique known to those skilled in the art, including but not limited to selective etching, hot phosphoric acid, and the like. FIG. 14 shows that the polysilicon channel layer 160 is exposed on the common source line 120 contact. The polysilicon channel layer 160 is exposed by removing the capture layer 156 and the tunnel oxide layer 158 in the common source line 120 contact area. FIG. 15 illustrates operation 60 of method 10, where the common source line is filled with a polysilicon layer 176. The polysilicon layer 176 can be doped or undoped. FIG. 16 shows the removal of the spacer material 172 from the slit pattern opening 170. The spacer material 172 can be removed by any suitable method known to those skilled in the art. In one or more embodiments, the spacer material 172 is removed by an isotropic etching process, such as wet etching using tetramethyl ammonium hydroxide (TMAH) or the like. FIG. 17 shows operation 65 of method 10, where one or more second layers (such as nitride) 110 are removed to form an opening 177. FIG. 18 shows operation 70, where in removing one or more second layers 110 (such as a nitride layer), a first side of the second layer 110 (such as a nitride layer) is exposed to the slit pattern opening 170, and the first side of the second layer 110 (such as a nitride layer) is exposed to an oxidant via the slit pattern opening 170 to oxidize the polysilicon 154 to form a blocking oxide layer 178. FIG. 19 shows operation 75 of method 10, where a word line is formed. The word line includes one or more of an oxide layer 180, a barrier layer 182, and a word line metal 184. The oxide layer 180 can include any suitable material known to those skilled in the art. In one or more embodiments, the oxide layer includes aluminum oxide. The barrier layer 182 can include any suitable material known to those skilled in the art. In one or more embodiments, the barrier layer 182 includes one or more of titanium nitride (TiN), tantalum nitride (TaN), or the like. In one or more embodiments, the word line metal 182 includes a bulk metal, and this bulk metal includes one or more of copper (Cu), cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), or rhodium (Rh). In one or more embodiments, the word line metal 184 includes tungsten (W). In other embodiments, the word line metal 184 includes ruthenium (Ru). FIGS. 20A - 20C show operation 80 of method 10, where the slit pattern opening 170 is filled with a filling material 186. FIG. 20B is an expanded view of region 185. FIG. 20C is an expanded view of region 187. The filling material 186 can be any suitable material known to those skilled in the art. In one or more embodiments, the filling material 186 includes one or more of a dielectric material or a conductor material. As used herein, the term "dielectric material" refers to a material layer that acts as an electrical insulator that can be polarized in an electric field. In one or more embodiments, the dielectric material includes an oxide, a carbon-doped oxide, silicon oxide (SiO), porous silicon dioxide (SiO 2) one or more of silicon oxide (SiO), silicon nitride (SiN), silicon oxide / nitride, carbide, oxycarbide, nitride, oxynitride, oxynitrogen carbide, polymer, phosphosilicate glass, fluorosilicate (SiOF) glass, or organosilicate glass (SiOCH). In one or more embodiments, the capture layer 156 is advantageously limited only between the blocking oxide 178 and the word line. Cell-to-cell interference and lateral diffusion are advantageously suppressed. In one or more embodiments, the selective deposition of the capture layer 156 advantageously suppresses variations in the shape and thickness of the capture layer 156. FIG. 21 shows operation 85 of method 10, in which a word line (W / L) contact is formed. The word line contact 235 extends through the memory stack 130 for a distance sufficient to terminate at one of the word lines. In one or more embodiments, the word line contact 235 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the word line contact 235 comprises one or more of metal, metal silicide, polysilicon, amorphous silicon, or EPI silicon. In one or more embodiments, the word line contact is doped with an N-type dopant or a P-type dopant to reduce contact resistance. In one or more embodiments, the metal of the word line contact 235 is selected from one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt). In one or more embodiments, a method of forming an electronic component includes removing one or more first layers from a film stack including alternating second and first layers, the first layers being removed from a first side of the first layers to leave an opening defined by one or more films including a polysilicon layer on a second side, the opening having a first thickness; trimming an adjacent second layer through the opening to increase the thickness of the opening from the first thickness to a second thickness and reduce a first second layer thickness to a second oxide layer thickness less than the first second layer thickness; and depositing a word line replacement material in the opening. Additional embodiments of the present disclosure relate to a processing tool 900 for forming the memory elements and methods, as shown in FIG. 22. The cluster tool 900 includes at least one central transfer station 921, 931 having a plurality of sides. Robots 925, 935 are positioned within the central transfer stations 921, 931 and are configured to move robot blades and wafers to each of these sides. The cluster tool 900 includes a plurality of processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918 connected to a central transfer station, and these processing chambers are also referred to as processing stations. Each processing chamber provides a separate processing area isolated from adjacent processing stations. The processing chamber can be any suitable chamber, including but not limited to a pre-cleaning chamber, a buffer chamber, a transfer space, a wafer orienter / degassing chamber, a cryogenic cooling chamber, a deposition chamber, an annealing chamber, an etching chamber, a selective oxidation chamber, an oxide layer thinning chamber, or a word line deposition chamber. The specific configuration of the processing chamber and components can vary depending on the cluster tool and should not be considered as limiting the scope of this disclosure. In some embodiments, the cluster tool 900 includes an oxide layer thinning chamber. The oxide layer thinning chamber of some embodiments includes one or more fluorine-based dry cleaning chambers. In some embodiments, the cluster tool 900 includes a pre-cleaning chamber connected to the central transfer station. In the embodiment shown in FIG. 22, the factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a load chamber 954 and an unload chamber 956 on the front portion 951 of the factory interface 950. Although the load chamber 954 is shown on the left side and the unload chamber 956 is shown on the right side, those skilled in the art will understand that this only represents one possible configuration. The size and shape of the load chamber 954 and the unload chamber 956 can vary depending on, for example, the substrate processed in the cluster tool 900. In the embodiment shown, the load chamber 954 and the unload chamber 956 are sized to accommodate a cassette in which a plurality of wafers are positioned. A robot 952 is located within the factory interface 950 and can move between the load chamber 954 and the unload chamber 956. The robot 952 is capable of transferring wafers from the cassette in the load chamber 954 through the factory interface 950 to the load lock chamber 960. The robot 952 is also capable of transferring wafers from the load lock chamber 962 through the factory interface 950 to the cassette in the unload chamber 956. As those skilled in the art will understand, the factory interface 950 can have more than one robot 952. For example, the factory interface 950 can have a first robot for transferring wafers between the load chamber 954 and the load lock chamber 960 and a second robot for transferring wafers between the load lock chamber 962 and the unload chamber 956. The illustrated cluster tool 900 has a first part 920 and a second part 930. The first part 920 is connected to the factory interface 950 via load lock chambers 960, 962. The first part 920 includes a first transfer chamber 921 in which at least one robot 925 is positioned. The robot 925 is also referred to as a robot wafer transfer mechanism. The first transfer chamber 921 is centered relative to the load lock chambers 960, 962, the processing chambers 902, 904, 916, 918, and the buffer chambers 922, 924. The robot 925 of some embodiments is a multi-arm robot capable of independently moving more than one wafer at a time. In some embodiments, the first transfer chamber 921 includes more than one robot wafer transfer mechanism. The robot 925 in the first transfer chamber 921 is configured to move wafers between the chambers around the first transfer chamber 921. Individual wafers are carried on wafer transfer blades located at the distal end of the first robot mechanism. After processing the wafers in the first part 920, the wafers can be transferred to the second part 930 via a transfer chamber. For example, the chambers 922, 924 can be one-way or two-way transfer chambers. The transfer chambers 922, 924 can be used, for example, to cryogenically cool the wafers before processing in the second part 930, or to allow the wafers to cool or post-process before being moved back to the first part 920. The system controller 990 communicates with the first robot 925, the second robot 935, the first plurality of processing chambers 902, 904, 916, 918, and the second plurality of processing chambers 906, 908, 910, 912, 914. The system controller 990 can be any suitable component that can control the processing chambers and the robots. For example, the system controller 990 can be a computer including a central processing unit, memory, suitable circuitry, and storage. The process can generally be stored as a software routine in the memory of the system controller 990, and when executed by a processor, this software routine causes the processing chambers to perform the processes of this disclosure. The software routine can also be stored and / or executed by a second processor (not shown) remote from the hardware controlled by the processor. Part or all of the methods of this disclosure can also be performed in hardware. Thus, the process can be implemented in software and executed in hardware using a computer system in a hardware implementation such as, for example, a specific application integrated circuit or other type of hardware implementation or a combination such as software and hardware. When executed by a processor, the software routine converts a general-purpose computer into a special-purpose computer (controller) that controls the operation of the chambers to perform the process. In some embodiments, the system controller 990 has a configuration to control a selective deposition chamber to selectively deposit a capture layer on a wafer at a temperature in the range of about 400 °C to about 900 °C in an atmosphere of hydrogen (H 2 ) gas and oxygen (O 2 ) gas at ambient pressure. In one or more embodiments, a processing tool includes: a central transfer station including a robot configured to move wafers; a plurality of processing stations, each processing station connected to the central transfer station and providing a processing area separate from the processing areas of adjacent processing stations, the processing stations including a capture layer selective deposition chamber; and a controller connected to the central transfer station and the processing stations, the controller configured to activate the robot to move the wafer between the processing stations and to control the processes occurring in each of the processing stations. In the context of describing the materials and methods discussed herein (especially in the context of the following patent claims for inventions), the use of the terms "a", "an", "the", and similar references is to be construed to cover the singular and the plural unless otherwise indicated herein or clearly contradicted by the context. Unless otherwise indicated herein, references to numerical ranges herein are merely intended as a simple way to individually refer to each separate value falling within the range, and each separate value is incorporated into this specification as if it were individually recited herein. Unless otherwise indicated herein or clearly contradicted by the context, all methods described herein can be performed in any suitable order. Unless otherwise claimed, the use of any and all examples or exemplary language (e.g., "such as") provided herein is merely intended to better illustrate the materials and methods and does not impose a limitation on the scope. No language in this specification should be construed as indicating any non-claimed element essential to the practice of the disclosed materials and methods. Throughout the specification, references to "one embodiment", "certain embodiments", "one or more embodiments", or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases "in one or more embodiments", "in certain embodiments", "in one embodiment", or "in an embodiment" appearing throughout the specification are not necessarily referring to the same embodiment of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments. Although the disclosure herein has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatuses of the disclosure without departing from the spirit and scope of the disclosure. Accordingly, the disclosure is intended to cover modifications and variations that come within the scope of the appended patent claims for inventions and their equivalents. 10: Method 15: Operation 20: Operation 25: Operation 30: Operation 35: Operation 40: Operation 45: Operation 50: Operation 55: Operation 60: Operation 65: Operation 70: Operation 75: Operation 80: Operation 85: Operation 100: Memory Element / Electronic Component 102: Substrate 103: Region 104: Polysilicon Layer / Oxide Layer 106: Oxide Layer / First Layer 108: Sacrificial Layer 110: Second Layer 112: Memory Stack / Sidewall Surface 114: Bottom / Bottom Surface 120: Common Source Line 122: Surface 130: Memory Stack 131: Step Structure 135: Top Surface 137: Filling Material 138: Surface 139: Surface 140: Mask Layer 141: Interlayer Dielectric 150: Memory Hole Channel / Opening 152: Recessed Area 154: Polysilicon Layer 155: Recessed Area 156: Capture Layer 158: Tunnel Oxide Layer 160: Polysilicon Channel Layer 162: Dielectric Material 164: Bit Line Pad 165: Region / Cell 167: Region 170: Slit Pattern Opening 172: Spacer Material 176: Polysilicon Layer 177: Opening 178: Blocking Oxide Layer 180: Oxide Layer 182: Barrier Layer 184: Word Line Metal 185: Region 186: Filling Material 187: Region 235: Word Line Contact 900: Processing Tool / Cluster Tool 902: Processing Chamber 904: Processing Chamber 906: Processing Chamber 908: Processing Chamber 910: Processing Chamber 912: Processing Chamber 914: Processing Chamber 916: Processing Chamber 918: Processing Chamber 920: First Part 921: Central Transfer Station / First Transfer Chamber 922: Buffer Chamber / Transfer Chamber 924: Buffer Chamber / Transfer Chamber 925: Robot 930: Second Part 931: Central Transfer Station 935: Robot 950: Factory Interface 952: Robot 954: Loading Chamber 956: Unloading Chamber 960: Loading Lock Chamber 962: Loading Lock Chamber 990: System Controller 992: CPU 994: Memory 996: I / O 998: Circuit To enable a detailed understanding of the above features of the present disclosure, the present disclosure briefly summarized above may be described in more detail by reference to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings only show typical embodiments of the present disclosure and should not be considered as limiting its scope, since the present disclosure may admit other equally effective embodiments. The embodiments described herein are shown by way of example and not limitation in the figures of the accompanying drawings, in which like reference numerals indicate like elements. FIG. 1 shows a process flowchart of a method for forming a memory element according to an embodiment described herein; FIG. 2 shows a cross-sectional view of an electronic component having a memory stack according to one or more embodiments; FIG. 3 shows a cross-sectional view of an electronic component after forming a stepped pattern of a memory stack according to one or more embodiments. FIG. 4A shows a cross-sectional view of an electronic component according to one or more embodiments; FIG. 4B shows a developed view of region 103 of the substrate of FIG. 4A according to one of the embodiments; FIG. 5A shows a cross-sectional view of an electronic component according to one or more embodiments; FIG. 5B shows a developed view of region 103 according to one or more embodiments; FIG. 6A shows a cross-sectional view of an electronic component according to one or more embodiments; FIG. 6B shows a developed view of region 103 according to one or more embodiments; FIG. 7A shows a cross-sectional view of an electronic component according to one or more embodiments; FIG. 7B shows a developed view of region 103 according to one or more embodiments; FIG. 8A shows a cross-sectional view of an electronic component according to one or more embodiments; FIG. 8B shows a developed view of region 103 according to one or more embodiments; FIG. 9A shows a cross-sectional view of an electronic component according to one or more embodiments; FIG. 9B shows a developed view of region 103 according to one or more embodiments; FIG. 10A shows a cross-sectional view of an electronic component according to one or more embodiments; FIG. 10B shows a developed view of region 165 according to one or more embodiments; FIG. 10C shows a developed view of region 167 according to one or more embodiments; FIG. 11 shows a cross-sectional view of an electronic component according to one or more embodiments; FIG. 12 shows a cross-sectional view of an electronic component according to one or more embodiments; FIG. 13 shows a cross-sectional view of an electronic component according to one or more embodiments; FIG. 14 shows a cross-sectional view of an electronic component according to one or more embodiments; FIG. 15 shows a cross-sectional view of an electronic component according to one or more embodiments; FIG. 16 shows a cross-sectional view of an electronic component according to one or more embodiments; FIG. 17 shows a cross-sectional view of an electronic component according to one or more embodiments; FIG. 18 shows a cross-sectional view of an electronic component according to one or more embodiments; FIG. 19 shows a cross-sectional view of an electronic component according to one or more embodiments; FIG. 20A shows a cross-sectional view of an electronic component according to one or more embodiments; FIG. 20B shows a developed view of region 185 according to one or more embodiments; FIG. 20C shows a developed view of region 187 according to one or more embodiments; FIG. 21 shows a cross-sectional view of an electronic component according to one or more embodiments; and FIG. 22 shows a cluster tool according to one or more embodiments. Domestic deposit information (please note in the order of deposit institution, date, number) None Foreign deposit information (please note in the order of deposit country, institution, date, number) None 102: Substrate 104: Polysilicon layer / oxide layer 106: Oxide layer / first layer 156: Capture layer 158: Tunnel oxide layer 160: Polysilicon channel layer 162: Dielectric material 176: Polysilicon layer 187: Region
Claims
1. A non-volatile memory device, comprising: a memory stack including a memory cell and a memory hole, the memory cell including a gate, a channel layer, and a trapping layer confined between the gate and the channel layer, and the memory hole extending through the memory stack and having a first portion and a second portion, the second portion including a common source layer, wherein the trapping layer is located on a sidewall of the common source layer and on a bottom surface of the memory hole.
2. The device according to claim 1, wherein the trapping layer comprises silicon nitride.
3. The device according to claim 1, wherein the memory stack comprises a plurality of alternating first material layers and word lines.
4. The device according to claim 3, wherein each of the first material layers comprises an oxide layer.
5. The device according to claim 3, wherein each of the word lines comprises one or more of an oxide, a barrier material, and a word line metal.
6. The device according to claim 1, wherein the common source layer comprises one or more of polysilicon and an oxide.
7. The device according to claim 1, further comprising a bit line pad on a top surface of the memory hole.
8. The device according to claim 3, further comprising a plurality of word line contacts in electrical communication with each of the word lines.
9. A processing tool, comprising: a central transfer station including a robot configured to move a wafer; a plurality of processing stations, each processing station connected to the central transfer station and providing a processing area separated from a processing area of an adjacent processing station, the plurality of processing stations including: a recessed chamber configured to recess a second material layer through an opening in a memory stack, the memory stack including an alternating layer of a first material layer and a second material layer on a common source line, to form a first recessed area adjacent to a sidewall surface of the second material layer, the common source line including one or more of a sacrificial layer, an oxide layer, and a polysilicon layer; a deposition chamber configured to deposit a deposition enabling layer (DEL) in the first recessed area, the deposition enabling layer (DEL) comprising polysilicon and having a hydrogen-terminated surface; a second recessed chamber configured to recess the deposition enabling layer (DEL) to remove a portion of the deposition enabling layer (DEL) and to form a second recessed area adjacent to the sidewall surface of the second material layer; a selective deposition chamber configured to selectively deposit a trapping layer in the second recessed area on the hydrogen-terminated surface of the deposition enabling layer (DEL), on the sidewall surface of the common source line, and on the bottom surface of the opening in the memory stack, but not on a sidewall surface of the first material layer; and a controller connected to the central transfer station and the plurality of processing stations, the controller configured to activate the robot to move wafers between the plurality of processing stations and to control a process occurring in each of the processing stations.
10. The processing tool according to claim 9, further comprising a second deposition chamber configured to deposit one or more transistor layers in the opening on the trapping layer.
11. The processing tool as described in claim 10 further includes a third deposition chamber configured to form a bit line pad on the transistor layer.
12. The processing tool as described in claim 11 further includes a patterning chamber configured to form a slit pattern opening through the memory stack.
13. The processing tool as described in claim 12 further includes a fourth deposition chamber configured to deposit a spacer material in the slit pattern opening.