Semiconductor memory devices

Abstract

An embodiment of a semiconductor memory device includes: a plurality of wiring layers, which are stacked on top of a semiconductor substrate with an insulating layer as a barrier; first and second memory pillars, which penetrate the plurality of wiring layers; and a plurality of first plugs, whose bottom surfaces are respectively connected to the plurality of wiring layers. The plurality of wiring layers includes: a first array region through which the first memory pillars penetrate the plurality of wiring layers; a second array region through which the second memory pillars penetrate the plurality of wiring layers; and a connection region having a plurality of connection portions respectively connected to the plurality of first plugs. The first array region, the connection region, and the second array region are arranged sequentially along a first direction.

Description

Technical Field

[0001] The implementation mainly concerns a semiconductor memory device. Prior Technology

[0002] As a semiconductor memory device, NAND (Not AND) type flash memory is known. Summary of the Invention

[0003] One embodiment provides a semiconductor memory device that can improve processing power.

[0004] An embodiment of a semiconductor memory device includes: a plurality of first wiring layers, which are stacked above a semiconductor substrate through a first insulating layer; first and second memory pillars, which equally penetrate the plurality of first wiring layers; and a plurality of first plugs, whose bottom surfaces are respectively connected to the plurality of first wiring layers. The plurality of first wiring layers includes: a first array region through which the first memory pillars penetrate the plurality of first wiring layers; a second array region through which the second memory pillars penetrate the plurality of first wiring layers; and a connection region forming a plurality of connection portions respectively connected to the plurality of first plugs. The first array region, the connection region, and the second array region are sequentially arranged along a first direction parallel to the semiconductor substrate. Simple Explanation of the Diagram

[0005] Figure 1 is a block diagram of the semiconductor memory device of the first embodiment. Figure 2 is a circuit diagram of the memory cell array of the semiconductor memory device in the first embodiment. Figure 3 is a top view of the memory cell array of the semiconductor memory device in the first embodiment. Figure 4 is a cross-sectional view along line A1-A2 of Figure 3. Figure 5 is a cross-sectional view along line B1-B2 in Figure 3. Figure 6 is a cross-sectional view along line C1-C2 in Figure 3. Figures 7 to 18 illustrate the manufacturing steps of the stepped portion of the memory cell array in the semiconductor memory device of the first embodiment. Figure 19 is a cross-sectional view of the memory cell array of the comparative example and the memory cell array of the semiconductor memory device of the first embodiment. Figure 20 is a top view of the memory cell array of the semiconductor memory device of the second embodiment. Figures 21 to 31 are diagrams illustrating the manufacturing steps of the stepped portion of the memory cell array in the semiconductor memory device of the second embodiment. Implementation

[0006] 1. First Implementation Form

[0007] The semiconductor memory device of the first embodiment will be described. Hereinafter, as a semiconductor memory device, a three-dimensional stacked NAND flash memory formed by three-dimensionally stacking memory cell transistors on a semiconductor substrate will be used as an example for description.

[0008] 1.1 Composition

[0009] 1.1.1 Overall Structure of Semiconductor Memory Devices First, Figure 1 will be used to illustrate the overall structure of a semiconductor memory device. Figure 1 is an example of a block diagram showing the basic overall structure of a semiconductor memory device. Furthermore, in the example in Figure 1, arrows are used to indicate a portion of the connection between the blocks, but the connections between the blocks are not limited to this.

[0010] As shown in Figure 1, the NAND flash memory 1 includes a memory cell array 10, a column decoder 11, a driver circuit 12, a sense amplifier 13, and a voltage generation circuit 14.

[0011] The memory cell array 10 comprises a plurality of blocks BLK (BLK0 to BLK3) which are collections of non-volatile memory cell transistors. Each block BLK comprises a plurality of string cells SU (SU0 to SU3) which are collections of NAND strings NS formed by connecting memory cell transistors in series. Furthermore, the number of blocks BLK and the number of string cells SU within the block BLK are arbitrary.

[0012] The column decoder 11 includes a block decoder (not shown) and hookup circuitry. The block decoder decodes the column address and, based on the decoding result, selects the column direction of the corresponding block BLK. The column decoder 11 is connected to the word lines and select gate lines of each block BLK via hookup circuitry.

[0013] The driver circuit 12 supplies the voltage required for data writing, reading, and deleting operations to the column decoder 11. This voltage is applied to the corresponding character lines and select gate lines via the column decoder 11.

[0014] When reading data, the sensing amplifier 13 reads the data from the memory cell transistor. When writing data, it transmits the written data to the memory cell transistor.

[0015] The voltage generation circuit 14 generates the voltage required for data writing, reading and deleting operations, and supplies it to the driver circuit 12 and the sensing amplifier 13, etc.

[0016] 1.1.2 Composition of Memory Cell Array

[0017] Next, the configuration of the memory cell array 10 will be explained using Figure 2. The example in Figure 2 represents block BLK0, but the configuration of other blocks BLK is the same.

[0018] As shown in Figure 2, block BLK0 contains, for example, four string units SU0 to SU3. Furthermore, each string unit SU contains a plurality of NAND strings NS. Each NAND string NS contains, for example, eight memory cell transistors MT (MT0 to MT7) and select transistors ST1 and ST2. The memory cell transistors MT have control gates and charge storage layers to non-volatilely store data.

[0019] Furthermore, the memory cell transistor MT can be either a MONOS type with an insulating film in the charge storage layer or an FG type with a conductive layer in the charge storage layer. In this embodiment, the MONOS type will be used as an example for explanation. Also, the number of memory cell transistors MT is not limited to 8; it can be 16, 32, 64, 96, 128, etc., and its quantity is not limited. Furthermore, the number of transistors ST1 and ST2 can be arbitrary, as long as there is one or more of each.

[0020] Eight memory cell transistors (MTs) are connected in series between the source of select transistor ST1 and the drain of select transistor ST2. More specifically, the current paths of memory cell transistors MT0 to MT7 are connected in series. Furthermore, the drain of memory cell transistor MT7 is connected to the source of select transistor ST1, and the source of memory cell transistor MT0 is connected to the drain of select transistor ST2.

[0021] The gates of the select transistors ST1 located in series units SU0 to SU3 are connected to different select gate lines SGD0 to SGD3 in each series unit SU. More specifically, for example, the gates of multiple select transistors ST1 located in series unit SU0 share a common connection to the select gate line SGD0.

[0022] The gates of the select transistors ST2 located within serial units SU0 to SU3 share a common gate connection to the select gate line SGS. That is, the gates of multiple select transistors ST2 located within the same block BLK share a common gate connection to the select gate line SGS. Furthermore, the gates of the select transistors ST2 located within serial units SU0 to SU3 can also be connected to different select gate lines SGS0 to SGS3 within each serial unit SU.

[0023] The control gates of memory cell transistors MT0 to MT7 located within the same block BLK are connected to word lines WL0 to WL7 respectively. More specifically, for example, the control gates of multiple memory cell transistors MT0 located within block BLK0 are connected to word line WL0.

[0024] The drains of multiple select transistors ST1 within a string cell SU are connected to different bit lines BL (BL0~BL(n-1), where n is a natural number greater than 2). That is, multiple NAND strings NS within a string cell SU are connected to different bit lines BL. Furthermore, the bit line BL shares a common connection between one NAND string NS contained in each string cell SU0~SU3 of each block BLK.

[0025] The source of the selected transistor ST2 in multiple blocks BLK is connected to the source line SL.

[0026] That is, a string cell SU is a collection of NAND strings NS connected to different bit lines BL and the same select gate line SGD. Furthermore, a block BLK is a collection of multiple string cells SU sharing a word line WL. Moreover, the memory cell array 10 is a collection of multiple blocks BLK sharing a bit line BL.

[0027] Furthermore, the configuration of the memory cell array 10 can also be other configurations. For example, the configuration of the memory cell array 10 is described in U.S. Patent Application No. 12 / 407,403, filed on March 19, 2009, entitled "Three-dimensional stacked non-volatile semiconductor memory". Furthermore, U.S. Patent Application No. 12 / 406,524, filed March 18, 2009, entitled "Three-dimensional stacked non-volatile semiconductor memory"; U.S. Patent Application No. 12 / 679,991, filed March 25, 2010, entitled "Non-volatile semiconductor memory device and method of manufacturing the same"; and U.S. Patent Application No. 12 / 532,030, filed March 23, 2009, entitled "Semiconductor memory and method of manufacturing the same"; are described herein by reference in their entirety.

[0028] 1.1.3 Planar Structure of Memory Cell Array

[0029] Next, the planar configuration of the memory cell array 10 will be explained using Figure 3. Figure 3 is a top view of the string cells SU0 to SU4 in a block BLK. Furthermore, in the example of Figure 3, the interlayer insulating film is omitted.

[0030] As shown in Figure 3, in the memory cell array 10 of this embodiment, serial cells SU0 and SU1 contain a word line WL and a select gate line SGS. Furthermore, a slit SHE is formed between the select gate line SGD0 of serial cell SU0 and the select gate line SGD1 of serial cell SU1, separating the select gate lines SGD0 and SGD1. The same applies to serial cells SU2 and SU3. A slit SLT is formed between serial cells SU1 and SU2, separating their respective select gate lines SGD and SGS, as well as the word line WL.

[0031] The memory cell array 10 includes two array sections, a stepped section, and two dummy stepped sections. More specifically, along a first direction D1 parallel to the semiconductor substrate, from one end of the memory cell array 10 to the other end, a dummy stepped section, an array section, a stepped section, an array section, and a dummy stepped section are sequentially arranged, with the stepped section disposed in the center of the memory cell array 10. That is, along the first direction D1 on the character line WL, there are regions corresponding to the two array sections, the stepped section, and the two dummy stepped sections, and a stepped section is provided between the two array sections.

[0032] Memory pillars MP corresponding to NAND strings NS are formed in the array section. Details regarding the construction of the memory pillars MP will be described below. In the example of Figure 3, in each string cell SU, a plurality of memory pillars MP are arranged in a row along the first direction D1. For example, the upper ends of the memory pillars MP in each string cell SU arranged along a second direction parallel to the semiconductor substrate and orthogonal to the first direction D1 are connected by bit lines BL.

[0033] The selection gate lines SGD0~SGD3 corresponding to the two array sections are separated in the stepped section. Therefore, in a single string cell SU, any one of the two array sections can be selected by selecting any one of the selection gate lines SGD obtained after separation.

[0034] Furthermore, the arrangement of memory columns MP in a single serial unit SU can be arbitrarily set. For example, along the first direction D1, they can be arranged in two rows side by side, or in a zigzag arrangement of four rows.

[0035] In the stepped section, a plurality of wiring layers corresponding to the select gate lines SGD and SGS, and the word lines WL0 to WL7 are led out in a stepped manner (hereinafter, the led-out section is referred to as "stepping"). That is, the stepping of word lines WL0 to WL7 is formed in the first direction D1 at the center of the wiring layer corresponding to word lines WL0 to WL7. A contact plug CC is formed on each stepping. Furthermore, in the stepped section, in order to connect the column decoder 11 (connection circuit) formed on the lower layer of the memory cell array 10 to the contact plug CC, a contact plug C4 is formed that penetrates the memory cell array 10. The upper ends of the contact plug CC and the contact plug C4 are connected by wiring layers. The contact plugs CC and C4 are made of conductive materials, such as tungsten (W) or titanium nitride (TiN) metal materials. Furthermore, an insulating layer (e.g., silicon oxide film) is formed on the side of the contact plug C4, but the contact plug C4 is not in contact with the wiring layer 103.

[0036] Each string unit SU's selection gate line SGD is separated into two by a stepped portion on the first direction D1, and the corresponding contact plugs CC and C4 of each selected gate line SGD after separation are respectively arranged along the first direction D1.

[0037] In the stepped section of the serial unit SU0, a step is provided between the two select gate lines SGD0 for the character line WL7. Furthermore, along the first direction D1, contact plugs C4 corresponding to the character lines WL6, WL4, WL2, and WL0, the select gate line SGS, and the character lines WL1, WL3, WL5, and WL7 are arranged sequentially through this step.

[0038] In the stepped section of the serial unit SU1, between the two select gate lines SGD1, along the first direction D1, are arranged the step surfaces of character lines WL6, WL4, WL2, and WL0, the select gate line SGS, and the character lines WL1, WL3, WL5, and WL7 in sequence. That is, the step surfaces of character lines WL0 to WL7 corresponding to serial units SU0 and SU1 are arranged in a row along the first direction D1. Furthermore, a contact plug CC is arranged on each step surface. That is, along the first direction D1, contact plugs CC corresponding to character lines WL6, WL4, WL2, and WL0, the select gate line SGS, and the character lines WL1, WL3, WL5, and WL7 are arranged in sequence.

[0039] The stepped portions of series units SU2 and SU3 are symmetrically arranged with stepped surfaces and contact plugs CC and C4, separated by a slit SLT from the stepped portions of series units SU0 and SU1.

[0040] More specifically, in the stepped section of the serial unit SU2, between the two select gate lines SGD2, along the first direction D1, are arranged the steps of character lines WL6, WL4, WL2, and WL0, the select gate line SGS, and the steps of character lines WL1, WL3, WL5, and WL7 in sequence. Furthermore, a contact plug CC is arranged on each step.

[0041] In the stepped section of the serial unit SU3, a step is provided between the two select gate lines SGD3 for the character line WL7. Furthermore, along the first direction D1, contact plugs C4 corresponding to the character lines WL6, WL4, WL2, and WL0, the select gate line SGS, and the character lines WL1, WL3, WL5, and WL7 are arranged sequentially through this step.

[0042] Furthermore, the stepped portion of serial unit SU0 can also form a stepped ground for the selector gate line SGS and the character line WL, and a contact plug CC can be formed in the stepped portion of serial unit SU1, corresponding to the selector gate line SGS and the character line WL. The stepped portions of serial units SU2 and SU3 are the same. Moreover, the configuration of the stepped ground in the first direction can be arbitrarily set.

[0043] Furthermore, a plurality of dummy posts HR are provided in the stepped section. These dummy posts HR penetrate multiple wiring layers corresponding to the selector gate lines SGD and SGS, and the character lines WL0 to WL7. The arrangement of the dummy posts is arbitrary. The dummy posts HR have insulating layers formed on their sides and bottom surfaces and are not electrically connected to other wiring. When the gaps corresponding to the selector gate lines SGD and SGS, and the character lines WL are embedded with a metal such as tungsten (W), the dummy posts HR function as posts that support the interlayer insulating film between the selector gate lines SGD and SGS, and the character lines WL, which become the gaps.

[0044] The dummy step is formed during the formation of the step. The width of the dummy step on direction D1 is narrower than the width of the step. Memory pillars MP and contact plugs CC and C4 are not formed in the dummy step. Alternatively, the dummy step may not be formed.

[0045] 1.1.4 Cross-sectional structure of memory cell array

[0046] Next, the cross-sectional configuration of the memory cell array 10 will be described using Figures 4 to 6. Figure 4 is a cross-sectional view of the memory cell array 10 along line A1-A2 shown in Figure 3. Figure 5 is a cross-sectional view of the memory cell array 10 along line B1-B2 shown in Figure 3. Figure 6 is a cross-sectional view of the memory cell array 10 along line C1-C2 shown in Figure 3. Furthermore, for the sake of simplicity, in the examples of Figures 4 and 5, the circuitry disposed on the lower layer of the memory cell array 10 is represented by blocks, and the wiring layers on the memory cylinders MP and contact plugs CC and C4 are omitted. Also, in the example of Figure 6, the circuitry disposed below the memory cell array 10 is omitted.

[0047] As shown in Figure 4, circuits such as a column decoder 11 and a sense amplifier 13 are formed on a semiconductor substrate 100, and a memory cell array 10 is formed above these circuits through an insulating layer 101. The insulating layer 101 is, for example, a silicon oxide film (SiO2). Furthermore, the circuits disposed below the memory cell array 10 are not limited to the column decoder 11 and the sense amplifier 13. More specifically, in the region of the memory cell array 10, a wiring layer 102 that functions as a source line SL is formed on the insulating layer 101, and then 10 wiring layers 103 that function as a select gate line SGS, word lines WL0~WL7, and a select gate line SGD are stacked on the wiring layer 102 with the insulating layer 101 separating the wiring layers. The wiring layers 102 and 103 are made of conductive materials, and metal materials such as W or TiN can also be used.

[0048] In the array section of the memory cell array 10, a memory column MP is formed that penetrates 10 wiring layers 103 and whose bottom surface is connected to the wiring layer 102.

[0049] In the stepped section of the serial unit SU1, steps are formed for the selector gate lines SGD and SGS, and the character lines WL0 to WL7. More specifically, along the first direction D1, a step is formed for the selector gate line SGD1, followed by steps of even-number character lines WL6, WL4, WL2, and WL0 in a two-step stepped manner, then a step is formed for the selector gate line SGS, followed by steps of odd-number character lines WL1, WL3, WL5, and WL7 in a two-step stepped manner, and finally a step is formed for the selector gate line SGD1.

[0050] Contact plugs CC are formed on each terrace. Furthermore, the contact plug CC corresponding to the select gate line SGD1 is formed by connecting to the column decoder 11 through 10 wiring layers 103 and 102. In the example of Figure 4, along the first direction D1, the following are arranged sequentially: contact plug C4 corresponding to the select gate line SGD1; 11 contact plugs CC corresponding to the select gate line SGD1, word lines WL6, WL4, WL2, and WL0; select gate line SGS; word lines WL1, WL3, WL5, and WL7; and the select gate line SGD1; and contact plug C4 corresponding to the select gate line SGD1.

[0051] As shown in Figure 5, a step is formed in the stepped section of the serial unit SU0, where the selection gate line SGD0 and the word line WL7 are connected. The step of word line WL7 is formed such that the contact plug C4 corresponding to the selection gate line SGS and the word lines WL0~WL7 passes through the 9-layer wiring layer 103 and wiring layer 102 corresponding to the selection gate line SGS and the word lines WL0~WL7, and is connected to the column decoder 11. A contact plug CC is formed on the step of the selection gate line SGD0. Furthermore, the contact plug C4 corresponding to the selection gate line SGD0 is formed such that it passes through the 10-layer wiring layer 103 and wiring layer 102, and is connected to the column decoder 11. In the example in Figure 5, along the first direction D1, there are sequentially arranged contact plugs C4 and CC corresponding to the select gate line SGD0, nine contact plugs C4 corresponding to the character lines WL6, WL4, WL2, and WL0, the select gate line SGS, and the character lines WL1, WL3, WL5, and WL7, and contact plugs CC and C4 corresponding to the select gate line SGD0.

[0052] Next, we will explain the detailed cross-sectional structure of the memory column MP.

[0053] As shown in Figure 6, the wiring layer 102, which functions as the source line SL, is shared by the string cells SU0 to SU3. A slit SLT is formed between string cells SU1 and SU2, extending along the first direction D1, separating the 10 wiring layers 103. Furthermore, slit SLTs are also formed between blocks BLK (not shown). Slits SHE are formed between string cells SU0 and SU1, and between string cells SU2 and SU3. The slit SHE formed between string cells SU0 and SU1 will separate gate lines SGD0 and SGD1. The slit SHE formed between string cells SU2 and SU3 will separate gate lines SGD2 and SGD3.

[0054] An insulating layer 101 is formed on a semiconductor substrate 100, with respect to circuits such as a sensing amplifier 13 (not shown), and a wiring layer 102 is formed on the insulating layer 101 to function as a source line SL.

[0055] On the wiring layer 102, an insulating layer 101 is separated between each wiring layer, forming a 10-layer wiring layer 103 from the bottom layer, which functions as the selective gate line SGS, character lines WL0~WL7 and selective gate line SGD.

[0056] The memory pillar MP includes a block insulating film 107, a charge storage layer 106, a tunnel insulating film 105, and a semiconductor layer 104. Furthermore, the memory pillar MP and word lines WL0~WL7 constitute memory cell transistors MT0~MT7. Similarly, the memory pillar MP and select gate lines SGD and SGS constitute select transistors ST1 and ST2.

[0057] More specifically, to form the memory cell pillar MP, a memory via is formed by penetrating the 10 wiring layers 103 and the insulating layer 101 to reach the wiring layer 102. A block insulating film 107, a charge storage layer 106, and a tunnel insulating film 105 are sequentially formed on the side of the memory via. The interior of the memory via is embedded by a semiconductor layer 104. The semiconductor layer 104 is the region for forming the channels of the memory cell transistor MT and the select transistors ST1 and ST2. The block insulating film 107 and the tunnel insulating film 105 are, for example, made of SiO2. The charge storage layer 106 is, for example, made of SiN. Furthermore, the charge storage layer 106, as a conductive material surrounded by insulating material, can also be formed as a floating gate structure. The semiconductor layer 104 is, for example, made of polysilicon.

[0058] On the memory cylinder MP, a contact plug 109 is formed for connection with the wiring of the upper layer. The contact plug 109 is formed of a conductive material, such as a metal material such as W or TiN, or Si doped with phosphorus (P).

[0059] A wiring layer 110 is formed on the contact plug 109 to function as a bit line BL. The wiring layer 110 is formed of a conductive material, or a metallic material such as W or TiN can be used.

[0060] 1.2 Methods for forming stepped sections

[0061] Next, the method for forming the stepped portion will be described using Figures 7 to 18. Figures 7 to 18 respectively show the plane of region RA in Figure 3, i.e., the stepped portion corresponding to one block BLK, a cross-section along line A1-A2 (hereinafter referred to as "A1-A2 cross-section"), and a cross-section along line B1-B2 (hereinafter referred to as "B1-B2 cross-section"). In this embodiment, the following method (hereinafter referred to as "backfill") will be described: after forming a structure equivalent to wiring layer 103 from sacrificial layer 120, sacrificial layer 120 is removed, and then wiring layer 103 is formed by embedding a conductive material. Hereinafter, the case where silicon nitride film (SiN) is used as sacrificial layer 120, and a multilayer film of TiN and W is used as conductive material will be described. TiN functions as a barrier layer to prevent, for example, W from reacting with the underlying Si, or as a bonding layer to improve the adhesion of W when W is formed. Furthermore, the sacrificial layer 120 is not limited to SiN. For example, it can also be a silicon oxynitride (SiON) film, as long as it is a material that can sufficiently achieve a wet etching selectivity ratio with the insulating layer 101 (e.g., SiO2). Also, the conductive material of the wiring layer 103 is not limited to a multilayer film of TiN and W. Furthermore, in the examples of Figures 7 to 18, for the sake of simplicity, the wiring layer 102 and the dummy pillar HR are omitted.

[0062] As shown in Figure 7, on the wiring layer 102 (not shown), 10 sacrificial layers 120 corresponding to the wiring layer 103 are stacked on the interlayer insulating layer 101, and the insulating layer 101 is further formed on the uppermost sacrificial layer 120.

[0063] As shown in Figure 8, the uppermost sacrificial layer 120 is then processed in the regions corresponding to the steps of character lines WL0~WL7 and select gate line SGS, the slit SHE between string units SU0 and SU1, and the slit SHE between string units SU2 and SU3. Then, the portion after the sacrificial layer 120 has been removed is embedded from the insulating layer 101. Thus, the uppermost sacrificial layer 120 is removed in a portion of the region shown in sections A1-A2 and B1-B2.

[0064] As shown in Figure 9, a protective layer 121 is then formed on the stepped portion of the string cells SU0 and SU3. The protective layer 121 functions as a mask when processing the stepped portion. The following explanation describes the case where polycrystalline Si is used as the protective layer 121. Furthermore, the protective layer 121 is not limited to polycrystalline Si. It can be any material that provides sufficient selectivity for dry etching compared to the insulating layer 101 and the sacrificial layer 120.

[0065] As shown in Figure 10, next, using photolithography, an anti-etching pattern 122 is formed for processing the stepped area of ​​the selector gate line SGS. Then, the insulating layer 101 and the sacrificial layer 120 are processed layer by layer. As a result, in the stepped area of ​​the selector gate line SGS shown in section A1-A2, two layers of sacrificial layer 120 from the top are removed. Also, in the stepped area of ​​character lines WL0~WL7, the topmost sacrificial layer 120 is removed. At this time, in the area shown in section B1-B2, since the upper layer is protected by the protective layer 121, the insulating layer 101 and the sacrificial layer 120 are not processed.

[0066] As shown in Figure 11, an anti-corrosion pattern 122 is then formed for processing the stepped regions of even-numbered element lines WL6, WL4, WL2, and WL0, as well as the selective gate line SGS. Then, the insulating layer 101 and the sacrificial layer 120 are processed layer by layer. In this way, in the stepped regions of even-numbered element lines WL6, WL4, WL2, and WL0 shown in section A1-A2, two layers of sacrificial layer 120 are removed from the top layer. In the stepped region of the selective gate line SGS, three layers of sacrificial layer 120 are removed from the top layer. Furthermore, in the stepped regions of odd-numbered element lines WL1, WL3, WL5, and WL7, one layer of sacrificial layer 120 is removed from the top layer. At this time, in the region shown in section B1-B2, since the upper layer is protected by the protective layer 121, the insulating layer 101 and the sacrificial layer 120 are not processed.

[0067] As shown in Figure 12, an anti-corrosion pattern 122 is then formed for the stepped areas of character line WL0, select gate line SGS, and character line WL1. Next, the insulating layer 101 and sacrificial layer 120 are processed in units of two layers each. Thus, in the stepped area of ​​character line WL0 shown in cross-section A1-A2, four layers of sacrificial layer 120 are removed from the top layer. In the stepped area of ​​select gate line SGS, five layers of sacrificial layer 120 are removed from the top layer. In the stepped area of ​​character line WL1, three layers of sacrificial layer 120 are removed from the top layer. Furthermore, in the stepped regions of character lines WL6, WL4, and WL2, two layers of sacrificial layer 120 are removed from the top layer, and in the stepped regions of character lines WL3, WL5, and WL7, one layer of sacrificial layer 120 is removed from the top layer. At this time, in the region shown in the B1-B2 section, since the upper layer is protected by the protective layer 121, the insulating layer 101 and the sacrificial layer 120 are not processed.

[0068] As shown in Figure 13, an anti-corrosion pattern 122 is then formed for processing the stepped regions of character lines WL2 and WL0, the select gate line SGS, and character lines WL1 and WL3. Then, the insulating layer 101 and the sacrificial layer 120 are processed in units of two layers each. Herein, in the stepped region of character line WL2 shown in cross-section A1-A2, four layers of sacrificial layer 120 are removed from the top layer. In the stepped region of character line WL0, six layers of sacrificial layer 120 are removed from the top layer. In the stepped region of select gate line SGS, seven layers of sacrificial layer 120 are removed from the top layer. In the stepped region of character line WL1, five layers of sacrificial layer 120 are removed from the top layer. In the stepped region of character line WL3, three layers of sacrificial layer 120 are removed from the top layer. Furthermore, in the stepped regions of character lines WL6 and WL4, two layers of sacrificial layer 120 from the top layer are removed, and in the stepped regions of character lines WL5 and WL7, one layer of sacrificial layer 120 from the top layer is removed. At this time, in the region shown in the B1-B2 section, since the upper layer is protected by the protective layer 121, the insulating layer 101 and the sacrificial layer 120 are not processed.

[0069] As shown in Figure 14, an anti-corrosion pattern 122 is then formed for processing the stepped regions of character lines WL4, WL2, and WL0, the select gate line SGS, and character lines WL1, WL3, and WL5. Then, the insulating layer 101 and the sacrificial layer 120 are processed in units of two layers each. Herein, in the stepped region of character line WL6 shown in cross-section A1-A2, two layers of sacrificial layer 120 are removed from the top layer. In the stepped region of character line WL4, four layers of sacrificial layer 120 are removed from the top layer. In the stepped region of character line WL2, six layers of sacrificial layer 120 are removed from the top layer. In the stepped region of character line WL0, eight layers of sacrificial layer 120 are removed from the top layer. In the step region of the selector gate line SGS, nine layers of sacrificial layer 120 are removed from the top layer. In the step region of character line WL1, seven layers of sacrificial layer 120 are removed from the top layer. In the step region of character line WL3, five layers of sacrificial layer 120 are removed from the top layer. In the step region of character line WL5, three layers of sacrificial layer 120 are removed from the top layer. Furthermore, in the step region of character line WL7, one layer of sacrificial layer 120 is removed from the top layer. At this time, in the region shown in the B1-B2 cross-section, since the upper layer is protected by the protective layer 121, the insulating layer 101 and the sacrificial layer 120 are not processed.

[0070] As shown in Figure 15, after removing the resist pattern 122 and the protective layer 121, the step regions of the character lines WL0~WL7 and the select gate line SGS are embedded with the insulating layer 101, and the surface of the insulating layer 101 is planarized using, for example, CMP (Chemical Mechanical Polishing). Then, for example, memory pillars MP and dummy pillars HR are formed.

[0071] As shown in Figure 16, next, contact plugs C4 corresponding to the character lines WL0~WL7 and the select gate lines SGD and SGS are formed.

[0072] As shown in Figure 17, firstly, a slotted surface layer (SLT) is fabricated to form a groove pattern. Next, the sacrificial layer 120 is backfilled using W and TiN to form the wiring layer 103. More specifically, when the sacrificial layer 120 is SiN, wet etching using phosphoric acid (H₃PO₄) is performed. This etches the sacrificial layer 120 from the groove pattern of the slotted surface layer (SLT), creating voids in the areas containing the sacrificial layer 120. Next, TiN and W are sequentially deposited to embed the voids. Then, the TiN and W formed on the sides and bottom of the slot and on the insulating layer 101 are removed to form the wiring layer 103. Finally, the groove pattern of the slotted surface layer (SLT) is embedded using SiO₂.

[0073] As shown in Figure 18, a contact plug CC is then formed on the steps of character lines WL0~WL7 and select gate lines SGD and SGS.

[0074] 1.3 Effects of this implementation

[0075] If configured as described in this embodiment, processing power can be improved. The following explains this effect.

[0076] In a three-dimensional stacked NAND flash memory, a plurality of wiring layers, functioning as word lines (WL), are stacked on top of a semiconductor substrate. These stacked wiring layers are led out in a stepped manner and connected to the column decoder 11 via contact plugs (CC). Therefore, if the distance from the contact plug (CC) to the memory cylinder (MP) increases, i.e., if the wiring length of the word lines (WL) increases, the RC delay increases due to the increase in wiring resistance and inter-wiring capacitance.

[0077] Figure 19 illustrates a specific example of the wiring length of the character lines WL. The upper section of Figure 19 shows a cross-section of the memory cell array with a stepped portion located at the end of the memory cell array, as a comparative example. The lower section of Figure 19 shows a cross-section of the memory cell array in this embodiment. Furthermore, in the example of Figure 19, for the sake of simplicity, the source line SL and the select gate lines SGD and SGS are omitted, and are represented as part of a plurality of character lines WL, specifically character lines WL4 to WL7.

[0078] As shown in Figure 19, if the wiring length from the contact plug CC to the end of the word line WL is set to L when a stepped portion is provided at the end of the memory cell array as a comparative example, then when a stepped portion is provided in the center of the memory cell array in this embodiment, the wiring length from the contact plug CC to the end of the word line WL becomes L / 2, which allows the wiring resistance and inter-wiring capacitance to be approximately half. Therefore, RC can be reduced.

[0079] Thus, in this embodiment, the stepped portion can be positioned in the center of the memory cell array 10, i.e., between the two array portions. This reduces RC delay in the memory cylinder MP located at the end of the word line WL, since the resistance of the word line WL is approximately half that of the inter-wiring capacitance. This reduces the delay in signal propagation speed in the word line WL, thereby improving the processing power of the semiconductor memory device.

[0080] Furthermore, since the wiring length of the word line WL is approximately half, the voltage drop in the word line WL can be reduced. Therefore, the voltage unevenness of the word line WL caused by the wiring length can be reduced, thereby reducing false writes and false reads. This improves the reliability of semiconductor memory devices.

[0081] 2. Second Implementation Form

[0082] Next, the second embodiment will be described. In the second embodiment, the configuration of the terraces, which differs from that in the first embodiment, will be explained. Hereinafter, only the aspects that differ from the first embodiment will be described.

[0083] 2.1 Planar Structure of Memory Cell Array

[0084] First, the planar configuration of the memory cell array 10 will be explained using Figure 20. Figure 20 is a top view of the string cells SU0 to SU4 in a block BLK. Furthermore, in the example of Figure 20, the interlayer insulating film is omitted.

[0085] As shown in Figure 20, in the memory cell array 10 of this embodiment, there are word lines WL and select gate lines SGS in the serial cells SU0 to SU4. Select gate lines SGD0 and SGD1 are separated by a slit SHE. Similarly, select gate lines SGD2 and SGD3 are separated by a slit SHE. Furthermore, select gate lines SGD1 and SGD2 are separated by a slit SHE and a slit SLT. That is, a slit SLT is formed in a portion between serial cells SU1 and SU2. Therefore, between serial cells SU1 and SU2, in the region where the slit SHE is formed, the select gate line SGS and the word line WL are connected.

[0086] The memory cell array 10, like the one in Figure 3 of the first embodiment, includes two array sections, a step section, and two dummy step sections.

[0087] In the stepped section of this embodiment, the steps of character lines WL0 to WL7 are arranged in two rows side by side along the first direction D1.

[0088] More specifically, in the stepped portion of the serial unit SU0, a step for the character line WL7 is formed between the two steps corresponding to the selection gate line SGD0. Furthermore, along the first direction D1, contact plugs C4 and CC corresponding to the selection gate line SGD0, contact plug C4 corresponding to the character lines WL6, WL2, WL3, and WL7, and contact plugs CC and C4 corresponding to the selection gate line SGD0 are arranged sequentially.

[0089] In the stepped section of the serial unit SU1, stepping stones for character lines WL6, WL2, WL3, and WL7 are formed along the first direction D1 between two stepping stones corresponding to the selection gate line SGD1. Furthermore, along the first direction D1, contact plugs C4 and CC corresponding to the selection gate line SGD1, contact plug CC corresponding to the character lines WL6, WL2, WL3, and WL7, and contact plugs CC and C4 corresponding to the selection gate line SGD1 are arranged sequentially.

[0090] In the stepped section of the serial unit SU2, between the two steps corresponding to the selection gate line SGD2, steps for character lines WL4 and WL0, selection gate line SGS, and character lines WL1 and WL5 are formed along the first direction D1. Furthermore, along the first direction D1, contact plugs C4 and CC corresponding to the selection gate line SGD2, contact plug CC corresponding to character lines WL4 and WL0, selection gate line SGS, and character lines WL1 and WL5, and contact plugs CC and C4 corresponding to the selection gate line SGD2 are sequentially arranged.

[0091] In the stepped section of the serial unit SU3, a step for the character line WL7 is formed between two steps corresponding to the selection gate line SGD3. Furthermore, along the first direction D1, contact plugs C4 and CC corresponding to the selection gate line SGD3, contact plug C4 corresponding to the character lines WL4 and WL0, the selection gate line SGS, and the character lines WL1 and WL5, and contact plugs CC and C4 corresponding to the selection gate line SGD3 are arranged sequentially.

[0092] Furthermore, the configuration of the steps and contact plugs CC and C4 in the stepped section of the serial unit SU0~SU3 can be set arbitrarily.

[0093] Furthermore, in the stepped section, a plurality of dummy posts HR are provided, which connect to a plurality of wiring layers corresponding to the selector gate lines SGD and SGS, and the character lines WL0~WL7. The configuration of the dummy posts is arbitrary.

[0094] 2.2 Methods for forming stepped sections

[0095] Next, the method of forming the stepped section will be explained using Figures 21 to 31. Figures 21 to 31 respectively show the plan of region RB in Figure 20, i.e., the stepped section corresponding to one block BLK, the cross-section along line D1-D2 (hereinafter referred to as the "D1-D2 cross-section"), and the cross-section along line E1-E2 (hereinafter referred to as the "E2-E2 cross-section"). Furthermore, in the examples of Figures 21 to 31, for the sake of simplicity, the wiring layer 102, which functions as the source line SL, and the dummy pillar HR are omitted.

[0096] As shown in Figure 21, on the wiring layer 102 (not shown), ten sacrificial layers 120 corresponding to the wiring layer 103 are stacked on the interlayer insulating layer 101, and the insulating layer 101 is further formed on the uppermost sacrificial layer 120.

[0097] As shown in Figure 22, the uppermost sacrificial layer 120 is then processed in the region corresponding to the steps of the character lines WL0~WL7 and the select gate line SGS, and the slits SHE between each string cell SU. In this embodiment, the uppermost sacrificial layer 120 corresponding to the select gate lines SGD0~SGD3 is separated using the slits SHE. Then, the portion after the sacrificial layer 120 has been removed is embedded using the insulating layer 101. Thus, in a portion of the region shown in cross-sections D1-D2 and E1-E2, the uppermost sacrificial layer 120 is removed. Then, for example, memory pillars MP and dummy pillars HR are formed.

[0098] As shown in Figure 23, a protective layer 121 is then formed on the stepped portion of the serial units SU0 and SU3.

[0099] As shown in Figure 24, an anti-corrosion pattern 122 is then formed for processing the stepped area of ​​the selectable gate line SGS. Next, the insulating layer 101 and the sacrificial layer 120 are processed layer by layer. In this way, in the stepped area of ​​the selectable gate line SGS shown in the E1-E2 cross section, two layers of sacrificial layer 120 from the top are removed. Furthermore, in the stepped area of ​​character lines WL0~WL7, the topmost sacrificial layer 120 is removed.

[0100] As shown in Figure 25, an anti-corrosion pattern 122 is then formed for the stepped regions of character lines WL4 and WL0, select gate line SGS, and character lines WL1 and WL5. Then, the insulating layer 101 and the sacrificial layer 120 are processed in units of two layers each. In this way, in the stepped regions of character lines WL4, WL0, WL1, and WL5 shown in section E1-E2, three layers of sacrificial layer 120 are removed from the top layer; in the stepped region of select gate line SGS, four layers of sacrificial layer 120 are removed from the top layer. Furthermore, in the stepped regions of character lines WL6, WL2, WL3, and WL7 shown in section D1-D2, one layer of sacrificial layer 120 is removed from the top layer.

[0101] As shown in Figure 26, an anti-corrosion pattern 122 is then formed for processing the stepped areas of character lines WL6, WL4, WL2, and WL0, as well as the select gate line SGS. Then, the insulating layer 101 and the sacrificial layer 120 are processed layer by layer. In this way, in the stepped areas of character lines WL6 and WL2 shown in cross-section D1-D2, two layers of sacrificial layer 120 are removed from the top layer. Also, in the areas of character lines WL3 and WL7, one layer of sacrificial layer 120 is removed from the top layer. In the stepped areas of character lines WL4 and WL0 shown in cross-section E1-E2, four layers of sacrificial layer 120 are removed from the top layer, and in the stepped area of ​​the select gate line SGS, five layers of sacrificial layer 120 are removed from the top layer. Furthermore, in the terrace region between character lines WL1 and WL5, the sacrificial layer 120 of 3 layers was removed.

[0102] As shown in Figure 27, an anti-corrosion pattern 122 is then formed for processing the stepped areas of character lines WL0~WL3 and the selector gate line SGS. Then, the insulating layer 101 and the sacrificial layer 120 are processed in units of four layers each. Herein, in the stepped area of ​​character line WL2 shown in cross section D1-D2, six layers of sacrificial layer 120 are removed from the top layer; in the stepped area of ​​character line WL3, five layers of sacrificial layer 120 are removed from the top layer; furthermore, in the stepped area of ​​character line WL6, two layers of sacrificial layer 120 are removed from the top layer; and in the stepped area of ​​character line WL7, one layer of sacrificial layer 120 is removed from the top layer. In the step region of character line WL0 shown in the E1-E2 profile, 8 layers of sacrificial layer 120 are removed from the top layer; in the step region of select gate line SGS, 9 layers of sacrificial layer 120 are removed from the top layer; and in the step region of character line WL1, 7 layers of sacrificial layer 120 are removed from the top layer. Furthermore, in the step region of character line WL4, 4 layers of sacrificial layer 120 are removed from the top layer; and in the step region of character line WL5, 3 layers of sacrificial layer 120 are removed from the top layer.

[0103] As shown in Figure 28, after removing the resist pattern 122 and the protective layer 121, the step areas of the character lines WL0~WL7 and the select gate line SGS are embedded with the insulating layer 101, and the surface of the insulating layer 101 is planarized using, for example, CMP.

[0104] As shown in Figure 29, next, contact plugs C4 corresponding to the character lines WL0~WL7 and the select gate lines SGD and SGS are formed.

[0105] As shown in Figure 30, firstly, a slot SLT is processed to form a groove pattern. Next, the sacrificial layer 120 is backfilled using W and TiN. Then, the TiN and W formed on the sides and bottom of the slot and on the insulating layer 101 are removed to form a wiring layer 103. Finally, the groove pattern of the slot SLT is embedded using SiO2.

[0106] As shown in Figure 31, next, contact plugs CC corresponding to the character lines WL0~WL7 and the select gate lines SGD and SGS are formed.

[0107] 2.3 Effects of this implementation method

[0108] If this embodiment is configured, the same effect as the first embodiment can be obtained.

[0109] Furthermore, in this embodiment, since the stepped character lines WL0~WL7 are arranged in two rows side-by-side along the first direction D1, the length of the stepped portion in the first direction D1 can be shortened. Therefore, the increase in wafer area can be suppressed.

[0110] 3. Examples of variations, etc.

[0111] The semiconductor memory device of the above embodiment includes: a plurality of first wiring layers (103), which are stacked above a semiconductor substrate through a first insulating layer; first and second memory pillars (MPs) that penetrate the plurality of first wiring layers; and a plurality of first plugs (CCs) whose bottom surfaces are respectively connected to the plurality of first wiring layers. The plurality of first wiring layers includes: a first array region through which the first memory pillars penetrate the plurality of first wiring layers; a second array region through which the second memory pillars penetrate the plurality of first wiring layers; and a connection region (step portion) that forms a plurality of connection portions (steps) respectively connected to the plurality of first plugs. The first array region, the connection region, and the second array region are arranged sequentially along a first direction parallel to the semiconductor substrate.

[0112] By applying the above embodiments, a semiconductor memory device with improved processing power can be provided. Furthermore, the embodiments are not limited to the embodiments already described, and various variations are possible.

[0113] For example, the semiconductor memory device in the above embodiments is not limited to three-dimensional stacked NAND flash memory. It can be applied to three-dimensional stacked memory such as ReRAM (Resistive Random Access Memory) formed by stacked word lines.

[0114] Furthermore, the "connection" in the above-described embodiments also includes a state in which the connection is indirectly made through intermediate intermediaries such as transistors or resistors.

[0115] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms and can be omitted, substituted, or modified in various ways without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention and are included within the scope of the invention described in the claims and their equivalents. [Related Applications]

[0116] This application enjoys priority to Japanese Patent Application No. 2018-46940 (filed on March 14, 2018). This application includes all contents of the basic application by reference to that basic application.

[0117] 1: NAND flash memory 10: Memory Cell Array 11: Column Decoder 12: Driver circuit 13: Sensing Amplifier 14: Voltage generation circuit 100: Semiconductor substrate 101: Insulation layer 102: Wiring layer 103: Wiring layer 104: Semiconductor layer 105: Tunnel insulation film 106: Charge storage layer 107: Block insulating film 109: Contact plug 110: Wiring layer 120: Sacrifice Layer 121: Protective layer 122: Anti-corrosion pattern BL(BL0~BL(n-1)): Bit line BLK (BLK0~BLK3): Block C4: Contact plug CC: Contact plug HR: Dummy Column MP: Memory Column MT (MT0~MT7): Memory Cell Electron NS: NAND string RA: Region SGD0: Select gate line SGD1: Select gate line SGD2: Select gate line SGD3: Select gate line SGS: Select Gate Line SHE: Narrow Slit SL: Source Line SLT: Slit ST1: Select Transistor ST2: Select Transistor SU (SU0~SU3): Serial unit WL0~WL7: Character lines

Claims

1. A semiconductor memory device comprising: a plurality of first conductive layers, stacked equally in a first direction and disposed between two nearest first slits in a second direction; a second conductive layer disposed above the plurality of first conductive layers and disposed between one of the two nearest first slits and a second slit; a third conductive layer disposed above the plurality of first conductive layers and disposed between the other of the two nearest first slits and the second slit; a first post extending in the first direction through the plurality of first conductive layers and the second conductive layer, and comprising a semiconductor layer; a second post extending in the first direction through the plurality of first conductive layers and the third conductive layer, and comprising a semiconductor layer; a first plug extending in the first direction and contacting the second conductive layer; and a second plug extending in the first direction and contacting the third conductive layer. The third plug extends in the first direction and penetrates the plurality of first conductive layers and the second conductive layer, and is electrically connected to the first plug; and the fourth plug extends in the first direction and penetrates the plurality of first conductive layers and the third conductive layer, and is electrically connected to the second plug.

2. The semiconductor memory device of claim 1, further comprising: a first insulating layer disposed between the third plug and the plurality of first conductive layers; and a second insulating layer disposed between the fourth plug and the plurality of first conductive layers; wherein the third plug and the fourth plug are not in contact with the plurality of first conductive layers.

3. The semiconductor memory device of claim 1, further comprising: a fifth plug extending in the first direction and in contact with a first layer of the plurality of first conductive layers; and a sixth plug extending in the first direction and in contact with a second layer of the plurality of first conductive layers; wherein the first layer and the second layer are arranged in a stepwise manner along a third direction intersecting the first direction and the second direction.

4. The semiconductor memory device of claim 3, wherein the first layer and the second layer are arranged in a two-stage stepwise shape.

5. The semiconductor memory device as claimed in claim 1, wherein each of the first and second pillars comprises: The third insulating layer, the charge storage layer, and the fourth insulating layer are sequentially disposed on the side surface of the aforementioned semiconductor layer.

6. The semiconductor memory device of claim 1 further includes: a circuit disposed below the plurality of first conductive layers, wherein the bottom surfaces of the third and fourth plugs are electrically coupled to the circuit.

7. The semiconductor memory device as claimed in claim 6, wherein the circuit described above is a column decoder.

8. The semiconductor memory device of claim 1 further includes: a fourth conductive layer disposed above the first and second pillars and electrically coupled to the semiconductor layer of the first pillar and the semiconductor layer of the second pillar.

9. The semiconductor memory device of claim 8, further comprising: a sensing amplifier, wherein the fourth conductive layer is electrically coupled to the sensing amplifier.

10. The semiconductor memory device of claim 1, further comprising: a fifth conductive layer disposed below the plurality of first conductive layers and in contact with the bottom surfaces of the first and second pillars.

11. The semiconductor memory device of claim 1, wherein the ends of the plurality of first conductive layers are arranged in a stepped manner along a third direction intersecting the first direction and the second direction.

12. The semiconductor memory device of claim 1, further comprising: a sixth conductive layer disposed above the plurality of first conductive layers and disposed in a third direction of the second conductive layer, the third direction intersecting the first and second directions; a seventh conductive layer disposed above the plurality of first conductive layers, disposed in the third direction of the third conductive layer and disposed in the second direction of the sixth conductive layer; a third post extending through the plurality of first conductive layers and the sixth conductive layer, and comprising a semiconductor layer; and a fourth post extending through the plurality of first conductive layers and the seventh conductive layer, and comprising a semiconductor layer; wherein the first and third plugs are disposed between the first and third posts, and the second and fourth plugs are disposed between the second and fourth posts.