Semiconductor substrate

Abstract

The semiconductor substrate includes a template substrate and a first semiconductor portion located above a first seed region and a growth inhibition region. The first semiconductor portion includes a first wing located above the aforementioned growth inhibition region. The first wing has a first nitride semiconductor layer, an aluminum-based semiconductor layer located on the first nitride semiconductor layer, and a second nitride semiconductor layer located on the aluminum-based semiconductor layer. The upper surface of the second nitride semiconductor layer has a lower silicon concentration compared to the upper surface of the first nitride semiconductor layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor substrate, etc. Prior Art

[0002] Patent Document 1 discloses a method (ELO method) in which a mask pattern including a mask portion and an opening portion is formed on a base substrate including a seed layer, and a nitride semiconductor layer is grown laterally on the mask portion using the seed layer exposed in the opening portion as a growth starting point. [Prior Art Literature] [Patent Document]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-251304 Summary of the Invention

[0004] [Problems to be solved by the invention] In the method of Patent Document 1, it is difficult to form a nitride semiconductor layer with high surface quality. [Technical means to solve the problem]

[0005] A semiconductor substrate in one embodiment of the present disclosure comprises: a template substrate comprising a first seed region and a growth inhibition region arranged in a first direction; and a first semiconductor portion located above the first seed region and the growth inhibition region; and the first semiconductor portion comprises a first wing portion located above the growth inhibition region; the first wing portion comprises a first nitride semiconductor layer, an aluminum-based semiconductor layer comprising aluminum and located on the first nitride semiconductor layer, and a second nitride semiconductor layer located on the aluminum-based semiconductor layer; and the upper surface of the second nitride semiconductor layer has a lower silicon concentration than the upper surface of the first nitride semiconductor layer. [Effects of the Invention]

[0006] The surface quality of the first wing is improved. Simple diagram description

[0007] FIG1 is a cross-sectional view showing the structure of a semiconductor substrate in one embodiment of the present disclosure. FIG2 is a top view showing the structure of a semiconductor substrate in one embodiment of the present disclosure. FIG3 is an enlarged microscope image showing a portion of a cross section of a semiconductor substrate according to an embodiment of the present disclosure. FIG4 is an enlarged view of region IV shown in FIG3 . FIG5 is an enlarged microscope image showing a main portion of a cross section of a semiconductor substrate according to an embodiment of the present disclosure. FIG6 is an enlarged cross-sectional view showing a portion of a semiconductor substrate in an embodiment of the present disclosure. FIG7 is a flow chart showing an example of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure. FIG8 is a flow chart showing an example of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure. FIG9 is a cross-sectional view showing an example of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure. FIG10 is a cross-sectional view showing an example of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure. FIG11 is a block diagram showing a semiconductor substrate manufacturing apparatus according to one embodiment of the present disclosure. FIG12 is a cross-sectional view showing the structure of the template substrate in Example 1. FIG. FIG13 is a cross-sectional view showing a configuration example of a base substrate. FIG14 is a cross-sectional view showing a configuration example of a template substrate. FIG15 is a cross-sectional view schematically showing the structure of the semiconductor substrate in Example 1. FIG. FIG16 is a top view schematically showing the structure of the semiconductor substrate in Example 1. FIG. FIG17 is a cross-sectional view showing an example of lateral growth of the first nitride semiconductor layer. FIG18 is a cross-sectional view showing an example of the growth of the Al-based semiconductor layer and the second nitride semiconductor layer. FIG19 is a graph showing the results of SIMS analysis of the semiconductor substrate in Example 1. FIG. FIG20 is a diagram showing a microscope image of the semiconductor substrate in Example 1 superimposed with the abundance ratio of each element analyzed by EDS. FIG21 is a top view showing another structural example of the semiconductor substrate in Example 1. FIG. FIG22 is a cross-sectional view showing another structural example of the semiconductor substrate in Example 1. FIG. FIG23 is a top view showing another structural example of the semiconductor substrate in Example 1. FIG. FIG24 is a cross-sectional view showing the method of separating the components in Example 1. FIG. FIG. 25 is a top view showing the method of separating components in Example 1. FIG. FIG26 is a top view showing another structural example of the semiconductor substrate in Example 1. FIG. FIG27 is a cross-sectional view schematically showing the structure of the semiconductor substrate in Example 2. FIG. FIG28 is a cross-sectional view schematically showing the structure of the semiconductor substrate in Example 3. FIG29 is a schematic diagram showing an example of the structure of an electronic device. FIG30 is a schematic diagram showing another configuration example of an electronic device. Implementation Method

[0008] [Semiconductor substrate] FIG1 is a cross-sectional view showing the structure of a semiconductor substrate according to one embodiment of the present disclosure. FIG2 is a top view showing the structure of a semiconductor substrate according to one embodiment of the present disclosure. As shown in FIG1 and FIG2 , a semiconductor substrate 10 includes: a template substrate TS including a first seed region S1 and a growth inhibition region DA arranged in a first direction (X direction); and a first semiconductor portion 8A located above the first seed region S1 and the growth inhibition region DA. The first semiconductor portion 8A includes a first wing portion F1 located above the growth inhibition region DA. The first wing portion F1 includes a first nitride semiconductor layer NS1, an aluminum-based semiconductor layer (hereinafter, Al-based semiconductor layer) ALS containing aluminum and located on the first nitride semiconductor layer NS1, and a second nitride semiconductor layer NS2 located on the Al-based semiconductor layer ALS. The upper surface N2T of the second nitride semiconductor layer NS2 has a lower silicon concentration than the upper surface N1T of the first nitride semiconductor layer NS1. Furthermore, the surface roughness of the aluminum-based semiconductor layer ALS of the first wing portion F1 may be smaller than the surface roughness of the first nitride semiconductor layer NS1.

[0009] In Figure 1, for ease of illustration, the portion of the top surface N1T of the first nitride semiconductor layer NS1 is highlighted with dark gray hatching. The top surface roughness and silicon concentration of the first nitride semiconductor layer NS1 can be determined simply within the top portion of the first nitride semiconductor layer NS1 (for example, the portion above the reference point where the thickness of the first nitride semiconductor layer NS1 is minimized, with the depth from the top surface being half the thickness). The Al-based semiconductor layer ALS can also be an Al-containing semiconductor layer (or compound semiconductor layer). The Al-based semiconductor layer ALS can, for example, include aluminum nitride (AlN) or a GaN-based semiconductor containing aluminum. The Al-based semiconductor layer ALS can include, for example, aluminum gallium nitride (AlGaN). The Al-based semiconductor layer ALS will be described in detail later.

[0010] The semiconductor substrate 10 can improve the surface quality of the first wing F1. For example, the surface of the first wing F1 can have high flatness and a low impurity concentration. This improved surface quality allows for the formation of high-quality functional layers above the first wing F1. By increasing the aspect ratio (the ratio of width to thickness) of the first nitride semiconductor layer NS1, the semiconductor substrate 10 achieves the following effects even if surface defects (such as surface roughness or impurity condensation) occur in the first nitride semiconductor layer NS1. Specifically, the Al-based semiconductor layer ALS, which contains highly reactive aluminum, functions as a planarizing film, allowing the thinner second nitride semiconductor layer NS2 with high surface quality to be formed on the Al-based semiconductor layer ALS. This results in a high-quality first wing F1 with a high aspect ratio (flatness). Impurities can be elements (e.g., Si) derived from at least one of the template substrate TS and the crystal growth apparatus (e.g., an MOCVD apparatus). The upper surface N2T of the second nitride semiconductor layer NS2 may also have a lower concentration of impurities (e.g., silicon) than the upper surface N1T of the first nitride semiconductor layer NS1. The upper surface roughness and silicon concentration of the second nitride semiconductor layer NS2 can be determined simply in the upper portion of the second nitride semiconductor layer NS2 (e.g., the portion above the point where the thickness of the second nitride semiconductor layer NS2 is minimum, with the depth from the upper surface being half the thickness). The first semiconductor portion 8A includes a first base portion B1 located above the first seed region S1. Details of each portion of the first semiconductor portion 8A will be described later.

[0011] In the semiconductor substrate 10 of this embodiment, the template substrate TS may include a base substrate BS, on which a mask pattern 6 is formed. The base substrate BS may include a main substrate 1 and a base layer 4 located above the main substrate 1. The mask pattern 6 may include a mask portion 5 that functions as a growth inhibition region DA and a first opening K1 corresponding to the first seed region S1. Specifically, the surface of the mask portion 5 may serve as the growth inhibition region DA. The template substrate TS may also be referred to as a growth substrate.

[0012] The first semiconductor portion 8A includes a nitride semiconductor. Furthermore, the first nitride semiconductor layer NS1, the Al-based semiconductor layer ALS, and the second nitride semiconductor layer NS2 each include a nitride semiconductor. Nitride semiconductors can be represented, for example, as AlxGayInzN (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1). Specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). GaN-based semiconductors are semiconductors containing gallium atoms (Ga) and nitrogen atoms (N). Typical examples include GaN, AlGaN, AlGaInN, and InGaN.

[0013] The first semiconductor portion 8A can be doped (e.g., n-type containing a donor) or undoped. A semiconductor substrate refers to a substrate containing a semiconductor. The main substrate 1 of the template substrate TS can contain a semiconductor (e.g., silicon or silicon carbide) or not. Examples of main substrates 1 that do not contain a semiconductor include sapphire substrates. The substrate comprising the main substrate 1 and the base layer 4 is sometimes referred to as a base substrate BS. The base substrate BS serves as a support base (base) for various upper layers.

[0014] The base layer 4 may have a single-layer structure or a multi-layer structure. The base layer 4 may have a multi-layer structure including a periodic structure. For example, the base layer 4 may include a seed portion (seed layer) that serves as the starting point for the growth of the nitride semiconductor, and a buffer portion (buffer layer, buffer layer) located between the main substrate 1 and the seed portion.

[0015] The first nitride semiconductor layer NS1 in the first semiconductor portion 8A can be formed on the template substrate TS using the epitaxial lateral overgrowth (ELO) method. In the ELO method, for example, a different substrate with a different lattice constant than the nitride semiconductor can be used as the main substrate 1. An inorganic compound film can be used as the mask portion 5, and the first seed region S1 exposed in the first opening K1 is used as the starting point for crystal growth. This allows the initial growth layer (primary growth layer) 8s to be formed on the first seed region S1. Subsequently, the first nitride semiconductor layer NS1 is laterally grown from the initial growth layer 8s to the mask portion 5. The initial growth layer 8s can also be referred to as a seed region.

[0016] In the first semiconductor portion 8A, the first base portion B1 located above the first opening portion K1 becomes a dislocation inheriting portion with more through dislocations, and the first wing portion F1 located above the mask portion 5 can be set as a low-defect portion with a through dislocation density lower than that of the dislocation inheriting portion.

[0017] The template substrate TS may also include a second seed region S2 adjacent to the first seed region S1 in the first direction (X direction) with the growth inhibition region DA interposed therebetween. The mask pattern 6 may include a second opening K2 corresponding to the second seed region S2. The template substrate TS may also have a shape in which the first seed region S1 and the growth inhibition region DA, which are arranged in the first direction (X direction), each have their longitudinal direction in a second direction (Y direction) perpendicular to the first direction. The template substrate TS may also have a shape in which the first seed region S1, the growth inhibition region DA, and the second seed region S2, which are arranged in the first direction, each have their longitudinal direction in the second direction.

[0018] The template substrate TS has a second semiconductor portion 8C located above the second seed region S2 and the growth inhibition region DA. The second semiconductor portion 8C includes a second base B2 located above the second seed region S2 and a second wing F2 located above the growth inhibition region DA. The first wing F1 and the second wing F2 are adjacent to each other with a gap G therebetween.

[0019] In one embodiment, the growth of the first nitride semiconductor layer NS1 may be stopped before the first nitride semiconductor layer NS1, which has grown laterally on the mask portion 5 from the initial growth layer 8s grown starting from the first seed region S1, and the first nitride semiconductor layer NS1, which has grown laterally on the mask portion 5 from the initial growth layer 8s grown starting from the second seed region S2, meet each other. Similar to the first semiconductor portion 8A described above, in the second semiconductor portion 8C, the second base portion B2 located above the second seed region S2 serves as a dislocation inheritance portion, and the second wing portion F2 located above the growth suppression area DA serves as a low-defect portion.

[0020] Hereinafter, the first semiconductor portion 8A and the second semiconductor portion 8C may be collectively referred to as the semiconductor portion 8, the first base portion B1 and the second base portion B2 may be collectively referred to as the base portion B, and the first wing portion F1 and the second wing portion F2 may be collectively referred to as the wing portion F. Furthermore, the first opening portion K1 and the second opening portion K2 of the mask pattern 6 may be collectively referred to as the opening portion K, and the first seed region S1 and the second seed region S2 may be collectively referred to as the seed region S. The semiconductor portion 8 may be a semiconductor layer 8, and the mask portion 5 may be a mask layer 5.

[0021] Hereinafter, the orientation from the main substrate 1 toward the semiconductor portion 8 may be referred to as "upward," and viewing an object from a line of sight parallel to the normal to the semiconductor substrate 10 (including perspective) is referred to as "top view." The seed region S and the growth inhibition area DA may be aligned in a first direction (a direction perpendicular to the thickness direction of the substrate, the X direction) when viewed from top. The positions (heights) of the seed region S (e.g., the surface of the base layer 4) and the growth inhibition area DA (e.g., the surface of the mask portion 5) in the thickness direction (vertical direction, Z direction) of the semiconductor substrate 10 may differ, be the same, or be substantially the same.

[0022] The first direction (X direction) can be the a-axis direction (<11-20> direction) of the semiconductor portion 8 (nitride semiconductor crystal such as GaN). The second direction (Y direction) perpendicular to the first direction can be the m-axis direction (<1-100> direction) of the semiconductor portion 8. The thickness direction of the semiconductor substrate 10 can be the c-axis direction (<1-100> direction) of the semiconductor portion 8. <0001> direction).

[0023] The semiconductor substrate 10 in this embodiment includes an initial growth layer 8s grown from a seed crystal region S, and a first nitride semiconductor layer NS1 grown from the initial growth layer 8s. The first nitride semiconductor layer NS1 can be a layer that highly suppresses vertical growth and grows laterally. In this case, lateral crystal growth can proceed faster than vertical crystal growth. Furthermore, the wing portion F in the semiconductor substrate 10 includes an Al-based semiconductor layer ALS formed on the first nitride semiconductor layer NS1, and a second nitride semiconductor layer NS2 formed on the Al-based semiconductor layer ALS. This improves the surface quality of the wing portion F. Furthermore, the thickness of the semiconductor portion 8 can be reduced. Furthermore, the second nitride semiconductor layer NS2 has the surface quality required, for example, for growing a device layer. The following is a brief description of the insights of this disclosure.

[0024] The surface quality of a nitride semiconductor layer (ELO layer) formed by the ELO method affects the growth characteristics and performance of semiconductor layers grown (e.g., epitaxially) on the ELO layer. Generally speaking, an ELO layer is formed using growth conditions that allow for both lateral and, to a certain extent, vertical growth. In this case, the surface quality of the ELO layer is improved by the vertical growth. For ease of explanation, this growth condition is referred to as "simultaneous vertical and horizontal growth conditions." The vertical direction refers to the thickness direction of the ELO layer.

[0025] The ELO layer formed using conventional simultaneous vertical and horizontal growth conditions has a relatively large thickness. Consequently, for example, defects (such as slip defects) may occur in the ELO layer due to a significant difference in stress (internal stress) between the ELO layer and the growth substrate. To reduce the thickness of the ELO layer, changing the growth conditions in the ELO method from simultaneous vertical and horizontal growth to one that suppresses vertical growth allows for a relatively thinner ELO layer. On the other hand, bumps (protrusions, projections) may sometimes form on the surface of the ELO layer, making it difficult to form device layers on the surface of the ELO layer. Therefore, the possibility of bumps is typically reduced by using simultaneous vertical and horizontal growth conditions in the ELO method.

[0026] Under these circumstances, the present inventors have gained the following insight. Specifically, to further suppress vertical growth (bringing it close to zero), they attempted to more rapidly alter the growth conditions of the ELO layer. The results revealed that, contrary to the expectation that crystal growth itself would cease (both vertical and lateral growth would cease), there exist conditions where the ELO layer can grow horizontally while highly suppressing vertical growth (highly flat growth conditions).

[0027] The highly flat growth conditions disclosed herein can reduce surface protrusions on the first nitride semiconductor layer NS1 formed by the ELO method, and allow the first nitride semiconductor layer NS1 to grow substantially only in the lateral direction. For example, the ratio of vertical growth to lateral growth in the first nitride semiconductor layer NS1 formed by the ELO method under highly flat growth conditions can be less than 0.2, less than 0.1, or less than 0.05.

[0028] The thickness direction of the first nitride semiconductor layer NS1 can be the c-axis direction of the nitride semiconductor. Under the highly flat growth conditions disclosed herein, for example, it is believed that on the top surface N1T of the first nitride semiconductor layer NS1, evaporation reactions are dominant before the attached raw material (particles derived therefrom) are extracted into the first nitride semiconductor layer NS1. On the other hand, it is believed that on the lateral growth end faces (e.g., the a-plane and r-plane of the nitride semiconductor), crystal growth reactions are occurring from the attached raw material (particles derived therefrom). Alternatively, there is a method for increasing the lateral growth rate of the ELO layer by using dimethylhydrazine as a nitrogen source (a Group V source). However, under the highly flat growth conditions disclosed herein, a general source other than dimethylhydrazine (e.g., NH3 gas) can be used as the nitrogen source.

[0029] Next, to form device layers (functional layers) on the thin and wide first nitride semiconductor layer NS1 formed using the highly flat growth conditions disclosed herein, an attempt was made to grow a semiconductor layer (e.g., GaN) on the first nitride semiconductor layer NS1. This resulted in preferential growth of the semiconductor layer at the end portion of the first nitride semiconductor layer NS1 (the portion away from the initial growth layer 8s), resulting in uneven formation of the semiconductor layer over the first nitride semiconductor layer NS1. Further investigation of this phenomenon revealed that the surface (top surface N1T) of the first nitride semiconductor layer NS1 formed using the highly flat growth conditions disclosed herein exhibits a nonuniformly high concentration of silicon and exhibits fine surface roughness on a microscopic scale.

[0030] Here, the semiconductor substrate 10 may include, for example, a silicon-based mask that functions as the growth inhibition region DA. In other words, the mask portion 5 may be a silicon-based mask. A silicon-based mask is a mask containing silicon, and may also be referred to as a silicon-containing mask. A silicon-based mask may be any mask containing silicon used in the ELO method. For example, a silicon-based mask may have the highest silicon content (in moles) among elements other than the negative element in its composition (elements that donate electrons to the negative element in a chemical bond). Specific examples of silicon-based masks will be described later.

[0031] The concentrated silicon on the top surface N1T of the first nitride semiconductor layer NS1 is believed to originate from the mask portion 5 or components within the film formation apparatus (e.g., an MOCVD apparatus). Furthermore, various analysis results suggest that a microstructure with tilted crystal planes is formed on the top surface N1T of the first nitride semiconductor layer NS1. The formation of silicon concentration and microstructures on the top surface N1T of the first nitride semiconductor layer NS1 effectively contributes to the highly suppressed vertical growth of the first nitride semiconductor layer NS1 under the highly flat growth conditions disclosed herein. Furthermore, it can be said that the first nitride semiconductor layer NS1 is in a state that makes it difficult to grow other nitride semiconductors (e.g., GaN) directly on the top surface N1T.

[0032] Therefore, in one embodiment of the present disclosure, the semiconductor substrate 10 includes an Al-based semiconductor layer ALS (e.g., AlGaN) located on the surface of the first nitride semiconductor layer NS1. Even on the top surface N1T of the first nitride semiconductor layer NS1 having the aforementioned surface condition, the Al-based semiconductor layer ALS can be easily and uniformly grown due to the action of aluminum. The Al-based semiconductor layer ALS can cover the side surfaces of the first nitride semiconductor layer NS1.

[0033] Furthermore, the semiconductor substrate 10 includes a second nitride semiconductor layer NS2 located on the surface of the Al-based semiconductor layer ALS. By interposing the Al-based semiconductor layer ALS as an intermediate layer, the second nitride semiconductor layer NS2 can be formed with reduced likelihood of surface ridges. Consequently, the surface quality of the second nitride semiconductor layer NS2 can be improved. The second nitride semiconductor layer NS2 can have the surface quality desired for forming a functional layer 9 (described later) having functions corresponding to the device structure. The functional layer 9 includes, for example, an active layer. Furthermore, in the semiconductor substrate 10, the thickness of the first nitride semiconductor layer NS1 can be made relatively thin, thereby improving the surface quality of the second nitride semiconductor layer NS2. Consequently, the thickness of the wing portion F can be adjusted, and the wing portion F can be formed with higher surface quality. For example, the semiconductor substrate 10 can have a wing portion F with uniform surface quality.

[0034] FIG3 is an enlarged microscopic image showing a portion of a cross section of a semiconductor substrate according to an embodiment of the present disclosure. FIG4 is an enlarged view of region IV shown in FIG3 . FIG5 is an enlarged microscopic image showing a key portion of a cross section of a semiconductor substrate according to an embodiment of the present disclosure. FIG3-5 show a cross section of a portion of the first wing F1 in the first semiconductor portion 8A. FIG3 also shows a state where a functional layer 9 is formed above the second nitride semiconductor layer NS2.

[0035] As shown in Figures 3-5 , the interface between the first nitride semiconductor layer NS1 and the Al-based semiconductor layer ALS has a concave-convex structure, rather than a flat surface. This corresponds to the surface (top surface N1T) of the first nitride semiconductor layer NS1 formed under the highly flat growth conditions disclosed herein. The top surface N1T of the first nitride semiconductor layer NS1 has a fine concave-convex structure.

[0036] The surface layer (portion of the upper surface N1T) of the first nitride semiconductor layer NS1 may have, for example, a plurality of recessed portions RP (also referred to as upper surface roughness) having a depth D1 of 20 nm to 80 nm. The roughness of the upper surface N1T of the first nitride semiconductor layer NS1 (also referred to as the upper surface roughness of the first nitride semiconductor layer NS1) may be 20 nm to 80 nm. The average roughness of the upper surface N1T of the first nitride semiconductor layer NS1 may be 45 nm to 55 nm. During the formation of the first nitride semiconductor layer NS1 using the highly flat growth conditions disclosed herein, longitudinal layering may be generated by, for example, etching a flat surface or forming a pyramidal shape with tilted crystal planes, thereby potentially forming an upper surface N1T having a finely textured concave-convex structure.

[0037] For each portion of the semiconductor portion 8, the silicon concentration can be measured (analyzed) in the depth direction using, for example, TOF-SIMS (Time of Flight-Secondary Ion Mass Spectrometry). The top surface N1T of the first nitride semiconductor layer NS1 has a significantly higher silicon concentration than the surface of the ELO layer formed using the previous simultaneous vertical and horizontal growth conditions. The silicon concentration distribution in the first direction (X direction) on the top surface N1T of the first nitride semiconductor layer NS1 of the semiconductor substrate 10 may be non-uniform. Here, the period from the start of film formation of the first nitride semiconductor layer NS1 according to the high-flat growth conditions disclosed herein to a certain extent is referred to as the initial growth period, and the period to the point at which film formation is completed is referred to as the final growth period. The portion of the top surface N1T of the first nitride semiconductor layer NS1 corresponding to the initial growth stage (near the initial growth layer 8s) can have a relatively high silicon concentration, while the portion of the top surface N1T corresponding to the final growth stage (the end away from the initial growth layer 8s) can also have a relatively low silicon concentration. This suggests that the film formation time used to grow the wide first nitride semiconductor layer NS1 under the highly flat growth conditions disclosed herein affects the uneven silicon concentration distribution on the surface (top surface N1T) of the first nitride semiconductor layer NS1.

[0038] The silicon concentration distribution in the top surface N1T of the first nitride semiconductor layer NS1 can be, for example, as follows. Specifically, in the first direction, for example, the ratio of the silicon concentration at the end portion (corresponding to the edge region JA, described later) of the top surface N1T of the first nitride semiconductor layer NS1 to the silicon concentration at the surface of the micro-growth portion SGP (see FIG. 6 ), described later, located above the seed region S, can be 0.60 to 0.85, or 0.70 to 0.75. For example, when the micro-growth portion SGP is absent, the ratio of the silicon concentration at the end portion of the top surface N1T of the first nitride semiconductor layer NS1 to the silicon concentration at the surface of the initial growth layer 8s (top surface 8sT, described later) can be 0.60 to 0.85, or 0.70 to 0.75. In the first semiconductor portion 8A, the silicon concentration of the first base portion B1 located above the first seed region S1 is set to 1. The silicon concentration at the front end surface of the first nitride semiconductor layer NS1 can be 0.60-0.85, or 0.70-0.75. Furthermore, in the first direction, for example, the ratio of the silicon concentration at the end side (corresponding to the edge region JA described later) to the silicon concentration of the portion of the surface of the first nitride semiconductor layer NS1 near the initial growth layer 8s (corresponding to the connection region CA described later) can be 0.60-0.85, or 0.70-0.75. When the silicon concentration at the end surface of the first nitride semiconductor layer NS1 on the first base portion B1 side is set to 1, the silicon concentration at the front end surface of the first nitride semiconductor layer NS1 can be 0.6-0.85, or 0.7-0.75. The front end portion of the first nitride semiconductor layer NS1 is a side surface portion of the first nitride semiconductor layer NS1 in the first direction (X direction).

[0039] On the other hand, the silicon concentration on the surface of the second nitride semiconductor layer NS2 can be relatively low. This is because the exposed area of the mask portion 5 is relatively small during the formation of the second nitride semiconductor layer NS2. Furthermore, the upper surface N2T of the second nitride semiconductor layer NS2 is formed by vertical growth. Vertical growth can be, for example, epitaxial growth. In this embodiment, the silicon concentration on the upper surface N2T of the second nitride semiconductor layer NS2 of the semiconductor substrate 10 can be lower than the silicon concentration on the upper surface N1T of the first nitride semiconductor layer NS1. In this embodiment, the silicon concentration on the upper surface N1T of the first nitride semiconductor layer NS1 of the semiconductor substrate 10 can be at least five times the silicon concentration on the upper surface N2T of the second nitride semiconductor layer NS2. The silicon concentration level on the upper surface N1T can vary depending on various conditions. Therefore, it is difficult to specify a specific numerical range, but the silicon concentration of the upper surface N1T can be, for example, 5 to 2000 times the silicon concentration of the upper surface N2T, or 5 to 1000 times. The silicon concentrations of the upper surface N1T and upper surface N2T can be calculated by, for example, dividing the wing F into five equal parts along the X-axis, measuring (analyzing) the silicon concentration at four points between the two endpoints using SIMS in the depth direction, and calculating the average value of the four points. For the upper surface N2T, the silicon concentration can be calculated using, for example, the peak signal intensity near the surface (e.g., a region approximately 1 nm deep or less) in the measurement profile using SIMS.

[0040] The top surface N1T has a higher silicon concentration than the interior of the first nitride semiconductor layer NS1 (the portion that has grown laterally from the initial growth layer 8s). The top surface N1T may include a silicon-concentrated layer formed in a film-like manner on the surface of the fine concavo-convex structure. The uneven concentration of silicon on the top surface N1T may occur when silicon is extracted into the nitride semiconductor crystals of the first nitride semiconductor layer NS1. The silicon-concentrated layer may be formed from nitride semiconductor crystals containing a relatively high concentration of silicon. The silicon-concentrated layer may be positioned on the top surface N1T to cover the entire surface of the fine concavo-convex structure, or it may have fine pores.

[0041] The Al-based semiconductor layer ALS includes a lower layer (first layer) FL that fills the upper surface roughness (fine uneven structure, multiple recesses) of the first nitride semiconductor layer NS1, and an upper layer (second layer) SL that is flatter than the lower layer FL. The aluminum concentration of the lower layer FL can be lower than that of the upper layer SL. The aluminum concentrations of the lower layer FL and the upper layer SL referred to herein may refer to the aluminum concentrations in the main portions of the lower layer FL and the upper layer SL, respectively, excluding the boundary portion (the dark gray portion shown in FIG5 ) described below. Filling the upper surface roughness indicates that the lower layer FL is located inside the recesses RP that form the upper surface roughness.

[0042] As shown in the examples of Figures 3 to 5 , the Al-based semiconductor layer ALS may include a first boundary portion BP1 located at the boundary between the lower layer FL and the upper layer SL, and a second boundary portion BP2 located at the boundary between the upper layer SL and the second nitride semiconductor layer NS2. The upper layer SL may include a main portion MP located between the first boundary portion BP1 and the second boundary portion BP2 in the height (thickness) direction. The main portion MP may be thicker than the first boundary portion BP1 and may also be thicker than the second boundary portion BP2.

[0043] The Al-based semiconductor layer ALS can be, for example, a layer containing AlGaN (AlGaN layer) or a layer containing AlN (AlN layer). In the example shown in FIG5 , when the Al-based semiconductor layer ALS is an AlGaN layer, the aluminum concentration of each portion of the Al-based semiconductor layer ALS is analyzed using, for example, EDS (Energy Dispersive X-ray Spectroscopy), as follows. Specifically, each portion of the Al-based semiconductor layer ALS can satisfy at least one of the following relationships regarding aluminum concentration. The aluminum concentration of the first boundary portion BP1 can be higher than that of the lower layer FL. The aluminum concentration of the first boundary portion BP1 can be higher than that of the main portion MP. The aluminum concentration of the first boundary portion BP1 can be higher than that of the second boundary portion BP2. Furthermore, the aluminum concentration of the second boundary portion BP2 can be higher than that of the main portion MP. The aluminum concentration of the top surface LST of the Al-based semiconductor layer ALS can be higher than that of the main portion MP. The aluminum concentration of the top surface LST can be higher than that of the second boundary portion BP2.

[0044] The lower layer FL fills the fine unevenness of the upper surface N1T of the first nitride semiconductor layer NS1, while the upper layer SL forms a flat upper surface LST. The following model can be considered as a model for the formation process of this Al-based semiconductor layer ALS. Specifically, compared to the stage where the lower layer FL grows on the upper surface N1T with fine unevenness, it is believed that Al extraction from the semiconductor crystal is easier when the lower layer FL forms a flat surface and the upper layer SL grows on the lower layer FL. Specifically, during the initial stages of the Al-based semiconductor layer ALS formation process, Al forms a growth starting point on the upper surface N1T. Later, during the growth of the lower layer FL, Al extraction becomes relatively difficult. Once the surface becomes flat (up to the first boundary BP1), the upper layer SL grows to contain Al with a composition close to that of the raw materials. The second boundary BP2 may also be generated during the formation of the second nitride semiconductor layer NS2 (due to heat and other influences). By flattening the surface (top surface LST) of the Al-based semiconductor layer ALS, the second nitride semiconductor layer NS2 can be easily formed on the Al-based semiconductor layer ALS, and the surface quality of the top surface N2T of the second nitride semiconductor layer NS2 can be improved. However, the above model (mechanism) is not limiting.

[0045] The roughness (top surface roughness) of the upper surface LST of the aluminum-based semiconductor layer ALS can be smaller than the top surface roughness of the first nitride semiconductor layer NS1. This facilitates improving the surface quality of the upper surface N2T of the second nitride semiconductor layer NS2. The roughness (top surface roughness) of the upper surface LST of the aluminum-based semiconductor layer ALS can be less than 20 nm, less than 5 nm, or even less than 1 nm.

[0046] The upper surface roughness of the first nitride semiconductor layer NS1, the second nitride semiconductor layer NS2, and the aluminum-based semiconductor layer ALS can be determined, for example, by measurement using an atomic force microscope (AFM) or visually confirmed from images taken with a scanning electron microscope (SEM) or a transmission electron microscope (TEM). The upper surface roughness of the second nitride semiconductor layer NS2 can be, for example, the maximum height roughness Rz measured using an AFM. When visually confirming the upper surface roughness of the first nitride semiconductor layer NS1 from a TEM image, the average of the depths D1 of a plurality of recesses RP (e.g., any ten recesses in the TEM image) can be used as the upper surface roughness. Here, if no concave portions are observed on the upper surface LST of the aluminum-based semiconductor layer ALS, or if the average depth of the observed concave portions is less than the upper surface roughness of the upper surface NST of the first nitride semiconductor layer NS1, the roughness (upper surface roughness) of the upper surface LST of the aluminum-based semiconductor layer ALS can be made smaller than the upper surface roughness of the first nitride semiconductor layer NS1. The upper surface roughness of the second nitride semiconductor layer NS2 can be, for example, less than 5 nm or less than 1 nm, or can be such that only atomic-level roughness (around 1 nm) is observed, with substantially no roughness.

[0047] FIG6 is an enlarged cross-sectional view showing a portion of a semiconductor substrate according to an embodiment of the present disclosure. In FIG6 , for ease of illustration, the portion of the upper surface N1T of the first nitride semiconductor layer NS1 is marked with dark gray hatching to illustrate the thickness.

[0048] As shown in FIG6 (also refer to FIG1 ), the first semiconductor portion 8A includes a first base portion B1 located above the first seed region S1. The top surface N1T of the first nitride semiconductor layer NS1 includes a connection region CA connected to the first base portion B1 and an edge region JA spaced apart from the first base portion B1 in the first direction (X direction). The silicon concentration in the connection region CA may be higher than that in the edge region JA. Furthermore, in the first semiconductor portion 8A, the top surface roughness of the connection region CA may be greater than the top surface roughness of the edge region JA. The first semiconductor portion 8A may include a micro-growth portion SGP, a portion of the first base portion B1 that has grown slightly from the top surface 8sT of the initial growth layer 8s. The first nitride semiconductor layer NS1 is a portion that has grown laterally from the side surface 8sS of the initial growth layer 8s substantially only above the growth inhibition region DA under the highly flat growth conditions disclosed herein. The first nitride semiconductor layer NS1 is in contact with the side surface 8sS of the initial growth layer 8s. Furthermore, the first nitride semiconductor layer NS1 has an edge E1 located above the mask portion 5 (growth inhibition area DA). The edge region JA is a region of the top surface N1T near the edge E1. For example, the edge region JA may be a region corresponding to the portion including the edge E1 when the top surface N1T is divided into five equal parts along the a-axis (X direction) in the cross-section shown in FIG6 .

[0049] The top surface N1T may include an intermediate region MA located between the connection region CA and the edge region JA. In the first semiconductor portion 8A, the silicon concentration in the intermediate region MA may be lower than that in the connection region CA and higher than that in the edge region JA. In the first semiconductor portion 8A, the upper surface roughness in the intermediate region MA may be greater than that in the connection region CA and less than that in the edge region JA.

[0050] In the semiconductor substrate 10 according to one embodiment of the present disclosure, for example, the ratio of the length W1 of the first nitride semiconductor layer NS1 in the first direction (X direction) to the thickness D10 can be 5.0 or greater. The ratio of the length W1 to the thickness D10 can be 6.0 or greater, or even 7.0 or greater. The thickness D10 of the first nitride semiconductor layer NS1 can be the distance in the thickness direction between the lowest point of the edge E1 of the first nitride semiconductor layer NS1 and the upper surface N1T (edge region JA). The thickness D10 can be the same as, or substantially the same as, the height of the portion of the initial growth layer 8s protruding from the mask portion 5. The height of the portion of the initial growth layer 8s protruding from the mask portion 5 can be the distance between the surface of the mask portion 5 and the upper surface 8sT of the initial growth layer 8s.

[0051] In the thickness direction (Z direction) of the semiconductor substrate 10, the thickness of each of the first nitride semiconductor layer NS1 and the second nitride semiconductor layer NS2 can be greater than that of the Al-based semiconductor layer ALS. The thickness D10 of the first nitride semiconductor layer NS1 can be, for example, 300 nm or greater, or 500 nm or greater. The upper limit of the thickness D10 of the first nitride semiconductor layer NS1 is not particularly limited, but the thickness D10 can be, for example, 5000 nm or less, 3000 nm or less, or 2000 nm or less. The thickness D2 of the second nitride semiconductor layer NS2 can be, for example, 10 μm or less, or 50 nm or more and 5 μm or less. The thickness D3 of the Al-based semiconductor layer ALS can be, for example, 60 nm or greater, or 200 nm or greater. If the thickness D3 of the Al-based semiconductor layer ALS is too small, the flatness of the top surface LST of the Al-based semiconductor layer ALS may become insufficient. The upper limit of the thickness D3 of the Al-based semiconductor layer ALS is not particularly limited, but the thickness D3 may be, for example, less than 1000 nm, less than 800 nm, or less than 600 nm.

[0052] The thickness D11 of the micro-growth portion SGP may be, for example, greater than 1 nm, or may be approximately 1 to 100 nm. The thickness D11 may be, for example, less than 3000 nm.

[0053] In the example shown in FIG. 1 and other figures, the top surface N1T of the first nitride semiconductor layer NS1 has a flat shape (a shape with the same or substantially the same height in the width direction), but this is not limiting. In the first nitride semiconductor layer NS1, as it grows substantially laterally under the highly flat growth conditions disclosed herein, the top surface N1T can be positioned higher in its macroscopic shape. For example, in the first nitride semiconductor layer NS1, the middle region MA and the edge region JA can be located higher than the connection region CA, and the edge region JA can also be located higher than the middle region MA (not shown). Even in the case of a tilted or curved top surface N1T, by forming the Al-based semiconductor layer ALS and the second nitride semiconductor layer NS2 above the first nitride semiconductor layer NS1, the top surface N2T of the second nitride semiconductor layer NS2 can be easily flattened. By forming the lower layer FL and the upper layer SL of the Al-based semiconductor layer ALS on the curved upper surface N1T, the upper surface LST of the Al-based semiconductor layer ALS can be configured to be flatter than the upper surface N1T. Therefore, the upper surface N2T of the second nitride semiconductor layer NS2 can have a flat shape.

[0054] The Al-based semiconductor layer ALS may, for example, contain 1.5 atomic % or more of aluminum. The aluminum content in the Al-based semiconductor layer ALS is expressed as a percentage, using, for example, the ratio of the atomic weight of aluminum as analyzed by EDS to the total atomic weight of Group III atoms (elements) in the Al-based semiconductor layer ALS. A high aluminum content in the Al-based semiconductor layer ALS facilitates growth of the Al-based semiconductor layer ALS onto the upper surface N1T of the first nitride semiconductor layer NS1. The Al-based semiconductor layer ALS may contain more than 1.5 atomic % of aluminum, or may contain 2.0 atomic % or more of aluminum.

[0055] Nitride semiconductors containing aluminum have lower requirements for surface quality during growth due to the effects of aluminum. Therefore, the edge E1 of the first nitride semiconductor layer NS1 of the semiconductor substrate 10 can be covered by the Al-based semiconductor layer ALS. Furthermore, the semiconductor substrate 10 can have a byproduct portion BP in contact with the growth inhibition area DA (here, the surface of the mask portion 5). A byproduct BPP can be formed as a byproduct during the growth of the Al-based semiconductor layer ALS. The byproduct portion BPP is located on the surface of the mask portion 5 where the first nitride semiconductor layer NS1 is not formed and comprises a nitride semiconductor containing aluminum. The byproduct BPP can comprise AlGaN or AlN. The byproduct portion BPP can have lower crystallinity than the Al-based semiconductor layer ALS and can be, for example, amorphous. The byproduct portion BPP can also be referred to as the third semiconductor portion.

[0056] The by-product portion BPP can function as a cover for the mask portion 5, thereby suppressing unintended Si doping (raw material transfer from the mask portion 5) of the second nitride semiconductor layer NS2 formed on the Al-based semiconductor layer ALS and the semiconductor crystal formed above the second nitride semiconductor layer NS2.

[0057] The second nitride semiconductor layer NS2 may also be formed on the surface of the Al-based semiconductor layer ALS, covering the edge E1 of the first nitride semiconductor layer NS1, and may also have an edge E2 located above the mask portion 5 (growth inhibition area DA). The second nitride semiconductor layer NS2 may not contain aluminum, or may contain aluminum, and the aluminum content may be lower than that of the Al-based semiconductor layer ALS. The second nitride semiconductor layer NS2 may contain aluminum diffused from the Al-based semiconductor layer ALS by being connected to the Al-based semiconductor layer ALS. In the second nitride semiconductor layer NS2, the aluminum concentration may decrease as it approaches the top surface N2T, compared to a portion near the top surface LST of the Al-based semiconductor layer ALS.

[0058] In the semiconductor substrate 10, the threading dislocation density of the upper surface N2T of the first wing portion F1 can be less than 1 / 5 of the threading dislocation density of the first base portion B1. For example, the threading dislocation density of the first wing portion F1 can be less than 1 / 10 of that of the first base portion B1, which is the dislocation inheriting portion. The threading dislocation density of the first wing portion F1, which is the low defect portion, can be set to less than 5×10 6 [pieces / cm 2], for example. Threading dislocations occur in the semiconductor portion 8 along its c-axis direction ( <0001> The through dislocation density can be determined, for example, by measuring the surface of each portion of the semiconductor portion 8 with CL (Cathode Luminescence) and counting the number of black dots in the CL measurement image.

[0059] Furthermore, for the semiconductor substrate 10, based on the CL measurement image, it is also possible to distinguish between regions formed by lateral growth (lateral growth regions) and regions formed by longitudinal growth (vertical growth regions). In the CL measurement image, the brightness of the lateral growth region and the vertical growth region may be different, allowing the boundary between them to be visually identified. It is confirmed that the first nitride semiconductor layer NS1 formed under the high-flat growth conditions disclosed herein is a lateral growth region, and that the second nitride semiconductor layer NS2, excluding the portion near the edge E2, at least the portion overlapping with the first nitride semiconductor layer NS1 when viewed from above, constitutes a vertical growth region. The portion of the second nitride semiconductor layer NS2 near the edge E2, in other words, the portion grown from the Al-based semiconductor layer ALS covering the edge E1 of the first nitride semiconductor layer NS1, can be a lateral growth region.

[0060] In one embodiment, the semiconductor substrate 10 includes a template substrate TS comprising a silicon wafer, a silicon carbide wafer, or a sapphire wafer. The first nitride semiconductor layer NS1 and the second nitride semiconductor layer NS2 may be layers comprising GaN (GaN layers). The mask portion 5 may comprise a silicon-based mask, for example, a silicon oxide film or a silicon nitride film. Materials for the mask portion 5 include silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxide (SiO2), silicon oxynitride (SiON), and the like. The mask portion 5 may be a single layer of these materials or a multilayer film (laminated film) combining these materials.

[0061] In the examples shown in Figures 1 and 6 , the wing portion F is in close contact with the mask portion 5 . However, this is not limiting. In one embodiment, the semiconductor substrate 10 may also have a gap between the mask portion 5 (growth inhibition area DA) and the first wing portion F1 . This gap can be created, for example, by spontaneously peeling off at least a portion of the wing portion F from the mask portion 5 during the formation of the semiconductor portion 8 when the temperature is lowered from the growth temperature (during cooling). Alternatively, the gap can be formed by positioning the first seed region S1 higher than the growth inhibition area DA (see the embodiments described below).

[0062] As described above, the semiconductor substrate 10 in one embodiment of the present disclosure includes a first semiconductor portion 8A including a first wing portion F1. The first wing portion F1 comprises a wide and relatively thin first nitride semiconductor layer NS1 formed using the highly flat growth conditions of the present disclosure, a relatively thin Al-based semiconductor layer ALS located on the first nitride semiconductor layer NS1, and a relatively thin second nitride semiconductor layer NS2 located on the Al-based semiconductor layer ALS. This improves the surface quality of the second nitride semiconductor layer NS2 even when the total thickness of the first semiconductor portion 8A is reduced. Consequently, a first wing portion F1 with high surface quality and a relatively thin thickness (thickness adjustment) can be achieved. In the semiconductor substrate 10, for example, when the width WF of the first wing portion F1 is approximately 25 μm, the total thickness Dt of the semiconductor portion 8 can be set to 4 μm or less, or even 3 μm or less. Theoretically, the total thickness Dt can also be set to 1 μm or less. The lower limit of the total thickness Dt can be set to 0.5 μm, for example. The ratio of the width WF of the first wing portion F1 of the semiconductor substrate 10 to the width WB of the base portion B can be 5 or more and 100 or less. The ratio of the width WF of the first wing portion F1 of the semiconductor substrate 10 to the total thickness Dt (aspect ratio) can be 20 or more and 300 or less.

[0063] Furthermore, when a silicon-based mask is used for mask portion 5, semiconductor substrate 10 includes a second nitride semiconductor layer NS2 having a significantly lower silicon concentration than a semiconductor layer formed using conventional simultaneous vertical and horizontal growth conditions. This has significant practical significance in that the silicon concentration of second nitride semiconductor layer NS2 incorporated into a portion of a semiconductor device can be more easily controlled (e.g., by easily adjusting the concentration using the raw material mixture composition).

[0064] [Manufacturing of semiconductor substrates] FIG7 is a flow chart showing an example of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure. FIG8 is a flow chart showing an example of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure. FIG9 is a cross-sectional view showing an example of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure. FIG10 is a cross-sectional view showing an example of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure.

[0065] As shown in Figures 7 to 10, a method for manufacturing a semiconductor substrate 10 according to one embodiment of the present disclosure includes the following steps: Step (S10) of preparing a template substrate TS including a first seed region S1 and a growth inhibition region DA arranged in a first direction (X direction); Step (S20) of growing an initial growth layer 8s on the first seed region S1; Step (S30) of growing a first nitride semiconductor layer NS1 having an upper surface roughness from a side surface 8sS of the initial growth layer 8s toward above the growth inhibition region DA; and Step (S40) of growing an Al-based semiconductor layer ALS to fill the upper surface roughness of the first nitride semiconductor layer NS1. After Step (S20), Step (S30) can be performed by changing the growth conditions. For example, by changing the raw material ratio and increasing the film formation temperature, the highly flat growth conditions of the present disclosure described above can be achieved.

[0066] In the method for manufacturing the semiconductor substrate 10, in S30, the first nitride semiconductor layer NS1 can be grown so that the thickness of the portion located on the initial growth layer 8s (micro-growth portion SGP) is less than one-fifth the thickness of the portion contacting the side surface of the initial growth layer 8s. In S30, growth can be stopped before the first nitride semiconductor layer NS1 grown from the initial growth layer 8s on the first seed region S1 and the first nitride semiconductor layer NS1 grown from the initial growth layer 8s on the second seed region S2 meet each other, thereby forming a first gap Gf. In S40, when the first gap Gf is formed, a byproduct portion BPP can be formed on the surface of the mask portion 5 not covered by the first nitride semiconductor layer NS1, concurrently with the formation of the Al-based semiconductor layer ALS. The Al-based semiconductor layer ALS and the byproduct portion BPP can be connected (continuous) to each other. In the method for manufacturing the semiconductor substrate 10 according to one embodiment of the present disclosure, a second gap Gs is provided above the byproduct portion BPP.

[0067] After the above-mentioned S40, the semiconductor substrate taken out from the film forming device (the semiconductor substrate in the state after the above-mentioned S40) also falls into the category of the semiconductor substrate 10 in one embodiment of the present disclosure.

[0068] In the method for manufacturing the semiconductor substrate 10 according to one embodiment of the present disclosure, after the above-mentioned S40, a step (S50) of forming a second nitride semiconductor layer NS2 on the Al-based semiconductor layer ALS is further performed. The silicon concentration of the upper surface N1T of the first nitride semiconductor layer NS1 can be at least five times the silicon concentration of the upper surface N2T of the second nitride semiconductor layer NS2. The semiconductor substrate 10 can have a gap (third gap) G between the first semiconductor portion 8A and the second semiconductor portion 8C. The width of the gap G can be less than 10 μm, less than 4 μm, or less than 3 μm. The presence of the gap G in the semiconductor substrate 10 can reduce the internal stress of the semiconductor portion 8. This can reduce cracks and defects (dislocations) in the semiconductor portion 8. This effect is particularly effective when the main substrate 1 is a different substrate.

[0069] FIG11 is a block diagram of a semiconductor substrate manufacturing apparatus according to one embodiment of the present disclosure. As shown in FIG11 , the semiconductor substrate manufacturing apparatus 30 includes an apparatus M10 for performing step S10 of FIG7 , an apparatus M20 for performing step S20 of FIG7 , an apparatus M30 for performing step S30 of FIG7 , an apparatus M40 for performing step S40 of FIG7 , an apparatus M50 for performing step S50 of FIG8 , and a control device MC for controlling the apparatus M10, apparatus M20, apparatus M30, apparatus M40, and apparatus M50. The apparatus M10 may include a sputtering apparatus. If a template substrate TS is prepared in advance, the manufacturing apparatus 30 may not include the apparatus M10. The apparatus M20, apparatus M30, apparatus M40, and apparatus M50 may include, for example, an MOCVD (Metal-Organic Chemical Vapor Deposition) apparatus. The apparatus M20, the apparatus M30, the apparatus M40, and the apparatus M50 may be a single apparatus, or the steps S20, S30, S40, and S50 may be performed by a single apparatus. The manufacturing apparatus 30 may not include the apparatus M50.

[0070] [Semiconductor components] The semiconductor portion 8 in the semiconductor substrate 10 has a low-defect portion, namely a wing portion F. The wing portion F can be used to form a semiconductor device. Specific examples of semiconductor devices include light-emitting diodes (LED (Light Emitting Diode) chips, semiconductor laser chips, etc.), light-emitting elements with light-emitting diodes mounted thereon, and light-emitting modules with light-emitting elements packaged thereon. Semiconductor devices are not limited to light-emitting devices and may include, for example, photodiodes and transistors (including power transistors and high electron mobility transistors).

[0071] [Other embodiments] In the semiconductor substrate 10 according to one embodiment of the present disclosure, the first nitride semiconductor layers NS1 grown in opposite directions can be joined together in S30. However, if the first nitride semiconductor layer NS1 is formed thinner, there is a high possibility of cracking or the like occurring when the first nitride semiconductor layers NS1 are joined together.

[0072] In addition, in the semiconductor substrate 10 in one embodiment of the present disclosure, there are multiple island-shaped portions grown from each of the multiple seed regions S, so that the above-mentioned first gap Gf between adjacent island-shaped portions is relatively small. Whereby, in the above-mentioned S50, the second nitride semiconductor layer NS2 can be positioned across the top of the multiple island-shaped portions. In this case, there may be no gap G.

[0073] In the semiconductor substrate 10 according to one embodiment of the present disclosure, in the template substrate TS, the growth suppression region DA can be a modified region of the base layer 4 or the main substrate 1, and the first seed region S1 (seed region S) can be a non-modified region of the base layer 4 or the main substrate 1. By subjecting the base layer 4 or the main substrate 1 to a plasma treatment, for example, the surface of the base layer 4 or the main substrate 1 can be modified.

[0074] During plasma processing, for example, argon plasma is irradiated onto a predetermined area of the base layer 4 or the main substrate 1 to modify the surface of the irradiated area, thereby forming a growth inhibition area DA. By introducing not only argon gas but also oxygen, nitrogen, hydrogen, and other gases into the chamber, the plasma processing can use oxygen plasma, nitrogen plasma, hydrogen plasma, or mixed plasmas of these, in addition to argon plasma. Thus, the growth inhibition area DA can contain argon, oxygen, nitrogen, or other impurities.

[0075] [Example 1] Hereinafter, first, the template substrate TS before the semiconductor portion 8 is formed will be described, and then the semiconductor substrate 10 will be described.

[0076] (Template substrate) 12 is a cross-sectional view schematically showing the structure of the template substrate in Example 1. As shown in FIG12 , in Example 1, the template substrate TS includes a base substrate BS including a main substrate 1 and a base layer 4 , and a mask pattern 6 may be formed on the base substrate BS.

[0077] Figure 13 is a cross-sectional view showing an example of a base substrate configuration. The base substrate BS can include a main substrate 1 and a base layer 4 formed on the main substrate 1. Furthermore, the base substrate BS can include a metal layer (Al layer) between the main substrate 1 and the base layer 4. The Al layer and the AlN layer serving as the base layer 4 can be formed continuously by sputtering. The base substrate BS can be formed from a free-standing single crystal substrate (e.g., a wafer cut from a bulk crystal) such as GaN or SiC. In this case, a mask pattern 6 can also be disposed on the single crystal substrate.

[0078] As the main substrate 1, a silicon substrate, a silicon carbide substrate (4H-SiC, 6H-SiC substrate), a sapphire substrate, a nitride substrate (GaN, AlN substrate, etc.), a ScMgAlO substrate, etc. can be used. The surface orientation of the main substrate 1 can be, for example, the (111) surface of a silicon substrate, or the 6H-SiC (0001) or 4H-SiC (0001) surface of a SiC substrate. The main substrate 1 can be 3C-SiC. These are examples, and the main substrate 1 only needs to have a material and a surface orientation that meet the following two conditions, and the specific material and surface orientation of the main substrate 1 are not necessarily limited. That is, first, the main substrate 1 only needs to form a seed region S and a growth inhibition region DA on the base substrate BS including the main substrate 1 to manufacture a template substrate TS. And, second, the main substrate 1 only needs to be able to grow the semiconductor portion 8 using the template substrate TS. By using an inexpensive substrate as the main substrate 1, the manufacturing costs of the template substrate TS and the semiconductor substrate 10 can be effectively reduced.

[0079] The base layer 4 can be made of a GaN-based semiconductor containing aluminum, aluminum nitride (AlN), silicon carbide (SiC), AlScN, graphene, or the like. An AlN layer, for example, can be formed using an MOCVD device to a thickness of approximately 10 nm to 5 μm. The base layer 4 can be formed at low temperatures (below 500°C), such as GaN, AlN, AlGaN, AlInN, AlGaInN, or Al. When a silicon substrate is used for the main substrate 1, it is desirable that the base layer 4 in contact with the silicon substrate contain substantially no gallium to prevent repeated melting. Substantially containing no element means that the element has not been intentionally added; however, its presence as an unintended impurity is permitted. The base layer 4 can be formed by sputtering. Using a sputtering device (such as PSD (pulse sputter deposition) or PLD (pulse laser deposition) for film formation can improve manufacturing efficiency. The base layer 4 can have at least one of the effects of improving the crystallinity of the initial growth layer 8s and relaxing the internal stress of the initial growth layer 8s. The base layer 4 can have a single layer structure, a multilayer structure, or a multilayer structure including a periodic structure.

[0080] The mask pattern 6 in the template substrate TS is formed on the base substrate BS using a material that inhibits the vertical growth (growth in the c-axis direction) of the nitride semiconductor. The template substrate TS may include a first seed region S1 that overlaps with the first opening K1 and a second seed region S2 that overlaps with the second opening K2 when viewed from above. The mask portion 5 may be, for example, a single layer film comprising any one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), or a laminated film comprising at least two of these.

[0081] The mask portion 5 is not necessarily limited to a silicon mask, as long as it can form the first nitride semiconductor layer NS1 from the initial growth layer 8s. Examples of materials for the mask portion 5 include diamond-like carbon, titanium nitride, molybdenum nitride, tungsten nitride, tantalum carbide, and further refractory metals (molybdenum, tungsten, platinum, etc.). The mask portion 5 can be a single layer composed of one of these materials, or a laminated film comprising at least two of these materials. In the semiconductor substrate 10 according to one embodiment of the present disclosure, the concentration of impurity components originating from the mask portion 5 on the upper surface N2T of the second nitride semiconductor layer NS2 can be lower than that on the upper surface N1T of the first nitride semiconductor layer NS1.

[0082] The thickness of the mask portion 5 may be, for example, 0.1 nm to 5 μm, or 10 nm to 1 μm. The width Wm (dimension in the X direction) of the mask portion 5 may be, for example, 10 μm to 20 μm, or 500 μm to 500 μm.

[0083] The opening K of the mask pattern 6 (the exposed portion of the seed region S) becomes the starting point for the growth of the initial growth layer 8s. The opening K can have a length shape with the first direction (X direction) as the width direction and the second direction (Y direction) as the length direction. The mask pattern 6 can arrange a plurality of openings K in the first direction (X direction). The opening K can have a tapered shape (a shape whose width narrows downward). The width Wk of the opening K (the dimension in the first direction) can be set to, for example, approximately 0.1 μm to 20 μm. The width Wk of the opening K can be smaller than the width Wm of the mask portion 5. The ratio of the thickness of the mask portion 5 to the width Wk of the opening K can be 3.0 or less. The smaller the width Wk of the opening K, the fewer through dislocations propagating from the opening K to the semiconductor portion 8 can be. In addition, the wing F (low defect portion) can be enlarged.

[0084] Figure 14 is a cross-sectional view showing an example of a template substrate configuration. As shown in Figure 14, the template substrate TS can be constructed by sequentially forming a base layer 4 (e.g., AlN) and a mask pattern 6 on a main substrate 1 (e.g., a silicon substrate). Alternatively, the template substrate TS can be constructed by sequentially forming a multilayer base layer 4 (including a buffer portion 2 and a seed portion 3) and a mask pattern 6 on the main substrate 1. The base layer 4 can be formed partially (e.g., in stripes) so as to overlap with the openings K of the mask pattern 6 when viewed from above. The template substrate TS can be constructed by forming a mask pattern 6 on a main substrate 1 (e.g., a SiC bulk crystal substrate or a GaN bulk crystal substrate). The template substrate TS is not limited to the example in which the mask pattern 6 is formed on the base substrate BS; a growth inhibition region DA and a seed region S can also be formed on the base substrate BS. For example, the growth inhibition region DA can be a surface-modified region of the main substrate 1 or the base layer 4, and the seed region S can also be the surface of the base layer 4. The seed region S may be located above the growth inhibition region DA.

[0085] The seed portion 3 is the starting point for the growth of the initial growth layer 8s and can function as a seed region S. For the seed portion 3, GaN-based semiconductors, aluminum nitride (AlN), silicon carbide (SiC), AlScN, graphene, etc. can be used. The seed portion 3 can be formed from a material containing at least Al and N. The material of the seed portion 3 can be a nitride semiconductor containing aluminum. The silicon carbide used for the seed portion 3 can be hexagonal 6H-SiC or 4H-SiC. As the seed portion 3, a GaN layer, AlN layer, AlGaN layer, AlInN layer, AlGaInN layer, etc. formed at a low temperature (below 500°C) can be used. The thickness of the seed portion 3 can be approximately 10 nm to 500 nm.

[0086] For example, when a silicon substrate is used for the main substrate 1 and a GaN-based semiconductor is used for the seed crystal portion 3, a buffer portion 2 comprising at least one of an AlN layer and a SiC (silicon carbide) layer may be provided to reduce the possibility of fusion between the main substrate and the seed crystal portion. The buffer portion 2 improves the crystallinity and flatness of the seed crystal portion 3. The thickness of the buffer portion 2 may be, for example, approximately 10 nm to 500 nm. The silicon carbide used for the buffer portion 2 may be hexagonal (6H-SiC, 4H-SiC) or cubic (4C-SiC). A sputtering apparatus may also be used to form at least one of the buffer portion 2 (e.g., aluminum nitride) and the seed crystal portion 3 (e.g., a GaN-based semiconductor).

[0087] The base layer 4 may include a strain relaxation layer. Examples of such a strain relaxation layer include an AlGaN superlattice structure and a grating structure in which the Al composition of AlGaN changes in stages. The strain relaxation layer can alleviate stress in the longitudinal direction of the semiconductor portion 8. At least one of the buffer portion 2 and the seed portion 3 may include a strain relaxation layer.

[0088] When using a main substrate 1 that does not fuse with the seed crystal portion 3, the buffer portion 2 may not be provided. Furthermore, when using a seed crystal portion 3 that is less reactive with the main substrate 1, the buffer portion 2 may not be provided.

[0089] As an example of a template substrate TS, a silicon substrate can be used for the main substrate 1, an AlN layer (approximately 30 nm to 300 nm, e.g., 150 nm) can be used for the buffer portion 2 of the base layer 4, a GaN-based graded layer can be used for the seed portion 3 of the base layer 4, and a silicon nitride film (SiN) can be used for the mask portion 5. The GaN-based graded layer can, for example, include a first Al0.6Ga0.4N layer (e.g., 300 nm) and a second GaN layer (e.g., 1-2 μm).

[0090] (Semiconductor Substrate) FIG15 is a cross-sectional view schematically illustrating the structure of the semiconductor substrate in Example 1. FIG16 is a top view schematically illustrating the structure of the semiconductor substrate in Example 1. As shown in FIG15 and FIG16 , the semiconductor substrate 10 in Example 1 includes a first semiconductor portion 8A and a second semiconductor portion 8C on a template substrate TS having a base substrate BS and a mask pattern 6. A gap G may be provided between the edge E2 of the first wing portion F1 in the first semiconductor portion 8A and the edge E3 of the second wing portion F2 in the second semiconductor portion 8C. Edges E2 and E3 may be inclined. The width of gap G may be the shortest distance between edges E2 and E3, and may be, for example, less than 10 μm, less than 5 μm, less than 3 μm, or less than 2 μm.

[0091] During the manufacturing process of the semiconductor substrate 10, a byproduct portion BPP may be formed as the Al-based semiconductor layer ALS is formed. The semiconductor substrate 10 may expose the mask portion 5 or the byproduct portion BPP in the gap G. The Al-based semiconductor layer ALS and the byproduct portion BPP may or may not be connected to each other. For example, the Al-based semiconductor layer ALS may not cover the entire edge E1 of the first nitride semiconductor layer NS1, and the byproduct portion BPP may be formed in a portion of the mask portion 5 where the first nitride semiconductor layer NS1 is not formed. Alternatively, a portion of the byproduct portion BPP may be covered by the second nitride semiconductor layer NS2.

[0092] The Al-based semiconductor layer ALS and the byproduct BPP may contain aluminum gallium nitride. In aluminum gallium nitride, the composition ratio of Al to Ga and Al may be, for example, 0.010 or greater, 0.015 or greater, or even 0.020 or greater. Furthermore, in aluminum gallium nitride, the composition ratio of Al to Ga and Al may be, for example, 0.20 or less. Aluminum gallium nitride may have a grating structure in which the Al composition changes stepwise along the thickness direction. The Al-based semiconductor layer ALS may contain aluminum gallium nitride as its main component. The byproduct BPP may have a smaller thickness than the Al-based semiconductor layer ALS. The surface roughness of the byproduct BPP may be greater than that of the Al-based semiconductor layer ALS.

[0093] FIG17 is a cross-sectional view showing an example of lateral growth of the first nitride semiconductor layer NS1. FIG18 is a cross-sectional view showing an example of growth of the Al-based semiconductor layer ALS and the second nitride semiconductor layer NS2. FIG17 and FIG18 show an example in which the mask pattern 6 has a rectangular opening K in cross-sectional view.

[0094] As shown in Figure 17, the initial growth layer 8s is first grown vertically, starting with the seed region S, which overlaps with the opening K. By controlling the growth conditions in the ELO method, the nitride semiconductor can be controlled to grow along the c-axis or the a-axis (X-direction).

[0095] As mentioned above, in general, lateral growth in the ELO method often uses growth conditions that allow for both lateral growth and, to a certain extent, vertical growth (simultaneous vertical and horizontal growth conditions). Examples of such conventional simultaneous vertical and horizontal growth conditions include a growth temperature of 1000-1200°C, a V / III ratio of 500-20,000, and a growth pressure of 50 kPa.

[0096] In the example shown in FIG17 , the growth conditions are significantly altered after the initial growth layer 8s is formed. Specifically, during the formation of the initial growth layer 8s, the growth temperature can be set to approximately 1030°C, and V / III can be set to approximately 2000. Growth of the initial growth layer 8s can be stopped when the initial growth layer 8s fills the opening K and the upper surface 8sT is higher than the growth inhibition area DA. The protrusion height Ds of the initial growth layer 8s (the height distance between the upper surface 8sT and the growth inhibition area DA) can be set to approximately 0.5 μm to 2 μm, for example.

[0097] After forming the initial growth layer 8s, the process transitions to high-flat growth conditions. For example, the growth temperature is increased, and the supply of raw materials (such as gallium and nitrogen sources) is reduced. This allows the first nitride semiconductor layer NS1 to essentially grow only laterally, using the initial growth layer 8s as the starting point. Under the high-flat growth conditions disclosed herein, the reduced supply of raw materials results in a relatively lower lateral growth rate compared to previous simultaneous vertical and horizontal growth conditions. During the growth of the first nitride semiconductor layer NS1, silicon concentration occurs on the upper surface N1T, forming a fine structure. On the upper surface N1T, the silicon concentration in the connection area CA can be higher than that in the edge area JA. Growth of the first nitride semiconductor layer NS1 can be stopped before the first nitride semiconductor layer NS1 grown from the initial growth layer 8s on the first seed region S1 and the first nitride semiconductor layer NS1 grown from the initial growth layer 8s on the second seed region S2 merge. In this way, the first gap Gf is formed. After the two first nitride semiconductor layers NS1 grown close to each other are joined, the joined portion can be removed by etching or the like to form the first gap Gf.

[0098] The width of the first nitride semiconductor layer NS1 is set to W1, and the thickness of the first nitride semiconductor layer NS1 is set to D10. Thickness D10 can be greater than the protruding height Ds of the initial growth layer 8s. Under the high-flat growth conditions disclosed herein, the first nitride semiconductor layer NS1 can undergo slight vertical growth. Furthermore, the upper surface N1T can be inclined or curved. On the upper surface N1T, the edge region JA (the portion near the edge E1) can be located higher than the connection region CA (the portion near the initial growth layer 8s). The ratio (W1 / D10) of the width W1 (dimension in the X direction) of the first nitride semiconductor layer NS1 to the thickness D10 can be set to, for example, 2.0 or greater. W1 / D10 can be set to 2.0 or greater, 4.0 or greater, 5.0 or greater, 7.0 or greater, or 10.0 or greater. Setting W1 / D10 to 2.0 or greater facilitates reducing internal stress in the first nitride semiconductor layer NS1. As a result, warping of the semiconductor substrate 10 can be reduced. The width W1 of the first nitride semiconductor layer NS1 can be, for example, 7.0 μm or greater, or 10.0 μm or greater, 20.0 μm or greater, or 40.0 μm or greater. The thickness D10 can be 10.0 μm or less, 5.0 μm or less, or 2.0 μm or less.

[0099] Next, as shown in FIG18 , an Al-based semiconductor layer ALS is grown to fill the roughened upper surface of the first nitride semiconductor layer NS1. By sequentially forming the first nitride semiconductor layer NS1 and the Al-based semiconductor layer ALS, the Al-based semiconductor layer ALS can be formed while the upper surface N1T is relatively active. For example, the growth temperature can be lowered from the high-flat growth conditions disclosed herein, and the raw material supply conditions can be varied. Specifically, for example, the supply of the raw material serving as the gallium source and the raw material serving as the nitrogen source can be maintained, while the raw material serving as the aluminum source can be supplied. The raw material supply amounts can be appropriately adjusted to match the composition of the Al-based semiconductor layer ALS, thereby forming the Al-based semiconductor layer ALS comprising a lower layer FL and an upper layer SL (see FIG4 and FIG5 ). The Al-based semiconductor layer ALS can be formed to cover the edge E1 of the first nitride semiconductor layer NS1. The portion of the Al-based semiconductor layer ALS covering the edge E1 does not need to have a multilayer structure like the lower layer FL and the upper layer SL. This is because the edge E1 does not have the fine structure of the upper surface N1T. Depending on the size of the first gap Gf, the Al-based semiconductor layer ALS may cover a portion of the edge E1, or the Al-based semiconductor layer ALS may not be in contact with the edge E1.

[0100] In the example shown in FIG18 , as the Al-based semiconductor layer ALS is formed, a byproduct portion BPP is formed in the second gap Gs. The byproduct portion BPP does not necessarily need to be connected to the Al-based semiconductor layer ALS. It is also possible that the byproduct portion BPP does not need to be formed in the second gap Gs. The byproduct portion BPP can be formed by adsorption and accumulation of the source material (atoms or molecules derived therefrom) that has reached the growth inhibition area DA (the surface of the mask portion 5).

[0101] Next, as shown in FIG18 , the second nitride semiconductor layer NS2 is formed on the Al-based semiconductor layer ALS. By sequentially forming the Al-based semiconductor layer ALS and the second nitride semiconductor layer NS2, the second nitride semiconductor layer NS2 can be formed while the upper surface LST is relatively active. For example, the supply of the raw material serving as the gallium source and the raw material serving as the nitrogen source is maintained, while the supply of the raw material serving as the aluminum source is stopped. The growth temperature can also be appropriately varied. In this manner, the second nitride semiconductor layer NS2 can be formed. In the example shown in FIG18 , the edge E2 of the second nitride semiconductor layer NS2 has an inclined surface (crystal plane). The edge E2 can be a crystal plane, for example, the (11-22) plane of the nitride semiconductor crystal or the (11-2β) plane (β is an integer). The edge E2 of the second nitride semiconductor layer NS2 can be non-inclined, in which case it can also be a plane along the c-axis of the nitride semiconductor crystal (for example, the (11-20) plane). During the growth of the second nitride semiconductor layer NS2, the raw materials may be further accumulated in the byproduct portion BPP.

[0102] In Example 1, the width Wm of the mask portion 5 is 50 μm, the width Wk of the opening K is 5 μm, the lateral width of the semiconductor portion 8 is 53 μm, the width WF of the wing portion F (dimension in the X direction) is 24 μm, the thickness D10 of the first nitride semiconductor layer NS1 is 2 μm, the thickness D3 of the Al-based semiconductor layer ALS is 150 nm, and the thickness D2 of the second nitride semiconductor layer NS2 is 0.5 μm (for reference symbols, see Figures 6 and 12). The aspect ratio of the semiconductor portion 8 is 53 μm / 2.65 μm = 20, and the aspect ratio of the wing portion F is 24 μm / 2.65 μm = 9.06, achieving a very high aspect ratio. Furthermore, the total thickness of the semiconductor portion 8 is approximately 4 μm or less, achieving a very high degree of thinning.

[0103] Figure 19 shows the results of SIMS analysis of the impurity concentrations in the template substrate TS, the first nitride semiconductor layer NS1, the Al-based semiconductor layer ALS, and the second nitride semiconductor layer NS2. SIMS analysis was performed using a CAMECA IMS-6f, with the primary ion species set to Cs+, the primary acceleration voltage set to 15.0 kV, and the detection area set to 8 μm. In Figure 19, the left vertical axis represents the concentrations of H (hydrogen), C (carbon), O (oxygen), and Si (silicon), respectively, while the right vertical axis represents the secondary ion intensities of Ga (gallium) and Al (aluminum). The horizontal axis represents the depth from the reference point. In Figure 19, H is represented by a solid line, C by a dashed line, O by a dotted line, Si by a thick line, Ga by a two-dot chain line, and Al by a thicker single-dot chain line. In Figure 19, the vertical dashed lines indicate the areas corresponding to the interfaces between the template substrate TS, the first nitride semiconductor layer NS1, the Al-based semiconductor layer ALS, and the second nitride semiconductor layer NS2. As shown in Figure 19, the silicon concentration in the upper surface N1T of the first nitride semiconductor layer NS1 (the interface between the first nitride semiconductor layer NS1 and the Al-based semiconductor layer ALS) is relatively higher than the silicon concentration in the upper surface N2T of the second nitride semiconductor layer NS2 (the left end of the figure). In Figure 19, higher concentrations are detected in the area corresponding to the upper surface N2T of the second nitride semiconductor layer NS2 (the left end of the figure), due to the influence of the atmosphere in the chamber where the surface is exposed. The values at depths of 0 to 15 nm are negligible. In reality, there is no significant difference in silicon concentration between the interior of the second nitride semiconductor layer NS2 and its upper surface N2T.

[0104] FIG20 also shows the results of EDS analysis of the abundance ratios of various elements (silicon, aluminum, etc.) superimposed on the TEM image of the first nitride semiconductor layer NS1 shown in FIG5 . TEM analysis was performed using a JEOL JEM-ARM200F, under the conditions of an accelerating voltage of 200 kV. EDS analysis was performed using a JEOL JED-2300T, under the conditions of an accelerating voltage of 200 kV, an irradiation current of approximately 80 pA, a time constant of approximately T4, and a dwell time of 20 s. In FIG20 , the vertical axis on the left represents the abundance ratios (%) of N (nitrogen), Ga (gallium), and Al (aluminum), respectively, at the point indicated by the bold right-pointing arrow in the center of the figure. The vertical axis on the right represents the abundance ratio (%) of Si (silicon), at the point indicated by the bold right-pointing arrow in the center of the figure. The horizontal axis represents the distance from the reference point. As shown in Figure 20, the silicon concentration on the top surface N1T of the first nitride semiconductor layer NS1 is approximately 0.5%, while other areas do not reach approximately 0.1%. This indicates that the silicon concentration on the top surface N1T of the first nitride semiconductor layer NS1 is higher than in other areas. Furthermore, in Figure 20, the aluminum content is approximately 8% in the first boundary portion BP1, approximately 6% in the second boundary portion BP2, approximately 2% in the lower layer FL, approximately 4% in the main portion MP, and approximately 7% in the top surface LST. Here, "approximately" means that the value includes a ±10% error.

[0105] Not limited to the examples shown in Figures 17 and 18 , the opening K may have a tapered shape (a shape whose width narrows toward the base substrate BS). The initial growth layer 8s may rise to the upper surface of the mask portion 5, and the width W2 of the upper surface 8sT may be greater than the width Wk of the opening K. The width W2 of the upper surface 8sT may correspond to the width WB of the first base portion B1 of the first semiconductor portion 8A in the semiconductor substrate 10 (see Figure 6 ).

[0106] In the examples shown in FIG. 17 and FIG. 18 , the back surface N1B of the first nitride semiconductor layer NS1 is in contact with the mask portion 5 , but the present invention is not limited thereto. The semiconductor substrate 10 may also have a gap between the back surface N1B and the mask portion 5 .

[0107] FIG21 is a top view showing another example of the structure of the semiconductor substrate 10 in Example 1. In FIG21 , various components are shaded for clarity. As shown in FIG21 , the first wing portion F1 can be divided into a plurality of portions PA arranged in a second direction (Y direction) perpendicular to the first direction (X direction). For example, a plurality of trenches TR extending in the X direction can be formed.

[0108] FIG22 is a cross-sectional view showing another example of the configuration of the semiconductor substrate 10 in Example 1. FIG23 is a top view showing another example of the configuration of the semiconductor substrate in Example 1. In FIG23 , various components are hatched in the top view for clarity. As shown in FIG22 and FIG23 , the semiconductor substrate 10 may include a functional layer (element layer) 9 including an active layer, located on the first semiconductor portion 8A. In the examples shown in FIG22 and FIG23 , the functional layer 9 is formed on the semiconductor portion 8A.

[0109] Functional layer 9 can be a single layer or a stack of layers. Functional layer 9 can include a p-type layer, an n-type layer, or an electron blocking layer. The active layer can have a quantum well structure. Functional layer 9 can have at least one of the following functions: serving as a component of a semiconductor element; protecting from external forces; protecting from static electricity; protecting from the intrusion of foreign matter such as water and oxygen; protecting from etching agents; an optical function; and a sensing function. Functional layer 9 can also be formed on the side surfaces (end faces) of the first semiconductor portion 8A and the second semiconductor portion 8C.

[0110] The second nitride semiconductor layer NS2 and the functional layer 9 can be made of GaN-based semiconductors and formed continuously using an MOCVD device. During the formation of the functional layer 9, due to its relatively thin thickness and the narrow width of the gap G, accumulation of raw materials on the byproduct portion BPP can be minimized. Furthermore, as described below, the semiconductor portion 8 and the functional layer 9 can be separated from the template substrate TS.

[0111] An anode EA and a cathode EC may be provided on the functional layer 9. The anode EA may be in contact with the p-type layer in the functional layer 9, and the cathode EC may be in contact with the n-type layer in the functional layer 9. In a plan view, at least a portion of the anode EA may be positioned so as to overlap with the first wing F1, or the entire anode EA may be positioned so as to overlap with the first wing F1. The first semiconductor portion 8A may include a third wing F3 located opposite the first wing F1 in the X direction across the first base B1. Similar to the first wing F1, the third wing F3 includes a first nitride semiconductor layer NS1, an Al-based semiconductor layer ALS, and a second nitride semiconductor layer NS2. The cathode EC may be in contact with the upper surface N2T of the second nitride semiconductor layer NS2 in the third wing F3.

[0112] The device structure comprising the semiconductor portion 8 and the functional layer 9 is referred to as a laminate LB. The semiconductor substrate 10 comprises a plurality of strip-shaped laminates LB. The functional layer 9 formed on the semiconductor portion 8 has at least the active region (e.g., the light-emitting region) formed above the wing portion F, enabling the fabrication of a very high-quality device.

[0113] FIG24 is a cross-sectional view illustrating the device separation method in Example 1. FIG25 is a top view illustrating the device separation method in Example 1. As shown in FIG24 and FIG25 , a semiconductor substrate 10 may include a plurality of device bodies 20 separated by a plurality of trenches TR on a base substrate BS. The device bodies 20 may include wing portions F, a functional layer 9, an anode EA, and a cathode EC.

[0114] The semiconductor substrate 10 can be formed into a plurality of element bodies 20 by etching a plurality of trenches TR in the laminate LB. Alternatively, the semiconductor substrate 10 can be divided into a plurality of portions PA (see FIG. 21 ) by forming a plurality of trenches TR in the semiconductor portion 8. The functional layer 9, anode EA, and cathode EC can then be formed on the portions PA. Alternatively, the semiconductor substrate 10 can be formed into a plurality of element bodies 20 by cleaving the laminate LB.

[0115] The mask portion 5 can be removed by etching using hydrofluoric acid, buffered hydrofluoric acid (BHF), or the like. In this case, the device body 20 can be easily separated from the base substrate BS. The semiconductor substrate 10 may have a gap between the back surface N1B of the thin first nitride semiconductor layer NS1 and the surface of the mask portion 5, or the mask portion 5 may not be removed. For example, the device body 20 may be bonded to the support substrate SK via bonding layers H1 and H2. Subsequently, the device body 20 can be separated from the base substrate BS by breaking the bond between the seed region S and the semiconductor portion 8 (initial growth layer 8s). The support substrate SK may have conductive pads in contact with the bonding layer H1 and conductive pads in contact with the bonding layer H2. The bonding layers H1 and H2 may be formed of solder material.

[0116] The device body (semiconductor device) 20 includes a first nitride semiconductor layer NS1, an Al-based semiconductor layer ALS containing aluminum and located on the first nitride semiconductor layer NS1, a second nitride semiconductor layer NS2 located on the Al-based semiconductor layer ALS, and a functional layer 9 located on the second nitride semiconductor layer NS2. The impurity concentration, i.e., silicon, of the upper surface N2T of the second nitride semiconductor layer NS2 is lower than that of the upper surface N1T of the first nitride semiconductor layer NS1. In the device body 20, the upper surface roughness of the aluminum-based semiconductor layer ALS can be smaller than that of the upper surface roughness of the first nitride semiconductor layer NS1. Specific examples of the device body 20 include light-emitting diodes (LEDs), semiconductor lasers, Schottky diodes, photodiodes, and transistors (including power transistors and high electron mobility transistors).

[0117] FIG26 is a top view showing another configuration example of the semiconductor substrate 10 in Example 1. As shown in FIG26 , the semiconductor substrate 10 can have the anode EA and cathode EC formed above the same wing F (e.g., the first wing F1). A trench TR (not shown) can be formed in the portion of the laminate LB located above the seed region S.

[0118] [Example 2] Fig. 27 is a cross-sectional view schematically showing the structure of the semiconductor substrate 10 in Example 2. In Fig. 27 , the black dots in the diagram at the positions indicated by the lead lines of symbols J1 and J2 represent the spaces (gap) between the wing portions F and the template substrate TS.

[0119] As shown in FIG27 , in the semiconductor substrate 10 of Example 2, the template substrate TS may have a ridge R on its upper surface, with the first seed region S1 located above the ridge R. Furthermore, a first gap J1 (gap J) may exist between the first semiconductor portion 8A and the mask portion 5. The first gap J1 can also be referred to as the space between the growth inhibition area DA and the first wing portion F1. The first wing portion F1 is separated from the mask portion 5, which functions as the growth inhibition area DA. The first seed region S1 (its surface) is located above the growth inhibition area DA. The first semiconductor portion 8A includes a first base portion B1 located above the first seed region S1 and a first wing portion F1 connected to the first base portion B1 and facing the growth inhibition area DA via the first gap J1.

[0120] When viewed from above, the base layer 4 of the template substrate TS may not overlap with the mask portion 5, or the base layer 4 may be contained within the ridge portion R. The upper surface of the ridge portion R (first seed region S1) may be formed of the base layer 4, and the side surfaces of the ridge portion R may be covered by the mask portion 5. The template substrate TS may include a portion of the mask portion 5 on the side surfaces of the ridge portion R. The base layer 4 may not be exposed on the side surfaces of the ridge portion R. The side surfaces of the ridge portion R may not contact the first wing portion F1 (first nitride semiconductor layer NS1). The side surfaces of the ridge portion R may entirely face the first gap J1. This reduces the contact area between the ridge portion R and the first wing portion F1, thereby reducing the defect density in the first wing portion F1.

[0121] The first semiconductor portion 8A can be formed as follows: after growing the initial growth layer 8s with the base layer 4 exposed in the ridge portion R as the starting point, the first nitride semiconductor layer NS1 is grown according to the high flatness growth conditions disclosed herein, and then the Al-based semiconductor layer ALS and the second nitride semiconductor layer NS2 are grown.

[0122] The semiconductor substrate 10 may have a second gap J2 (gap J) between the second semiconductor portion 8C and the mask portion 5. The second gap J2 may also have the same structure as the first gap J1. The template substrate TS shown in the example of Figure 27 can be formed by etching the main substrate 1 and the base layer 4 using a resist, forming the mask portion 5, and then stripping the resist. The main substrate 1 may include a protrusion Q on its main surface, and at least a portion of the protrusion Q may be included in the ridge portion R. The side surface of the ridge portion R of the semiconductor substrate 10 (mask portion 5) may be in contact with the first wing portion F1 (first nitride semiconductor layer NS1).

[0123] [Example 3] FIG28 is a cross-sectional view schematically illustrating the structure of semiconductor substrate 10 in Example 3. As shown in FIG28 , in semiconductor substrate 10 in Example 3, the modified region of base layer 4 of template substrate TS becomes growth inhibition region DA. The method for modifying the surface of base layer 4 to form growth inhibition region DA is not particularly limited. For example, base layer 4 may be subjected to plasma treatment, annealing, or impurity ion implantation. Base layer 4 may serve as seed crystal portion 3.

[0124] In the example shown in FIG28 , after protrusions 4Q are formed on the surface of base layer 4, a growth inhibition region DA is formed in the base layer 4 excluding the protruding surfaces (high-position surfaces) of protrusions 4Q. The surface of protrusions 4Q in ridge R can serve as the first seed region S1. The first semiconductor portion 8A can be formed by growing an initial growth layer 8s starting from the base layer 4 exposed at the ridge R, then growing a first nitride semiconductor layer NS1 under the highly flat growth conditions disclosed herein, followed by growing an Al-based semiconductor layer ALS and a second nitride semiconductor layer NS2.

[0125] [Other configuration examples] FIG29 is a schematic diagram showing an example of the configuration of an electronic device. The electronic device 55 in FIG29 includes a semiconductor element 25 having a semiconductor portion 8, a drive substrate 23 on which the semiconductor element 25 is mounted, and a control circuit 27 that controls the drive substrate 23. FIG30 is a schematic diagram showing another example of the configuration of an electronic device. The device area (device portion) PA may not be separated from the template substrate TS. The electronic device 55 in FIG30 includes a semiconductor substrate 10 having a template substrate TS and a device area PA, a drive substrate 23 on which the semiconductor substrate 10 is mounted, and a control circuit 27 that controls the drive substrate 23. In this case, the main substrate 1 included in the template substrate TS can be a light-transmitting substrate (e.g., a sapphire substrate). Examples of the electronic device 55 include light-emitting devices, display devices, laser emitting devices (including Fabry-Perot type and surface emitting types), measuring devices, lighting devices, communication devices, information processing devices, and power control devices.

[0126] [Additional Notes] The invention disclosed herein has been described above based on various figures and embodiments. However, the invention disclosed herein is not limited to the aforementioned embodiments and examples. Specifically, the invention disclosed herein can be modified in various ways within the scope of this disclosure. Embodiments obtained by appropriately combining the technical methods disclosed in different embodiments and examples are also included within the technical scope of this disclosure. In other words, it should be noted that those skilled in the art can readily make various variations or modifications based on this disclosure. Furthermore, it should be noted that such variations or modifications are within the scope of this disclosure.

[0127] [Summarize] The semiconductor substrate in Sample 1 of the present disclosure comprises: a template substrate comprising a first seed region and a growth inhibition region arranged in a first direction; and a first semiconductor portion located above the first seed region and the growth inhibition region; and the first semiconductor portion comprises a first wing portion located above the growth inhibition region; the first wing portion comprises a first nitride semiconductor layer, an aluminum-based semiconductor layer comprising aluminum and located on the first nitride semiconductor layer, and a second nitride semiconductor layer located on the aluminum-based semiconductor layer; the upper surface of the second nitride semiconductor layer has a lower silicon concentration than the upper surface of the first nitride semiconductor layer.

[0128] The semiconductor substrate in aspect 2 of the present disclosure is as described in aspect 1, wherein the surface roughness of the aluminum-based semiconductor layer may be smaller than the surface roughness of the first nitride semiconductor layer.

[0129] The semiconductor substrate in Aspect 3 of the present disclosure is as described in Aspect 1 or 2 above, wherein the silicon concentration on the upper surface of the first nitride semiconductor layer may be at least 5 times the silicon concentration on the upper surface of the second nitride semiconductor layer.

[0130] The semiconductor substrate in aspect 4 of the present disclosure is any one of aspects 1 to 3, wherein the silicon concentration distribution in the first direction on the upper surface of the first nitride semiconductor layer is non-uniform.

[0131] The semiconductor substrate in Aspect 5 of the present disclosure is any of Aspects 1 to 4, wherein the first semiconductor portion includes a first base located above the first seed region, the upper surface of the first nitride semiconductor layer includes a connection region connected to the first base, and an edge region separated from the first base in the first direction, and the silicon concentration of the connection region is higher than the silicon concentration of the edge region.

[0132] The semiconductor substrate in Aspect 6 of the present disclosure is any of Aspects 1 to 5, wherein the first semiconductor portion includes a first base located above the first seed region, the upper surface of the first nitride semiconductor layer includes a connection region connected to the first base and an edge region separated from the first base in the first direction, and the upper surface roughness of the connection region is greater than the upper surface roughness of the edge region.

[0133] The semiconductor substrate in Aspect 7 of the present disclosure is any one of Aspects 1 to 6, wherein the ratio of the length of the first nitride semiconductor layer in the first direction to the thickness is greater than 5.0.

[0134] The semiconductor substrate in aspect 8 of the present disclosure is any one of aspects 1 to 7, wherein the aluminum-based semiconductor layer covers the side surfaces of the first nitride semiconductor layer.

[0135] The semiconductor substrate in aspect 9 of the present disclosure is any one of aspects 1 to 8, and further comprises a silicon-based mask functioning as the growth inhibition region.

[0136] The semiconductor substrate in aspect 10 of the present disclosure is any one of aspects 1 to 9, wherein the surface of the first nitride semiconductor layer has a plurality of recesses with a depth of 20 to 80 nm.

[0137] The semiconductor substrate in aspect 11 of the present disclosure is any one of aspects 1 to 10, wherein the first and second nitride semiconductor layers are thicker than the aluminum-based semiconductor layer.

[0138] The semiconductor substrate in aspect 12 of the present disclosure is any one of aspects 1 to 11, wherein the through dislocation density on the upper surface of the first wing portion may be less than 1 / 5 of the through dislocation density of the first base portion.

[0139] The semiconductor substrate in Aspect 13 of the present disclosure is as described in any one of Aspects 1 to 12 above, wherein the aluminum-based semiconductor layer contains 1.5 atomic % or more of aluminum.

[0140] The semiconductor substrate in aspect 14 of the present disclosure is like aspect 10, wherein the aluminum-based semiconductor layer includes a lower layer at least a portion of which is located inside the depression of the recessed portion of the first nitride semiconductor layer, and an upper layer flatter than the lower layer, and the lower layer has a lower aluminum concentration than the upper layer.

[0141] The semiconductor substrate in Aspect 15 of the present disclosure is as described in any one of Aspects 1 to 14 above, wherein the aluminum-based semiconductor layer comprises a layer of AlGaN or AlN.

[0142] The semiconductor substrate in aspect 16 of the present disclosure is any one of aspects 1 to 15, wherein the template substrate comprises a silicon wafer, a silicon carbide wafer, or a sapphire wafer, and the first and second nitride semiconductor layers comprise GaN layers.

[0143] The semiconductor substrate in Aspect 17 of the present disclosure is as described in any one of Aspects 1 to 16 above, wherein a functional layer including an active layer is provided above the first wing.

[0144] The semiconductor substrate in state 18 of the present disclosure is any of the above-mentioned states 1 to 17, wherein the above-mentioned template substrate has a second seed region and a second semiconductor portion located above the above-mentioned second seed region and the above-mentioned growth inhibition region, the above-mentioned second semiconductor portion includes a second base portion located above the above-mentioned second seed region and a second wing portion located above the above-mentioned growth inhibition region, and the above-mentioned first wing portion and the above-mentioned second wing portion are adjacent to each other with a gap therebetween.

[0145] The semiconductor substrate in aspect 19 of the present disclosure is any one of aspects 1 to 18, wherein a gap is left between the growth inhibition region and the first wing.

[0146] The manufacturing method of the semiconductor substrate in the state sample 20 disclosed in the present invention includes the following steps: preparing a template substrate including a first seed region and a growth inhibition region arranged in a first direction; growing an initial growth layer on the above-mentioned first seed region; growing a first nitride semiconductor layer having an upper surface roughness from the side of the above-mentioned initial growth layer toward the top of the above-mentioned growth inhibition region; and growing an aluminum-based semiconductor layer in a manner to fill the upper surface roughness of the above-mentioned first nitride semiconductor layer.

[0147] The method for manufacturing a semiconductor substrate in aspect 21 of the present disclosure is the same as aspect 20, which includes the step of forming a second nitride semiconductor layer on the aluminum-based semiconductor layer.

[0148] The method for manufacturing the semiconductor substrate in state sample 22 of the present disclosure is like the above-mentioned state sample 20 or 21, wherein the above-mentioned first nitride semiconductor layer is grown in such a manner that the thickness of the portion located on the above-mentioned initial growth layer becomes less than 1 / 5 of the thickness of the portion in contact with the side surface of the above-mentioned initial growth layer.

[0149] The method for manufacturing a semiconductor substrate in aspect 23 of the present disclosure is as described in any of aspects 20 to 22 above, wherein the silicon concentration on the upper surface of the first nitride semiconductor layer is more than five times the silicon concentration on the upper surface of the second nitride semiconductor layer.

[0150] The semiconductor substrate manufacturing apparatus in aspect 24 of the present disclosure performs each step in any one of aspects 20 to 23 described above.

[0151] The semiconductor element in state sample 25 of the present disclosure comprises: a first nitride semiconductor layer; an aluminum-based semiconductor layer comprising aluminum and located on the first nitride semiconductor layer; a second nitride semiconductor layer located on the aluminum-based semiconductor layer; and a functional layer located on the second nitride semiconductor layer; and the upper surface of the second nitride semiconductor layer has a lower silicon concentration than the upper surface of the first nitride semiconductor layer.

[0152] 1: Main base board 2: Buffer 3: Seed crystal part 4: Basal layer 4Q:convex part 5: Mask 6: Mask pattern 8: Semiconductor Department 8A:1st Semiconductor Division 8C: 2nd semiconductor unit 8s: Initial growth layer 8sS: Side 8sT: Upper surface 9: Functional layer 10:Semiconductor substrate 20: Component body 23: Drive substrate 25:Semiconductor components 27: Control circuit 30: Semiconductor substrate manufacturing equipment 55: Electronic machines ALS: Al-based semiconductor layer B: base B1: Base 1 B2: Second base BP1: 1st Boundary Section BP2: Second Boundary Section BPP:By-product BS: Base substrate CA:Connection Area D1: Depth D2: Thickness D3: Thickness D10:Thickness D11:Thickness DA: Growth inhibition area Ds: protrusion height Dt: Total thickness E1: Edge E2: Edge E3: Edge EA: Anode EC: cathode F: Wing F1: Wing 1 F2: 2nd wing F3: Wing 3 FL: Lower level G: Gap Gf: 1st gap Gs: Second gap H1: Bonding layer H2: Bonding layer IV: Region J: Gap J1: First gap J2: Second gap JA: Marginal Area K: Opening K1: 1st opening K2: 2nd opening LB:Laminated body LST: Upper Surface M10, M20, M30, M40, M50: devices MA: Middle Area MC: Control device MP:Main Department N1B: Back N1T: Top surface N2T: Top surface NS1: 1st nitride semiconductor layer NS2: Second nitride semiconductor layer PA: Component area Q:convex part R: ridge RP: concave part S: Seed area S1: 1st seed crystal area S2: Second seed crystal area S10: Step S20: Step S30: Step S40: Step S50: Step SGP: Micro Growth Part SK: Support substrate SL: Upper TR: Groove TS: Template Substrate W1: Length W2: width WB: Width WF: Width Wk: width Wm: width

Claims

1. A semiconductor substrate comprising: a template substrate comprising a first seed region and a growth inhibition region arranged in a first direction; and a first semiconductor portion located above the first seed region and the growth inhibition region; wherein the first semiconductor portion comprises a first wing portion located above the growth inhibition region; the first wing portion comprises a first nitride semiconductor layer, an aluminum-based semiconductor layer comprising aluminum and located on the first nitride semiconductor layer, and a second nitride semiconductor layer located on the aluminum-based semiconductor layer; an upper surface of the second nitride semiconductor layer has a lower silicon concentration than an upper surface of the first nitride semiconductor layer.

2. The semiconductor substrate according to claim 1, wherein the surface roughness of the aluminum-based semiconductor layer is smaller than the surface roughness of the first nitride semiconductor layer.

3. The semiconductor substrate according to claim 1, wherein the silicon concentration on the upper surface of the first nitride semiconductor layer is at least 5 times the silicon concentration on the upper surface of the second nitride semiconductor layer.

4. The semiconductor substrate according to claim 1, wherein the silicon concentration distribution in the first direction on the upper surface of the first nitride semiconductor layer is non-uniform.

5. A semiconductor substrate as claimed in claim 4, wherein the first semiconductor portion includes a first base portion located above the first seed region; the upper surface of the first nitride semiconductor layer includes a connection region connected to the first base portion and an edge region separated from the first base portion in the first direction; and the silicon concentration of the connection region is higher than the silicon concentration of the edge region.

6. A semiconductor substrate as claimed in claim 4, wherein the first semiconductor portion includes a first base portion located above the first seed region; the upper surface of the first nitride semiconductor layer includes a connection region connected to the first base portion and an edge region separated from the first base portion in the first direction; and the upper surface roughness of the connection region is greater than the upper surface roughness of the edge region.

7. The semiconductor substrate according to any one of claims 1 to 6, wherein a ratio of the length to the thickness of the first nitride semiconductor layer in the first direction is 5.0 or greater.

8. The semiconductor substrate according to any one of claims 1 to 6, wherein the aluminum-based semiconductor layer covers side surfaces of the first nitride semiconductor layer.

9. The semiconductor substrate according to any one of claims 1 to 6, comprising a silicon-based mask functioning as the growth inhibition region.

10. The semiconductor substrate according to any one of claims 1 to 6, wherein the surface of the first nitride semiconductor layer has a plurality of recesses with a depth of 20 to 80 nm.

11. The semiconductor substrate according to any one of claims 1 to 6, wherein the first and second nitride semiconductor layers are thicker than the aluminum-based semiconductor layer.

12. The semiconductor substrate according to claim 5 or 6, wherein the threading dislocation density of the upper surface of the first wing portion is less than or equal to 1 / 5 of the threading dislocation density of the first base portion.

13. The semiconductor substrate according to any one of claims 1 to 6, wherein the aluminum-based semiconductor layer contains 1.5 atomic % or more of aluminum.

14. A semiconductor substrate as claimed in claim 10, wherein the aluminum-based semiconductor layer comprises a lower layer at least a portion of which is located inside the depression of the recessed portion of the first nitride semiconductor layer, and an upper layer flatter than the lower layer; the lower layer has a lower aluminum concentration than the upper layer.

15. The semiconductor substrate according to any one of claims 1 to 6, wherein the aluminum-based semiconductor layer comprises a layer of AlGaN or AlN.

16. The semiconductor substrate of claim 15, wherein the template substrate comprises a silicon wafer, a silicon carbide wafer, or a sapphire wafer; and the first and second nitride semiconductor layers comprise GaN layers.

17. The semiconductor substrate according to any one of claims 1 to 6, further comprising a functional layer including an active layer above the first wing portion.

18. A semiconductor substrate as described in any one of claims 1 to 6, wherein the above-mentioned template substrate has a second seed region and a second semiconductor portion located above the above-mentioned second seed region and the above-mentioned growth inhibition region; the above-mentioned second semiconductor portion includes a second base portion located above the above-mentioned second seed region and a second wing portion located above the above-mentioned growth inhibition region; and the above-mentioned first wing portion and the above-mentioned second wing portion are adjacent to each other with a gap therebetween.

19. The semiconductor substrate according to any one of claims 1 to 6, wherein a gap is left between the growth inhibition region and the first wing.

20. A method for manufacturing a semiconductor substrate, comprising the following steps: preparing a template substrate comprising a first seed region and a growth inhibition region arranged in a first direction; growing an initial growth layer on the first seed region; growing a first nitride semiconductor layer having an upper surface roughness from the side of the initial growth layer toward above the growth inhibition region; and growing an aluminum-based semiconductor layer in a manner to fill the upper surface roughness of the first nitride semiconductor layer.

21. The method for manufacturing a semiconductor substrate according to claim 20, comprising the step of forming a second nitride semiconductor layer on the aluminum-based semiconductor layer.

22. A method for manufacturing a semiconductor substrate as claimed in claim 20 or 21, wherein the first nitride semiconductor layer is grown in such a manner that the thickness of the portion located on the initial growth layer becomes less than 1 / 5 of the thickness of the portion in contact with the side surface of the initial growth layer.

23. The method for manufacturing a semiconductor substrate according to claim 21, wherein the silicon concentration on the upper surface of the first nitride semiconductor layer is at least 5 times the silicon concentration on the upper surface of the second nitride semiconductor layer.

24. A semiconductor substrate manufacturing apparatus, which performs the steps of claim 20.

25. A semiconductor element comprising: a first nitride semiconductor layer; an aluminum-based semiconductor layer comprising aluminum and located on the first nitride semiconductor layer; a second nitride semiconductor layer located on the aluminum-based semiconductor layer; and a functional layer located on the second nitride semiconductor layer; and the upper surface of the second nitride semiconductor layer has a lower silicon concentration than the upper surface of the first nitride semiconductor layer.