Semiconductor memory devices and their manufacturing methods

Abstract

This invention provides a semiconductor memory device with excellent properties and a method for manufacturing the same. The semiconductor memory device includes: a plurality of first conductive layers equally arranged in a first direction, extending along a second direction intersecting the first direction and a third direction intersecting both the first and second directions; and a memory structure extending along the first direction, comprising a first semiconductor layer opposite to the plurality of first conductive layers and a gate insulating layer disposed between the first semiconductor layer and the plurality of first conductive layers. The first semiconductor layer comprises monocrystalline silicon and impurities. The impurities comprise: a first metal element capable of forming silica; and a second metal element constituting a metal material with a coefficient of linear expansion greater than that of silicon.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device and a method for manufacturing the same. Prior Technology

[0002] A known semiconductor memory device comprises: a substrate; a plurality of conductive layers stacked in equal layers in a direction intersecting the surface of the substrate; a semiconductor layer facing the plurality of conductive layers; and a gate insulating layer disposed between the conductive layers and the semiconductor layer. The gate insulating layer has a memory portion capable of storing data, such as an insulating charge storage layer or a conductive charge storage layer with a floating gate. Summary of the Invention

[0003] A semiconductor memory device with excellent properties and a method for manufacturing the same are provided.

[0004] One embodiment of a semiconductor memory device includes: a plurality of first conductive layers equally arranged in a first direction, extending along a second direction intersecting the first direction and a third direction intersecting both the first and second directions; and a memory structure extending along the first direction, comprising a first semiconductor layer opposite to the plurality of first conductive layers and a gate insulating layer disposed between the first semiconductor layer and the plurality of first conductive layers. The first semiconductor layer comprises monocrystalline silicon and impurities. The impurities comprise: a first metal element capable of forming silica; and a second metal element constituting a metal material with a coefficient of linear expansion greater than that of silicon. Simple Explanation of the Diagram

[0005] Figure 1 is a schematic circuit diagram showing the configuration of the memory die MD according to the first embodiment. Figure 2 is a stereoscopic view showing the pattern of the structure of the memory chip MD. Figure 3 is a bottom view showing the pattern of the structure of a chip CM. Figure 4 is a schematic bottom view showing a partial configuration of the chip CM. Figure 5 is a patterned cross-sectional view showing a partial structure of a memory chip (MD). Figure 6 is a patterned cross-sectional view showing a partial composition of Figure 5. Figure 7 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 8 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 9 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 10 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 11 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 12 is a schematic cross-sectional view used to illustrate the manufacturing method. Figures 13(A) to (C) are schematic cross-sectional views used to illustrate the manufacturing method. Figure 14 is a graph used to illustrate the manufacturing method. Figure 15 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 16 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 17 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 18 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 19 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 20 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 21 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 22 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 23 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 24 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 25 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 26 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 27 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 28 is a schematic cross-sectional view used to illustrate the manufacturing method. Figure 29 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the second embodiment. Implementation

[0006] Next, with reference to the drawings, the semiconductor memory device and its manufacturing method according to the embodiments will be described in detail. Furthermore, the following embodiments are merely examples and are not intended to limit the present invention. Also, the following drawings are schematic diagrams, and for ease of explanation, some components may be omitted. Additionally, sometimes the same symbols are used to mark common parts in multiple embodiments, and explanations are omitted.

[0007] Furthermore, when "semiconductor memory device" is mentioned in this specification, it sometimes refers to a memory chip, and sometimes to a memory system that includes a controller chip, such as a memory chip, memory card, or SSD (Solid State Drive). Additionally, it sometimes refers to a device including a host computer, such as a smartphone, tablet, or personal computer.

[0008] Furthermore, in this specification, when referring to the situation where the first component is "electrically connected to" the second component, it can mean that the first component is directly connected to the second component, or that the first component is connected to the second component via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in an OFF state, the first transistor is "electrically connected to" the third transistor.

[0009] Furthermore, in this specification, the direction parallel to the upper surface of the substrate is referred to as the X direction, the direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and the direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0010] Furthermore, in this specification, the direction intersecting the specified surface is sometimes referred to as the first direction, the direction along the specified surface is referred to as the second direction, and the direction along the specified surface intersecting the second direction is referred to as the third direction. These first, second, and third directions may correspond to any of the Z, Y, and X directions, or they may not correspond to each other.

[0011] Furthermore, in this specification, the terms "upper" or "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction closer to the substrate along the Z direction is called "lower." Also, when referring to a component as a lower surface or lower end, it refers to the surface or end of the component on the substrate side; when referring to an upper surface or upper end, it refers to the surface or end of the component on the opposite side of the substrate. Furthermore, the surface intersecting the X or Y direction is called a side surface, etc.

[0012] Furthermore, in this specification, when referring to "width," "length," or "thickness" in a specified direction regarding the structure, components, etc., it sometimes refers to the width, length, or thickness in a cross-section observed using SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy).

[0013] [First Implementation] [Circuit Structure] Figure 1 is a schematic equivalent circuit diagram showing the configuration of the semiconductor memory device according to the first embodiment.

[0014] The semiconductor memory device of this embodiment includes a memory cell array (MCA) and peripheral circuitry (PC) for controlling the MCA.

[0015] The memory cell array (MCA) has a plurality of memory blocks (MB). Each of the plurality of memory blocks (MB) has a plurality of serial cells (SU). Each of the plurality of serial cells (SU) has a plurality of memory cells (MU). One end of each of the plurality of memory cells (MU) is connected to the peripheral circuitry (PC) via a bit line (BL). The other end of each of the plurality of memory cells (MU) is connected to the peripheral circuitry (PC) via a common source line (SL).

[0016] A memory cell MU has one or more drain select transistors (STDs) connected in series between the bit line BL and the source line SL, multiple memory cells MC, and one or more source select transistors (STS). Hereinafter, the drain select transistor (STD) and the source select transistor (STS) are sometimes referred to simply as select transistors (STD, STS).

[0017] A memory cell (MC) is a field-effect transistor (memory transistor) comprising a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film contains a memory portion capable of storing data. This memory portion is, for example, a silicon nitride (SiN) film or a charge storage film with a floating gate. The threshold voltage of the memory cell (MC) varies depending on the amount of charge in the charge storage film. Furthermore, the gate electrodes of the plurality of memory cells (MC) contained in a memory cell (MU) are respectively connected to word lines (WL). These word lines (WL) are interconnected using memory cells (MC) located at the same position in the series direction of all memory cells (MU) in a memory block (MB).

[0018] Select transistors (STD, STS) are field-effect transistors that function as channel regions, consisting of a semiconductor layer, a gate insulating film, and a gate electrode. In this example, a memory cell MU has two drain select transistors (STD) and two source select transistors (STS). However, a memory cell MU may have one STD and one STS, or more than three. Select gate lines (SGD, SGS) are connected to the gate electrodes of the select transistors (STD, STS).

[0019] The drain select gate line SGD is set separately according to the string unit SU, and is connected to all drain select transistors STD in one string unit SU. In Figure 1, the drain select gate line SGD connected to each string unit SU is represented as drain select gate line SGD1, SGD2, ..., SGDn-1, SGDn.

[0020] The source select gate line (SGS) is commonly connected to all source select transistors (STS) in one memory block (MB).

[0021] [Structure of Memory Chip MD] Figure 2 is a schematic exploded perspective view showing an example of the configuration of the semiconductor memory device according to this embodiment. The semiconductor memory device of this embodiment includes a memory die MD. The memory die MD includes a chip CM that includes a memory cell array MCA and a chip CP that includes peripheral circuitry PC.

[0022] A plurality of bonding pad electrodes PX are provided on the upper surface of the wafer CM. A plurality of first bonding electrodes PI1 are provided on the lower surface of the wafer CM. A plurality of second bonding electrodes PI2 are provided on the upper surface of the wafer CP. Hereinafter, regarding the wafer CM, the surface with the plurality of first bonding electrodes PI1 is referred to as the front side, and the surface with the plurality of bonding pad electrodes PX is referred to as the back side. Similarly, regarding the wafer CP, the surface with the plurality of second bonding electrodes PI2 is referred to as the front side, and the surface opposite to the front side is referred to as the back side. In the illustrated example, the front side of the wafer CP is positioned above the back side of the wafer CP, and the back side of the wafer CM is positioned above the front side of the wafer CM.

[0023] The chip CM and chip CP are arranged with the front sides of the chip CM and the front sides of the chip CP facing each other. A plurality of first bonding electrodes PI1 and a plurality of second bonding electrodes PI2 are respectively provided and positioned to bond with the plurality of second bonding electrodes PI2. The first bonding electrodes PI1 and the second bonding electrodes PI2 function as bonding electrodes for bonding the chip CM and the chip CP and making them electrically conductive. The pad electrode PX functions as an electrode for electrically connecting the memory chip MD to a controller chip (not shown).

[0024] Furthermore, in the example of Figure 2, the corners a1, a2, a3, and a4 of the chip CM correspond to the corners b1, b2, b3, and b4 of the chip CP, respectively.

[0025] Figure 3 is a schematic bottom view showing the structure of the chip CM. Figure 4 is a schematic bottom view showing an enlarged view of the structure shown in part A of Figure 3. Furthermore, Figure 4 is a top view showing the structure of Figure 5 cut along lines C-C' and D-D' and viewed in the direction of the arrows, arranged in the X direction. Figure 5 is a schematic cross-sectional view showing the memory die MD cut along line B-B' as shown in Figure 4 and viewed in the direction of the arrows. Figure 6 is a schematic cross-sectional view showing an enlarged view of the structure shown in part E of Figure 5.

[0026] [Structure of a Chip CM] For example, as shown in Figure 3, the wafer CM has four memory cell array regions RMCA arranged in the X and Y directions, a memory cell array peripheral region RMCAE disposed along the outer periphery of the memory cell array regions RMCA, a plurality of pad electrode regions RPX corresponding to a plurality of pad electrodes PX, and an edge sealing region RE disposed along the outer edge of the wafer CM.

[0027] The memory cell array region RMCA has a plurality of memory blocks MB arranged in the Y direction. Between adjacent memory blocks MB in the Y direction, as shown in Figures 4 and 5, inter-block structures ST extending along the X and Z directions are respectively arranged. The memory cell array region RMCA has a conductive layer 112 disposed on the upper surface of the plurality of memory blocks MB and the plurality of inter-block structures ST. Furthermore, a wiring layer 160 is disposed below the plurality of memory blocks MB. Furthermore, a wiring layer 170 is disposed above the conductive layer 112, separated by an insulating layer 102. An insulating layer 107 is disposed above the wiring layer 170.

[0028] As shown in Figure 5, the memory block MB has a plurality of conductive layers 110 arranged in the Z direction and a plurality of memory structures 100 extending along the Z direction.

[0029] The plurality of conductive layers 110 are generally plate-shaped conductive layers extending along the X and Y directions. The conductive layers 110 may also comprise laminated films such as titanium nitride (TiN) barrier conductive films and metal films such as tungsten (W). Furthermore, the conductive layers 110 may also contain, for example, polycrystalline silicon containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). An insulating layer 101, such as silicon oxide (SiO2), is disposed between the plurality of conductive layers 110 arranged in the Z direction.

[0030] One or more of the uppermost conductive layers 110 among the plurality of conductive layers 110 function as the gate electrode of the source select gate line SGS and the plurality of source select transistors STS (Fig. 1) connected to the source select gate line SGS. Hereinafter, this conductive layer 110 is sometimes referred to as conductive layer 110 (SGS).

[0031] One or more of the bottommost conductive layers 110 among the plurality of conductive layers 110 function as drain-select gate lines SGD and gate electrodes of the plurality of drain-select transistors STD (Fig. 1) connected to the drain-select gate lines SGD. Hereinafter, this conductive layer 110 is sometimes referred to as conductive layer 110 (SGD).

[0032] The plurality of conductive layers 110 disposed between conductive layer 110 (SGS) and conductive layer 110 (SGD) function as gate electrodes for word lines WL and a plurality of memory cells MC (Fig. 1) connected to word lines WL. Hereinafter, this conductive layer 110 is sometimes referred to as conductive layer 110 (WL).

[0033] The memory structure 100 includes a semiconductor layer 120 extending along the Z direction and a gate insulating film 130 disposed between a plurality of conductive layers 110 and the semiconductor layer 120. One or more source select transistors (STS) are formed at positions in the memory structure 100 opposite to the conductive layer 110 (SGS) (Figure 1). One or more drain select transistors (STD) are formed at positions in the memory structure 100 opposite to the conductive layer 110 (SGD) (Figure 1). A plurality of memory cells (MC) are formed at positions in the memory structure 100 opposite to the conductive layer 110 (WL) (Figure 1).

[0034] For example, as shown in FIG4, the memory structure 100 is arranged in a prescribed pattern in the X and Y directions. The semiconductor layer 120 in the memory structure 100 functions as a channel region for a plurality of memory cells, for example. The semiconductor layer 120 is, for example, a single-crystal silicon (Si) semiconductor layer. Furthermore, sometimes the semiconductor layer 120 contains the following impurities. For example, as shown in FIG5, the semiconductor layer 120 has a generally bottomed cylindrical shape, and an insulating layer 125 such as silicon oxide is disposed in the central portion. Furthermore, the outer peripheral surface of the semiconductor layer 120 faces the conductive layer 110. A gate insulating film 130 is disposed between the semiconductor layer 120 and the conductive layer 110.

[0035] A conductive layer 112, such as polycrystalline silicon (Si), is disposed on top of the uppermost insulating layer 101. An impurity region containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B) is disposed at the upper end of the semiconductor layer 120. The upper end of the semiconductor layer 120 is covered by a gate insulating film 130. By removing a portion of the gate insulating film 130, a portion of the side surface of the upper end of the semiconductor layer 120 is exposed, thereby electrically connecting it to the conductive layer 112.

[0036] At the lower end of the semiconductor layer 120, an impurity region containing N-type impurities such as phosphorus (P) is provided. This impurity region covers the lower end of the insulating layer 125. Furthermore, this impurity region is electrically connected to the bit line BL. The bit line BL is electrically connected to the wafer CP via the aforementioned first bonding electrode PI1.

[0037] The gate insulating film 130 has a generally cylindrical shape covering the outer peripheral surface of the semiconductor layer 120. For example, as shown in FIG6, the gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a barrier insulating film 133 deposited between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating film 131 and the barrier insulating film 133 are, for example, insulating films such as silicon oxide (SiO2). The charge storage film 132 is, for example, a film capable of storing charge such as silicon nitride (Si3N4). The tunnel insulating film 131, the charge storage film 132, and the barrier insulating film 133 have a generally cylindrical shape and extend along the outer peripheral surface of the semiconductor layer 120 in the Z direction.

[0038] Furthermore, Figure 6 shows an example where the gate insulating film 130 has a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may also have a floating gate such as polycrystalline silicon containing N-type or P-type impurities.

[0039] For example, as shown in Figures 4 and 5, the inter-block structure ST extends along the X and Z directions, and the plurality of conductive layers 110 and the plurality of insulating layers 101 are divided along the Y direction according to the memory blocks MB. The inter-block structure ST includes, for example, conductive layers 141 extending along the X and Z directions, and insulating layers 142 such as silicon oxide (SiO2) disposed on the Y-direction side of the conductive layers 141. The conductive layers 141 may also include, for example, a stacked film of barrier conductive films such as titanium nitride (TiN) and metal films such as tungsten (W). The conductive layers 141 function as part of the source lines, for example. The upper end of the conductive layers 141 is located above the upper surface of the uppermost insulating layer 101. Furthermore, the upper end of the conductive layers 141 is electrically connected to the conductive layers 112.

[0040] The conductive layer 112 may, for example, contain polycrystalline silicon containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). The conductive layer 112 functions as part of a source line, for example. The conductive layer 112 is in contact with the upper surface of the insulating layer 101, the upper end of the semiconductor layer 120, and the upper end of the conductive layer 141.

[0041] The conductive layer 110 (SGD) is divided in the Y direction by the inter-string insulating layer SHE according to the string unit SU. Therefore, the conductive layer 110 (SGD) has a smaller width in the Y direction compared to the other conductive layers 110 (SGS) and 110 (WL). The conductive layer 110 (SGD) is electrically independent according to the string unit SU.

[0042] Furthermore, in this example, as shown in Figure 4, five inter-cell insulating layers (SHEs) are provided between the inter-block structures ST. The central SHE in the Y direction is arranged to overlap with the dummy memory structures 100 arranged in the X direction at the center of the Y direction of the memory block MB. The other SHEs are arranged to connect with the columns of memory structures 100 between them, which are adjacent in the Y direction and arranged in the X direction.

[0043] [Chip CP Structure] For example, as shown in Figure 5, the chip CP includes a substrate 200 and a plurality of transistors Tr disposed on the front side of the substrate 200. These transistors Tr are connected within the chip CM via the aforementioned second bonding electrode PI2, and function as peripheral circuitry PC for controlling the memory cell array MCA. For example, during readout operations, the peripheral circuitry PC supplies voltage to the current path including bit lines BL, semiconductor layer 120, conductive layer 110, conductive layer 112, and conductive layer 141, and determines the data recorded in the memory cells based on whether current is flowing.

[0044] When the peripheral circuit PC reads (or writes) data to the memory cell MC, it applies a driving voltage to the conductive layer 110 (SGD) corresponding to the serial cell SU to be accessed, turning on only the drain select transistor STD of the selected serial cell SU. Alternatively, when reading (or writing) data to the memory cell MC, the peripheral circuit PC can also apply a driving voltage to one conductive layer 110 (SGS) contained in the selected serial cell SU. Furthermore, the peripheral circuit PC can also turn off the source select transistor STS connected to another conductive layer (SGS). This allows the memory cell MC, which is not involved in the read operation, to be in a floating state.

[0045] [Manufacturing Method] Next, referring to Figures 7-28, the manufacturing method of memory die (MD) will be described. Figures 7-28 are diagrams used to explain this manufacturing method. Figures 7-12 and 16-20 show cross-sections corresponding to a portion of Figure 5, and Figures 21-28 show cross-sections corresponding to Figure 5. Furthermore, Figures 13 and 15 are schematic cross-sectional views used to illustrate the operation of this manufacturing method. Figure 14 is a graph used to illustrate the operation of this manufacturing method.

[0046] When manufacturing the memory die (MD) of this embodiment, for example, as shown in FIG7, an insulating layer 102 such as silicon oxide (SiO2) is formed on a substrate 300. This step is performed, for example, by a method such as CVD (Chemical Vapor Deposition). Next, a conductive layer 112A such as silicon, a sacrificial layer 103A such as silicon oxide (SiO2), a sacrificial layer 103B such as silicon nitride (SiN), a sacrificial layer 103C such as silicon oxide (SiO2), and a conductive layer 112B such as silicon are formed on the insulating layer 102. The conductive layers 112A and 112B may, for example, contain polycrystalline silicon containing N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). Next, a plurality of insulating layers 101, such as silicon oxide (SiO2), and a plurality of sacrificial layers 110A (first sacrificial layers), such as silicon nitride (SiN), are alternately formed on the conductive layer 112B. These steps are performed, for example, by a method such as CVD. Next, a cover insulating layer 104 is formed on the uppermost insulating layer 101. This step is performed, for example, by a method such as CVD.

[0047] Next, for example, as shown in Figure 8, using a mask (not shown), a plurality of memory vias 100A are formed at positions corresponding to the memory structure 100. The memory vias 100A extend along the Z-direction and penetrate a plurality of insulating layers 101, a plurality of sacrificial layers 110A, a conductive layer 112B, and sacrificial layers 103C, 103B, and 103A, reaching the middle of the conductive layer 112A. This step is performed, for example, by a method such as RIE (Reactive Ion Etching).

[0048] Next, for example, as shown in FIG9, a gate insulating film 130 (tunnel insulating film 131, charge storage film 132, and barrier insulating film 133), a semiconductor layer 120A, and an insulating layer 125A are formed on the upper surface of the covering insulating layer 104 and the inner peripheral surface of the memory hole 100A. The semiconductor layer 120A may contain, for example, amorphous silicon (a-Si). The insulating layer 125A may contain, for example, silicon oxide (SiO2). The semiconductor layer 120A and the insulating layer 125A may be formed, for example, by CVD or the like. Alternatively, on the inner peripheral surface of the memory hole 100A, before forming the gate insulating film 130, insulating layers such as silicon oxide (SiO2) may be formed in the portions of the conductive layers 112A and 112B exposed to the memory hole 100A, for example, by thermal oxidation or the like.

[0049] Next, for example, as shown in FIG10, a sacrificial core 126 is formed inside the insulating layer 125A formed in the memory hole 100A. The sacrificial core 126 comprises a metallic material or a metal compound material having a larger coefficient of linear expansion than silicon (Si). For example, the sacrificial core 126 comprises a metallic material containing at least one metallic element selected from zinc (Zn), indium (In), silver (Ag), gold (Au), cobalt (Co), zirconium (Zr), aluminum (Al), titanium (Ti), yttrium (Y), and copper (Cu), or a metal compound material containing at least one metal compound material selected from ZrO2, Al2O3, TiC, TiNi, Y2O3, and AlN.

[0050] Next, for example, as shown in Figure 11, the upper surfaces of the sacrificial core 126 and the insulating layer 125A are removed up to the middle height of the insulating layer 104. This step is performed, for example, by wet etching, RIE, or other methods.

[0051] Next, for example, as shown in FIG12, a semiconductor layer 122 is formed on the semiconductor layer 120A and the sacrificial core 126. The semiconductor layer 122 includes, for example, amorphous silicon (a-Si). Furthermore, a metal layer 111 is formed on the semiconductor layer 122. The metal layer 111 contains a metal element capable of forming silicates with silicon, such as at least one of nickel, palladium, and cobalt. Hereinafter, an example of nickel as the metal layer 111 will be described. The semiconductor layer 122 and the metal layer 111 are formed, for example, by a method such as CVD.

[0052] Next, the semiconductor layer 120A is crystallized using MILC (Metal Induced Lateral Crystallization). Specifically, the wafer CM is subjected to a long-term crystallization annealing at 400-800°C. Here, nickel atoms contained in the metal layer 111 diffuse into the amorphous silicon of the semiconductor layer 122, where nickel silicate (NiSi2) crystallizes and grows. This crystallization continues during the crystallization annealing process, promoting both Ni diffusion and silicon crystallization within the semiconductor layer 122, until it reaches the semiconductor layer 120A, and then moves from one end to the other in the Z direction within the semiconductor layer 120A.

[0053] Figure 13 is a diagram illustrating the details of the MILC method described above, and is an enlarged schematic cross-sectional view of semiconductor layer 120A. As shown in Figure 13(a), at the interface S1 between the amorphous silicon semiconductor layer 120A and the silicate layer 123, nickel atoms in the silicate layer 123 diffuse into the Ni semiconductor layer 120A, forming the silicate layer 123 at the diffusion sites. On the other hand, within the silicate layer 123, in the region S2, pores V corresponding to the nickel atoms Ni that have diffused to the semiconductor layer 120A are generated. These pores V diffuse within the silicate layer 123, reaching the interface S3 between the silicate layer 123 and the semiconductor layer 120. At the interface S3, pores V condense, and silicon crystals grow. Furthermore, as shown in Figures 13(a), (b), and (c), during the movement of the silicate layer 123 from one end of the semiconductor layer 120A to the other, the amorphous silicon semiconductor layer 120A crystallizes, forming a silicon semiconductor layer 120 including monocrystalline silicon. Furthermore, the term "monocrystalline silicon" here is not limited to completely "monocrystalline silicon," but also includes "crystallized silicon" that has a larger maximum grain width than "polycrystalline silicon" and is close to that of monocrystalline silicon.

[0054] The crystallization process described above using the MILC method requires prolonged heating. However, if the crystallization annealing time is too long, amorphous silicon is more likely to polycrystalline. Polycrystalline silicon has a higher resistivity than monocrystalline silicon, resulting in a decrease in unit current.

[0055] To accelerate the crystallization rate of MILC, it is effective to (1) facilitate the formation of pores V; (2) promote the diffusion of pores V; and (3) make pores V disappear easily. According to the knowledge and understanding of the inventors, applying tensile stress in the advancing direction (Z direction) of crystallization to the semiconductor layer 120A is more effective in promoting the above-mentioned (1) to (3).

[0056] Figure 14 is a graph showing the relationship between the stress applied to the semiconductor layer 120A in the advancing direction (Z direction) before crystallization and the change in energy required for Ni atom movement. According to Figure 14, the greater the applied tensile stress at any of the following locations—NiSi2 / a-Si interface S1, NiSi2 bulk S2, and c-Si / NiSi2 interface S3—the easier it is for Ni atoms to move.

[0057] Therefore, in this embodiment, a metal material or metal compound material with a larger coefficient of linear expansion than silicon is used as the sacrificial core 126. Figure 15 is a schematic cross-sectional view showing a portion of the semiconductor layer 120 and the sacrificial core 126 during the crystallization annealing step. As shown in Figure 15, during crystallization annealing, the sacrificial core 126 expands in the crystallization advance direction (Z direction), resulting in tensile stress being applied to the semiconductor layers 120 and 120A in the crystallization advance direction (Z direction). Therefore, crystallization is promoted, and a single-crystal semiconductor layer 120 is produced. Furthermore, the insulating layer 125A functions as a shielding layer to prevent the reaction between the metal elements contained in the sacrificial core 126 and the semiconductor layers 120 and 120A during crystallization annealing.

[0058] After the crystallization annealing using the MILC method is completed, as shown in Figure 16, an adsorption layer 124 comprising amorphous silicon is formed on the crystallized semiconductor layer 122. This step is performed by methods such as CVD.

[0059] Next, a heat treatment is performed. Here, the adsorption layer 124 adsorbs nickel atoms remaining in the semiconductor layer 120. After the heat treatment, as an impurity, a small amount of a first metal element (e.g., nickel) capable of forming silica, which was not completely adsorbed during the adsorption treatment, may remain in the semiconductor layer 120. Also, a small amount of a second metal element, exceeding the insulating layer 125A, may remain in the semiconductor layer 120 and migrate to the sacrificial core 126 contained therein. Furthermore, the content ratio of the second metal element is smaller than that of the first metal element.

[0060] Next, as shown in Figure 17, the adsorption layer 124, semiconductor layer 122, sacrificial core 126, and insulating layer 125A are removed. This step is performed, for example, by methods such as RIE or wet etching.

[0061] Next, as shown in Figure 18, the semiconductor layer 120 is thinned. This reduces the thickness of the semiconductor layer 120. This step can be performed, for example, by wet etching.

[0062] Next, as shown in Figure 19, an insulating layer 125 is formed in the center of the semiconductor layer 120. This forms the memory structure 100B. This step is performed, for example, by a method such as CVD.

[0063] Next, for example, as shown in FIG20, a portion of the insulating layer 125, the semiconductor layer 120, and the gate insulating film 130 is removed to expose the uppermost cover insulating layer 104. Furthermore, the upper ends of the semiconductor layer 120 and the insulating layer 125 are excavated deeper below the upper surface of the cover insulating layer 104. This step is performed, for example, by a method such as RIE.

[0064] Next, for example, as shown in FIG21, a semiconductor layer 121 is formed above the semiconductor layer 120 and the insulating layer 125. The semiconductor layer 121 contains, for example, amorphous silicon containing N-type impurities such as phosphorus (P). This step is performed, for example, by a method such as CVD. Next, for example, a portion of the semiconductor layer 121 is removed by a method such as RIE to expose the covering insulating layer 104. Next, an insulating layer 105 is formed on the covering insulating layer 104 and the semiconductor layer 121. This step is performed, for example, by a method such as CVD.

[0065] Next, for example, as shown in Figure 22, a trench STA is formed at the location where the inter-block structure ST is formed. The trench STA extends along the Z and X directions, and the insulating layer 105, the covering insulating layer 104, the insulating layer 101, the sacrificial layer 110A, the conductive layer 112B, the sacrificial layer 103C, and the sacrificial layer 103B are broken in the Y direction, thereby exposing the upper surface of the sacrificial layer 103A. This step is performed, for example, by a method such as RIE. Next, a protective film 140B, such as silicon nitride, is formed on the side surface of the trench STA in the Y direction. This step is performed, for example, by forming an insulating film such as silicon nitride on the side surface and bottom surface of the trench STA in the Y direction by a method such as CVD, and then removing the portion of the insulating film covering the bottom surface of the trench STA by a method such as RIE.

[0066] Next, for example, as shown in FIG23, a portion of the sacrificial layers 103A, 103B, 103C and the gate insulating film 130 is removed, thereby exposing a portion of the semiconductor layer 120. This step is performed, for example, by a method such as wet etching.

[0067] Next, for example, as shown in FIG24, a semiconductor layer is formed on the portion obtained after removing a portion of the sacrificial layers 103A, 103B, 103C and the gate insulating film 130. The newly formed semiconductor layer and the conductive layers 112A and 112B form a conductive layer 112. Then, the semiconductor layer formed in the trench STA is removed. This step is performed, for example, by methods such as epitaxial growth and RIE.

[0068] Next, for example, as shown in FIG25, the protective film 140B is removed, and the sacrificial layer 110A is removed via the STA trench. This step is performed, for example, by a method such as wet etching. Thereby, a hollow structure is formed, comprising a plurality of insulating layers 101 disposed in the Z direction, and a memory structure 100B supporting the insulating layers 101.

[0069] Next, for example, as shown in FIG26, a conductive layer 110 is formed in the hollow portion. This step is performed, for example, by a method such as CVD. Next, an insulating layer 142 constituting the inter-block structure ST is formed in the trench STA. Next, a conductive layer 141 is formed at the center in the Y direction of the insulating layer 142, and a contact 161 is formed. These steps are performed, for example, by a method such as CVD and RIE. The insulating layer 142 extends from the insulating layer 105 to the conductive layer 112. The conductive layer 141 penetrates the insulating layer 105, and its lower end is electrically connected to the conductive layer 112. The contact 161 penetrates the insulating layer 105 and is electrically connected to the semiconductor layer 121 of the memory structure 100B.

[0070] Next, for example, as shown in FIG27, a photoresist is formed on the insulating layer 105, and a mask 106 is formed by photolithography. Using the mask 106, a groove SHEA is formed that separates the insulating layer 105, the covering insulating layer 104, the insulating layer 101, and the conductive layer 110 (SGD) in the Y direction. This step is performed, for example, by a method such as RIE.

[0071] Next, for example, as shown in FIG28, an inter-cell insulating layer SHE is formed in the slot SHEA. Next, an insulating layer 105 is deposited on the insulating layer 105. Next, the insulating layer 105 is etched in a predetermined pattern to form a contact 162 and a bit line BL connected to the contact 161.

[0072] Then, an insulating layer 105 is deposited on the bit line BL to form the wiring layer 160 shown in FIG5, thereby manufacturing the chip CM.

[0073] [Effect] According to this embodiment, since tensile stress can be applied to the semiconductor layer 120A by the thermal expansion of the sacrificial core 126 during the MILC step, the crystallization speed of the semiconductor layer 120A can be increased. This provides a semiconductor memory device with the excellent characteristics of a semiconductor layer that crystallizes well as a channel.

[0074]

[0075] [Second Implementation] Figure 29 is a schematic cross-sectional view illustrating the manufacturing method of the semiconductor memory device according to the second embodiment.

[0076] In the second embodiment, as shown in FIG29, a sacrificial layer 126A (second sacrificial layer) is formed inside the insulating layer 125A formed in the memory hole 100C to replace the sacrificial core 126 used in the first embodiment. An insulating layer 125B is formed inside the sacrificial layer 126A. The sacrificial layer 126A contains a metallic material or a metal compound material having a larger coefficient of linear expansion than silicon (Si). For example, the sacrificial layer 126A contains a metallic material containing at least one metallic element selected from zinc (Zn), indium (In), silver (Ag), gold (Au), cobalt (Co), zirconium (Zr), aluminum (Al), titanium (Ti), yttrium (Y), and copper (Cu), or contains at least one metal compound material selected from ZrO2, Al2O3, TiC, TiNi, Y2O3, and AlN.

[0077] Next, similar to the first embodiment, the insulating layer 125B, the sacrificial layer 126A, and the upper surface of the insulating layer 125A are removed to a position covering the middle height of the insulating layer 104, and a semiconductor layer 122 is formed on the semiconductor layer 120A and the sacrificial layer 126A. The semiconductor layer 122 includes, for example, amorphous silicon (a-Si). Furthermore, a metal layer 111 is formed on the semiconductor layer 122. The metal layer 111 contains a metal element capable of forming silicates with silicon, for example, nickel. Next, the semiconductor layer 120A is crystallized using the MILC method.

[0078] Next, similar to the first embodiment, after forming an adsorption layer 124 comprising amorphous silicon on the crystallized semiconductor layer 122, a heat treatment is performed. Here, the adsorption layer 124 adsorbs nickel atoms remaining in the semiconductor layer 120. After the heat treatment, as an impurity, sometimes a small amount of a first metal element (e.g., nickel) capable of forming silica, which was not completely adsorbed during the adsorption treatment, remains in the semiconductor layer 120. Also, sometimes a small amount of a second metal element, exceeding the amount contained in the sacrificial layer 126A that migrated from the insulating layer 125A to the semiconductor layer 120, remains in the semiconductor layer 120. Furthermore, the content ratio of the second metal element is smaller than the content ratio of the first metal element.

[0079] Next, in the same manner as in the first embodiment, the adsorption layer 124, semiconductor layer 122, sacrificial layer 126A, insulating layer 125B, and insulating layer 125A are removed. Subsequent steps are the same as in the first embodiment.

[0080] In the second embodiment, since the thermal expansion of the sacrificial layer 126A can be used to apply tensile stress to the semiconductor layer 120A during the MILC step, the crystallization speed of the semiconductor layer 120A can be increased. This provides a semiconductor memory device with the excellent characteristics of a semiconductor layer that crystallizes well as a channel. [other] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways and can be omitted, substituted, or modified in various ways without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included in the scope of the invention described in the claims and its equivalents.

[0081] 100: Memory Structure 100A: Memory Hole 100B: Memory Structure 100C: Memory Hole 101: Insulation layer 102: Insulation layer 103A: Sacrificial Layer 103B: Sacrificial Layer 103C: Sacrificial Layer 104: Covering insulation layer 105: Insulation layer 107: Insulation layer 110: Conductive layer 110A: Sacrificial Layer 111: Metal layer 112: Conductive layer 112A: Conductive layer 112B: Conductive layer 120: Semiconductor layer 120A: Semiconductor layer 122: Semiconductor layer 123: Silicone layer 124: Adsorption layer 125: Insulation layer 125A: Sacrificial Core 125B: Insulation layer 126: Sacrificial Core 126A: Sacrificial Layer 130: Gate insulating film 131: Tunnel insulation film 132: Charge storage membrane 133: Barrier insulating film 140B: Protective film 141: Conductive layer 142: Insulation layer 160: Wiring layer 170: Wiring layer 200:Substrate 300:Substrate a1, a2, a3, a4, b1, b2, b3, b4: Corners BL: Bitline CM: Chip CP: chip MB: Memory Block MC: Memory Cell MCA: Memory Cell Array MD: Memory chip MU: Memory Unit PC: Peripheral Circuits PI1: First bonding electrode PI2: Second bonding electrode PX: Bonding pad electrode RE: Edge sealing area RMCA: Memory Cell Array Region RMCAE: Peripheral region of memory cell array RPX: Solder pad electrode area SGD, SGD1~SGDn: Drain-selective gate lines SGS: Select Gate Line SHE: Inter-cell insulation layer SHEA: slot ST: Inter-block structure STA: slot STD: Drain Select Transistor STS: Source Selective Transistor SL: Source Line SU: Serial unit Tr: transistor WL: Character Line

Claims

1. A semiconductor memory device comprising: a plurality of first conductive layers equally arranged in a first direction and extending along a second direction intersecting the first direction and a third direction intersecting the first and second directions; and a memory structure extending along the first direction and including a first semiconductor layer opposite to the plurality of first conductive layers and a gate insulating layer disposed between the first semiconductor layer and the plurality of first conductive layers; wherein the first semiconductor layer comprises monocrystalline silicon and impurities, the impurities comprising: a first metal element capable of forming silica; and a second metal element constituting a metal material with a coefficient of linear expansion greater than that of silicon.

2. The semiconductor memory device of claim 1, wherein the first metallic element comprises at least one of nickel, palladium, and cobalt.

3. The semiconductor memory device of claim 2, wherein the first metallic element is nickel.

4. The semiconductor memory device of claim 1, wherein the second metallic element comprises at least one of zinc, indium, silver, gold, cobalt, zirconium, aluminum, titanium, yttrium, and copper.

5. The semiconductor memory device of claim 1, wherein the content ratio of the second metal element contained in the impurity is smaller than the content ratio of the first metal element.

6. A method for manufacturing a semiconductor memory device, comprising: alternately depositing a first insulating layer and a first sacrificial layer in a first direction; forming memory vias extending along the first direction in the first insulating layer and the first sacrificial layer; forming a second insulating layer inside the memory vias; forming a first semiconductor layer comprising amorphous silicon inside the second insulating layer of the memory vias; forming a metal layer comprising a first metal element capable of forming silica at one end of the first semiconductor layer in the first direction; and performing a first heat treatment to crystallize the amorphous silicon of the first semiconductor layer into a single crystal; wherein, in the method for manufacturing the semiconductor memory device, after forming the first semiconductor layer and before forming the metal layer, a third insulating layer is formed inside the first semiconductor layer, and a sacrificial core comprising a second metal element having a larger coefficient of linear expansion than the first semiconductor layer is formed inside the third insulating layer; and after performing the first heat treatment, the sacrificial core and the third insulating layer are removed. A fourth insulating layer is formed inside the first semiconductor layer.

7. The method for manufacturing a semiconductor memory device as claimed in claim 6, wherein the first metallic element comprises at least one of nickel, palladium, and cobalt.

8. The method for manufacturing a semiconductor memory device as claimed in claim 7, wherein the first metallic element is nickel.

9. The method for manufacturing a semiconductor memory device as claimed in claim 6, wherein the sacrificial core comprises a metallic material containing at least one metallic element selected from zinc, indium, silver, gold, cobalt, zirconium, aluminum, titanium, yttrium, and copper, or a metallic compound material containing at least one metallic compound selected from ZrO2, Al2O3, TiC, TiNi, Y2O3, and AlN.

10. A method for manufacturing a semiconductor memory device as claimed in claim 6, wherein, before forming the metal layer, a second semiconductor layer is formed at one end of the first semiconductor layer in the first direction, and the metal layer is formed on the second semiconductor layer.

11. A method for manufacturing a semiconductor memory device as claimed in claim 6, wherein after the first heat treatment, a third semiconductor layer is formed on one end of the first semiconductor layer in the first direction, and a second heat treatment is performed to adsorb the first metal element onto the second semiconductor layer.

12. The method for manufacturing a semiconductor memory device as claimed in claim 6, wherein the first semiconductor layer is thinned after the sacrificial core and the third insulating layer are removed and before the fourth insulating layer is formed.

13. A method for manufacturing a semiconductor memory device, comprising: alternately depositing a first insulating layer and a first sacrificial layer in a first direction; forming memory vias extending along the first direction in the first insulating layer and the first sacrificial layer; forming a second insulating layer inside the memory vias; forming a first semiconductor layer comprising amorphous silicon inside the second insulating layer of the memory vias; forming a metal layer comprising a first metal element capable of forming silica at one end of the first semiconductor layer in the first direction; and performing a first heat treatment to crystallize the amorphous silicon of the first semiconductor layer into a single crystal; wherein, after forming the first semiconductor layer and before performing the first heat treatment, a second sacrificial layer extending along the first direction comprising a second metal element having a larger coefficient of linear expansion than the first semiconductor layer is formed near the first semiconductor layer; and after performing the first heat treatment, the second sacrificial layer is removed.

14. A method for manufacturing a semiconductor memory device as claimed in claim 13, wherein after the formation of the first semiconductor layer and before the formation of the metal layer, a third insulating layer is formed inside the first semiconductor layer, and a second sacrificial layer is formed inside the third insulating layer.

15. A method for manufacturing a semiconductor memory device as claimed in claim 14, wherein after the first heat treatment is performed, the second sacrificial layer and the third insulating layer are removed, and a fourth insulating layer is formed inside the first semiconductor layer.

16. A method for manufacturing a semiconductor memory device as claimed in claim 13, wherein, before forming the metal layer, a second semiconductor layer is formed at one end of the first semiconductor layer in the first direction, and the metal layer is formed on the second semiconductor layer.

17. A method for manufacturing a semiconductor memory device as claimed in claim 16, wherein after the first heat treatment, a third semiconductor layer is formed on one end of the first semiconductor layer in the first direction, and a second heat treatment is performed to adsorb the first metal element onto the third semiconductor layer.

18. A method for manufacturing a semiconductor memory device as claimed in claim 15, wherein the first semiconductor layer is thinned after the removal of the second sacrificial layer and the third insulating layer and before the formation of the fourth insulating layer.

19. The method for manufacturing a semiconductor memory device as claimed in claim 13, wherein the first metallic element is nickel.

20. The method for manufacturing a semiconductor memory device as claimed in claim 13, wherein the second sacrificial layer comprises a metallic material containing at least one metallic element selected from zinc, indium, silver, gold, cobalt, zirconium, aluminum, titanium, yttrium, and copper, or a metallic compound material containing at least one metallic compound selected from ZrO2, Al2O3, TiC, TiNi, Y2O3, and AlN.