Semiconductor device and method of forming the same

Abstract

A device includes first, second, third, and fourth transistors and first and second conductors. The first transistor is coupled to a first node and includes a first gate. The second transistor is coupled to the first node and includes a second gate. The third transistor is coupled to a second node and includes a third gate separated from the first gate in a first direction. The fourth transistor is coupled to the second node and includes a fourth gate. The first conductor is located on a first metal layer above the front side of a substrate and is coupled to the first gate and the second node. The second conductor is located on a second metal layer below the back side of the substrate and is coupled to the fourth gate and the first node.

Description

Technical Field

[0001] none Prior Technology

[0002] The semiconductor integrated circuit (IC) industry produces a wide variety of digital devices to solve problems in many different fields. Some of these digital devices (such as memory macros) are configured to store data. As integrated circuits become smaller and more complex, the resistance of the conductive lines within these digital devices changes, thus affecting the operating voltage of these devices and the overall performance of the integrated circuit. Summary of the Invention

[0003] none Simple Explanation of the Diagram

[0004] When read with reference to the accompanying drawings, the following detailed description is the best way to understand the nature of this disclosure. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation. [ ] Figure 1 is a block diagram of a memory circuit according to some embodiments. Figure 2 is a circuit diagram of a corresponding memory cell that can be used in Figure 1 according to some embodiments. Figures 3A to 3D are corresponding diagrams of the layout design of corresponding integrated circuits according to some embodiments. Figures 4A to 4F are diagrams of the body circuit according to some embodiments. Figures 5A to 5F are diagrams of the body circuit according to some embodiments. Figures 6A to 6D are diagrams of the body circuit according to some embodiments. Figures 7A to 7D are layout designs based on some embodiments. Figures 8A to 8D are diagrams of the body circuit according to some embodiments. Figures 9A to 9G are diagrams of the body circuit according to some embodiments. Figures 10A to 10B are corresponding functional flowcharts of corresponding methods for manufacturing IC components according to some embodiments. Figures 11A to 11I are cross-sectional views of an intermediate element structure obtained by manufacturing a first mating contact on the front side of an integrated circuit and a second mating contact on the back side of an integrated circuit, according to some embodiments. Figure 12 is a flowchart of a method for manufacturing an integrated circuit according to some embodiments. Figure 13 is a flowchart of a method for generating an integrated circuit layout design according to some embodiments. Figure 14 is a schematic diagram of a system for designing IC layout and manufacturing IC circuits according to some embodiments. Figure 15 is a block diagram of an IC manufacturing system and its associated IC manufacturing process according to at least one embodiment of the present disclosure. Implementation

[0005] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For instance, in the following description, the formation of a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, in various instances, references to numbers and / or letters may be repeated. This repetition is for simplicity and clarity and does not, in itself, define the relationship between the various embodiments and / or configurations discussed.

[0006] Additionally, for ease of description, spatial relative terms such as "beneath," "below," "lower," "above," and "upper," and similar terms, may be used herein to describe the relationship between one element or feature as illustrated in the figures and another. Besides the orientations depicted in the figures, these spatial relative terms are intended to also cover different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly.

[0007] According to some embodiments, the memory unit includes a first transistor of a first type.

[0008] In some embodiments, the first transistor is coupled to a first storage node. In some embodiments, the first transistor includes a first gate on a first layer.

[0009] In some embodiments, the memory cell further includes a second transistor of a second type different from the first type. In some embodiments, the second transistor is coupled to the first storage node. In some embodiments, the second transistor includes a second gate on a second level located below the first level.

[0010] In some embodiments, the memory cell further includes a third transistor of a first type. In some embodiments, the third transistor is coupled to a second storage node. In some embodiments, the third transistor includes a third gate on a first level. In some embodiments, the third gate is separated from the first gate at least in a first direction.

[0011] In some embodiments, the memory cell further includes a fourth transistor of a second type. In some embodiments, the fourth transistor is coupled to a second storage node. In some embodiments, the fourth transistor includes a fourth gate on a second level.

[0012] In some embodiments, the memory cell further includes a first conductor extending along a second direction different from the first direction. In some embodiments, the first conductor is located on a first metal layer above the front side of the substrate. In some embodiments, the first conductor is coupled to a first gate and a second storage node.

[0013] In some embodiments, the memory cell also includes a second conductor extending along a second direction. In some embodiments, the second conductor is located on a second metal layer below the back side of the substrate. In some embodiments, the second metal layer is different from the first metal layer. In some embodiments, the second conductor is coupled to a fourth gate and a first storage node.

[0014] In some embodiments, the first conductor serves as the first mating contact on the front side of the memory cell, and the second conductor serves as the second mating contact on the back side of the memory cell. Compared to other methods, this improves the wiring resources of the memory cell and reduces the area of ​​the memory cell.

[0015] In some embodiments, by using a first conductor as a first mating side contact on the front side of the memory cell and a second conductor as a second mating side contact on the back side of the memory cell, at least one of the first conductor or the second conductor has a simpler design than other methods that have a more complex L-shape and use at least one additional shield.

[0016] Figure 1 is a block diagram of a memory circuit 100 according to some embodiments.

[0017] Figure 1 has been simplified for ease of explanation. In some embodiments, the memory circuit 100 may include various other elements besides those shown in Figure 1, or be otherwise arranged to perform the operations discussed below.

[0018] The memory circuit 100 is an IC having memory partitions 102A, 102B, 102C and 102D, global control circuit 100GC and global input / output (GIO) circuit 100BL.

[0019] Each memory partition 102A, memory partition 102B, memory partition 102C, and memory partition 102D includes a memory bank 110U and a memory bank 110L adjacent to the bit line (WL) drive circuit 110AC and the local control circuit 110LC. Each memory bank 110U and memory bank 110L includes a memory cell array 110AR and a local input / output (LIO) circuit 110BS.

[0020] Memory partitions (e.g., memory partitions 102A, 102B, 102C, and 102D) are part of memory circuitry 100, which includes a subset of memory (not shown in Figure 1) and adjacent circuitry configured to selectively access the subset of memory during programming and read operations. In the embodiment of Figure 1, memory circuitry 100 includes a total of four partitions. In some embodiments, memory circuitry 100 may contain more than or less than four partitions.

[0021] GIO circuit 100BL is configured to control access to one or more electrical paths (e.g., bit lines) of each memory in the respective memory bank 110U or memory bank 110L of each memory partition 102A, memory partition 102B, memory partition 102C, and memory partition 102D, for example, by generating one or more bit line signals. In some embodiments, GIO circuit 100BL includes global bit line driver circuitry. In some embodiments, GIO circuit 100BL is coupled to each memory bank 110U and memory bank 110L via corresponding global bit lines (not shown).

[0022] The global control circuit 100GC is configured to control some or all programming and read operations on each memory partition 102A, memory partition 102B, memory partition 102C and memory partition 102D, for example by generating and / or outputting one or more control and / or enable signals.

[0023] In some embodiments, the global control circuit 100GC includes one or more analog circuits configured to engage with memory partitions 102A, 102B, 102C, and 102D, to program data in one or more memories, and / or to use data received from one or more memories in one or more circuit operations. In some embodiments, the global control circuit 100GC includes one or more global address decoder or pre-decoder circuits configured to output one or more address signals to the WL drive circuit 110AC of each memory partition 102A, 102B, 102C, and 102D.

[0024] Each WL driver circuit 110AC is configured to generate a word line signal on the corresponding word line WL. In some embodiments, each WL driver circuit 110AC is configured to output the word line signal on the corresponding word line WL to the adjacent memory banks 110U and 110L of the corresponding memory partitions 102A, 102B, 102C, and 102D.

[0025] Each local control circuit 110LC is an electronic circuit configured to receive one or more address signals. Each local control circuit 110LC is configured to generate a signal corresponding to a neighboring subset of a memory identified by the one or more address signals. In some embodiments, the neighboring subset of the memory corresponds to a column of the memory. In some embodiments, each local control circuit 110LC is configured to generate each signal as a complementary signal pair. In some embodiments, each local control circuit 110LC is configured to output a signal to a corresponding bit line driver circuit within the adjacent WL driver circuit 110AC of the respective memory partitions 102A, 102B, 102C, and 102D. In some embodiments, the local control circuit 110LC includes memory decoder circuitry.

[0026] Each LIO circuit 110BS is configured to correspond to a GIO circuit 100BL (e.g., based on one or more BL control signals) and selectively access one or more bit lines coupled to an adjacent subset of the memory of the corresponding memory cell array 110AR (as shown in Figure 2). In some embodiments, the adjacent subset of the memory corresponds to a column of the memory. In some embodiments, the LIO circuit 110BS includes bit line selection circuitry.

[0027] Each LIO circuit 110BS includes one or more circuits 114. For ease of illustration, the circuits 114 are not shown in the memory banks 110U and 110L of memory partitions 102B, 102C, and 102D. In some embodiments, each circuit 114 includes at least one sense amplifier circuit. In some embodiments, according to some examples, during a read operation, the sense amplifier circuit is configured to read data from at least one memory cell 112 in a corresponding row of memory cells in the corresponding memory cell array 110AR. In some embodiments, each circuit 114 in the LIO circuit 110BS is coupled to a corresponding row of memory cells 112 in the memory cell array 110AR.

[0028] Each memory bank 110U and memory bank 110L contains a corresponding memory cell array 110AR, which includes memory cells or memory cells 112. The memory cells or memory cells 112 are configured to be accessed by adjacent LIO circuits 110BS and adjacent WL drive circuits 110AC.

[0029] Each memory cell array 110AR includes a memory array 112 with N columns and M rows, where M and N are positive integers. The columns of cells in the memory cell array 112 are arranged along a first direction X. The columns of cells in the memory cell array 112 are arranged along a second direction Y. The second direction Y is different from the first direction X. In some embodiments, the second direction Y is perpendicular to the first direction X. In some embodiments, each memory cell array 110AR is divided into an upper region and a lower region (not shown). In some embodiments, each row of memory cells 112 in the memory cell array 110AR is coupled to a corresponding circuit 114 in the LIO circuit 110BS.

[0030] Memory 112 is shown in memory banks 110U and 110L of memory partition 102A. For ease of illustration, memory 112 is not shown in memory banks 110U and 110L of memory partitions 102B, 102C, and 102D. Memory 112 is an electrical, electromechanical, electromagnetic, or other device configured to store bit data represented by logical states. At least one logical state of memory 112 can be programmed in a write operation and detected in a read operation. In some embodiments, the logical state corresponds to the voltage level of the charge stored in a given memory 112. In some embodiments, the logical state corresponds to the physical characteristics of a component of a given memory 112, such as voltage, current, resistance, or magnetic direction.

[0031] In some embodiments, memory 112 includes one or more single-port (SP) static random-access memory (SRAM) cells. In some embodiments, memory 112 includes one or more dual-port (DP) SRAM cells. In some embodiments, memory 112 includes one or more multi-port (MP) SRAM cells. In some embodiments, memory 112 includes one or more SRAM cells, including complementary FET (CFET) transistors. Different types of memory cells in memory 112 are all within the scope of this disclosure. In some embodiments, memory 112 includes one or more dynamic random-access memory (DRAM) cells. In some embodiments, memory 112 includes one or more one-time programmable (OTP) memories, such as electronic fuse or antifuse devices, flash memory, random-access memory (RAM), resistive RAM, ferroelectric RAM, magnetoresistive RAM, rewritable programmable read-only memory (EPROM), electronically rewritable programmable read-only memory (EEPROM), etc. In some embodiments, memory 112 is an OTP memory containing one or more OTP memory cells.

[0032] Other configurations of the memory circuit 100 are also within the scope of this disclosure.

[0033] Figure 2 is a circuit diagram of a corresponding memory cell 200 in Figure 1, according to some embodiments.

[0034] Figure 2 is a circuit diagram of the memory cell 200 of Figure 1, according to some embodiments.

[0035] The memory cell 200 can be used as one or more memory cells MCBs in at least one of the memory cell array 110AR of Figure 1 or the memory cell 112 of Figure 1.

[0036] Memory cell 200 is a six-transistor (ST) single-port (SP) SRAM memory cell. In some embodiments, memory cell 200 employs a number of transistors other than six. Other types of memory are also within the scope of the various embodiments.

[0037] The memory cell 200 includes P-field-effect transistors (PFET transistors) PU1 and PU2, as well as NFET transistors PD1, PD2, PG1, and PG2.

[0038] PFET transistors PU1 and PU2, together with NFET transistors PD1 and PD2, form a cross-latch or a pair of cross-coupled inverters. For example, PFET transistors PU1 and PD1 form a first inverter, while PFET transistors PU2 and PD2 form a second inverter.

[0039] The source terminals of PFET transistors PU1 and PU2 are both configured as voltage supply nodes NODE_1. Each voltage supply node NODE_1 is connected to the first voltage source VDD.

[0040] The drain terminals of PFET transistor PU1, the drain terminals of NFET transistor PD1, the gate terminals of PFET transistor PU2, the gate terminals of NFET transistor PD2, and the source terminals of NFET transistor PG1 are all connected together and configured as a storage node NDB.

[0041] The drain terminals of PFET transistor PU2, the drain terminals of NFET transistor PD2, the gate terminals of PFET transistor PU1, the gate terminals of NFET transistor PD1, and the source terminals of NFET transistor PG2 are all connected together and configured as storage node ND.

[0042] The source terminals of each NFET transistor PD1 and NFET transistor PD2 are configured as a power reference voltage node (unlabeled) with a reference voltage source VSS. The source terminals of each NFET transistor PD1 and NFET transistor PD2 are also coupled to the reference voltage source VSS.

[0043] The word line WL is coupled to the gate terminals of each NFET transistor PG1 and NFET transistor PG2. The word line WL is also called the write control line because the NFET transistors PG1 and PG2 are configured to be controlled by signals on the word line WL to transfer data between the bit line BLB / bit line BL and the corresponding nodes NDB / ND.

[0044] In some embodiments, the signal of the word line WL is equal to the voltage source VDD. In some embodiments, when the signal of the word line WL is equal to the voltage source VDD, NFET transistors PG1 and PG1 are turned on.

[0045] The drain terminal of NFET transistor PG1 is coupled to bit line BLB. The drain terminal of NFET transistor PG2 is connected to bit line BL.

[0046] Bit line BL and bit line BLB are configured as data input and output for memory cell 200. In some embodiments, during a write operation, applying a logic value to bit line BL and applying an opposite logic value to bit line BLB enables the logic value on the bit line to be written to memory cell 200.

[0047] Each bit line BL and bit line BLB is called a "data line" because the data carried on the bit line BL and bit line BLB is written to the corresponding node ND and node NDB, and read from the corresponding node ND and node NDB.

[0048] Other configurations of memory unit 200 are also within the scope of this disclosure.

[0049] Figures 3A to 3D are corresponding diagrams of corresponding portions 300A, 300B, 300C, and 300D of the layout design 300 of the corresponding integrated circuit according to some embodiments.

[0050] Layout design 300 is the layout of the integrated circuit 400 or memory cell 200 in Figures 4A to 4F. Layout design 300 is the layout of the memory cell 200 in Figure 2.

[0051] Part 300A includes one or more features of layout design 300, including an active layer or oxide diffusion (OD) layer, a gate (POLY or PO) layer, a cut gate or cut POLY (CPOLY or CPO) layer, a metal overdiffusion (MD) layer, a metal overdiffusion local interconnect (MDLI) layer, a via on gate (VG) layer, a via overdiffusion (VD) layer, and a metal 0 (MO) layer.

[0052] Part 300B includes one or more features of a layout design 300 including an OD layer, a POLY layer, a CPO layer, a back-side metal diffusion (BMD) layer, an MDLI layer, a back-side via gate (BVG) layer, a back-side via diffusion (BVD) layer, and a back-side metal O (BM0) layer.

[0053] Part 300C includes one or more features of the VG layer, VD layer, and M0 layer of layout design 300.

[0054] Part of 300D includes one or more features of the layout design 300, including BVG layer, BVD layer and BMO layer.

[0055] Figures 3A to 3D are the corresponding diagrams of the corresponding parts 300A, 300B, 300C and 300D of the layout design 300, and have been simplified for ease of explanation.

[0056] For ease of illustration, certain elements marked in one or more of Figures 1 to 9G and Figures 11A to 11I are not marked in one or more of Figures 1 to 9G and Figures 11A to 11I. In some embodiments, layout design 300 includes additional elements not shown in Figures 3A to 3D. Layout design 300 includes one or more features of OD layer, POLY layer, CPO layer, MD layer, MDLI layer, VG layer, VD layer, MO layer, BMD layer, BVG layer, BVD layer, and BMO layer.

[0057] In some embodiments, at least layout design 300 or layout design 700 in Figures 3A to 3D or Figures 7A to 7D, or at least integrated circuits 400, 500, 600, 800, 900, or 1100 in Figures 4A to 4F, 5A to 5F, 6A to 6D, 8A to 8D, 9A to 9G, or 11A to 11I, include additional elements not shown in one or more of Figures 3A to 3D, 4A to 4F, 5A to 5F, 6A to 6D, 7A to 7D, 8A to 8D, 9A to 9G, or 11A to 11I.

[0058] The layout design 300 can be used to manufacture the integrated circuits 400 of Figures 4A to 4F.

[0059] Part 300A is the layout of part 400A of integrated circuit 400 in Figure 4A, part 300B is the layout of part 400B of integrated circuit 400 in Figure 4B, part 300C is the layout of part 400C of integrated circuit 400 in Figure 4C, and part 300D is the layout of part 400D of integrated circuit 400 in Figure 4D. For the sake of brevity, similar detailed descriptions are omitted.

[0060] Layout design 300 includes unit 301. Unit 301 has unit boundaries 301a and 301b extending along a first direction X, and unit boundaries 301c and 301d extending along a second direction Y. In some embodiments, at least one of the first direction X, the second direction Y, or the third direction Z is different from another of the first direction X, the second direction Y, or the third direction Z. In some embodiments, layout design 300 is adjacent to other unit layout designs (not shown) along unit boundaries 301c and 301d. In some embodiments, layout design 300 is adjacent to other unit layout designs (not shown) along unit boundaries 301a and 301b extending in the first direction X. In some embodiments, layout design 300 is a single-height standard unit. In some embodiments, unit 301 may be used to manufacture unit 401.

[0061] In some embodiments, cell 301 is a standard cell, and layout design 300 corresponds to the layout of the standard cell defined by cell boundaries 301a, 301b, 301c, and 301d. In some embodiments, cell 301 is a predefined portion of layout design 300, including one or more transistors and electrical connections configured to perform one or more circuit functions. In some embodiments, cell 301 is surrounded by cell boundaries 301a, 301b, 301c, and 301d, and therefore corresponds to a region of a functional circuit component or device that is part of a standard cell. In some embodiments, layout design 300 is a layout design of a memory cell, such as memory cell 200 in Figure 2.

[0062] The layout design 300 includes one or more active region layout patterns 302a or 302b (collectively referred to as "active region pattern group 302") extending along the second direction Y, or one or more active region layout patterns 304a or 304b (collectively referred to as "active region pattern group 304").

[0063] The embodiments disclosed herein use the term "layout pattern," and for the sake of brevity, it will also be referred to as "pattern" in the remainder of this disclosure.

[0064] Active region pattern group 302 is located above active region pattern group 304.

[0065] Active region patterns 302a and 302b of active region pattern group 302 are separated from each other in the first direction X. Active region patterns 304a and 304b of active region pattern group 304 are separated from each other in the first direction X.

[0066] Active region patterns 302a and 304a are separated from each other in the third direction Z. Active region patterns 302b and 304b are separated from each other in the third direction Z.

[0067] The active area pattern group 302 can be used to manufacture corresponding active area groups 402 for integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100. This active area pattern group 304 can be used to manufacture corresponding active area groups 404 for integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100.

[0068] In some embodiments, at least one of the active region groups 402 or 404 is located on the front side 403a of integrated circuit 100, integrated circuit 200, integrated circuit 400, integrated circuit 500, integrated circuit 600, integrated circuit 800, integrated circuit 900, or integrated circuit 1100. In some embodiments, at least one of the active region groups 402 or 404 corresponds to the source and drain regions of one or more complementary FET (CFET) transistors. In some embodiments, at least one of the active region groups 402 or 404 corresponds to the source and drain regions of one or more nanosheet transistors or nanowire transistors. Other transistor types are also within the scope of this disclosure. In some embodiments, at least one of the active region groups 402 or 404 corresponds to the source and drain regions of one or more finFET transistors.

[0069] In some embodiments, active region patterns 302a and 302b can be used to manufacture corresponding active regions 402a and 402b in active region group 402 of integrated circuit 100, integrated circuit 200, integrated circuit 400, integrated circuit 500, integrated circuit 600, integrated circuit 800, integrated circuit 900, or integrated circuit 1100. In some embodiments, active region patterns 304a and 304b can be used to manufacture corresponding active regions 404a and 404b in active region group 404 of integrated circuit 100, integrated circuit 200, integrated circuit 400, integrated circuit 500, integrated circuit 600, integrated circuit 800, integrated circuit 900, or integrated circuit 1100.

[0070] In some embodiments, active region pattern group 302 and active region pattern group 304 are referred to as oxide diffusion (OD) regions, which define at least the source or drain diffusion regions of integrated circuit 100, integrated circuit 200, integrated circuit 400, integrated circuit 500, integrated circuit 600, integrated circuit 800, integrated circuit 900 or integrated circuit 1100 or layout design 300.

[0071] In some embodiments, active region patterns 302a and 302b can be used to fabricate the source and drain regions of NFET transistors in integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100, and active region patterns 304a and 304b can be used to fabricate the source and drain regions of PFET transistors in integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100.

[0072] In some embodiments, active region patterns 302a and 302b can be used to fabricate the source and drain regions of PFET transistors in integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100, and active region patterns 304a and 304b can be used to fabricate the source and drain regions of NFET transistors in integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100.

[0073] In some embodiments, active region pattern group 302 or active region pattern group 304 is located in the first layout layer. In some embodiments, the first layout layer corresponds to an effective level or OD layer of layout design 300 or one or more of integrated circuits 100, 200, 400, 500, 600, 800, 900 or 1100.

[0074] The number of other configurations, arrangements, or patterns on other layout layers in active area pattern group 302 or active area pattern group 304 is within the scope of this disclosure.

[0075] The layout design 300 also includes one or more gate patterns 306a or 306b (collectively referred to as "gate pattern group 306") extending along the first direction X, and one or more gate patterns 308a or 308b (collectively referred to as "gate pattern group 308").

[0076] Gate pattern group 306 is located above gate pattern group 308.

[0077] In some embodiments, gate patterns 306a and 308a are separated from each other in the third direction Z. In some embodiments, gate patterns 306b and 308b are separated from each other in the third direction Z.

[0078] Gate pattern group 306 can be used to manufacture corresponding gate groups 406 for integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100. Gate pattern group 308 can be used to manufacture corresponding gate groups 408 for integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100.

[0079] In some embodiments, gate pattern 306a or gate pattern 306b can be used to manufacture corresponding gate 406a or gate 406b in gate group 406 of integrated circuit 100, integrated circuit 200, integrated circuit 400, integrated circuit 500, integrated circuit 600, integrated circuit 800, integrated circuit 900, or integrated circuit 1100. In some embodiments, gate pattern 308a or gate pattern 308b can be used to manufacture corresponding gate 408a or gate 408b in gate group 408 of integrated circuit 100, integrated circuit 200, integrated circuit 400, integrated circuit 500, integrated circuit 600, integrated circuit 800, integrated circuit 900, or integrated circuit 1100.

[0080] In some embodiments, at least one of the gate group 406 or gate group 408 is located on the front side 403a of the integrated circuit 100, integrated circuit 200, integrated circuit 400, integrated circuit 500, integrated circuit 600, integrated circuit 800, integrated circuit 900 or integrated circuit 1100.

[0081] In some embodiments, Figures 3A through 3D show each gate pattern in gate pattern group 306 and gate pattern group 308, labeled “PD1, PU1, PD2, PU2, PG1, PG2, X1, X2” to identify the corresponding transistor in the second figure made from the gate patterns in Figures 3A through 3D, and omitted for brevity.

[0082] In some embodiments, at least one of labels X1 or X2 is a corresponding dummy transistor on the back side of layout design 300. In some embodiments, the dummy transistor is a non-functional transistor. In some embodiments, the dummy transistor is a transistor whose source and / or drain are replaced by a corresponding insulating region (e.g., insulating region 480a in Figure 6C).

[0083] In some embodiments, gate pattern group 306 or gate pattern group 308 encapsulates active region pattern group 302 and active region pattern group 304. In some embodiments, at least a portion of gate pattern group 306 or gate pattern group 308 is located above active region pattern group 302 and active region pattern group 304. In some embodiments, at least another portion of gate pattern group 306 or gate pattern group 308 is located below active region pattern group 302 and active region pattern group 304.

[0084] Gate pattern group 306 or gate pattern group 308 is located on the second layout layer. In some embodiments, the second layout layer is different from the first layout layer. In some embodiments, the second layout layer corresponds to a POLY layer (also called a PO layer or MG layer) of one or more of layout design 300 or layout design 700 or integrated circuit 100, integrated circuit 200, integrated circuit 400, integrated circuit 500, integrated circuit 600, integrated circuit 800, integrated circuit 900 or integrated circuit 1100. In some embodiments, the POLY layer is above the BMD layer and the BMO layer.

[0085] The number of other configurations, arrangements or patterns on other layout layers in gate pattern group 306 or gate pattern group 308 is within the scope of this disclosure.

[0086] The layout design 300 also includes one or more cutting feature patterns 340a, 340b, 340c or 340d (collectively referred to as "cutting feature pattern group 340") extending along the second direction Y.

[0087] The cutting feature pattern group 340 is located above the gate pattern group 306 or the gate pattern group 308.

[0088] At least one of the cutting feature patterns 340a, 340b, 340c or 340d is separated from the other of the cutting feature patterns 340a, 340b, 340c or 340d in at least one of the first direction X or the second direction Y.

[0089] In some embodiments, the cut feature pattern group 340 overlaps with at least a portion of the gate pattern of the gate pattern group 306 or the gate pattern group 308. In some embodiments, the cut feature pattern group 340 overlaps with other underlying patterns (not shown) of other layout layers of the layout design 300 (e.g., BMO, BMD, Active, MD, etc.).

[0090] In some embodiments, cutting feature patterns 340a, 340b, 340c, or 340d are identified at corresponding positions of the removed gate portions 440a, 440b, 440c, or 440d in the removed gate portion group 440 that were removed during operation 1004 of methods 1000A to 1000B (Figures 10A to 10B).

[0091] In some embodiments, the cutting feature pattern 340b can be used to separate gate 406b2 and gate 406b1 from each other. In some embodiments, the cutting feature pattern 340b can be used to separate gate 408b2 and gate 408b1 from each other.

[0092] In some embodiments, the cutting feature pattern 340c can be used to separate gate 406a2 and gate 406a1 from each other. In some embodiments, the cutting feature pattern 340c can be used to separate gate 408a2 and gate 408a1 from each other.

[0093] In some embodiments, the cutting feature pattern group 340 is referred to as a "cut metal gate (CMG) pattern group". In some embodiments, cutting feature patterns 340b and 340c are referred to as having a "zigzag shape". In some embodiments, cutting feature pattern 340b is offset from cutting feature pattern 340c in the second direction Y, thereby forming a "zigzag shape". In some embodiments, the side portion of cutting feature pattern 340b is not aligned with the side portion of cutting feature pattern 340c in the second direction Y. In some embodiments, a single side portion of cutting feature pattern 340b is aligned with a single side portion of cutting feature pattern 340c in the second direction Y.

[0094] Other configurations in the cutting feature pattern group 340, arrangements on other layout layers, or the number of patterns are all within the scope of this disclosure. In some embodiments, at least one cutting feature pattern in the cutting feature pattern group 340 is not included in the layout design 300.

[0095] The cutting feature pattern group 340 is located on the second layout layer.

[0096] Other configurations in the cutting feature pattern group 340, arrangements on other layout layers, or the number of patterns are all within the scope of this disclosure.

[0097] The layout design 300 also includes one or more contact patterns 310a, 310b, 310c, and 310d (collectively referred to as "contact pattern group 310") extending along the first direction X.

[0098] Each contact pattern in the contact pattern group 310 is spaced apart from the adjacent contact pattern in the contact pattern group 310 at least in the first direction X or the second direction Y.

[0099] Contact pattern group 310 can be used to manufacture corresponding contact group 410 for integrated circuit 100, integrated circuit 200, integrated circuit 400, integrated circuit 500, integrated circuit 600, integrated circuit 800, integrated circuit 900 or integrated circuit 1100.

[0100] In some embodiments, contact patterns 310a, 310b, 310c, and 310d of contact pattern group 310 can be used to manufacture corresponding contacts 410a, 410b, 410c, and 410d of contact pattern group 410. In some embodiments, contact pattern group 310 is also referred to as metal diffusion (MD) pattern group.

[0101] In some embodiments, at least one of the contact patterns 310a, 310b, 310c, and 310d in the contact pattern group 310 can be used to manufacture the source or drain terminal of an NFET for an integrated circuit 100, integrated circuit 200, integrated circuit 400, integrated circuit 500, integrated circuit 600, integrated circuit 800, integrated circuit 900, or integrated circuit 1100.

[0102] In some embodiments, at least one of the contact patterns 310a, 310b, 310c, and 310d in the contact pattern group 310 can be used as the source or drain terminal of a PFET transistor in the fabrication of integrated circuit 100, integrated circuit 200, integrated circuit 400, integrated circuit 500, integrated circuit 600, integrated circuit 800, integrated circuit 900, or integrated circuit 1100.

[0103] In some embodiments, contact pattern 310a can be used to manufacture the source / drain terminals of NFET transistor PD1, contact pattern 310b can be used to manufacture the source / drain terminals of NFET transistor PG1, contact pattern 310c can be used to manufacture the source / drain terminals of NFET transistor PG2, and contact pattern 310d can be used to manufacture the source / drain terminals of NFET transistor PD2.

[0104] In some embodiments, contact pattern group 310 overlaps with active area pattern group 302 or active area pattern group 304. This group of contact patterns 310 is located in a third layout layer. In some embodiments, the third layout layer corresponds to a contact layer or MD layer of layout design 300 or one or more of integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100. In some embodiments, the third layout layer differs from at least one of the first or second layout layers. Other configurations in contact pattern group 310, arrangements on other layout layers, or the number of patterns are all within the scope of this disclosure.

[0105] The layout design 300 also includes one or more contact patterns 312a, 312b, 312c, and 312d (collectively referred to as "contact pattern group 312") extending along the first direction X.

[0106] Each contact pattern in the contact pattern group 312 is spaced apart from the adjacent contact pattern in the contact pattern group 312 at least in the first direction X or the second direction Y.

[0107] These contact patterns 310 and 312 are separated from each other in the third direction Z.

[0108] In some embodiments, contact patterns 310a and 312a are separated from each other in the third direction Z. In some embodiments, contact patterns 310b and 312b are separated from each other in the third direction Z. In some embodiments, contact patterns 310c and 312c are separated from each other in the third direction Z. In some embodiments, contact patterns 310d and 312d are separated from each other in the third direction Z.

[0109] Contact pattern group 312 can be used to manufacture corresponding contact group 412 for integrated circuit 100, integrated circuit 200, integrated circuit 400, integrated circuit 500, integrated circuit 600, integrated circuit 800, integrated circuit 900 or integrated circuit 1100.

[0110] In some embodiments, contact patterns 312a, 312b, 312c, and 312d in contact pattern group 312 can be used to manufacture corresponding contacts 412a, 412b, 412c, and 412d in contact member group 412. In some embodiments, contact member group 412 is located on the front side 403a of integrated circuit 400. In some embodiments, other layers (e.g., back-side layers) can access contact member group 412 from the back side 403b of integrated circuit 400. In some embodiments, the back side 403b of integrated circuit 400 is opposite to the front side of integrated circuit 400. In some embodiments, contact pattern group 312 is also referred to as back-side MD (BMD) pattern group.

[0111] In some embodiments, contact pattern 312a can be used to manufacture the source / drain terminals of PFET transistor PU1, contact pattern 312b can be used to manufacture the source / drain terminals of PFET transistor X1, contact pattern 312c can be used to manufacture the source / drain terminals of PFET transistor X2, and contact pattern 312d can be used to manufacture the source / drain terminals of PFET transistor PU2.

[0112] In some embodiments, at least one of the PFET transistor X1 or PFET transistor X2 is a corresponding dummy transistor.

[0113] In some embodiments, the contact pattern group 312 overlaps with the active area pattern group 302 or the active area pattern group 304. This group of contact patterns 312 is located in a fourth layout layer. In some embodiments, the fourth layout layer corresponds to the back-side contact layer or back-side MD (BMD) layer of layout design 300 or one or more of integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100. In some embodiments, the fourth layout layer differs from at least one of the first, second, or third layout layers.

[0114] In some embodiments, the BMD layer is above the BMO layer. In some embodiments, the BMD layer is located below the back side 403b of the integrated circuit 400. In some embodiments, the BMD layer is below the OD layer, POLY layer, MD layer, and MO layer.

[0115] Other configurations in contact pattern group 312, arrangements on other layout layers, or the number of patterns are all within the scope of this disclosure.

[0116] The layout design 300 also includes one or more contact patterns 314a and 314b (collectively referred to as "contact pattern group 314") extending along the second direction Y.

[0117] Each contact pattern in the contact pattern group 314 is spaced apart from the adjacent contact pattern in the contact pattern group 314 at least in the first direction X or the second direction Y.

[0118] In some embodiments, contact pattern group 314 is located between contact pattern group 310 and contact pattern group 312. Contact pattern 314a is located between contact pattern 310a and contact pattern 310b. Contact pattern 314a is located between contact pattern 312a and contact pattern 312b. Contact pattern 314b is located between contact pattern 310c and contact pattern 310d. Contact pattern 314b is located between contact pattern 312c and contact pattern 312d.

[0119] In some embodiments, contact pattern 314a includes one or more individual discontinuous patterns. In some embodiments, contact pattern 314b includes one or more individual discontinuous patterns.

[0120] Contact patterns 314a and 314b are separated from each other in the first direction X.

[0121] Contact pattern group 314 can be used to manufacture corresponding contact group 414 for integrated circuit 100, integrated circuit 200, integrated circuit 400, integrated circuit 500, integrated circuit 600, integrated circuit 800, integrated circuit 900 or integrated circuit 1100.

[0122] In some embodiments, contact patterns 314a and 314b of contact pattern group 314 can be used to manufacture corresponding contacts 414a and 414b of contact member group 414. In some embodiments, contact member group 414 is located on the front side 403a of integrated circuit 400. In some embodiments, contact pattern group 314 is also referred to as local interconnect (MDLI) pattern group.

[0123] In some embodiments, at least one contact pattern 314a or contact pattern 314b in the contact pattern group 314 can be used to manufacture an interconnect structure that can be used to connect the source or drain terminals of one of the NFET or PFET transistors of the integrated circuit 100, integrated circuit 200, integrated circuit 400, integrated circuit 500, integrated circuit 600, integrated circuit 800, integrated circuit 900 or integrated circuit 1100.

[0124] In some embodiments, contact pattern 314a can be used to fabricate the drain / source terminals of NFET transistor PD1, NFET transistor PG1, PFET transistor PU1, and PFET transistor X1.

[0125] In some embodiments, contact pattern 314a corresponds to node NDB in Figure 2, and similar detailed descriptions are omitted for brevity.

[0126] In some embodiments, contact pattern 314b can be used to fabricate the drain / source terminals of NFET transistor PG2, NFET transistor PD2, PFET transistor X2, and PFET transistor PU2.

[0127] In some embodiments, contact pattern 314b corresponds to node ND of Figure 2, and similar detailed descriptions are omitted for brevity.

[0128] In some embodiments, at least a first portion of the contact pattern group 314 overlaps with one or more of the active region pattern groups 302 or 304. In some embodiments, at least a second portion of the contact pattern group 314 is located between the active region pattern groups 302 or 304. In some embodiments, at least a third portion of the contact pattern group 314 is coplanar with the contact pattern group 310 or 312.

[0129] Contact pattern group 314 is located in the fifth layout layer. In some embodiments, the fifth layout layer corresponds to the MDLI layer of layout design 300 or one or more of integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100. In some embodiments, the fifth layout layer is different from at least one of the first or second layout layers.

[0130] In some embodiments, the MDLI layer includes an MD layer and a BMD layer. In some embodiments, the MDLI layer is lower than the M0 layer. In some embodiments, the MDLI layer is higher than the BMO layer.

[0131] Other configurations in contact pattern group 314, arrangements on other layout layers, or the number of patterns are all within the scope of this disclosure.

[0132] The layout design 300 also includes one or more conductive feature patterns 330a, 330b, 330c, 330d, and 330e (collectively referred to as "conductive feature pattern group 330") extending along the second direction Y.

[0133] Each conductive feature pattern in the conductive feature pattern group 330 is spaced apart from another conductive feature pattern in the conductive feature pattern group 330 in the first direction X.

[0134] The conductive feature pattern group 330 overlaps with at least one of the active region pattern group 302 or active region pattern group 304, gate pattern group 306 or gate pattern group 308, or contact pattern group 310, contact pattern group 312 or contact pattern group 314.

[0135] The conductive feature pattern group 330 can be used to manufacture corresponding conductor groups 430 of integrated circuit 100, integrated circuit 200, integrated circuit 400, integrated circuit 500, integrated circuit 600, integrated circuit 800, integrated circuit 900 or integrated circuit 1100. Conductive feature patterns 330a, 330b, 330c, 330d, and 330e can be used to manufacture corresponding conductors 430a, 430b, 430c, 430d, and 430e of integrated circuit 100, integrated circuit 200, integrated circuit 400, integrated circuit 500, integrated circuit 600, integrated circuit 800, integrated circuit 900 or integrated circuit 1100. In some embodiments, at least one conductor in the conductor group 430 is located on the front side 403a of the integrated circuit 100, integrated circuit 200, integrated circuit 400, integrated circuit 500, integrated circuit 600, integrated circuit 800, integrated circuit 900 or integrated circuit 1100.

[0136] In some embodiments, the conductive feature pattern group 330 is located in the sixth layout layer. In some embodiments, the sixth layout layer differs from at least one of the first, second, third, fourth, or fifth layout layers. In some embodiments, the sixth layout layer corresponds to the MO layer of layout design 300 or one or more of integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100. In some embodiments, the MO layer is higher than the OD layer, POLY layer, MD layer, BMD layer, MDLI layer, and BMO layer.

[0137] In some embodiments, the conductive feature pattern group 330 corresponds to five M0 wiring tracks. Other numbers of M0 wiring tracks are also within the scope of this disclosure.

[0138] Other configurations in the conductive feature pattern group 330, arrangements on other layout layers, or the number of patterns are all within the scope of this disclosure.

[0139] The layout design 300 also includes one or more conductive feature patterns 332a, 332b, 332c, 332d, and 332e (collectively referred to as "conductive feature pattern group 332") extending along the first direction X.

[0140] Each conductive feature pattern in the conductive feature pattern group 332 is spaced apart from another conductive feature pattern in the conductive feature pattern group 332 in at least one of the first direction X or the second direction Y.

[0141] The conductive feature pattern group 332 overlaps with at least one of the active region pattern group 302 or active region pattern group 304, gate pattern group 306 or gate pattern group 308, contact pattern group 310, contact pattern group 312 or contact pattern group 314, or conductive feature pattern group 330.

[0142] Conductive feature pattern group 330 and conductive feature pattern group 332 are separated from each other in the third direction Z. In some embodiments, conductive feature pattern 330a is separated from at least one of conductive feature pattern 332a or conductive feature pattern 332b in the third direction Z. In some embodiments, conductive feature pattern 330c and conductive feature pattern 332c are separated from each other in the third direction Z. In some embodiments, conductive feature pattern 330e is separated from at least one of conductive feature pattern 332d or conductive feature pattern 332e in the third direction Z.

[0143] This conductive feature pattern group 332 can be used to manufacture corresponding conductor groups 432 for integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100. Conductive feature patterns 332a, 332b, 332c, 332d, and 332e can be used to manufacture corresponding conductors 432a, 432b, 432c, 432d, and 432e for integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100. In some embodiments, at least one conductor in the conductor group 432 is located on the back side 403b of the integrated circuit 100, integrated circuit 200, integrated circuit 400, integrated circuit 500, integrated circuit 600, integrated circuit 800, integrated circuit 900 or integrated circuit 1100.

[0144] In some embodiments, the conductive feature pattern group 332 is located in the seventh layout layer. In some embodiments, the seventh layout layer differs from at least one of the first, second, third, fourth, fifth, or sixth layout layers. In some embodiments, the seventh layout layer corresponds to the BMO layer of layout design 300 or one or more of integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100. In some embodiments, the BMO layer is below the OD layer, POLY layer, MD layer, BMD layer, MDLI layer, and BMO layer.

[0145] In some embodiments, the conductive feature pattern group 332 corresponds to three BMO wiring tracks. Other numbers of BMO wiring tracks are also within the scope of this disclosure.

[0146] In some embodiments, conductive feature pattern 330c can be used as a first mating side contact pattern on the front side of layout design 300, and conductive feature pattern 332c can be used as a second mating side contact pattern on the back side of layout design 300, thereby improving wiring resources and reducing area compared with other methods.

[0147] Other configurations in the conductive feature pattern group 332, arrangements on other layout layers, or the number of patterns are all within the scope of this disclosure.

[0148] The layout design 300 also includes one or more through-hole patterns 320a, 320b, 320c, 320d, and 320e (collectively referred to as "through-hole pattern group 320").

[0149] The via pattern group 320 can be used to manufacture corresponding via groups 420 for integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100. In some embodiments, via patterns 320a, 320b, 320c, 320d, and 320e in the via pattern group 320 can be used to manufacture corresponding vias 420a, 420b, 420c, 420d, and 420e in the via group 420 for integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100.

[0150] In some embodiments, the through-hole pattern group 320 is located between the contact pattern group 310 and the conductive feature pattern group 330.

[0151] The through-hole pattern 320a is located between the contact pattern 310a and the conductive feature pattern 330a.

[0152] The through-hole pattern 320b is located between the contact pattern 310b and the conductive feature pattern 330b.

[0153] The through-hole pattern 320c is located between the contact pattern 310c and the conductive feature pattern 330d.

[0154] The through-hole pattern 320d is located between the contact pattern 310d and the conductive feature pattern 330e.

[0155] The through-hole pattern 320e is located between the contact pattern 314b and the conductive feature pattern 330c.

[0156] Via pattern group 320 is located in a via over-diffusion (VD) layer of one or more layout designs 300 or integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100. In some embodiments, the VD layer is above the OD layer, POLY layer, MD layer, BMD layer, MDLI layer, and BMO layer. In some embodiments, the VD layer is below the MO layer. In some embodiments, the VD layer is located between the MD layer and the MO layer. In some embodiments, the VD layer is located between the third layout layer and the sixth layout layer. Other layout layers are also within the scope of this disclosure.

[0157] At least the other configurations in the through-hole pattern group 320, the arrangement on other layout layers, or the number of patterns are all within the scope of this disclosure.

[0158] The layout design 300 also includes one or more through-hole patterns 322a, 322b, and 322c (collectively referred to as "through-hole pattern group 322").

[0159] The via pattern group 322 can be used to manufacture corresponding via groups 422 of integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100. In some embodiments, via patterns 322a, 322b, and 322c in the via pattern group 322 can be used to manufacture corresponding vias 422a, 422b, and 422c in the via group 422 of integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100.

[0160] In some embodiments, the through-hole pattern group 322 is located between the contact pattern group 312 and the conductive feature pattern group 332.

[0161] The through-hole pattern 322a is located between the contact pattern 312a and the conductive feature pattern 332b.

[0162] The through-hole pattern 322b is located between the contact pattern 312d and the conductive feature pattern 332d.

[0163] The through-hole pattern 322c is located between the contact pattern 314a and the conductive feature pattern 332c.

[0164] Via pattern group 322 is located on the back-side via over-diffusion (BVD) layer of one or more layout designs 300 or integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100. In some embodiments, the BVD layer is below the OD layer, POLY layer, MD layer, BMD layer, and MO layer. In some embodiments, the BVD layer is above the BMO layer. In some embodiments, the BVD layer is between the BMD layer and the BMO layer. In some embodiments, the BVD layer is located between the fourth layout layer and the seventh layout layer. Other layout layers are also within the scope of this disclosure.

[0165] At least the other configurations in the through-hole pattern group 322, the arrangement or number of patterns on other layout layers are all within the scope of this disclosure.

[0166] The layout design 300 also includes one or more through-hole patterns 324a (collectively referred to as "through-hole pattern group 324").

[0167] The via pattern group 324 can be used to manufacture corresponding via groups 424 of integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100. In some embodiments, the via pattern 324a in the via pattern group 324 can be used to manufacture corresponding vias 424a in the via group 424 of integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100.

[0168] In some embodiments, the via pattern group 324 is located between the gate pattern group 306 and the conductive feature pattern group 330. The via pattern 324a is located between the gate pattern 306a and the conductive feature pattern 330c.

[0169] The via pattern group 324 is located on the gate-on-gate (VG) layer of one or more layout designs 300 or integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100. In some embodiments, the VG layer is above the OD layer, POLY layer, MD layer, MDLI layer, BMD layer, and BMO layer. In some embodiments, the VG layer is below the M0 layer. In some embodiments, the VG layer is located between the POLY layer and the M0 layer. In some embodiments, the VG layer is located between the second layout layer and the sixth layout layer. Other layout layers are also within the scope of this disclosure.

[0170] At least the other configurations in the through-hole pattern group 324, the arrangement on other layout layers, or the number of patterns are all within the scope of this disclosure.

[0171] The layout design 300 also includes one or more through-hole patterns 326a, 326b, and 326c (collectively referred to as "through-hole pattern group 326").

[0172] The via pattern group 326 can be used to manufacture corresponding via groups 426 for integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100. In some embodiments, via patterns 326a, 326b, and 326c in the via pattern group 326 can be used to manufacture corresponding vias 426a, 426b, and 426c in the via group 426 for integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100.

[0173] In some embodiments, the through-hole pattern group 326 is located between the gate pattern group 308 and the conductive feature pattern group 332.

[0174] The through-hole pattern 326a is located between the gate pattern 308b and the conductive feature pattern 332a.

[0175] The through-hole pattern 326b is located between the gate pattern 308a and the conductive feature pattern 332e.

[0176] The through-hole pattern 326c is located between the gate pattern 308b and the conductive feature pattern 332c.

[0177] The via pattern group 326 is located in the back-side gate via (BVG) layer of one or more layout designs 300 or integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100. In some embodiments, the BVG layer is below the OD layer, POLY layer, MD layer, MDLI layer, BMD layer, and MO layer. In some embodiments, the BVG layer is above the BMO layer. In some embodiments, the BVG layer is located between the POLY layer and the BMO layer. In some embodiments, the BVG layer is located between the second layout layer and the seventh layout layer. Other layout layers are also within the scope of this disclosure.

[0178] At least the other configurations in the through-hole pattern group 326, the arrangement on other layout layers, or the number of patterns are all within the scope of this disclosure.

[0179] In some embodiments, the cutting feature pattern 340b can be used to separate gates 406b2 and 406b1 from each other, and can also be used to separate gates 408b2 and 408b1 from each other. In some embodiments, the cutting feature pattern 340c can be used to separate gates 406a2 and 406a1 from each other, and can also be used to separate gates 408a2 and 408a1 from each other.

[0180] In some embodiments, by including a cutting feature pattern group 340 in the layout design 300, the cutting feature pattern 340b is deviated from the cutting feature pattern 340c in the second direction Y, thereby causing the positions where gates 406b2 / 408b2 and gates 406b1 / 408b1 are separated from each other in the second direction Y to be different from the positions where gates 406a2 / 408a2 and gates 406a1 / 408a1 are separated from each other.

[0181] In some embodiments, by separating gates 406b2 / 408b2 and 406b1 / 408b1 at positions different from the separation positions of gates 406a2 / 408a2 and 406a1 / 408a1, conductive feature pattern 330c can be used as a first mating side contact pattern on the front side of layout design 300, and conductive feature pattern 332c can be used as a second mating side contact pattern on the back side of layout design 300, thereby improving the wiring resources of layout design 300 and reducing the area of ​​layout design 300 compared with other methods.

[0182] In some embodiments, by using conductive feature pattern 330c as the first mating side contact pattern on the front side of layout design 300 and using conductive feature pattern 332c as the second mating side contact pattern on the back side of layout design 300, at least one of conductive feature pattern 330c or conductive feature pattern 332c has a simpler design than other methods that have a more complex L-shape and use at least one additional mask.

[0183] Other configurations in layout design 300, and the number of arrangements or patterns on other layout layers, are all within the scope of this disclosure.

[0184] Figures 4A through 4F are diagrams of an integrated circuit 400 according to some embodiments.

[0185] Figures 4A to 4F are corresponding diagrams of the corresponding parts 400A, 400B, 400C, 400D, and 400F of the integrated circuit 400, which have been simplified for ease of explanation.

[0186] Part 400A includes one or more characteristics of the OD layer, POLY layer, CPO layer, MD layer, MDLI layer, VG layer, VD layer, and M0 layer of integrated circuit 400. Part 400A is manufactured from Part 300A.

[0187] Part 400B includes one or more characteristics of the OD layer, POLY layer, CPO layer, BMD layer, MDLI layer, BVG layer, BVD layer, and BMO layer of integrated circuit 400. Part 400B is manufactured from part 300B.

[0188] Part 400C includes one or more features of the VG layer, VD layer, and M0 layer of integrated circuit 400. Part 400C is manufactured from part 300C.

[0189] Part 400D includes one or more features of the BVG layer, BVD layer, and BMO layer of integrated circuit 400. Part 400D is manufactured from Part 300D.

[0190] Figures 4E to 4F are corresponding cross-sectional views of the integrated circuit 400 according to some embodiments. Figure 4E is a cross-sectional view of the integrated circuit 400 intersecting with plane A-A' according to some embodiments. Figure 4F is a cross-sectional view of the integrated circuit 400 intersecting with plane B-B' according to some embodiments.

[0191] Components that are identical or similar to one or more of those in Figures 1, 2, 3A to 3D, 4A to 4F, 5A to 5F, 6A to 6D, 7A to 7D, 8A to 8D, 9A to 9G, or 11A to 11I are assigned the same reference number, and therefore their detailed description is omitted.

[0192] Integrated circuit 400 is manufactured according to layout design 300. Integrated circuit 400 is a unit 401. The structural relationships (including alignment, length, and width) and configuration and layers of integrated circuits 400, 500, 600, 800, 900, or 1100 are similar to those of layout design 300 in Figures 3A to 3D, and for the sake of brevity, similar detailed descriptions will not be described again in at least Figures 4A to 4F. For example, in some embodiments, at least one or more widths, lengths, or spacings of layout design 300 or layout design 700 are similar to the corresponding widths, lengths, or spacings of integrated circuits 400, 500, 600, 800, 900, or 1100, and similar detailed descriptions are omitted for brevity. For example, in some embodiments, at least cell boundary 301a or cell boundary 301b is similar to at least corresponding cell boundary 401a or cell boundary 401b of integrated circuit 400, and such detailed descriptions are omitted for brevity.

[0193] The integrated circuit 400 includes active region groups 402 and 404, gate groups 406 and 408, a gate removal portion group 440, contact groups 410, 412, 414, conductor groups 430 and 432, via groups 420, 422, 424, and 426, and a substrate 490 or insulating region 492.

[0194] The active region group 402 includes at least one or more active regions 402a and active regions 402b.

[0195] Active region group 404 includes at least one or more active regions 404a and active regions 404b.

[0196] Active region groups 402 and 404 are embedded in substrate 490. Substrate 490 has a front side 403a and a back side 403b opposite to the front side 403a. In some embodiments, at least one active region group 402 and active region group 404, gate group 406 and gate group 408, or contact group 410, contact group 412, or contact group 414 is formed in the front side 403a of substrate 490.

[0197] In some embodiments, at least one via group 422 or via group 426 is formed in the back side 403b of substrate 490.

[0198] In some embodiments, active region groups 402 and 404 correspond to the active regions of a CFET transistor. In some embodiments, active region group 402 includes a drain region and a source region grown through an epitaxial growth process. In some embodiments, active region group 402 includes a drain region and a source region, at which epitaxial material is grown. In some embodiments, active region groups 402 and 404 correspond to the nanosheet structure (not labeled) of a nanosheet transistor.

[0199] Other transistor types are also within the scope of this disclosure. For example, in some embodiments, the active region group 402 corresponds to the nanowire structure of a nanowire transistor (not shown). In some embodiments, the active region group 402 corresponds to the planar structure of a planar transistor (not shown). In some embodiments, the active region group 402 corresponds to the fin structure of a finFET (not shown).

[0200] In some embodiments, active regions 402a and 402b correspond to the source and drain regions of the NFET transistors of integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100, while active regions 404a and 404b correspond to the source and drain regions of the PFET transistors of integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100.

[0201] In some embodiments, active regions 402a and 402b correspond to the source and drain regions of the PFET transistors of integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100, while active regions 404a and 404b correspond to the source and drain regions of the NFET transistors of integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100.

[0202] In some embodiments, at least active region 402a or active region 402b is an N-type doped S / D region, and at least active region 404a or active region 404b is a P-type doped S / D region embedded in the dielectric material of substrate 490. In some embodiments, at least active region 402a or active region 402b is a P-type doped S / D region, and at least active region 404a or active region 404b is an N-type doped S / D region embedded in the dielectric material of substrate 490.

[0203] In some embodiments, the active region 404a includes at least one of the active regions 404a1, 404a2, or 404a3.

[0204] In some embodiments, the active region 404a3 is the source / drain of the PFET transistor PU1.

[0205] In some embodiments, the active region 404a2 is the drain / source of the PFET transistor PU1.

[0206] In some embodiments, the active region 404a1 is the drain / source of the PFET transistor X1. In some embodiments, the active region 404a1 includes an insulating region 480a (as shown in Figures 6C to 6D). In some embodiments, the active region 404a1 is a dummy active region in which the insulating region 480a has been removed and filled.

[0207] In some embodiments, the active region 404b includes at least one of active region 404b1, active region 404b2, or active region 404b3.

[0208] In some embodiments, the active region 404b3 is the source / drain of the PFET transistor PU2.

[0209] In some embodiments, the active region 404b2 is the drain / source of the PFET transistor PU2.

[0210] In some embodiments, the active region 404b1 is the drain / source of the PFET transistor X2. In some embodiments, the active region 404b1 includes an insulating region 480b (as shown in Figures 6C to 6D). In some embodiments, the active region 404b1 is a dummy active region in which the insulating region 480b has been removed and filled.

[0211] In some embodiments, at least one of the insulating regions 480a or 480b is a dielectric material. In some embodiments, the dielectric material includes silicon dioxide, silicon oxynitride, silicon nitride, etc.

[0212] The number of other configurations, arrangements or structures on other layout layers in active region group 402 or active region group 404 is within the scope of this disclosure.

[0213] Insulating region 492 is configured to electrically isolate one or more elements from each other, including active region groups 402 and 404, gate groups 406 and 408, contact groups 410, 412, 414, conductor groups 430 and 432, via groups 420, 422, 424, or 426. In some embodiments, insulating region 492 comprises a plurality of insulating regions deposited at different times during methods 1000A to 1000B (Figures 10A to 10B). In some embodiments, insulating region 492 is a dielectric material. In some embodiments, the dielectric material includes silicon dioxide, silicon oxynitride, silicon nitride, etc.

[0214] Other configurations in insulation region 492, arrangements on other layout layers, or other numbers of portions are all within the scope of this disclosure.

[0215] The gate group 406 includes one or more gates 406a or 406b.

[0216] The gate group 408 includes one or more gates 408a or 408b.

[0217] Gate groups 406 and 408 correspond to one or more gates of transistors PD1, PU1, PD2, PU2, PG1, PG2, X1, and X2 of integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100. In some embodiments, each gate in gate groups 406 and gate groups 408 shown in Figures 4A to 4F is labeled with “PD1, PU1, PD2, PU2, PG1, PG2, X1, X2” to identify the transistor in Figure 2 that has the corresponding gate in Figures 4A to 4F, 5A to 5F, 6A to 6D, 7A to 7D, 8A to 8D, 9A to 9G, and 11A to 11I, and is omitted for brevity.

[0218] Gate 406a includes one or more gates 406a1 or 406a2.

[0219] Gate 406b includes one or more gates 406b1 or gate 406b2.

[0220] Gate 408a includes one or more gates 408a1 or gate 408a2.

[0221] Gate 408b includes one or more gates 408b1 or gate 408b2.

[0222] In some embodiments, gate 406a1 is the gate of NFET transistor PD1, gate 406a2 is the gate of NFET transistor PG2, gate 406b1 is the gate of NFET transistor PG1, and gate 406b2 is the gate of NFET transistor PD2.

[0223] In some embodiments, gate 408a1 is the gate of PFET transistor PU1, gate 408a2 is the gate of PFET transistor X2, gate 408b1 is the gate of PFET transistor X1, and gate 408b2 is the gate of PFET transistor PU2.

[0224] In some embodiments, gates 406a1 and 406a2 are separated from each other in a first direction X by removing gate portion 440c.

[0225] In some embodiments, gates 406b1 and 406b2 are separated from each other in a first direction X by removing gate portion 440b.

[0226] In some embodiments, gates 408a1 and 408a2 are separated from each other in a first direction X by removing gate portion 440c.

[0227] In some embodiments, gates 408b1 and 408b2 are separated from each other in a first direction X by removing gate portion 440b.

[0228] In some embodiments, the first side of the insulating region 440c contacts the first side of the gate 406a1 / gate 408a1. In some embodiments, the first side of the insulating region 440b contacts the first side of the gate 406b1 / gate 408b1. In some embodiments, the first side of the insulating region 440c is offset from the first side of the insulating region 440b in the first direction X.

[0229] In some embodiments, the second side of the insulating region 440c contacts the first side of the gate 406a2 / gate 408a2. In some embodiments, the second side of the insulating region 440b contacts the first side of the gate 406b2 / gate 408a2. In some embodiments, the second side of the insulating region 440c is offset from the second side of the insulating region 440b in a first direction X.

[0230] In some embodiments, a pair of offset elements in the first direction X are a pair of elements having corresponding edges along the second direction Y and not aligned in the second direction Y.

[0231] In some embodiments, the first side of gate 406a1 / gate 408a1 is offset from the first side of gate 406b1 / gate 408b1 in the first direction X.

[0232] In some embodiments, the first side of gate 406a2 / gate 408a2 is offset from the first side of gate 406b2 / gate 408b2 in the first direction X.

[0233] In some embodiments, gates 406a1 and 406a2 are identical continuous structures. In some embodiments, gates 408a1 and 408a2 are identical continuous structures. In some embodiments, gates 406b1 and 406b2 are identical continuous structures. In some embodiments, gates 408b1 and 408b2 are identical continuous structures.

[0234] In some embodiments, gate 406a1 and gate 408a1 are coupled together. In some embodiments, gate 406a1 and gate 408a1 are part of the same continuous structure.

[0235] In some embodiments, gate 406a2 and gate 408a2 are coupled together. In some embodiments, gate 406a2 and gate 408a2 are part of the same continuous structure.

[0236] In some embodiments, gate 406b1 and gate 408b1 are coupled together. In some embodiments, gate 406b1 and gate 408b1 are part of the same continuous structure.

[0237] In some embodiments, gate 406b2 and gate 408b2 are coupled together. In some embodiments, gate 406b2 and gate 408b2 are part of the same continuous structure.

[0238] In some embodiments, gates 406a1, 406a2, 406b1 or 406b2 and their corresponding gates 408a1, 408a2, 408b1 or 408b2 are separated from each other by an insulating region (not shown) in the third direction Z.

[0239] In some embodiments, gate group 406 or gate group 408 encapsulates active region group 402 or active region group 404.

[0240] Other configurations, arrangements or quantities of gates in gate group 406 and gate group 408 are within the scope of this disclosure.

[0241] The gate removal group 440 includes one or more gate removal portions 440a, 440b, 440c, or 440d.

[0242] In some embodiments, one or more gate removal portions 440a, 440b, 440c, or 440d are corresponding insulating regions (not labeled) similar to insulating region 492, and therefore such detailed descriptions are omitted.

[0243] In some embodiments, removing the gate portion 440a separates the gate 406a1 from the gate in the adjacent cell along the cell boundary 401c.

[0244] In some embodiments, removing the gate portion 440d separates the gate 406b2 from the gate in the adjacent cell along the cell boundary 401d.

[0245] In some embodiments, removing the gate portion 440a separates the gate 408a1 from the gate in the adjacent cell along the cell boundary 401c.

[0246] In some embodiments, removing the gate portion 440d separates the gate 408b2 from the gate in the adjacent cell along the cell boundary 401d.

[0247] In some embodiments, removing the gate portion 440c separates the gate 406a1 from the gate 406a2 along a first direction X.

[0248] In some embodiments, the gate portion 440c is removed to separate the gate 408a1 from the gate 408a2 along the first direction X.

[0249] In some embodiments, the gate portion 440b is removed to separate the gate 406b1 from the gate 406b2 along the first direction X.

[0250] In some embodiments, the gate portion 440b is removed to separate the gate 408b1 from the gate 408b2 along the first direction X.

[0251] In some embodiments, one or more gate removal portions 440a, 440b, 440c, or 440d are configured to electrically isolate the gates adjacent to the corresponding one or more gate removal portions 440a, 440b, 440c, or 440d.

[0252] The removal of other configurations in gate group 440, arrangements on other layout layers, or the number of gate portions removed are all within the scope of this disclosure.

[0253] The contact assembly 410 includes one or more contacts 410a, 410b, 410c, or 410d.

[0254] The contact assembly 412 includes one or more contacts 412a, 412b, 412c, or 412d.

[0255] Each contact in contact group 410 or contact group 412 corresponds to one or more drain or source terminals of transistors PD1, PU1, PD2, PU2, PG1, PG2, X1, and X2 of integrated circuit 100, integrated circuit 200, integrated circuit 400, integrated circuit 500, integrated circuit 600, integrated circuit 800, integrated circuit 900, or integrated circuit 1100.

[0256] In some embodiments, one or more contacts in the contact group 410 overlap with a pair of active regions in the active region group 402, thereby electrically connecting the source or drain of the transistor to the pair of active regions in the active region group 402.

[0257] In some embodiments, one or more contacts in the contact group 412 overlap with a pair of active regions in the active region group 404, thereby electrically connecting the source or drain of the transistor to the pair of active regions in the active region group 404.

[0258] In some embodiments, contact group 410 or contact group 412 encapsulates active region group 402 or active region group 404.

[0259] In some embodiments, contact 410a is the source / drain terminal of NFET transistor PD1.

[0260] In some embodiments, contact 410b is the source / drain terminal of NFET transistor PG1.

[0261] In some embodiments, contact 410c is the source / drain terminal of NFET transistor PG2.

[0262] In some embodiments, contact 410d is the source / drain terminal of NFET transistor PD2.

[0263] In some embodiments, contact 412a is the source / drain terminal of PFET transistor PU1.

[0264] In some embodiments, contact 412b is the source / drain terminal of PFET transistor X1.

[0265] In some embodiments, contact 412c is the source / drain terminal of PFET transistor X2.

[0266] In some embodiments, contact 412d is the source / drain terminal of PFET transistor PU2.

[0267] The contact assembly 414 includes one or more contacts 414a or 414b.

[0268] In some embodiments, contact 414a is the drain / source terminal of NFET transistor PD1, the drain / source terminal of NFET transistor PG1, the drain / source terminal of PFET transistor PU1, and the drain / source terminal of PFET transistor X1.

[0269] In some embodiments, contact 414a corresponds to node NDB in Figure 2, and similar detailed descriptions are omitted for brevity.

[0270] In some embodiments, contact 414b is the drain / source terminal of NFET transistor PG2, the drain / source terminal of NFET transistor PD2, the drain / source terminal of PFET transistor X2, and the drain / source terminal of PFET transistor PU2.

[0271] In some embodiments, contact 414b corresponds to node ND in Figure 2, and similar detailed descriptions are omitted for brevity.

[0272] Other configurations, arrangements on other layout layers, or the number of contacts in contact groups 410, 412, and 414 are all within the scope of this disclosure.

[0273] The conductor group 430 includes one or more conductors 430a, 430b, 430c, 430d, or 430e.

[0274] The conductor group 432 includes one or more conductors 432a, 432b, 432c, 432d, or 432e.

[0275] Conductor group 430 is an M0 wiring track. Conductor group 432 is a BMO wiring track. In some embodiments, conductor groups 430 and 432 are wiring tracks in other layers. In some embodiments, conductor group 430 corresponds to 5 M0 wiring tracks. In some embodiments, conductor group 432 corresponds to 3 BMO wiring tracks.

[0276] In some embodiments, conductor 430a is configured to provide a reference voltage source VSS, conductor 430b is a bit line BLB, conductor 430c is a mating contact, conductor 430d is a bit line BL, and conductor 430e is configured to provide a reference voltage source VSS.

[0277] In some embodiments, conductor 432a is a bit line WL, conductor 432b is configured to provide a voltage source VDD, conductor 432c is a mating contact, conductor 432d is configured to provide a voltage source VDD, and conductor 432e is a character line WL.

[0278] Other configurations in conductor groups 430 and 432, arrangements on other layout layers, or the number of conductors are all within the scope of this disclosure.

[0279] The through-hole group 420 includes one or more through holes 420a, 420b, 420c, 420d, or 420e.

[0280] The through-hole group 422 includes one or more through holes 422a, 422b or 422c.

[0281] The via group 424 includes one or more vias 424a.

[0282] The through-hole group 426 includes one or more through holes 426a, 426b or 426c.

[0283] The via group 420 is configured to electrically couple the corresponding source or drain region of the active region group 402 to the conductor group 430 through the contact group 410 or contact group 414, and vice versa. The via group 420 is located between the contact group 410 or contact group 414 and the conductor group 430.

[0284] The via group 422 is configured to electrically couple the corresponding source or drain region of the active region group 404 to the conductor group 432 through the contact group 412 or contact group 414, and vice versa. The via group 422 is located between the contact group 412 or contact group 414 and the conductor group 432.

[0285] Through-hole group 424 is configured to electrically couple one or more gates in gate group 406 to conductor group 430 and vice versa. Through-hole group 424 is located between gate group 406 and conductor group 430.

[0286] Through-hole group 426 is configured to electrically couple one or more gates in gate group 408 to conductor group 432 and vice versa. Through-hole group 426 is located between gate group 408 and conductor group 432.

[0287] Through hole 420a electrically connects conductor 430a and contact 410a together. Through hole 420b electrically connects conductor 430b and contact 410b together. Through hole 420c electrically connects conductor 430d and contact 410c together. Through hole 420d electrically connects conductor 430e and contact 410d together. Through hole 420e electrically connects conductor 430c and contact 414b together.

[0288] Through hole 422a electrically connects conductor 432b to contact 412a. Through hole 422b electrically connects conductor 432d to contact 412d. Through hole 422c electrically connects conductor 432c to contact 414a.

[0289] Through hole 424a electrically connects conductor 430c and gate 406a1 together.

[0290] Through-hole 426a electrically connects conductor 432a to gate 408b1. Through-hole 426b electrically connects conductor 432e to gate 408a2. Through-hole 426c electrically connects conductor 432c to gate 408b2.

[0291] In some embodiments, at least one width of a through hole in a through hole group 420, through hole group 422, through hole group 424 or through hole group 426 in the first direction X is equal to at least one width of another through hole in a through hole group 420, through hole group 422, through hole group 424 or through hole group 426 in the first direction X.

[0292] In some embodiments, at least one width of a through hole in a through hole group 420, through hole group 422, through hole group 424 or through hole group 426 in the first direction X is different from at least one width of another through hole in a through hole group 420, through hole group 422, through hole group 424 or through hole group 426 in the first direction X.

[0293] Other configurations, arrangements or numbers of through holes in through hole groups 420, 422, 424 and 426 are within the scope of this disclosure.

[0294] In some embodiments, at least one gate in gate group 406 or gate group 408 is formed of doped or undoped polycrystalline silicon (or polycrystalline silicon). In some embodiments, at least one gate in gate group 406 or gate group 408 comprises a metal, such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof.

[0295] In some embodiments, at least one contact in contact group 410, contact group 412, or contact group 414, or at least one conductor in conductor group 430 or conductor group 432, or at least one via in via group 420, via group 422, via group 424, or via group 426 comprises one or more layers of conductive material, metal, metal compound, or doped semiconductor. In some embodiments, the conductive material comprises tungsten, cobalt, ruthenium, copper, etc., or combinations thereof. In some embodiments, the metal comprises at least Cu (copper), Co, W, Ru, Al, etc. In some embodiments, the metal compound comprises at least AlCu, W-TiN, TiSix, NiSix, TiN, TaN, etc. In some embodiments, the doped semiconductor comprises at least doped silicon, etc.

[0296] In some embodiments, conductor 430c electrically connects the node ND of memory cell 200 to the gates of NFET transistor PD1 and NFET transistor PU1 on the front side 403a of integrated circuit 400. For example, in some embodiments, conductor 430c electrically couples gate 406a1 and contact 414b together on the front side 403a of integrated circuit 400.

[0297] In some embodiments, conductor 432c electrically connects the node NDB of memory cell 200 to the gates of NFET transistor PD2 and NFET transistor PU2 on the back side 403b of integrated circuit 400. For example, in some embodiments, conductor 432c electrically couples gate 408b2 and contact 414a together on the back side 403b of integrated circuit 400.

[0298] In some embodiments, the positions where gates 406b2 / 408b2 and 406b1 / 408b1 are separated from each other in the second direction Y are different from the positions where gates 406a2 / 408a2 and 406a1 / 408a1 are separated from each other in the second direction Y.

[0299] In some embodiments, by separating gates 406b2 / 408b2 and 406b1 / 408b1 at positions different from the separation positions of gates 406a2 / 408a2 and 406a1 / 408a1, conductor 430c can be used as a first mating contact on the front side 403a of the integrated circuit 400, and conductor 432c can be used as a second mating contact on the back side 403b of the integrated circuit 400, thereby improving the wiring resources of the integrated circuit 400 and reducing the area of ​​the integrated circuit 400 compared with other methods.

[0300] In some embodiments, by using conductor 430c as a first mating contact on the front side 403a of the integrated circuit 400 and by using conductor 432c as a second mating contact on the back side 403b of the integrated circuit 400, at least one of conductor 430c or conductor 432c has a simpler design than other methods that have a more complex L-shape and use at least one additional shield.

[0301] Other configurations, arrangements of other layers, or number of elements in the integrated circuit 400 are all within the scope of this disclosure.

[0302] Figures 5A through 5F are diagrams of an integrated circuit 500 according to some embodiments.

[0303] Figures 5A to 5D are corresponding diagrams of parts 500A, 500B, 500C, and 500D of the integrated circuit 500, which have been simplified for ease of explanation.

[0304] Part 500A includes one or more characteristics of the OD layer, POLY layer, CPO layer, MD layer, MDLI layer, VG layer, VD layer, and M0 layer of integrated circuit 500. Part 500A is manufactured using a layout design similar to at least Part 300A, and similar detailed descriptions are omitted for brevity.

[0305] Part 500B includes one or more characteristics of the OD layer, POLY layer, CPO layer, BMD layer, MDLI layer, BVG layer, BVD layer, and BMO layer of integrated circuit 500. Part 500B is manufactured using a layout design at least similar to that of Part 300B, and similar detailed descriptions are omitted for brevity.

[0306] Part 500C includes one or more features of the VG, VD, and M0 layers of integrated circuit 400. Part 500C is manufactured with a layout design at least similar to that of Part 300C, and similar detailed descriptions are omitted for brevity.

[0307] Part 500D includes one or more features of the BVG layer, BVD layer, and BMO layer of integrated circuit 400. Part 500D is manufactured with a layout design at least similar to that of Part 300D, and similar detailed descriptions are omitted for brevity.

[0308] Figures 5E to 5F are corresponding cross-sectional views of the integrated circuit 500 according to some embodiments. Figure 5E is a cross-sectional view of the integrated circuit 500 intersecting with plane C-C' according to some embodiments. Figure 5F is a cross-sectional view of the integrated circuit 500 intersecting with plane D-D' according to some embodiments.

[0309] In some embodiments, the integrated circuit 500 is a memory cell 200.

[0310] Integrated circuit 500 is manufactured using a similar layout design to integrated circuit 500.

[0311] In some embodiments, the integrated circuit 500 is manufactured using a layout design similar to that of layout design 300, therefore a similar detailed description is omitted. The structural relationships (including alignment, length, and width) and configuration and layers of the integrated circuit 500 are similar to those of the integrated circuit 400 in Figures 4A to 4F, and for the sake of brevity, a similar detailed description will not be described again in at least Figures 5A to 5F.

[0312] Integrated circuit 500 is unit 501.

[0313] Integrated circuit 500 is a variant of integrated circuit 400 in Figures 4A to 4F; for the sake of brevity, similar detailed descriptions are omitted.

[0314] Compared to the integrated circuit 400 in Figures 4A to 4F, conductor group 530 replaces conductor group 430 of integrated circuit 400, and conductor group 532 replaces conductor group 432 of integrated circuit 400, and similar detailed descriptions are omitted for brevity.

[0315] The integrated circuit 500 includes at least active region groups 402 and 404, gate groups 406 and 408, a gate removal portion group 440, contact groups 410, 412, 414, conductor groups 530 and 532, via groups 420, 422, 424, and 426, a substrate 490, and an insulating region 492.

[0316] The conductor group 530 includes at least one of conductor 430a, conductor 430b, conductor 530c, conductor 430d, or conductor 430e.

[0317] Compared to integrated circuit 400, conductor 530c in conductor group 530 replaces conductor 430c in conductor group 430, and similar detailed descriptions are omitted for brevity.

[0318] Compared to conductor 430c of integrated circuit 400, conductor 530c of integrated circuit 500 has a larger area, and similar detailed descriptions are omitted for the sake of brevity.

[0319] In some embodiments, conductor 530c includes conductive portion 530c1, conductive portion 530c2 and conductive portion 530c3.

[0320] In some embodiments, conductive portion 530c2 is a central portion connected to each of conductive portions 530c1 and conductive portions 530c3. In some embodiments, a first end of conductive portion 530c1 is connected to a first side of conductive portion 530c2. In some embodiments, conductive portion 530c3 is connected to a second side of conductive portion 530c2 at a second end.

[0321] In some embodiments, the first side of the conductive portion 530c2 is opposite to the second side of the conductive portion 530c2. In some embodiments, the first end of the conductive portion 530c2 is opposite to the second end of the conductive portion 530c2.

[0322] In some embodiments, conductor 530c has a zigzag shape.

[0323] Compared to conductor 430c of integrated circuit 400, conductor 530c of integrated circuit 500 has an increased length in the second direction Y and an increased width in the first direction X, resulting in conductor 530c having an increased area.

[0324] In some embodiments, increasing the area of ​​conductor 530c leads to a reduction in capacitive coupling between conductors 430b and 430d, thereby improving the speed and performance of the integrated circuit 500 compared to other methods.

[0325] Conductor group 530 is an M0 wiring track. In some embodiments, conductor group 530 is a wiring track in another layer. In some embodiments, conductor group 530 corresponds to 5 M0 wiring tracks. Other M0 track assignments or numbers are within the scope of this disclosure.

[0326] Other configurations in conductor group 530, arrangements on other layout layers, or the number of conductors are all within the scope of this disclosure.

[0327] The conductor group 532 includes at least one of conductor 432a, conductor 432b, conductor 532c, conductor 432d, or conductor 432e.

[0328] Compared to integrated circuit 400, conductor 532c in conductor group 532 replaces conductor 432c in conductor group 432, and similar detailed descriptions are omitted for brevity.

[0329] Compared to conductor 432c of integrated circuit 400, conductor 532c of integrated circuit 500 has an increased area, and similar detailed descriptions are omitted for the sake of brevity.

[0330] In some embodiments, conductor 532c includes conductive portion 532c1, conductive portion 532c2 and conductive portion 532c3.

[0331] In some embodiments, conductive portion 532c2 is a central portion connected to each of conductive portions 532c1 and conductive portions 532c3. In some embodiments, a first end of conductive portion 532c1 is connected to a first side of conductive portion 532c2. In some embodiments, conductive portion 532c3 is connected to a second side of conductive portion 532c2 at a second end.

[0332] In some embodiments, the first side of the conductive portion 532c2 is opposite to the second side of the conductive portion 532c2. In some embodiments, the first end of the conductive portion 532c2 is opposite to the second end of the conductive portion 532c2.

[0333] In some embodiments, conductor 532c has a zigzag shape.

[0334] Compared to conductor 432c of integrated circuit 400, conductor 532c of integrated circuit 500 has an increased length in the second direction Y and an increased width in the first direction X, resulting in conductor 532c having an increased area.

[0335] In some embodiments, increasing the area of ​​conductor 532c leads to a reduction in capacitive coupling between conductors 432b and 432d, thereby improving the speed and performance of the integrated circuit 500 compared to other methods.

[0336] Conductor group 532 is a BMO wiring track. In some embodiments, conductor group 532 is a wiring track in another layer. In some embodiments, conductor group 532 corresponds to 3 BMO wiring tracks. Other BMO track assignments or numbers are within the scope of this disclosure.

[0337] Other configurations in conductor group 532, arrangements on other layout layers, or the number of conductors are all within the scope of this disclosure.

[0338] In some embodiments, by including conductor 530c in the integrated circuit 500, capacitive coupling between bit line BL and bit line BLB is reduced, thereby improving the speed and performance of the integrated circuit 500 compared to other methods.

[0339] In some embodiments, the integrated circuit 500 achieves one or more of the advantages described herein.

[0340] Other configurations, arrangements of other layers, or number of elements in the integrated circuit 500 are all within the scope of this disclosure.

[0341] Figures 6A through 6D are diagrams of an integrated circuit 600 according to some embodiments.

[0342] Figures 6A to 6D are the corresponding diagrams of parts 600A, 600B, 600C, and 600D of the integrated circuit 600, which have been simplified for ease of explanation.

[0343] Part 600A includes one or more characteristics of the OD layer, POLY layer, CPO layer, MD layer, MDLI layer, VG layer, VD layer and M0 layer of the integrated circuit 600.

[0344] Part 600B includes one or more features of the OD layer, POLY layer, CPO layer, BMD layer, MDLI layer, BVG layer, BVD layer and BMO layer of the integrated circuit 600.

[0345] Figures 6C to 6D are corresponding cross-sectional views of the integrated circuit 600 according to some embodiments. Figure 6C is a cross-sectional view of the integrated circuit 600 intersecting with plane E-E' according to some embodiments. Figure 6D is a cross-sectional view of the integrated circuit 600 intersecting with plane F-F' according to some embodiments.

[0346] Integrated circuit 600 is manufactured using a similar layout design to integrated circuit 600.

[0347] Integrated circuit 600 is a variant of integrated circuit 400 in Figures 4A to 4D, and similar detailed descriptions are omitted for brevity. Compared to integrated circuit 400 in Figures 4A to 4D, integrated circuit 600 includes two rows of storage cells (e.g., cells 601A and 601B), and similar detailed descriptions are omitted for brevity.

[0348] The integrated circuit 600 includes units 601A and 601B. In some embodiments, at least one of unit 601A or unit 601B is a memory unit 200. In some embodiments, at least one of unit 601A or unit 601B is a variant of the integrated circuit 400 of Figures 4A to 4D, and similar detailed descriptions are omitted for brevity.

[0349] Unit 601A is located in row COL1.

[0350] Unit 601B is located in row COL2. In some embodiments, row COL2 is adjacent to or directly adjacent to row COL1.

[0351] Compared to the integrated circuit 400 in Figures 4A to 4D, each element of unit 601A is located in a single row (e.g., row COL1), while the integrated circuit 400 in Figures 4A to 4D is located in two rows, and similar detailed descriptions are omitted for brevity.

[0352] Compared to the integrated circuit 400 in Figures 4A to 4D, each element of unit 601B is located in a single row (e.g., row COL2), while the integrated circuit 400 in Figures 4A to 4D is located in two rows, and similar detailed descriptions are omitted for brevity.

[0353] Compared to the integrated circuit 400 in Figures 4A to 4D, contact group 610 replaces contact group 410 of integrated circuit 400, contact group 612 replaces contact group 412 of integrated circuit 400, gate removal portion group 640 replaces gate removal portion group 440 of integrated circuit 400, conductor group 630 replaces conductor group 430 of integrated circuit 400, conductor group 632 replaces conductor group 432 of integrated circuit 400, via group 620 replaces via group 420 of integrated circuit 400, via group 622 replaces via group 422 of integrated circuit 400, via group 624 replaces via group 424 of integrated circuit 400, via group 626 replaces via group 426 of integrated circuit 400, and similar detailed descriptions are omitted for brevity.

[0354] Unit 601A includes active region groups 402 and 404, gate groups 406 and 408, gate removal portion group 640, contact group 610, contact group 612, contact group 414, conductor group 630, conductor group 632, through-hole group 620, through-hole group 622, through-hole group 624, through-hole group 626, substrate 490, and insulating region 492.

[0355] The contact assembly 610 includes at least one of contact 410a, contact 410b, or contact 410c.

[0356] Compared to integrated circuit 400, each contact 410b and contact 410c of integrated circuit 600 is located in a single row (e.g., row COL1), and similar detailed descriptions are omitted for brevity.

[0357] Compared to integrated circuit 400, the contacts 410a of integrated circuit 600 are located in two rows (e.g., row COL1 and row COL2), and similar detailed descriptions are omitted for brevity.

[0358] In some embodiments, the reference voltage source VSS is powered by a single contact (e.g., contact 410a) via the rearrangement unit 601A (as shown in Figures 6A to 6D).

[0359] Other configurations in contact group 610, arrangements on other layout layers, or the number of contacts are all within the scope of this disclosure.

[0360] The contact assembly 612 includes at least one of contact 412a, contact 412b, or contact 412c.

[0361] Compared to integrated circuit 400, each contact 412b and contact 412c of integrated circuit 600 is located in a single row (e.g., row COL1), and similar detailed descriptions are omitted for brevity.

[0362] Compared to integrated circuit 400, the contacts 412a of integrated circuit 600 are located in two rows (e.g., row COL1 and row COL2), and similar detailed descriptions are omitted for brevity.

[0363] In some embodiments, the voltage source VDD is powered by a single contact (e.g., contact 412a) via the rearrangement unit 601A (as shown in Figures 6A to 6D).

[0364] Other configurations in contact group 612, arrangements on other layout layers, or the number of contacts are all within the scope of this disclosure.

[0365] Compared to integrated circuit 400, each contact 414a and contact 414b of integrated circuit 600 is located in a single row (e.g., row COL1), and similar detailed descriptions are omitted for brevity.

[0366] Conductor group 630 includes at least one of conductor 430b, conductor 630c, or conductor 430d. For ease of illustration, conductor 430b (e.g., bit line BLB) and conductor 430b (e.g., bit line BL) are not shown in Figures 6A to 6D, and similar detailed descriptions are omitted for brevity.

[0367] Compared to integrated circuit 400, conductor 630c in conductor group 630 replaces conductor 430c in conductor group 430, and similar detailed descriptions are omitted for brevity.

[0368] Conductor group 630 is an M0 wiring track. In some embodiments, conductor group 630 is a track for wiring in other layers. Other M0 track assignments or numbers are within the scope of this disclosure.

[0369] Other configurations in conductor group 630, arrangements on other layout layers, or the number of conductors are all within the scope of this disclosure.

[0370] The conductor group 632 includes at least one of conductor 432a, conductor 432b or conductor 632c.

[0371] For ease of illustration, conductors 432a (e.g., character line WL) and 432b (e.g., character line WL) are not shown in Figures 6A to 6D, and similar detailed descriptions are omitted for brevity. In some embodiments, conductors 432a and 432b are a single continuous structure configured as character line WL.

[0372] Compared to integrated circuit 400, conductor 632c in conductor group 632 replaces conductor 432c in conductor group 432, and similar detailed descriptions are omitted for brevity.

[0373] Conductor group 632 is a BMO wiring track. In some embodiments, conductor group 632 is a wiring track in another layer. Other BMO track assignments or numbers are within the scope of this disclosure.

[0374] Other configurations in conductor group 632, arrangements on other layout layers, or the number of conductors are all within the scope of this disclosure.

[0375] The gate removal portion group 640 includes at least one of the gate removal portion 640a, gate removal portion 640b, or gate removal portion 640c.

[0376] In some embodiments, one or more gate removal portions 640a, 640b, or 640c are corresponding insulation regions (not labeled) similar to insulation region group 492, and therefore such detailed descriptions are omitted.

[0377] In some embodiments, removing the insulating region of gate portion 640a is configured to electrically insulate gate 406a2 from adjacent gates. In some embodiments, removing the insulating region of gate portion 640a is configured to electrically insulate gate 408a2 from adjacent gates.

[0378] In some embodiments, the insulating region of the removed gate portion 640a is configured to electrically insulate gate 406b2 from adjacent gates. In some embodiments, the insulating region of the removed gate portion 640a is configured to electrically insulate gate 408b2 from adjacent gates.

[0379] In some embodiments, the insulating region of the removed gate portion 640a is configured to electrically insulate gate 406a1 from adjacent gates. In some embodiments, the insulating region of the removed gate portion 640a is configured to electrically insulate gate 408a1 from adjacent gates.

[0380] In some embodiments, the insulating region of the removed gate portion 640a is configured to electrically insulate gate 406b1 from adjacent gates. In some embodiments, the insulating region of the removed gate portion 640a is configured to electrically insulate gate 408b1 from adjacent gates.

[0381] In some embodiments, the insulating region of the removed gate portion 640b is configured such that gates 406a2, 406a1, 406b2, 406b1, 408a2, 408a1, 408b2 and 408b1 in row COL1 of cell 601B are electrically insulated from the gates in row COL2 of cell 601B.

[0382] In some embodiments, the insulation region of the gate portion 640c is removed and configured such that the gate in row COL2 of cell 601B is electrically insulated from the adjacent gate in another row.

[0383] Compared to integrated circuit 400, the gates 406a2, 406a1, 406b2, 406b1, 408a2, 408a1, 408b2, and 408b1 of integrated circuit 600 are all located in a single row (e.g., row COL1), and similar descriptions are omitted for brevity.

[0384] Compared to the gate removal portions 440b and 440c of the integrated circuit 400, the gate removal portions 640a, 640b, and 640c of the integrated circuit 600 have rectangular shapes in the first direction X and the second direction Y.

[0385] The removal of other configurations in gate group 640, arrangements on other layout layers, or the number of gate portions removed are all within the scope of this disclosure.

[0386] The through-hole group 620 includes at least one of through-hole 420a, through-hole 420b, through-hole 420c or through-hole 620e.

[0387] Compared to integrated circuit 400, via 620e in via group 620 replaces via 420e in via group 420, and similar detailed descriptions are omitted for brevity.

[0388] Compared to integrated circuit 400, via 620e of via group 620 is electrically connected to conductor 630c and contact 414a, and similar detailed descriptions are omitted for brevity.

[0389] Other configurations in via group 620, arrangements on other layout layers, or the number of vias are all within the scope of this disclosure.

[0390] The through-hole group 622 includes at least one of through-hole 422a or through-hole 622c.

[0391] Compared to integrated circuit 400, via 622c in via group 622 replaces via 422c in via group 422, and similar detailed descriptions are omitted for the sake of brevity.

[0392] Compared to integrated circuit 400, via 622c in via group 622 is electrically connected to conductor 632c and contact 414b, and similar detailed descriptions are omitted for brevity.

[0393] Other configurations in via group 622, arrangements on other layout layers, or the number of vias are all within the scope of this disclosure.

[0394] The through-hole group 624 includes at least one through-hole 624a.

[0395] Compared to integrated circuit 400, via 624a in via group 622 replaces via 424a in via group 424, and similar detailed descriptions are omitted for brevity.

[0396] Compared to integrated circuit 400, via 624a in via group 624 is electrically connected to conductor 630c and gate 406b2, and similar detailed descriptions are omitted for brevity.

[0397] Other configurations in via group 624, arrangements on other layout layers, or the number of vias are all within the scope of this disclosure.

[0398] The through-hole group 626 includes at least one of through-hole 426a, through-hole 426b or through-hole 626c.

[0399] Compared to integrated circuit 400, via 626c in via group 626 replaces via 426c in via group 426, and similar detailed descriptions are omitted for brevity.

[0400] Compared to integrated circuit 400, via 626c in via group 626 is electrically connected to conductor 632c and gate 408a1, and similar detailed descriptions are omitted for brevity.

[0401] Other configurations in via group 626, arrangements on other layout layers, or the number of vias are all within the scope of this disclosure.

[0402] In some embodiments, unit 601B includes the same elements as unit 601A. The labels of the same elements in unit 601B are changed by adding "-2" to the end of the corresponding elements in unit 601B, and similar detailed descriptions are omitted for brevity. For example, bit line BL in unit 601A is labeled as "bit line BL-2" in unit 601B, and similar detailed descriptions are omitted for brevity.

[0403] Unit 601B includes active region groups 402 and 404, gate groups 406 and 408, gate removal portion group 640, contact group 610, contact group 612, contact group 414, conductor group 630, conductor group 632, through-hole group 620, through-hole group 622, through-hole group 624, through-hole group 626, substrate 490, and insulating region 492.

[0404] In some embodiments, conductor 630c electrically connects the node NDB of memory cell 200 to the gates of NFET transistor PD2 and NFET transistor PU2 on the front side 403a of integrated circuit 600. For example, in some embodiments, conductor 630c electrically couples gate 406b2 and contact 414a together on the front side 403a of integrated circuit 600.

[0405] In some embodiments, conductor 632c electrically connects the node ND of memory cell 200 to the gates of NFET transistor PU1 and NFET transistor PD1 on the back side 403b of integrated circuit 600. For example, in some embodiments, conductor 632c electrically couples gate 408a1 and contact 414b together on the back side 403b of integrated circuit 600.

[0406] In some embodiments, conductor 630c can be used as a first mating contact on the front side 403a of the integrated circuit 600, while conductor 632c can be used as a second mating contact on the back side 403b of the integrated circuit 600, thereby improving the wiring resources of the integrated circuit 600 and reducing the area of ​​the integrated circuit 600 compared with other methods.

[0407] In some embodiments, by using conductor 630c as a first mating contact on the front side 403a of the integrated circuit 600 and by using conductor 632c as a second mating contact on the back side 403b of the integrated circuit 600, at least one of conductor 630c or conductor 632c has a simpler design than other methods that have a more complex L-shape and use at least one additional shield.

[0408] In some embodiments, the integrated circuit 600 achieves one or more of the advantages described herein.

[0409] Other configurations, arrangements of other layers, or number of elements in the integrated circuit 600 are all within the scope of this disclosure.

[0410] Figures 7A to 7D are diagrams of layout design 700 according to some embodiments.

[0411] Figures 7A to 7D are the corresponding diagrams of parts 700A, 700B, 700C, and 700D of the layout design 700, which have been simplified for ease of explanation.

[0412] Part 700A includes one or more features of the OD layer, POLY layer, CPO layer, MD layer, MDLI layer, VG layer, VD layer and M0 layer of layout design 700.

[0413] Part 700B includes one or more features of the OD layer, POLY layer, CPO layer, BMD layer, MDLI layer, BVG layer, BVD layer and BMO layer of layout design 700.

[0414] Part 700C includes one or more features of the VG layer, VD layer, and M0 layer of layout design 700.

[0415] Part of the 700D includes one or more features of the layout design of the BVG layer, BVD layer and BMO layer.

[0416] The layout design 700 can be used to manufacture the integrated circuits 800 in Figures 8A to 8D.

[0417] In some embodiments, layout design 700 is memory unit 200.

[0418] Layout design 700 is unit 701.

[0419] Layout design 700 is a variation of layout design 300 in figures 3A to 3D, and similar detailed descriptions are omitted for the sake of brevity.

[0420] Compared with the layout design 300 in Figures 3A to 3D, the cutting feature pattern group 740 replaces the cutting feature pattern group 340 of the layout design 300, the conductive feature pattern group 730 replaces the conductive feature pattern group 330 of the layout design 300, the conductive feature pattern group 732 replaces the conductive feature pattern group 332 of the layout design 300, the through hole pattern group 724 replaces the through hole pattern group 324 of the layout design 300, and the through hole pattern group 726 replaces the through hole pattern group 326 of the layout design 300. For the sake of brevity, similar detailed descriptions are omitted.

[0421] The layout design 700 includes at least one or more of the following: active area pattern groups 302 and 304, gate pattern groups 306 and 308, cutting feature pattern group 740, contact pattern group 310, contact pattern group 312, contact pattern group 314, conductive feature pattern group 730, conductive feature pattern group 732, through-hole pattern group 320, through-hole pattern group 322, through-hole pattern group 724, or through-hole pattern group 726.

[0422] The conductive feature pattern group 730 includes at least one of conductive feature pattern 330a, conductive feature pattern 330b, conductive feature pattern 330c, conductive feature pattern 330d, or conductive feature pattern 330e.

[0423] Compared to layout design 300, conductive feature pattern 730c in conductive feature pattern group 730 replaces conductive feature pattern 330c in conductive feature pattern group 330, and for the sake of brevity, similar detailed descriptions are omitted.

[0424] The conductive feature pattern group 730 is an M0 wiring track. In some embodiments, the conductive feature pattern group 730 is wired in other layers. In some embodiments, the conductive feature pattern group 730 corresponds to 5 M0 wiring tracks. Other M0 track assignments or numbers are within the scope of this disclosure.

[0425] Other configurations in the conductive feature pattern group 730, arrangements on other layout layers, or the number of conductive feature patterns are all within the scope of this disclosure.

[0426] The conductive feature pattern group 732 includes at least one of conductive feature pattern 332a, conductive feature pattern 332b, conductive feature pattern 332c, conductive feature pattern 332d, or conductive feature pattern 332e.

[0427] Compared to layout design 300, conductive feature pattern 732c in conductive feature pattern group 732 replaces conductive feature pattern 332c in conductive feature pattern group 332, and for the sake of brevity, similar detailed descriptions are omitted.

[0428] The conductive feature pattern group 732 is a BMO wiring track. In some embodiments, the conductive feature pattern group 732 is a wiring track in another layer. In some embodiments, the conductive feature pattern group 732 corresponds to three BMO wiring tracks. Other BMO track assignments or numbers are within the scope of this disclosure.

[0429] Other configurations in the conductive feature pattern group 732, arrangements on other layout layers, or the number of conductive feature patterns are all within the scope of this disclosure.

[0430] The cutting feature pattern group 740 includes at least one of the cutting feature patterns 340a, 740b, and 340d.

[0431] Compared to layout design 300, cutting feature pattern 740b in cutting feature pattern group 740 replaces cutting feature pattern 340b and feature pattern 340c in cutting feature pattern group 340, and similar detailed descriptions are omitted for the sake of brevity.

[0432] Compared with the cutting feature patterns 340b and 340c of layout design 300, the cutting feature pattern 740b of layout design 700 does not have a "zigzag shape", and therefore has a "rectangular shape" in both the first direction X and the second direction Y. For the sake of brevity, a similar detailed description is omitted.

[0433] Compared with the cutting feature patterns 340b and 340c of layout design 300, the cutting feature pattern 740b of layout design 700 has a uniform shape in the second direction Y.

[0434] Compared with the cutting feature patterns 340b and 340c of layout design 300, the cutting feature pattern 740b of layout design 700 has an increased width in the first direction X, and similar detailed descriptions are omitted for the sake of brevity.

[0435] In some embodiments, by increasing the width of the cutting feature pattern 740b in the first direction X, the cutting feature pattern 740b has an increased area compared to the cutting feature pattern 340b and the cutting feature pattern 340c.

[0436] In some embodiments, increasing the width of the cutting feature pattern 740b results in an increase in the area of ​​the cutting feature pattern 740b, thereby increasing the distance between gates 406a1 / 408a1 and 406a2 / 408a2, and thus increasing the distance between gates 406b1 / 408b1 and 406b2 / 408b2.

[0437] Other configurations in the cutting feature pattern group 740, arrangements at other layout levels, or the number of cutting feature patterns are all within the scope of this disclosure.

[0438] The through-hole pattern group 724 includes at least one through-hole pattern 724a.

[0439] Compared to layout design 300, through hole pattern 724a of through hole pattern group 724 replaces through hole pattern 324a of through hole pattern group 324, and similar detailed descriptions are omitted for the sake of brevity.

[0440] Compared with the through-hole pattern 324a of layout design 300, the through-hole pattern 724a of layout design 700 has an increased width W1a in the first direction X. For the sake of brevity, a similar detailed description is omitted.

[0441] In some embodiments, by increasing the width W1a of the through-hole pattern 724a in the first direction X of the layout design 700, the area of ​​the through-hole pattern 724a is increased.

[0442] In some embodiments, as the width of the cutting feature pattern 740b increases in the first direction X, the width W1a of the through hole pattern 724c also increases in the first direction X.

[0443] Other configurations in the via pattern group 724, arrangements on other layout layers, or the number of via patterns are all within the scope of this disclosure.

[0444] The through-hole pattern group 726 includes at least one of through-hole pattern 326a, through-hole pattern 326b or through-hole pattern 726c.

[0445] Compared to layout design 300, through hole pattern 726c of through hole pattern group 726 replaces through hole pattern 326c of through hole pattern group 326, and similar detailed descriptions are omitted for the sake of brevity.

[0446] Compared to the through-hole pattern 326c of layout design 300, the through-hole pattern 726c of layout design 700 has an increased width W1b in the first direction X. For the sake of brevity, a similar detailed description is omitted.

[0447] In some embodiments, by increasing the width W1b of the through-hole pattern 726c in the first direction X of the layout design 700, the area of ​​the through-hole pattern 726c is increased.

[0448] In some embodiments, as the width of the cutting feature pattern 740b increases in the first direction X, the width W1b of the through hole pattern 726c also increases in the first direction X.

[0449] Other configurations in the via pattern group 726, arrangements on other layout layers, or the number of via patterns are all within the scope of this disclosure.

[0450] In some embodiments, at least one of the through-hole patterns 724a or 726c is referred to as a "slotted through-hole pattern".

[0451] In some embodiments, layout design 700 achieves one or more of the advantages described herein.

[0452] Other configurations, arrangements of other layers, or number of elements in layout design 700 are all within the scope of this disclosure.

[0453] Figures 8A to 8D are diagrams of an integrated circuit 800 according to some embodiments.

[0454] Figures 8A to 8D are corresponding diagrams of parts 800A, 800B, 800C, and 800D of the integrated circuit 800, which have been simplified for ease of explanation.

[0455] Part of the 800A includes one or more characteristics of the OD layer, POLY layer, CPO layer, MD layer, MDLI layer, VG layer, VD layer and M0 layer of the integrated circuit 800.

[0456] Part of 800B includes one or more characteristics of the OD layer, POLY layer, CPO layer, BMD layer, MDLI layer, BVG layer, BVD layer and BMO layer of integrated circuit 800.

[0457] Part of 800C includes one or more features of the VG layer, VD layer, and M0 layer of integrated circuit 800.

[0458] Part of 800D includes one or more features of the BVG layer, BVD layer and BMO layer of integrated circuit 800.

[0459] The integrated circuit 800 is manufactured according to the layout design 700 of Figures 7A to 7D.

[0460] In some embodiments, the integrated circuit 800 is a memory cell 200.

[0461] The integrated circuit 800 is unit 801.

[0462] Integrated circuit 800 is a variant of integrated circuit 400 in Figures 4A to 4D; for the sake of brevity, similar detailed descriptions are omitted.

[0463] Compared to the integrated circuit 400 in Figures 4A to 4D, the gate removal portion group 840 replaces the gate removal portion group 440 of the integrated circuit 400, the conductor group 830 replaces the conductor group 430 of the integrated circuit 400, the conductor group 832 replaces the conductor group 432 of the integrated circuit 400, the via group 824 replaces the via group 424 of the integrated circuit 400, the via group 826 replaces the via group 426 of the integrated circuit 400, and similar detailed descriptions are omitted for brevity.

[0464] The integrated circuit 800 includes active region groups 402 and 404, gate groups 406 and 408, a gate removal portion group 840, contact groups 410, 412, 414, conductor groups 830 and 832, via groups 420, 422, 824, and 826, a substrate 490, and an insulating region 492.

[0465] The conductor group 830 includes at least one of conductor 430a, conductor 430b, conductor 430c, conductor 430d, or conductor 430e.

[0466] Compared to integrated circuit 400, conductor 830c in conductor group 830 replaces conductor 430c in conductor group 430, and similar detailed descriptions are omitted for brevity.

[0467] Conductor group 830 is an M0 wiring track. In some embodiments, conductor group 830 is a track for wiring in other layers. In some embodiments, conductor group 830 corresponds to 5 M0 wiring tracks. Other M0 track assignments or numbers are within the scope of this disclosure.

[0468] Other configurations, arrangements, or numbers of conductors in conductor group 830 are all within the scope of this disclosure.

[0469] The conductor group 832 includes at least one of conductor 432a, conductor 432b, conductor 432c, conductor 432d or conductor 432e.

[0470] Compared to integrated circuit 400, conductor 832c in conductor group 832 replaces conductor 432c in conductor group 432, and similar detailed descriptions are omitted for brevity.

[0471] Conductor group 832 is a BMO wiring track. In some embodiments, conductor group 832 is a wiring track in another layer. In some embodiments, conductor group 832 corresponds to 3 BMO wiring tracks. Other BMO track assignments or numbers are within the scope of this disclosure.

[0472] Other configurations in conductor group 832, arrangements on other layout layers, or the number of conductors are all within the scope of this disclosure.

[0473] The gate removal group 840 includes at least one of the gate removal portion 440a, gate removal portion 840b, or gate removal portion 440d.

[0474] In some embodiments, one or more gate removal portions 440a, 840b (as shown in Figure 9E), or 440d are corresponding insulation regions (not labeled) similar to insulation region group 492, and therefore such detailed descriptions are omitted.

[0475] In some embodiments, the insulating region of the removed gate portion 840b is configured to electrically insulate gates 406a1 and 406a2 from each other. In some embodiments, the insulating region of the removed gate portion 840b is configured to electrically insulate gates 408a1 and 408a2 from each other.

[0476] In some embodiments, the insulating region of the removed gate portion 840b is configured to electrically insulate gate 406b1 from gate 406b2. In some embodiments, the insulating region of the removed gate portion 840b is configured to electrically insulate gate 408b1 from gate 408b2.

[0477] Compared to integrated circuit 400, the gate removal portion 840b of the gate removal portion group 840 (as shown in Figure 9E) replaces the gate removal portions 440b and 440c of the gate removal portion group 440, and similar detailed descriptions are omitted for brevity.

[0478] Compared to the gate removal portions 440b and 440c of the integrated circuit 400, the gate removal portion 840b of the integrated circuit 800 does not have a "zigzag" shape, and therefore has a "rectangular shape" in both the first direction X and the second direction Y. For the sake of brevity, a similar detailed description is omitted.

[0479] Compared to the gate removal portions 440b and 440c of the integrated circuit 400, the gate removal portion 840b of the integrated circuit 800 has the same shape in the second direction Y.

[0480] In some embodiments, the first side of the insulating region 840b contacts the first side of the gate 406a1 / gate 408a1 and the first side of the gate 406b1 / gate 408b1.

[0481] In some embodiments, the second side of the insulating region 440c contacts the first side of the gate 406a2 / gate 408a2 and the first side of the gate 406b2 / gate 408a2.

[0482] In some embodiments, the first side of gate 406a1 / gate 408a1 is aligned with the first side of gate 406b1 / gate 408b1 in the second direction Y.

[0483] In some embodiments, the first side of gate 406a2 / gate 408a2 is aligned with the first side of gate 406b2 / gate 408b2 in the second direction Y.

[0484] Compared to the gate removal portions 440b and 440c of the integrated circuit 400, the gate removal portion 840b of the integrated circuit 800 has an increased width in the first direction X, and similar detailed descriptions are omitted for brevity.

[0485] In some embodiments, by increasing the width of the removed gate portion 840b in the first direction X, the removed gate portion 840b has an increased area compared to the removed gate portion 440b and the removed gate portion 440c.

[0486] In some embodiments, by increasing the width of the removed gate portion 840b, the area of ​​the removed gate portion 840b is increased, thereby increasing the distance between gates 406a1 / 408a1 and 406a2 / 408a2 in the first direction X, and thus increasing the distance between gates 406b1 / 408b1 and 406b2 / 408b2 in the first direction X.

[0487] The removal of other configurations in gate group 840, arrangements on other layout layers, or the number of gate portions removed are all within the scope of this disclosure.

[0488] The through-hole group 824 includes at least one through-hole 824a.

[0489] Compared to integrated circuit 400, via 824a in via group 824 replaces via 424a in via group 424, and similar detailed descriptions are omitted for brevity.

[0490] Compared to the via 424a of the integrated circuit 400, the via 824a of the integrated circuit 800 has an increased width W2a in the first direction X. For the sake of brevity, a similar detailed description is omitted.

[0491] In some embodiments, the area of ​​the via 824a is increased by increasing the width W2a of the via 824a in the first direction X.

[0492] In some embodiments, since the width of the removed gate portion 840b increases in the first direction X, the width W2a of the through hole 824c also increases in the first direction X so as to electrically connect to the gate 406a1.

[0493] Other configurations in via group 824, arrangements on other layout layers, or the number of vias are all within the scope of this disclosure.

[0494] The through-hole group 826 includes at least one of through-hole 426a, through-hole 426b or through-hole 826c.

[0495] Compared to integrated circuit 400, via 826c of via group 826 replaces via 426c of via group 426, and similar detailed descriptions are omitted for brevity.

[0496] Compared to the via 426c of the integrated circuit 400, the via 826c of the integrated circuit 800 has an increased width W2b in the first direction X. For the sake of brevity, a similar detailed description is omitted.

[0497] In some embodiments, the area of ​​the via 826c is increased by increasing the width W2b of the via 826c in the first direction X.

[0498] In some embodiments, as the width of the removed gate portion 840b increases in the first direction X, the width W2b of the through hole 826c also increases in the first direction X to electrically connect to the gate 408b2.

[0499] In some embodiments, at least one width of a through hole in through hole group 420, through hole group 422, through hole group 824 or through hole group 826 in the first direction X is equal to at least one width of another through hole in through hole group 420, through hole group 422, through hole group 824 or through hole group 826 in the first direction X.

[0500] In some embodiments, at least one width of a through hole in a through hole group 420, through hole group 422, through hole group 824 or through hole group 826 in the first direction X is different from at least one width of another through hole in a through hole group 420, through hole group 422, through hole group 824 or through hole group 826 in the first direction X.

[0501] Other configurations in via group 826, arrangements on other layout layers, or the number of vias are all within the scope of this disclosure.

[0502] In some embodiments, at least one of the through holes 824a or 826c is referred to as a "slotted through hole".

[0503] In some embodiments, the integrated circuit 800 achieves one or more of the advantages described herein.

[0504] Other configurations, arrangements of other layers, or number of elements in the integrated circuit 800 are all within the scope of this disclosure.

[0505] Figures 9A to 9G are diagrams of an integrated circuit 900 according to some embodiments.

[0506] Figures 9A to 9D represent the corresponding portions 900A, 900B, and 900C of the integrated circuit 900. The corresponding diagram for the 900D section [、] has been simplified for ease of explanation.

[0507] Part 900A includes one or more characteristics of the OD layer, POLY layer, CPO layer, MD layer, MDLI layer, VG layer, VD layer, and M0 layer of integrated circuit 900. Part 900A is manufactured using a layout design at least similar to that of Part 700A, and similar detailed descriptions are omitted for brevity.

[0508] Part 900B includes one or more characteristics of the OD layer, POLY layer, CPO layer, BMD layer, MDLI layer, BVG layer, BVD layer, and BMO layer of the integrated circuit 900. Part 900B is manufactured using a layout design at least similar to that of Part 700B, and similar detailed descriptions are omitted for brevity.

[0509] Part 900C includes one or more features of the VG, VD, and M0 layers of integrated circuit 800. Part 900C is manufactured using a layout design at least similar to that of Part 700C, and similar detailed descriptions are omitted for brevity.

[0510] Part 900D includes one or more features of the BVG layer, BVD layer, and BMO layer of integrated circuit 800. Part 900D is manufactured with a layout design at least similar to that of Part 700D, and similar detailed descriptions are omitted for brevity.

[0511] Figures 9E to 9G are corresponding cross-sectional views of an integrated circuit 900 according to some embodiments. Figure 9E is a cross-sectional view of the integrated circuit 900 intersecting with plane G-G' according to some embodiments. Figure 9F is a cross-sectional view of the integrated circuit 900 intersecting with plane H-H' according to some embodiments. Figure 9G is a cross-sectional view of the integrated circuit 900 intersecting with plane I-I' according to some embodiments.

[0512] In some embodiments, the integrated circuit 900 is a memory cell 200.

[0513] Integrated circuit 900 is manufactured using a similar layout design to integrated circuit 900.

[0514] In some embodiments, the integrated circuit 900 is manufactured using a layout design similar to that of layout design 700, therefore a similar detailed description is omitted. The structural relationships (including alignment, length, and width) and configuration and layers of the integrated circuit 900 are similar to those of the integrated circuit 800 in Figures 8A to 8D. Furthermore, for the sake of brevity, a similar detailed description will not be described in at least Figures 9A to 9G.

[0515] The integrated circuit 900 is unit 901.

[0516] Integrated circuit 900 is a variant of integrated circuit 800 in Figures 8A to 8D, and similar detailed descriptions are omitted for the sake of brevity.

[0517] Compared to the integrated circuit 800 in Figures 8A to 8D, conductor group 930 replaces conductor group 430 of integrated circuit 800, and conductor group 932 replaces conductor group 432 of integrated circuit 800, and similar detailed descriptions are omitted for brevity.

[0518] The integrated circuit 900 includes at least active region groups 402 and 404, gate groups 406 and 408, a gate removal portion group 440, contact groups 410, 412, 414, conductor groups 930 and 932, via groups 420, 422, 424, and 426, a substrate 490, and an insulating region 492.

[0519] The conductor group 930 includes at least one of conductor 430a, conductor 430b, conductor 430c, conductor 430d, or conductor 430e.

[0520] Compared to integrated circuit 800, conductor 930c in conductor group 930 replaces conductor 830c in conductor group 830, and similar detailed descriptions are omitted for brevity.

[0521] Compared to conductor 830c of integrated circuit 800, conductor 930c of integrated circuit 900 has an increased length L2a in the second direction Y. For the sake of brevity, a similar detailed description is omitted.

[0522] Compared to conductor 830c of integrated circuit 800, conductor 930c has an increased area by increasing its length L2a in the second direction Y.

[0523] In some embodiments, increasing the area of ​​conductor 930c leads to a reduction in capacitive coupling between conductors 430b and 430d, thereby improving the speed and performance of the integrated circuit 900 compared to other methods.

[0524] Conductor group 930 is an M0 wiring track. In some embodiments, conductor group 930 is a track for wiring in other layers. In some embodiments, conductor group 930 corresponds to 5 M0 wiring tracks. Other M0 track assignments or numbers are within the scope of this disclosure.

[0525] Other configurations in conductor group 930, arrangements on other layout layers, or the number of conductors are all within the scope of this disclosure.

[0526] The conductor group 932 includes at least one of conductor 432a, conductor 432b, conductor 432c, conductor 432d or conductor 432e.

[0527] Compared to integrated circuit 800, conductor 932c in conductor group 932 replaces conductor 832c in conductor group 832, and similar detailed descriptions are omitted for brevity.

[0528] Compared to conductor 832c of integrated circuit 800, conductor 932c of integrated circuit 900 has an increased length L2b in the second direction Y. For the sake of brevity, a similar detailed description is omitted.

[0529] Compared to conductor 832c of integrated circuit 800, conductor 930c has an increased area by increasing the length L2b of conductor 932c in the second direction Y.

[0530] In some embodiments, increasing the area of ​​conductor 932c leads to a reduction in capacitive coupling between conductors 432b and 432d, thereby improving the speed and performance of the integrated circuit 900 compared to other methods.

[0531] Conductor group 932 is a BMO wiring track. In some embodiments, conductor group 932 is a wiring track in another layer. In some embodiments, conductor group 932 corresponds to 3 BMO wiring tracks. Other BMO track assignments or numbers are within the scope of this disclosure.

[0532] Other configurations in conductor group 932, arrangements on other layout layers, or the number of conductors are all within the scope of this disclosure.

[0533] In some embodiments, by including conductor 930c in the integrated circuit 900, the capacitive coupling between bit line BL and bit line BLB is reduced, thereby improving the speed and performance of the integrated circuit 900 compared to other methods.

[0534] In some embodiments, the integrated circuit 900 achieves one or more of the advantages described herein.

[0535] Other configurations, arrangements of other layers, or number of elements in the integrated circuit 900 are all within the scope of this disclosure.

[0536] Figures 10A to 10B are corresponding functional flowcharts of methods 1000A to 1000B for manufacturing IC components according to some embodiments. It should be understood that additional operations may be performed before, during, and / or after method 1000A shown in Figure 10A, and some other processes may only be briefly described herein.

[0537] It should be understood that additional operations may be performed before, during, and / or after method 1000B shown in Figure 10B, and some other processes may only be briefly described here.

[0538] In some embodiments, the order of other operations of methods 1000A, 1000B, 1200, or 1300 is within the scope of this disclosure. Methods 1000A, 1000B, 1200, or 1300 include exemplary operations, but these operations are not necessarily performed in the order shown. Operations may be added, replaced, reordered, and / or eliminated as needed, according to the spirit and scope of the disclosed embodiments. In some embodiments, at least one or more operations of methods 1000A, 1000B, 1200, or 1300 are not performed.

[0539] In some embodiments, method 1000A is an embodiment of operation 1204 of method 1200. In some embodiments, method 1000A, method 1000B, or method 1200 and method 1300 can be used to manufacture or produce at least integrated circuit 100, integrated circuit 200, integrated circuit 400, integrated circuit 500, integrated circuit 600, integrated circuit 800, integrated circuit 900, or integrated circuit 1100, or integrated circuit having characteristics similar to at least layout design 300 or layout design 700.

[0540] In operation 1002 of method 1000A, a first set of transistors and a second set of transistors are fabricated on the front side 403a of a semiconductor wafer 490 or a substrate. In some embodiments, the first set of transistors or the second set of transistors in method 1000A includes one or more transistors from at least one active region group 402 or active region group 404. In some embodiments, the first set of transistors or the second set of transistors in method 1000A includes one or more transistors as described herein.

[0541] In some embodiments, operation 1002 includes fabricating source and drain regions of a transistor assembly in a first well, as further described in method 1000B. In some embodiments, the first well contains a p-type dopant. In some embodiments, the p-type dopant includes boron, aluminum, or other suitable p-type dopant. In some embodiments, the first well includes an epitaxial layer grown over a substrate. In some embodiments, the epitaxial layer is doped by adding a dopant during an epitaxial process. In some embodiments, the epitaxial layer is doped by ion implantation after its formation. In some embodiments, the first well is formed through a doped substrate. In some embodiments, doping is performed by ion implantation. In some embodiments, the first well has a dopant concentration ranging from 1 x 10¹² atoms / cm³ to 1 x 10¹⁴ atoms / cm³.

[0542] In some embodiments, the first well includes an n-type dopant. In some embodiments, the n-type dopant includes phosphorus, arsenic, or other suitable n-type dopant. In some embodiments, the concentration of the n-type dopant ranges from about 1 x 10¹² atoms / cm³ to about 1 x 10¹⁴ atoms / cm³.

[0543] In some embodiments, the formation of the source / drain features includes: removing a portion of the substrate to form a groove at the edge of the spacer, followed by performing a filling process by filling the groove in the substrate. In some embodiments, after removing the pad oxide layer or sacrificial oxide layer, the groove is etched, for example, by wet etching or dry etching. In some embodiments, an etching process is performed to remove a portion of the top surface of the active region adjacent to the isolation region (e.g., STI region). In some embodiments, the filling process is performed via epitaxial or epitaxial (epi) processes. In some embodiments, a growth process performed concurrently with the etching process is used to fill the groove, wherein the growth rate of the growth process is greater than the etching rate of the etching process. In some embodiments, a combination of growth and etching processes is used to fill the groove. For example, a layer of material is grown in the groove, and then the grown material is etched to remove a portion of the material. The etched material is then subjected to a subsequent growth process until the material in the groove reaches the desired thickness. In some embodiments, the growth process continues until the top surface of the material is above the top surface of the substrate. In some embodiments, the growth process continues until the top surface of the material is coplanar with the top surface of the substrate. In some embodiments, a portion of the first well is removed by an isotropic or anisotropic etching process. The etching process selectively etches the first well without etching the gate structure and any spacers. In some embodiments, reactive ion etching (RIE), wet etching, or other suitable techniques are used to perform the etching process. In some embodiments, semiconductor material is deposited in a trench to form source / drain features. In some embodiments, an epitaxial process is performed to deposit semiconductor material in the trench. In some embodiments, the epitaxial process includes selective epitaxial growth (SEG), CVD, molecular beam epitaxy (MBE), other suitable processes, and / or combinations thereof. The epitaxial process uses gaseous and / or liquid precursors that interact with the substrate composition. In some embodiments, the source / drain features include epitaxially grown silicon (epi Si), silicon carbide, or silicon germanium. In some cases, the source / drain features of the IC element associated with the gate structure are in-situ doped or undoped during the epitaxial process. When the source / drain features are undoped during the epitaxial process, in some cases, the source / drain features are doped during subsequent processes. Subsequent doping processes are achieved through ion implantation, plasma ion immersion implantation, gas and / or solid source diffusion, other suitable processes, and / or combinations thereof. In some embodiments, the source / drain features are further exposed to an annealing process after the formation of the source / drain features and / or after subsequent doping processes.

[0544] In some embodiments, operation 1002 also includes operation 1002a. In some embodiments, operation 1002a includes forming a first gate region of a second set of transistors. In some embodiments, the first gate region of the second set of transistors in method 1000A includes gate group 408.

[0545] In some embodiments, operation 1002 also includes operation 1002b. In some embodiments, operation 1002b includes forming a first insulating material on the first gate structure of the second set of transistors. In some embodiments, operation 1002b includes forming the first insulating material over at least the first gate structure of the first gate region of the second set of transistors. In some embodiments, the first insulating material includes an insulating region similar to insulating region 492. In some embodiments, operation 1002b is not performed.

[0546] In some embodiments, operation 1002 also includes operation 1002c. In some embodiments, operation 1002c includes forming a second gate region of the first set of transistors. In some embodiments, the second gate region of the first set of transistors in method 1000A includes gate group 406. In some embodiments, operations 1002a and 1002c are performed simultaneously.

[0547] In some embodiments, the first gate region and the second gate region are located between the drain region and the source region. In some embodiments, the first gate region and the second gate region are located above the first well and the substrate. In some embodiments, operating the first gate region and the second gate region in operations 1002a and 1002c includes performing one or more deposition processes to form one or more dielectric material layers. In some embodiments, the deposition processes include chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other processes suitable for depositing one or more material layers. In some embodiments, fabricating the first gate region and the second gate region includes performing one or more deposition processes to form one or more conductive material layers. In some embodiments, fabricating the first gate region and the second gate region includes forming a gate electrode or a dummy gate electrode. In some embodiments, fabricating the gate region includes depositing or growing at least one dielectric layer, such as a gate dielectric layer. In some embodiments, the gate region is formed using doped or undoped polysilicon (or polysilicon). In some embodiments, the first gate region and the second gate region comprise metals, such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof.

[0548] In some embodiments, forming a first insulating material on the first gate structure of the second set of transistors operating 1002b includes performing one or more deposition processes to form one or more dielectric material layers and / or insulating material layers. In some embodiments, the one or more deposition processes for forming one or more dielectric material layers and / or insulating material layers include CVD, PECVD, ALD, or other processes suitable for depositing one or more material layers. In some embodiments, forming a first insulating material on the first gate structure of the second set of transistors includes performing one or more deposition processes to form one or more insulating material layers. In some embodiments, the first insulating material is a dielectric material. In some embodiments, the dielectric material includes silicon dioxide, silicon oxynitride, etc.

[0549] In some embodiments, operations 1002a, 1002b, and 1002c are replaced by forming a first gate region and a second gate region of the second set of transistors, removing a portion of the first gate region and the second gate region of the second set of transistors, and forming a first insulating material between the first gate structure and the second gate structure of the second set of transistors. In some embodiments, the gate removal process is a POLY dicing process including one or more etching processes. In some embodiments, the gate removal process includes one or more etching processes suitable for removing portions of the gate structure. In some embodiments, a mask is used to specify the portion of the gate structure to be cut or removed. In some embodiments, the mask is a hard mask. In some embodiments, the mask is a soft mask. In some embodiments, etching corresponds to plasma etching, reactive ion etching, chemical etching, dry etching, wet etching, other suitable processes, any combination thereof, etc.

[0550] In some embodiments, the gate removal process of operation 1002a, operation 1002b or operation 1002c further includes the formation of gate group 406 or gate group 408, and the cutting area is identified by the cutting feature pattern group 340 of Figures 3A to 3D.

[0551] In some embodiments, operation 1002 also includes operation 1002d. In some embodiments, operation 1002d includes depositing a first conductive material on at least one of the first layer, the second layer, or the third layer to form at least one of a corresponding first set of contacts, the second set of contacts, or the third set of contacts.

[0552] In some embodiments, the first set of contacts, the second set of contacts, and the third set of contacts are part of the first set of transistors and the second set of transistors.

[0553] In some embodiments, the first set of contacts includes contact group 410 or contact group 610.

[0554] In some embodiments, the second set of contacts includes contact group 412 or contact group 612.

[0555] In some embodiments, the third set of contacts includes contact group 414.

[0556] In operation 1004 of method 1000A, a first set of vias is formed on the front side 403a of a wafer or substrate on a VD layer or VG layer (e.g., a VD layer or VG layer). In some embodiments, the first set of vias in method 1000A includes at least one or more portions of a via group 420, via group 424, via group 620, via group 624, or via group 824.

[0557] In some embodiments, operation 1004 includes forming a first set of self-aligned contacts (SACs) in an insulating layer above the wafer front side 403a. In some embodiments, the first set of vias is electrically connected to at least a first set of transistors or a second set of transistors.

[0558] In operation 1006 of method 1000A, a second conductive material is deposited on the substrate front side 403a of the first metal layer, thereby forming a first set of conductors (e.g., M0) on the wafer or substrate front side 403a of the first metal layer.

[0559] In some embodiments, operation 1006 includes at least depositing a first set of conductive regions over the front side 403a of the integrated circuit. In some embodiments, the first set of conductors in method 1000A includes one or more portions of at least one conductor group 430, conductor group 530, conductor group 630, conductor group 830, or conductor group 930.

[0560] In some embodiments, the first set of conductors includes a first mating side contact, a bit line BL, and a bit line BLB.

[0561] In operation 1008 of method 1000A, the back side 403b of a wafer or substrate is thinned. In some embodiments, operation 1010 includes a thinning process performed on the back side 403b of the semiconductor wafer or substrate. In some embodiments, the thinning process includes grinding operations and polishing operations (e.g., chemical mechanical polishing (CMP)) or other suitable processes. In some embodiments, after the thinning process, a wet etching operation is performed to remove defects formed on the back side 403b of the semiconductor wafer or substrate.

[0562] In operation 1010 of method 1000A, a second set of vias is formed on the back side 403b of a thinned wafer or substrate on a BVD layer or BVG layer (e.g., a BVD layer or a BVG layer). In some embodiments, the second set of vias in method 1000A includes one or more portions of at least one via group 422, via group 426, via group 622, via group 626, or via group 826.

[0563] In some embodiments, operation 1010 includes forming a second set of self-aligned contacts (SACs) in an insulating layer above the wafer back side 403b. In some embodiments, the second set of vias is electrically connected to at least the first set of transistors or the second set of transistors.

[0564] In operation 1012 of method 1000A, a second conductive material is deposited on the substrate back side 403b of the second metal layer, thereby forming a second set of conductors (e.g., BMO) on the wafer or substrate back side 403b of the second metal layer.

[0565] In some embodiments, operation 1012 includes at least depositing a second set of conductive regions over the back side 403b of the integrated circuit. In some embodiments, the second set of conductors in method 1000A includes one or more portions of at least one conductor group 432, conductor group 532, conductor group 632, conductor group 832, or conductor group 932.

[0566] In some embodiments, the second set of conductors is electrically coupled to at least the second set of transistors through the second set of vias.

[0567] In some embodiments, the second set of conductors includes a second mating side contact and a word line WL. In some embodiments, the second set of transistors is configured to receive word line signals on the word line from the back side.

[0568] In some embodiments, one or more operations 1002, 1004, 1006, 1010, or 1012 of method 1000A include forming an opening in an insulating layer (not shown) above a substrate using a combination of photolithography and material removal processes. In some embodiments, the photolithography process includes patterning a photoresist (e.g., a positive or negative photoresist). In some embodiments, the photolithography process includes forming a hard mask, an anti-reflective structure, or other suitable photolithographic structure. In some embodiments, the material removal process includes a wet etching process, a dry etching process, a RIE process, laser drilling, or other suitable etching process. The opening is then filled with a conductive material, such as copper, aluminum, titanium, nickel, tungsten, or other suitable conductive material. In some embodiments, the opening is filled using CVD, PVD, sputtering, ALD, or other suitable formation processes.

[0569] In some embodiments, at least one or more operations of method 1000A or method 1000B are performed by system 1500 of Figure 15. In some embodiments, at least one method, such as method 1000A (discussed above) or 1000B (discussed below), is performed wholly or partially by at least one manufacturing system (including system 1500). One or more operations of method 1000A or method 1000B are performed by IC manufacturing plant 1540 (Figure 15) to manufacture IC device 1560. In some embodiments, one or more operations of method 1000A or method 1000B are performed by manufacturing tool 1552 to manufacture wafer 1542.

[0570] In some embodiments, the conductive material includes copper, aluminum, titanium, nickel, tungsten, or other suitable conductive materials. In some embodiments, CVD, PVD, sputtering, ALD, or other suitable forming processes are used to fill the openings and trenches. In some embodiments, after depositing the conductive material in one or more of operations 1002d, 1006, 1008, or 1012, the conductive material is planarized to provide a smooth surface for subsequent steps.

[0571] Figure 10B is a functional flowchart of a method 1000B for manufacturing an IC element according to some embodiments.

[0572] It should be understood that additional operations may be performed before, during, and / or after method 1000B shown in Figure 10B, and some other processes may only be briefly described here.

[0573] In some embodiments, method 1000B is an embodiment of operation 1204 of method 1200.

[0574] Figures 11A to 11I are cross-sectional views of an intermediate element structure obtained by fabricating a first mating contact on the front side of the integrated circuit and a second mating contact on the back side of the integrated circuit, according to some embodiments. In some embodiments, Figures 11A to 11I are cross-sectional views of the intermediate element structure of the integrated circuit 600.

[0575] The component structures in Figures 11A to 11I correspond to an intermediate version of the integrated circuit 600 along line E-E' in Figures 6A to 6B.

[0576] In operation 1020 of method 1000B, a first set of transistors and a first set of dummy gates of transistors are fabricated on the front side 403a of a semiconductor wafer or substrate.

[0577] In some embodiments, the device structure prepared in operation 1020 includes the device structure 1100A of FIG11A.

[0578] In the cross-sectional view of Figure 11A, the source region 1102a and the drain region 1102b are part of the active region 1102 of the n-type or p-type transistor and are formed on the front side 403a of the substrate 490.

[0579] The substrate 490 includes a front side 403a and a back side 403b.

[0580] The substrate 490 also includes alternating layers of a first group of semiconductor layers 1103 and a second group of semiconductor layers 1190.

[0581] In some embodiments, the first set of semiconductor layers 1103 includes a plurality of low-Ge SiGe layers. In some embodiments, the second set of semiconductor layers 1190 includes one or more Si layers.

[0582] In some embodiments, the substrate 490 also includes a layer 1150 between the first set of semiconductor layers 1103 and the second set of semiconductor layers 1190.

[0583] In some embodiments, layer 1150 includes at least one high-Ge SiGe layer.

[0584] A dummy gate 1104 is formed on the top surface of the substrate 490. In some embodiments, the dummy gate 1104 comprises a polycrystalline silicon material.

[0585] In operation 1022 of method 1000B, a first set of recessed regions is formed in a first region of the front side 403a of a semiconductor wafer or substrate. In some embodiments, operation 1022 includes performing a first etching process in the first region of the front side 403a of the semiconductor wafer or substrate.

[0586] In some embodiments, the first set of groove regions is also referred to as the first set of source / drain groove regions.

[0587] In some embodiments, the device structure prepared in operation 1022 includes device structure 1100B of Figure 11B.

[0588] In the cross-sectional view of Figure 11B, a first set of recessed regions 1161 are formed in the first region 1160 of the front side 403a of the substrate 490.

[0589] In operation 1024 of method 1000B, a second set of recessed regions is formed in a second region of the front side 403a of the semiconductor wafer or substrate. In some embodiments, operation 1024 includes performing a second etching process in the second region of the front side 403a of the semiconductor wafer or substrate.

[0590] In some embodiments, the second set of groove regions is also referred to as the second set of source / drain groove regions.

[0591] In some embodiments, the second etching process includes one or more etching processes with high etching selectivity to remove portions of the first set of semiconductor layers 1103 without removing portions of the second set of semiconductor layers 1190.

[0592] In some embodiments, the device structure prepared in operation 1024 includes the device structure 1100C of Figure 11C.

[0593] In the cross-sectional view of Figure 11C, the second set of recessed regions 1163 are formed in the second region 1162 of the front side 403a of the substrate 490.

[0594] In operation 1026 of method 1000B, an inner spacer region 1152 is formed in the second set of recessed regions. In some embodiments, operation 1028 includes depositing a first set of insulating regions in the second set of recessed regions. In some embodiments, operation 1026 includes performing a first deposition process to form the inner spacer region.

[0595] In some embodiments, the device structure prepared in operation 1026 includes device structure 1100D of figure 11D.

[0596] In the cross-sectional view of Figure 11D, the inner spacer region 1152 is formed in the second set of recessed regions 1163 on the front side 403a of the substrate 490.

[0597] In operation 1028 of method 1000B, a third set of recessed regions is formed in a third region of the front side 403a of the semiconductor wafer or substrate. In some embodiments, operation 1028 includes performing a third etching process in the third region of the front side 403a of the semiconductor wafer or substrate.

[0598] In some embodiments, the device structure prepared in operation 1028 includes device structure 1100E of Figure 11E.

[0599] In the cross-sectional view of Figure 11E, a third set of recessed regions 1171 are formed in the third region 1170 of the front side 403a of the substrate 490. In some embodiments, operation 1028 includes removing layer 1150 through a third etching process.

[0600] In some embodiments, the third etching process includes one or more etching processes with high etching selectivity to remove portions of layer 1150 without removing portions of the inner spacer region 1152, the first set of semiconductor layers 1103, and the second set of semiconductor layers 1190.

[0601] In operation 1030 of method 1000B, an insulating layer is formed in the third set of recessed regions. In some embodiments, operation 1030 includes depositing a second set of insulating regions in the third set of recessed regions.

[0602] In some embodiments, operation 1030 includes performing a second deposition process to form an insulating layer between the first set of transistors and the second set of transistors. In some embodiments, operation 1030 includes performing a second deposition process to form a dielectric layer between the first set of transistors and the second set of transistors.

[0603] In some embodiments, the device structure prepared in operation 1030 includes device structure 1100F of figure 11F.

[0604] In the cross-sectional view of Figure 11F, the insulating layer 1172 is formed in the third set of recessed regions 1171.

[0605] In operation 1032 of method 1000B, a first set of source / drain regions of the first set of transistors and a second set of source / drain regions of the second set of transistors are formed in the first set of recessed regions.

[0606] In some embodiments, operation 1032 includes performing one or more epitaxial growth processes to form one or more epitaxial layers in a first set of recessed regions.

[0607] In some embodiments, one or more epitaxial layers are doped by adding dopants during the epitaxial process. In some embodiments, one or more epitaxial layers are doped by ion implantation after the formation of the epitaxial layers.

[0608] In some embodiments, the device structure prepared in operation 1032 includes the device structure 1100G of Figure 11G.

[0609] In the cross-sectional view of Figure 11G, the first source / drain region 1174 of the first group of transistors and the second source / drain region 1176 of the second group of transistors are formed in the first recessed region 1161.

[0610] In operation 1034 of method 1000B, a first set of gates of the first set of transistors and a second set of gates of the second set of transistors are formed.

[0611] In some embodiments, operation 1034 includes performing a replacement polysilicon gate (RPG) cycle to form a first set of gates for a first set of transistors and a second set of gates for a second set of transistors.

[0612] In some embodiments, the gate materials of the first group of gates and the second group of gates have work functions that correspond to the corresponding channel materials.

[0613] In some embodiments, operation 1034 corresponds to one or more of operations 1002a, 1002b, or 1002c.

[0614] In some embodiments, the device structure prepared in operation 1034 includes device structure 1100H of Figure 11H.

[0615] In the cross-sectional view of Figure 11H, the first gate 1180 of the first group of transistors and the second gate 1181 of the second group of transistors are formed.

[0616] In some embodiments, the first group of gates 1180 corresponds to the gate group 406, therefore a similar detailed description is omitted. In some embodiments, the second group of gates 1181 corresponds to the gate group 408, therefore a similar detailed description is omitted.

[0617] In operation 1036 of method 1000B, one or more back-end (BEOL) processes are performed to manufacture a first set of vias and a second set of vias, as well as a first set of conductors and a second set of conductors.

[0618] In some embodiments, operation 1036 includes fabricating a first set of through holes and a first set of conductors on the front side of the substrate, and fabricating a second set of through holes and a second set of conductors on the back side of the substrate.

[0619] In some embodiments, operation 1036 further includes manufacturing a first set of contacts, a second set of contacts, and a third set of contacts.

[0620] In some embodiments, operation 1036 corresponds to one or more of operation 1002d, operation 1004, operation 1006, operation 1010, or operation 1012.

[0621] In some embodiments, the device structure prepared in operation 1036 includes the device structure 1100I of Figure 11I.

[0622] In the cross-sectional view of Figure 11I, the first group of through holes 1182 of the first group of transistors and the second group of through holes 1184 of the second group of transistors are formed.

[0623] In some embodiments, the first group of through holes 1182 corresponds to through hole groups 420 and 424, therefore a similar detailed description is omitted. In some embodiments, the second group of through holes 1184 corresponds to through hole groups 422 and 426, therefore a similar detailed description is omitted.

[0624] In some embodiments, one or more of the operations of methods 1000A to 1000B, method 1200, or method 1300 are not performed.

[0625] One or more operations of methods 1200 to 1300 are performed by a process apparatus configured to execute instructions for manufacturing integrated circuits (e.g., at least integrated circuit 100, integrated circuit 200, integrated circuit 400, integrated circuit 500, integrated circuit 600, integrated circuit 800, integrated circuit 900, or integrated circuit 1100). In some embodiments, one or more operations of methods 1200 to 1300 are performed using the same process apparatus as used in one or more different operations of methods 1200 to 1300. In some embodiments, one or more operations of methods 1200 to 1300 are performed using a process apparatus different from the process apparatus that performs one or more different operations of methods 1200 to 1300. In some embodiments, the sequence of operations of methods 1000A to 1000B, method 1200, or method 1300 is within the scope of this disclosure. Methods 1000A to 1000B, 1200, or 1300 include exemplary operations, but these operations are not necessarily performed in the order shown. Operations in methods 1000A to 1000B, 1200, or 1300 may be added, replaced, rearranged, and / or eliminated as needed, in accordance with the spirit and scope of the disclosed embodiments.

[0626] Figure 12 is a flowchart of a method 1200 for forming or manufacturing an integrated circuit according to some embodiments. It should be understood that additional operations may be performed before, during, and / or after the method 1200 shown in Figure 12, and some other operations may only be briefly described herein. In some embodiments, method 1200 may be used to form an integrated circuit, such as at least integrated circuit 100, integrated circuit 200, integrated circuit 400, integrated circuit 500, integrated circuit 600, integrated circuit 800, integrated circuit 900, or integrated circuit 1100. In some embodiments, method 1200 may be used to form an integrated circuit having one or more similar features and similar structural relationships to layout design 300 or layout design 700.

[0627] In operation 1202 of method 1200, a layout design for an integrated circuit is generated. Operation 1202 is performed by a process device (e.g., processor 1402 (Figure 14)) configured to execute instructions for generating the layout design. In some embodiments, the layout design of method 1200 includes one or more patterns of at least layout design 300 or layout design 700, or features similar to one or more of at least integrated circuit 100, integrated circuit 200, integrated circuit 400, integrated circuit 500, integrated circuit 600, integrated circuit 800, integrated circuit 900, or integrated circuit 1100. In some embodiments, the layout design of this application employs a Graphical Database System (GDSII) file format. In some embodiments, operation 1202 corresponds to method 1300 of Figure 13.

[0628] In operation 1204 of method 1200, an integrated circuit is manufactured based on a layout design. In some embodiments, operation 1204 of method 1200 includes manufacturing at least one mask based on a layout design, and manufacturing an integrated circuit based on at least one mask. In some embodiments, operation 1204 corresponds to methods 1000A to 1000B of figures 10A to 10B.

[0629] Figure 13 is a flowchart of a method 1300 for generating an integrated circuit layout design according to some embodiments. It should be understood that additional operations may be performed before, during, and / or after method 1300 shown in Figure 13, and this document may only briefly describe some other processes. In some embodiments, method 1300 is an embodiment of operation 1202 of method 1200. In some embodiments, method 1300 can be used to generate one or more layout patterns of at least layout design 300 or layout design 700, or similar to one or more features of at least integrated circuit 100, integrated circuit 200, integrated circuit 400, integrated circuit 500, integrated circuit 600, integrated circuit 800, integrated circuit 900, or integrated circuit 1100.

[0630] In some embodiments, method 1300 can be used to generate one or more layout patterns having structural relationships including alignment, length and width, and configurations and layers of at least layout design 300 or layout design 700, or one or more features similar to at least integrated circuit 100, integrated circuit 200, integrated circuit 400, integrated circuit 500, integrated circuit 600, integrated circuit 800, integrated circuit 900 or integrated circuit 1100, and for the sake of brevity, similar detailed descriptions will not be described again in Figure 13.

[0631] In operation 1302 of method 1300, a set of active region patterns is generated or placed on a layout design. In some embodiments, the active region pattern set of method 1300 includes at least a portion of one or more patterns in active region pattern group 302 or active region pattern group 304. In some embodiments, the active region pattern group of method 1300 includes one or more regions similar to active region group 402 or active region group 404. In some embodiments, the active region pattern group of method 1300 includes one or more patterns or similar patterns in an OD layer.

[0632] In operation 1304 of method 1300, a gate pattern set is generated or placed on a layout design. In some embodiments, the gate pattern set of method 1300 includes at least a portion of one or more patterns from gate pattern set 306 or gate pattern set 308 or cut feature pattern set 340 or cut feature pattern set 740. In some embodiments, the active gate pattern set of method 1300 includes one or more regions similar to gate set 406 or gate set 408 or the removed gate portion set 440. In some embodiments, the gate pattern set of method 1300 includes one or more patterns or similar patterns in a POLY layer.

[0633] In operation 1306 of method 1300, a first set of conductive patterns is generated or placed on a layout design. In some embodiments, the first set of conductive patterns of method 1300 includes at least a portion of one or more patterns of contact pattern group 310. In some embodiments, the first set of conductive patterns of method 1300 includes one or more patterns similar to contact group 410 or contact group 610. In some embodiments, the first set of conductive patterns of method 1300 includes one or more patterns or similar patterns in an MD layer.

[0634] In operation 1308 of method 1300, a second set of conductive patterns is generated or placed on a layout design. In some embodiments, the second set of conductive patterns of method 1300 includes at least a portion of one or more patterns of contact pattern group 312. In some embodiments, the second set of conductive patterns of method 1300 includes one or more patterns similar to contact group 412 or contact group 612. In some embodiments, the second set of conductive patterns of method 1300 includes one or more patterns or similar patterns in a BMD layer.

[0635] In operation 1310 of method 1300, a third set of conductive patterns is generated or placed on a layout design. In some embodiments, the third set of conductive patterns of method 1300 includes at least a portion of one or more patterns of contact pattern group 314. In some embodiments, the third set of conductive patterns of method 1300 includes one or more patterns similar to contact group 414. In some embodiments, the third set of conductive patterns of method 1300 includes one or more patterns or similar patterns in an MDLI layer.

[0636] In operation 1312 of method 1300, a first set of via patterns is generated or placed on a layout design. In some embodiments, the first set of via patterns in method 1300 includes at least a portion of one or more patterns from via pattern group 320, via pattern group 324, or via pattern group 724. In some embodiments, the first set of via patterns in method 1300 includes one or more via patterns at least similar to via group 420, via group 424, via group 624, via group 624, or via group 824. In some embodiments, the first set of via patterns in method 1300 includes one or more patterns or similar vias in a VG layer or VD layer.

[0637] In operation 1314 of method 1300, a second set of via patterns is generated or placed on a layout design. In some embodiments, the second set of via patterns in method 1300 includes at least a portion of one or more patterns from via pattern group 322, via pattern group 326, or via pattern group 726. In some embodiments, the second set of via patterns in method 1300 includes one or more via patterns similar to at least one via group 422, via group 426, via group 622, via group 626, or via group 826. In some embodiments, the second set of via patterns in method 1300 includes one or more patterns or similar vias in a BVG layer or BVD layer.

[0638] In operation 1316 of method 1300, a fourth set of conductive patterns is generated or placed on a layout design. In some embodiments, the fourth set of conductive patterns in method 1300 includes at least a portion of one or more patterns from at least one conductive pattern group 330 or conductive pattern group 730. In some embodiments, the fourth set of conductive patterns in method 1300 includes one or more conductive patterns similar to at least one conductor group 430, conductor group 530, conductor group 630, conductor group 830, or conductor group 930. In some embodiments, the fourth set of conductive patterns in method 1300 includes one or more patterns or similar conductors in the MO layer.

[0639] In operation 1318 of method 1300, a fifth set of conductive patterns is generated or placed on a layout design. In some embodiments, the fifth set of conductive patterns in method 1300 includes at least a portion of one or more patterns from at least one conductive pattern group 332 or conductive pattern group 732. In some embodiments, the fifth set of conductive patterns in method 1300 includes one or more conductive patterns similar to at least one conductor group 432, conductor group 532, conductor group 632, conductor group 832, or conductor group 932. In some embodiments, the fifth set of conductive patterns in method 1300 includes one or more patterns or similar conductors in a BMO layer.

[0640] Figure 14 is a schematic diagram of a system 1400 for designing IC layout and manufacturing IC circuits according to some embodiments.

[0641] In some embodiments, system 1400 generates or places one or more IC layout designs as described herein. System 1400 includes a hardware processor 1402 and a nontransitory computer-readable storage medium 1404 (e.g., memory 1404) wherein computer program code 1406, i.e., a set of executable instructions 1406, is encoded (i.e., stored). Computer-readable storage medium 1404 is configured to interface with a manufacturing machine for producing integrated circuits. Processor 1402 is electrically coupled to computer-readable storage medium 1404 via bus 1408. Processor 1402 is also electrically coupled to I / O interface 1410 via bus 1408. Network interface 1412 is also electrically connected to processor 1402 via bus 1408. Network interface 1412 is connected to network 1414, enabling processor 1402 and computer-readable storage medium 1404 to be connected to external components via network 1414. Processor 1402 is configured to execute computer program code 1406 encoded in computer-readable storage medium 1404 so that system 1400 can be used to perform some or all of the operations described in methods 1200 to 1300.

[0642] In some embodiments, the processor 1402 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0643] In some embodiments, computer-readable storage media 1404 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, computer-readable storage media 1404 includes semiconductor or solid-state disks, magnetic tapes, portable computer disk drives, random access memory (RAM), read-only memory (ROM), hard disks, and / or optical discs. In some embodiments using optical discs, computer-readable storage media 1404 includes read-only optical discs (CD-ROM), CD-R / W, and / or digital video discs (DVDs).

[0644] In some embodiments, storage medium 1404 stores computer program code 1406 configured to cause system 1400 to perform methods 1200 to 1300. In some embodiments, storage medium 1404 also stores information required to perform methods 1200 to 1300, as well as information generated during the execution of methods 1200 to 1300. For example, layout design 1416, user interface 1418, and manufacturing unit 1420, and / or a set of executable instructions to perform the operations of methods 1200 to 1300. In some embodiments, layout design 1416 includes one or more layout patterns of at least layout design 300 or layout design 700, or features similar to at least integrated circuit 100, integrated circuit 200, integrated circuit 400, integrated circuit 500, integrated circuit 600, integrated circuit 800, integrated circuit 900, or integrated circuit 1100.

[0645] In some embodiments, storage medium 1404 stores instructions (e.g., computer code 1406) for interfacing with a manufacturing machine. These instructions (e.g., computer code 1406) enable processor 1402 to generate manufacturing instructions readable by the manufacturing machine to efficiently implement method 1200 or method 1300 in the manufacturing process.

[0646] System 1400 includes an I / O interface 1410. In some embodiments, the I / O interface 1410 includes a keyboard, numeric keypad, mouse, trackball, touchpad, and / or cursor arrow keys for transmitting messages and instructions to processor 1402.

[0647] System 1400 also includes a network interface 1412 coupled to processor 1402. Network interface 1412 allows system 1400 to communicate with network 1414, to which one or more other computer systems are connected. Network interface 1412 includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, and WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-2094. In some embodiments, methods 1200 to 1300 are implemented in two or more systems 1400, and information such as layout design and user interface is exchanged between different systems 1400 via network 1414.

[0648] System 1400 is configured to receive layout-related information via I / O interface 1410 or network interface 1412. This information is transmitted to processor 1402 via bus 1408 to determine a layout design for producing at least integrated circuits 100, 200, 400, 500, 600, 800, 900, or 1100. The layout design is then stored as layout design 1416 in computer-readable storage medium 1404. System 1400 is configured to receive user interface-related information via I / O interface 1410 or network interface 1412. This information is stored in computer-readable storage medium 1404 as user interface 1418. System 1400 is configured to receive information related to manufacturing unit 1420 via I / O interface 1410 or network interface 1412. This information is stored as manufacturing unit 1420 in computer-readable storage medium 1404. In some embodiments, manufacturing unit 1420 includes manufacturing information used by system 1400. In some embodiments, manufacturing unit 1420 corresponds to mask manufacturing 1534 in Figure 15.

[0649] In some embodiments, methods 1200 to 1300 are executed as standalone software applications by a processor. In some embodiments, methods 1200 to 1300 are performed as software applications as part of an additional software application. In some embodiments, methods 1200 to 1300 are performed as add-ons to a software application. In some embodiments, methods 1200 to 1300 are performed as software applications as part of an EDA tool. In some embodiments, methods 1200 to 1300 are performed as software applications used by an EDA tool. In some embodiments, the EDA tool is used to generate layouts of integrated circuit devices. In some embodiments, the layout is stored on a non-transitory computer-readable medium. In some embodiments, the layout is generated using tools such as VIRTUOSO® provided by CADENCE DESIGN SYSTEMS, Inc., or other suitable layout generation tools. In some embodiments, the layout is generated based on a netlist built from a schematic-based design. In some embodiments, methods 1200 to 1300 are implemented by a manufacturing apparatus to fabricate integrated circuits using a set of masks fabricated based on one or more layout designs generated by system 1400. In some embodiments, system 1400 is a manufacturing apparatus configured to fabricate integrated circuits using a set of masks fabricated based on one or more layout designs disclosed herein. In some embodiments, system 1400 of Figure 14 produces integrated circuit layout designs that are smaller than those of other methods. In some embodiments, system 1400 of Figure 14 produces layout designs for integrated circuit structures that occupy a smaller area and provide better wiring resources than other methods.

[0650] Figure 15 is a block diagram of an integrated circuit (IC) manufacturing system 1500 and its associated IC manufacturing processes according to at least one embodiment of the present disclosure. In some embodiments, based on the layout diagram, the manufacturing system 1500 is used to manufacture (A) at least one of one or more semiconductor masks or (B) at least one component in a semiconductor integrated circuit layer.

[0651] In Figure 15, the IC manufacturing system 1500 (hereinafter referred to as "System 1500") includes entities such as a design company 1520, a masking company 1530, and an IC manufacturer / processor ("Factory") 1540. They interact during the design, development, and manufacturing cycles, and / or provide services related to the manufacture of IC components 1560. The entities in System 1500 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, one or more of the design company 1520, masking company 1530, and IC wafer fab 1540 are owned by a single, larger company. In some embodiments, one or more of the design company 1520, masking company 1530, and IC wafer fab 1540 coexist in a shared facility and use shared resources.

[0652] Design company (or design team) 1520 generates IC design layout 1522. IC design layout 1522 includes various geometric patterns designed for IC component 1560. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute the various components of the IC component 1560 to be manufactured. The layers are combined to form various IC features. For example, a portion of IC design layout 1522 includes various IC features such as active regions, gate electrodes, source electrodes and drain electrodes, metal lines or vias for interlayer interconnects, and openings in pads. Formed on a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design company 1520 implements appropriate design procedures to form IC design layout 1522. Design processes include one or more of logic design, physical design, or place-and-route. IC design layout 1522 is presented in one or more data files containing geometric pattern information. For example, IC design layout 1522 may be represented in GDSII file format or DFII file format.

[0653] Masking company 1530 includes data preparation 1532 and mask manufacturing 1534. Masking company 1530 uses IC design layout 1522 to manufacture one or more masks 1545 for use in manufacturing various layers of IC device 1560 according to IC design layout 1522. Masking company 1530 performs mask data preparation 1532, in which IC design layout 1522 is converted into a representative data file (RDF). Mask data preparation 1532 provides the RDF to mask manufacturing 1534. A mask writer converts the RDF into an image on a substrate, such as a mask (photomask) 1545 or a semiconductor wafer 1542. IC design layout 1522 is manipulated by mask data preparation 1532 to conform to the specific characteristics of the mask writer and / or the requirements of IC manufacturer 1540. In Figure 15, mask data preparation 1532 and mask manufacturing 1534 are shown as separate elements. In some embodiments, mask data preparation 1532 and mask manufacturing 1534 can be collectively referred to as mask data preparation.

[0654] In some embodiments, mask data preparation 1532 includes optical proximity correction (OPC), which uses photolithographic enhancement techniques to compensate for image errors, such as those caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout 1522. In some embodiments, mask data preparation 1532 includes further resolution enhancement techniques (RET), such as off-axis emission, sub-resolution auxiliary patterning, phase-transfer masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0655] In some embodiments, mask data preparation 1532 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout that has undergone the process in OPC. These mask creation rules include certain geometric and / or connectivity constraints to ensure sufficient margin to account for variations in the semiconductor manufacturing process, etc. In some embodiments, the MRC modifies the IC design layout to compensate for constraints during mask manufacturing 1534, which may undo some modifications performed by the OPC to satisfy the mask creation rules.

[0656] In some embodiments, mask data preparation 1532 includes lithography process inspection (LPC), which simulates the process performed by IC manufacturing plant 1540 to manufacture IC device 1560. The LPC simulates this process based on IC design layout 1522 to establish an analog manufacturing device, such as IC device 1560. Process parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as spatial image contrast, depth of field (DOF), mask error enhancement factor (MEEF), other suitable factors, and combinations thereof. In some embodiments, after establishing the analog manufacturing equipment via LPC, if the shape of the analog equipment is not close enough to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 1522.

[0657] It should be understood that, for clarity, the description of the masking data preparation 1532 above has been simplified. In some embodiments, data preparation 1532 includes additional functions, such as logical operations (LOPs), to modify the IC design layout according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1522 during data preparation 1532 can be performed in various different sequences.

[0658] After mask data preparation 1532 and during mask manufacturing 1534, a mask 1545 or a set of masks 1545 is manufactured based on a modified IC design layout 1522. In some embodiments, mask manufacturing 1534 includes performing one or more photolithographic exposures based on the IC design layout 1522. In some embodiments, based on the modified IC design layout 1522, a pattern is formed on the mask (photomask or photomask) 1545 using a mechanism of electron beam (e-beam) or multiple electron beams. The mask 1545 can be formed using a variety of techniques. In some embodiments, the mask 1545 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. Radiation beams (e.g., ultraviolet (UV) beams) used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer are blocked by the opaque areas and pass through the transparent areas. In one example, the binary version of the mask 1545 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another example, mask 1545 is formed using a phase transfer technique. In the phase transfer mask (PSM) version of mask 1545, various features in the pattern formed on the mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase transfer mask version can be attenuated PSM or alternating PSM. The mask produced by mask fabrication 1534 can be used in a variety of processes. For example, such a mask can be used in ion implantation processes to form various doped regions in a semiconductor wafer, in etching processes to form various etched regions in a semiconductor wafer, and / or for other suitable processes.

[0659] IC wafer fab 1540 is an IC manufacturing entity that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC wafer fab 1540 is a semiconductor foundry. For example, there may be one manufacturing facility for front-end manufacturing (FEOL manufacturing) of multiple IC products, a second manufacturing facility that can provide back-end manufacturing (BEOL manufacturing) for the interconnection and packaging of IC products, and a third manufacturing facility that can provide other services for the foundry entity.

[0660] IC wafer fab 1540 includes wafer fabrication tool 1552 (hereinafter referred to as "fabrication tool 1552") configured to perform various manufacturing operations on semiconductor wafer 1542 such that IC device 1560 is manufactured according to a mask (e.g., mask 1545). In various embodiments, manufacturing tool 1552 includes a wafer lithography machine, ion implanter, photoresist coating machine, processing chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes discussed herein.

[0661] IC manufacturing plant 1540 uses a mask 1545, fabricated by mask company 1530, to manufacture IC device 1560. Therefore, IC manufacturing plant 1540 uses IC design layout 1522 at least indirectly to manufacture IC device 1560. In some embodiments, IC manufacturing plant 1540 uses mask 1545 to manufacture semiconductor wafer 1542 to form IC device 1560. In some embodiments, IC manufacturing includes performing one or more photolithography exposures at least indirectly based on IC design layout 1522. Semiconductor wafer 1542 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 1542 also includes one or more of various doped regions, dielectric features, multilayer interconnects, etc. (formed in subsequent manufacturing steps).

[0662] System 1500 is shown as having design company 1520, masking company 1530, or IC foundry 1540 as separate components or entities. However, it should be understood that one or more of design company 1520, masking company 1530, or IC foundry 1540 are part of the same component or entity.

[0663] In some embodiments, one or more operations of method 1300 are not performed. Furthermore, the various PFET or NFET transistors shown in this disclosure have specific doping types (e.g., N-type or P-type) for illustrative purposes only. The embodiments of this disclosure are not limited to specific transistor types, and one or more PFET or NFET transistors shown in this disclosure can be replaced by corresponding transistors of different transistor / dopane types. Similarly, the low or high logic values ​​of the various signals used in the above description are merely illustrative. The embodiments of this disclosure are not limited to specific logic values ​​at signal activation and / or deactivation. Different logic values ​​are selected within the scope of the various embodiments. Different numbers of transistors are selected within the scope of the various embodiments in this disclosure.

[0664] This specification relates to a memory cell. In some embodiments, the memory cell includes a first transistor of a first type coupled to a first storage node, the first transistor including a first gate on a first level. In some embodiments, the memory cell further includes a second transistor of a second type different from the first type, coupled to the first storage node, the second transistor including a second gate on a second level below the first level. In some embodiments, the memory cell further includes a third transistor of a first type coupled to a second storage node, the third transistor including a third gate on a first level, the third gate being separated from the first gate in at least a first direction. In some embodiments, the memory cell further includes a fourth transistor of a second type coupled to the second storage node, the fourth transistor including a fourth gate on a second level. In some embodiments, the memory cell further includes a first conductor extending along a second direction different from the first direction, the first conductor being located on a first metal layer above the front side of a substrate and coupled to the first gate and the second storage node. In some embodiments, the memory cell further includes a second conductor extending along the second direction, the second conductor being located on a second metal layer below the back side of a substrate and coupled to the fourth gate and the first storage node, the second metal layer being different from the first metal layer.

[0665] In some embodiments, each of the first gate, second gate, third gate, and fourth gate extends along a first direction, and the first gate and third gate are further separated from each other in a second direction. In some embodiments, the second gate and fourth gate are separated from each other in the first direction and the second direction.

[0666] In some embodiments, the device further includes: a first transmission gate transistor of a first type coupled to a first node, the first transmission gate transistor including a fifth gate located on a first level. In some embodiments, the device further includes: a second transmission gate transistor of a second type coupled to a second node, the second transmission gate transistor including a sixth gate located on a first level, wherein the fifth gate and the sixth gate extend along a first direction, the third gate and the fifth gate are separated from each other in the first direction, and the first gate and the sixth gate are separated from each other in the first direction.

[0667] In some embodiments, the device further includes: a first contact extending along a first direction, located on a third layer, and electrically coupled to the source / drain of a first transmission gate transistor; a second contact extending along a second direction, located on a third layer, and electrically coupled to the source / drain of a second transmission gate transistor; a third contact extending along a second direction, located on the third layer and a fourth layer different from the third layer, and electrically coupled to the source / drain of the first transistor, the source / drain of the second transistor, and the source / drain of the first transmission gate transistor; and a fourth contact extending along a second direction, located on the third and fourth layers, and electrically coupled to the source / drain of the third transistor, the source / drain of the fourth transistor, and the source / drain of the second transmission gate transistor.

[0668] In some embodiments, the device further includes: a first through-hole for electrically coupling a first conductor to a fourth contact, the first through-hole being located between the first conductor and the fourth contact; and a second through-hole for electrically coupling the first conductor to a first gate, the second through-hole being located between the first conductor and the first gate.

[0669] In some embodiments, the device further includes: a third conductor extending along a second direction, located on a first metal layer, coupled to a first contact, and configured as a bit line; a fourth conductor extending along the second direction, located on the first metal layer, coupled to a second contact, and configured as a bit line; a third via electrically coupling the third conductor to the first contact, the third via being located between the third conductor and the first contact; and a fourth via electrically coupling the fourth conductor to the second contact, the fourth via being located between the fourth conductor and the second contact; wherein the first conductor, the second conductor, the third conductor, and the fourth conductor are separated from each other in a first direction.

[0670] In some embodiments, the device further includes: a first insulating region located between a first gate and a sixth gate, the first insulating region being configured to electrically insulate the first gate and the sixth gate from each other; and a second insulating region located between a fifth gate and a third gate, the second insulating region being configured to electrically insulate the fifth gate and the third gate from each other; wherein a first side of the first insulating region contacts a first side of the first gate, a first side of the second insulating region contacts a first side of the fifth gate, and a first side of the first insulating region is offset from the first side of the second insulating region in a first direction.

[0671] In some embodiments, the first through hole has a first width in a first direction, and the second through hole has a second width in a first direction, wherein the first width is equal to the second width.

[0672] In some embodiments, the device further includes: a third through-hole for electrically coupling the second conductor to a third contact, the third through-hole being located between the second conductor and a third gate; and a fourth through-hole for electrically coupling the second conductor to a fourth gate, the fourth through-hole being located between the second conductor and the fourth gate.

[0673] In some embodiments, the third through hole has a first width in the first direction; the fourth through hole has a second width in the first direction; the first width is equal to the second width.

[0674] In some embodiments, the first conductor or the second conductor includes: a first conductive portion extending along a second direction; a second conductive portion extending along the second direction; and a third conductive portion extending along the second direction, wherein the third conductive portion is a central portion connected to the first conductive portion and the second conductive portion on corresponding opposite sides.

[0675] Another aspect of this specification relates to a memory cell. In some embodiments, the memory cell includes a first transistor of a first type, the first transistor including a first drain / source and a first gate on a first level. In some embodiments, the memory cell further includes a second transistor of a second type different from the first type, the second transistor including a second drain / source and a second gate on a second level below the first level. In some embodiments, the memory cell further includes a third transistor of a first type, the third transistor including a third drain / source and a third gate on the first level. In some embodiments, the memory cell further includes a fourth transistor of a second type, the fourth transistor including a fourth drain / source and a fourth gate on a second level, the fourth gate being separated from the second gate in at least a first direction. In some embodiments, the memory cell further includes a first conductor extending along a second direction different from the first direction, the first conductor being located on a first metal layer above the front side of a substrate, overlapping with the first gate, and coupled to the first gate, the third drain / source, and the fourth drain / source. In some embodiments, the memory cell further includes a second conductor extending along a second direction, the second conductor being located on a second metal layer below the back side of the substrate, overlapping with a fourth gate, and coupled to the fourth gate, a first drain / source, and a second drain / source, and the second metal layer being located below the first metal layer.

[0676] In some embodiments, the device further includes: a first transmission gate transistor of a first type, coupled to a first transistor and a second transistor, the first transmission gate transistor including a fifth drain / source and the fifth gate being located on a first level; and a second transmission gate transistor of a second type, coupled to a third transistor and a fourth transistor, the second transmission gate transistor including a sixth drain / source and the sixth gate being located on a first level.

[0677] In some embodiments, each of the first gate, second gate, third gate, fourth gate, fifth gate, and sixth gate extends along a first direction; the first gate and the third gate are separated from each other in the first direction and the second direction; the second gate and the fourth gate are further separated from each other in the second direction; the third gate and the fifth gate are separated from each other in the first direction; and the first gate and the sixth gate are separated from each other in the first direction.

[0678] In some embodiments, the device further includes: a first contact extending along a second direction, located on a third layer and a fourth layer different from the third layer, and electrically coupled to a first drain / source of a first transistor, a second drain / source of a second transistor, and a fifth drain / source of a first transmission gate transistor; and a second contact extending along the second direction, located on the third layer and the fourth layer, and electrically coupled to a third drain / source of a third transistor, a fourth drain / source of a fourth transistor, and a sixth drain / source of the second transmission gate transistor.

[0679] In some embodiments, the device further includes: a first through-hole for electrically coupling a first conductor to a second contact, the first through-hole being located between the first conductor and the second contact; and a second through-hole for electrically coupling the first conductor to a first gate, the second through-hole being located between the first conductor and the first gate.

[0680] In some embodiments, the device further includes: a first insulating region located between a first gate and a sixth gate, the first insulating region being configured to electrically insulate the first gate and the sixth gate from each other; and a second insulating region located between a fifth gate and a third gate, the second insulating region being configured to electrically insulate the fifth gate and the third gate from each other; wherein a first side of the first insulating region contacts a first side of the first gate, a first side of the second insulating region contacts a first side of the fifth gate, and the first side of the first insulating region is aligned with the first side of the second insulating region in a second direction.

[0681] In some embodiments, the device further includes: a third through-hole for electrically coupling the second conductor to the first contact, the third through-hole being located between the second conductor and the first gate; and a fourth through-hole for electrically coupling the second conductor to the fourth gate, the fourth through-hole being located between the second conductor and the fourth gate.

[0682] In some embodiments, the first through hole has a first width in a first direction; the second through hole has a second width in a first direction; the third through hole has a third width in a first direction; and the fourth through hole has a fourth width in a first direction; the first width is less than the second width, and the third width is less than the fourth width.

[0683] Another aspect of this specification relates to a method of manufacturing a memory cell. In some embodiments, the method includes fabricating a first set of transistors and a second set of transistors on the front side of a substrate, the first set of transistors being stacked on top of the second set of transistors. In some embodiments, the method further includes fabricating a first set of vias on the front side of the substrate, the first set of vias being electrically connected to at least the first set of transistors. In some embodiments, the method further includes depositing a first conductive material on the front side of the substrate on a first metal layer to form a first set of conductors, the first set of conductors being electrically coupled to at least the first set of transistors through the first set of vias, the first set of conductors including a first conductor electrically coupling a first gate of the first set of transistors and a first storage node of the memory cell together. In some embodiments, the method further includes thinning the back side of the substrate opposite to the front side. In some embodiments, the method further includes fabricating a second set of vias on the back side of the thinned substrate, the second set of vias being electrically connected to at least the second set of transistors. In some embodiments, the method further includes depositing a second conductive material on a second metal layer on the back side of a thinned substrate to form a second set of conductors, the second set of conductors being electrically coupled to at least a second set of transistors through a second set of vias, the second set of conductors including a second conductor electrically coupling a second gate of the second set of transistors and a second storage node of a memory cell together.

[0684] The foregoing summary outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0685] 100: Memory circuit (integrated circuit) 100BL: Global Input / Output Circuit (GIO Circuit) 100GC: Global Control Circuit 102A: Memory Partition 102B: Memory partition 102C: Memory Partition 102D: Memory Partition 110AC: Bit line drive circuit (WL drive circuit) 110AR: Memory Cell Array 110BS: Partial Input / Output Circuit (LIO Circuit) 110L: Memory Bank 110LC: Local control circuit 110U: Memory Bank 112: Memory unit (memory) (memory array) 114: Circuit 200: Memory Unit (Integrated Circuit) 300: Layout Design 300A: Partial 300B: Partial 300C: Partial 300D: Partial 301: Unit 301a: Element Boundary 301b: Element Boundary 301c: Element Boundary 301d: Element boundary 302: Active Area Pattern Group 302a: Active Area Layout Pattern (Active Area Pattern) 302b: Active Area Layout Pattern (Active Area Pattern) 304: Active Area Pattern Group 304a: Active Area Layout Pattern (Active Area Pattern) 304b: Active Area Layout Pattern (Active Area Pattern) 306: Gate Pattern Group 306a: Gate pattern 306b: Gate pattern 308: Gate Pattern Group 308a: Gate pattern 308b: Gate pattern 310: Contact Pattern Group 310: Contact Pattern 310a: Contact Pattern 310b: Contact Pattern 310c: Contact Pattern 310d: Contact Pattern 312: Contact Pattern Group 312a: Contact Pattern 312b: Contact Pattern 312c: Contact Pattern 312d: Contact Pattern 314: Contact Pattern Group 314a: Contact Pattern 314b: Contact Pattern 320: Through-hole pattern group 320a: Through-hole pattern 320b: Through-hole pattern 320c: Through-hole pattern 320d: Through-hole pattern 320e: Through-hole pattern 322: Through-hole pattern group 322a: Through-hole pattern 322b: Through-hole pattern 322c: Through-hole pattern 324: Through-hole pattern group 324a: Through-hole pattern 326: Through-hole pattern group 326a: Through-hole pattern 326b: Through-hole pattern 326c: Through-hole pattern 330: Conductive Feature Pattern Group 330a: Conductive feature pattern 330b: Conductive feature pattern 330c: Conductive feature pattern 330d: Conductive feature pattern 330e: Conductive feature pattern 332: Conductive Feature Pattern Group 332a: Conductive feature pattern 332b: Conductive feature pattern 332c: Conductive feature pattern 332d: Conductive feature pattern 332e: Conductive feature pattern 340: Cutting Feature Pattern Group 340a: Cutting feature pattern 340b: Cutting feature pattern 340c: Cutting feature pattern 340d: Cutting feature pattern 400: Integrated Circuits 400A: Partial 400B: Partial 400C: Partial 400D: Partial 400F: Partial 401: Unit 401a: Element Boundary 401b: Element Boundary 401c: Element Boundary 401d: Element boundary 402: Active Region Group 402a: Active Region 402b: Active Region 403a: Front 403b: Dorsal side 404: Active Region Group 404a: Active Region 404a1: Active Region 404a2: Active Region 404a3: Active Region 404b: Active Region 404b1: Active Region 404b2: Active Region 404b3: Active Region 406: Gate group 406a: Gate 406a1: Gate 406a2: Gate 406b: Gate 406b1: Gate 406b2: Gate 408: Gate group 408a: Gate 408a1: Gate 408a2: Gate 408b: Gate 408b1: Gate 408b2: Gate 410: Contact assembly 410a: Contact element 410b: Contact element 410c: Contact element 410d: Contact element 412: Contact assembly 412a: Contact element 412b: Contact element 412c: Contact element 412d: Contact element 414: Contact assembly 414a: Contacts 414b: Contacts 420: Through-hole group 420a: Through hole 420b: Through hole 420c: Through hole 420d: Through hole 420e: Through hole 422: Through-hole group 422a: Through hole 422b: Through hole 422c: Through hole 424: Through-hole group 424a: Through hole 426: Through-hole group 426a: Through hole 426b: Through hole 426c: Through hole 430: Conductor Group 430a: Conductor 430b: Conductor 430c: Conductor 430d: Conductor 430e: Conductor 432: Conductor Group 432a: Conductor 432b: Conductor 432c: Conductor 432d: Conductor 432e: Conductor 440: Remove gate assembly 440a: Remove gate section 440b: Remove the gate portion (insulation area) 440c: Remove the gate portion (insulation area) 440d: Gate section removed 480a: Insulation area 480b: Insulation area 490: Substrate (Wafer) 492: Insulation Area 500: Integrated Circuits 500A: Partial 500B: Partial 500C: Partial 500D: Partial 501: Unit 530: Conductor Group 530c: Conductor 530c1: Conductive part 530c2: Conductive part 530c3: Conductive part 532: Conductor Group 532c: Conductor 532c1: Conductive part 532c2: Conductive part 532c3: Conductive part 600: Integrated Circuits 600A: Partial 600B: Partial 600C: Partial 600D: Partial 601A: Unit 601B: Unit 610: Contact assembly 612: Contact assembly 620: Through-hole group 620e: Through hole 622: Through-hole group 622c: Through hole 624: Through-hole group 624a: Through hole 626: Through-hole group 626c: Through hole 630: Conductor Group 630c: Conductor 632: Conductor Group 632c: Conductor 640: Remove gate assembly 640a: Remove gate section 640b: Remove gate section 640c: Gate section removed 610: Contact assembly 612: Contact assembly 700: Layout Design 700A: Partial 700B: Partial 700C: Partial 700D: Partial 701: Unit 724: Through-hole pattern group 724a: Through-hole pattern 724c: Through-hole pattern 726: Through-hole pattern group 726c: Through-hole pattern 730: Conductive Feature Pattern Group 730c: Conductive feature pattern 732: Conductive Feature Pattern Group 732c: Conductive feature pattern 740: Cutting Feature Pattern Group 740b: Cutting Feature Pattern 800: Integrated Circuits 800A: Partial 800B: Partial 800C: Partial 800D: Partial 801: Unit 824: Through-hole group 824a: Through hole 824c: Through hole 826: Through-hole group 826c: Through hole 830: Conductor Group 830c: Conductor 832: Conductor Group 832c: Conductor 840: Remove gate assembly 840b: Remove the gate portion (insulation area) 840b: Remove gate section 900: Integrated Circuits 900A: Partial 900B: Partial 900C: Partial 900D: Partial 901: Unit 930: Conductor Group 930c: Conductor 932: Conductor Group 932c: Conductor 1000A: Method 1000B: Method 1002: Operation 1002a: Operation 1002b: Operation 1002c: Operation 1002d: Operation 1004: Operation 1006: Operation 1008: Operation 1010: Operation 1012: Operation 1020: Operation 1022: Operation 1024: Operation 1026: Operation 1028: Operation 1030: Operation 1032: Operation 1034: Operation 1036: Operation 1100: Integrated Circuits 1100A: Device Structure 1100B: Device Structure 1100C: Device Structure 1100D: Device Structure 1100E: Device Structure 1100F: Device Structure 1100G: Device Structure 1100H: Device Structure 1100I: Device Structure 1102: Active Region 1102a: Source region 1102b: Drainage Region 1103: Semiconductor layer 1104: Dummy gate 1150: Floor 1152: Inner Spacing Region 1160: Region 1161: Depressed area 1162: Region 1163: Depressed area 1170: Region 1171: Depressed area 1172: Insulation layer 1174: Source / Drain Region 1176: Source / Drain Region 1180: Gate 1181: Gate 1182: First group of through holes 1184: Second group of through holes 1190: Semiconductor layer 1200: Method 1202: Operation 1204: Operation 1300: Method 1302: Operation 1304: Operation 1306: Operation 1308: Operation 1310: Operation 1312: Operation 1314: Operation 1316: Operation 1318: Operation 1400: System 1402: Processor 1404: Storage Media (Memory) 1406: Code (Instruction) 1408: Busbar 1410:I / O interface 1412: Network Interface 1414: Internet 1416: Layout Design 1418: User Interface 1420: Manufacturing Unit 1500: System 1520: Design Company 1522: IC Design Layout 1530: Mask Company 1532: Data Preparation 1534: Mask Manufacturing 1540: IC manufacturing plant (IC wafer fab) 1542: Wafer 1545: Mask 1552: Manufacturing tools 1560: IC Components A-A': Plane Active: Active layer B-B': Plane BL: Bitline BLB: Bit Lines BM0: Backside metal layer 0 BMD: Backside metal diffusion layer BVD: Backside via diffusion layer BVG: Backside through-hole gate layer C-C': Plane COL1: line COL2: line CPO: Cutting the gate layer (cutting the POLY layer) CPOLY: Cutting the gate layer (cutting the POLY layer) D-D': Plane E-E': Plane (line) F-F': Plane G-G': Plane H-H': Plane I-I': Plane L2a: Length L2b: Length M0: Metal 0 layer MCB: Memory Unit MD: Metal overdiffusion layer MDLI: Metal Overdiffused Local Interconnect Layer MG: Gate Layer ND: Node NDB: Node NODE_1: Voltage Supply Node OD: Oxide Diffusion Layer PD1: NFET transistor PD2: NFET transistor PG1: NFET transistor PG2: NFET transistor PO: Gate layer POLY: Gate layer PU1: PFET transistor PU2: PFET transistor VD: Through-hole diffusion layer VDD: Voltage source VG: Gate upper via layer VSS: Reference voltage source W1a: Width W1b: Width W2a: Width W2b: width WL: Bitline X: First direction X1: PFET transistor X2: PFET transistor Y: Second direction Z: Third-party direction

[0686] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. An apparatus comprising: a first transistor of a first type coupled to a first node, the first transistor including a first gate located on a first level; a second transistor of a second type different from the first type coupled to the first node, the second transistor including a second gate located on a second level below the first level; a third transistor of the first type coupled to a second node, the third transistor including a third gate located on the first level, the third gate being separated from the first gate at least in a first direction; and a fourth transistor of the second type coupled to the second node, the fourth transistor including a fourth gate located on the second level. A first conductor extends along a second direction different from the first direction, the first conductor is located on a first metal layer above a front side of a substrate, and is coupled to the first gate and the second node; and a second conductor extends along the second direction, the second conductor is located on a second metal layer below a back side of the substrate, and is coupled to the fourth gate and the first node, the second metal layer being different from the first metal layer.

2. The apparatus of claim 1, wherein each of the first gate, the second gate, the third gate and the fourth gate extends along the first direction, the first gate and the third gate are further separated from each other in the second direction, and the second gate and the fourth gate are separated from each other in the first direction and the second direction.

3. The apparatus of claim 2, further comprising: a first transmission gate transistor of the first type coupled to the first node, the first transmission gate transistor including a fifth gate located on the first level; and a second transmission gate transistor of the second type coupled to the second node, the second transmission gate transistor including a sixth gate located on the first level, wherein the fifth gate and the sixth gate extend along the first direction, the third gate and the fifth gate are separated from each other in the first direction, and the first gate and the sixth gate are separated from each other in the first direction.

4. The apparatus of claim 3, further comprising: a first contact extending along the first direction, located on a third layer, and electrically coupled to a source / drain of the first transmission gate transistor; a second contact extending along the second direction, located on the third layer, and electrically coupled to a source / drain of the second transmission gate transistor; a third contact extending along the second direction, located on the third layer and a fourth layer different from the third layer, and electrically coupled to a source / drain of the first transistor, a source / drain of the second transistor, and the source / drain of the first transmission gate transistor; and a fourth contact extending along the second direction, located on the third layer and the fourth layer, and electrically coupled to a source / drain of the third transistor, a source / drain of the fourth transistor, and the source / drain of the second transmission gate transistor.

5. The apparatus of claim 4, further comprising: a first through-hole electrically coupling the first conductor to the fourth contact, the first through-hole being located between the first conductor and the fourth contact; and a second through-hole electrically coupling the first conductor to the first gate, the second through-hole being located between the first conductor and the first gate.

6. The apparatus of claim 5, further comprising: a third conductor extending along the second direction, located on the first metal layer, coupled to the first contact, and configured as a bit line; a fourth conductor extending along the second direction, located on the first metal layer, coupled to the second contact, and configured as a bit line; a third via electrically coupling the third conductor to the first contact, the third via being located between the third conductor and the first contact; and a fourth via electrically coupling the fourth conductor to the second contact, the fourth via being located between the fourth conductor and the second contact; wherein the first conductor, the second conductor, the third conductor, and the fourth conductor are separated from each other in the first direction.

7. The apparatus of claim 5, further comprising: a first insulating region located between the first gate and the sixth gate, the first insulating region being configured to electrically insulate the first gate and the sixth gate from each other; and a second insulating region located between the fifth gate and the third gate, the second insulating region being configured to electrically insulate the fifth gate and the third gate from each other; wherein a first side of the first insulating region contacts a first side of the first gate, a first side of the second insulating region contacts a first side of the fifth gate, and the first side of the first insulating region is offset from the first side of the second insulating region in a first direction.

8. The apparatus of claim 7, wherein the first through-hole has a first width in the first direction, the second through-hole has a second width in the first direction, and the first width is equal to the second width.

9. The apparatus of claim 7, further comprising: a third through-hole electrically coupling the second conductor to the third contact, the third through-hole being located between the second conductor and the third contact; and a fourth through-hole electrically coupling the second conductor to the fourth gate, the fourth through-hole being located between the second conductor and the fourth gate.

10. The apparatus of claim 9, wherein the third through-hole has a first width in the first direction; the fourth through-hole has a second width in the first direction; and the first width is equal to the second width.

11. The apparatus of claim 9, wherein the first conductor or the second conductor comprises: a first conductive portion extending along the second direction; a second conductive portion extending along the second direction; and a third conductive portion extending along the second direction, wherein the third conductive portion is a central portion connected to the first conductive portion and the second conductive portion on corresponding opposite sides.

12. An apparatus comprising: a first transistor of a first type, the first transistor including a first drain / source and a first gate, the first gate being located on a first layer; a second transistor of a second type different from the first type, the second transistor including a second drain / source and a second gate, the second gate being located on a second layer below the first layer; a third transistor of the first type, the third transistor including a third drain / source and a third gate, the third gate being located on the first layer; and a fourth transistor of the second type, the fourth transistor including a fourth drain / source and a fourth gate, the fourth gate being located on the second layer, the fourth gate being separated from the second gate at least in a first direction; A first conductor extends along a second direction different from the first direction, the first conductor is located on a first metal layer above a front side of a substrate, overlaps with the first gate, and is coupled to the first gate, the third drain / source, and the fourth drain / source; and a second conductor extends along the second direction, the second conductor is located on a second metal layer below a back side of the substrate, overlaps with the fourth gate, and is coupled to the fourth gate, the first drain / source, and the second drain / source, and the second metal layer is located below the first metal layer.

13. The apparatus of claim 12, further comprising: a first transmission gate transistor of the first type coupled to the first transistor and the second transistor, the first transmission gate transistor including a fifth drain / source and a fifth gate located on the first level; and a second transmission gate transistor of the second type coupled to the third transistor and the fourth transistor, the second transmission gate transistor including a sixth drain / source and a sixth gate located on the first level.

14. The apparatus of claim 13, wherein each of the first gate, the second gate, the third gate, the fourth gate, the fifth gate, and the sixth gate extends along the first direction; the first gate and the third gate are separated from each other in the first direction and the second direction; the second gate and the fourth gate are further separated from each other in the second direction; the third gate and the fifth gate are separated from each other in the first direction; and the first gate and the sixth gate are separated from each other in the first direction.

15. The apparatus of claim 14, further comprising: a first contact extending along the second direction, located on a third layer and a fourth layer different from the third layer, and electrically coupled to the first drain / source of the first transistor, the second drain / source of the second transistor, and the fifth drain / source of the first transmission gate transistor; and a second contact extending along the second direction, located on the third layer and the fourth layer, and electrically coupled to the third drain / source of the third transistor, the fourth drain / source of the fourth transistor, and the sixth drain / source of the second transmission gate transistor.

16. The apparatus of claim 15, further comprising: a first through-hole electrically coupling the first conductor to the second contact, the first through-hole being located between the first conductor and the second contact; and a second through-hole electrically coupling the first conductor to the first gate, the second through-hole being located between the first conductor and the first gate.

17. The apparatus of claim 16, further comprising: a first insulating region located between the first gate and the sixth gate, the first insulating region being configured to electrically insulate the first gate and the sixth gate from each other; and a second insulating region located between the fifth gate and the third gate, the second insulating region being configured to electrically insulate the fifth gate and the third gate from each other; wherein a first side of the first insulating region contacts a first side of the first gate, a first side of the second insulating region contacts a first side of the fifth gate, and the first side of the first insulating region is aligned with the first side of the second insulating region in a second direction.

18. The apparatus of claim 17, further comprising: a third through-hole electrically coupling the second conductor to the first contact, the third through-hole being located between the second conductor and the first contact; and a fourth through-hole electrically coupling the second conductor to the fourth gate, the fourth through-hole being located between the second conductor and the fourth gate.

19. The apparatus of claim 18, wherein the first through-hole has a first width in the first direction; the second through-hole has a second width in the first direction; the third through-hole has a third width in the first direction; the fourth through-hole has a fourth width in the first direction; the first width is smaller than the second width, and the third width is smaller than the fourth width.

20. A method comprising: fabricating a first set of transistors and a second set of transistors on a front side of a substrate, the first set of transistors stacked on top of the second set of transistors; fabricating a first set of vias on the front side of the substrate, the first set of vias being electrically coupled to at least the first set of transistors; depositing a first conductive material on a first metal layer on the front side of the substrate to form a first set of conductors, the first set of conductors being electrically coupled to at least the first set of transistors through the first set of vias, the first set of conductors including a first conductor, the first conductor electrically coupling a first gate of the first set of conductors to a first node of a device; and thinning a back side of the substrate opposite to the front side; A second set of vias is formed on the back side of the thinned substrate, the second set of vias being electrically coupled to at least the second set of transistors; and a second conductive material is deposited on a second metal layer on the back side of the thinned substrate to form a second set of conductors, the second set of conductors being electrically coupled to at least the second set of transistors through the second set of vias, the second set of conductors including a second conductor that electrically couples a second gate of the second set of transistors to a second node of the device.