Cold edge low temperature electrostatic chuck
The ESC design with cooling channels, a thin bonding layer, and two temperature zones addresses temperature control issues in plasma etching, enhancing etching rate and uniformity while reducing complexity and costs.
Patent Information
- Application Number
- TW110138496
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2020-10-20
- Filing Date
- 2021-10-18
- Publication Date
- 2026-08-01
- Estimated Expiration
- 2041-10-17
AI Technical Summary
Existing electrostatic chucks (ESCs) in plasma processing chambers fail to effectively control wafer temperature during plasma etching, leading to uneven etching rates and profiles due to high thermal conductivity at the wafer edges, which can impact the quality of semiconductor wafers and increase system costs with multiple temperature zones and components.
The ESC design incorporates a base plate with cooling channels, a thin bonding layer, and inner and outer heating elements to create two temperature zones, promoting heat conduction cooling and maintaining a cold edge temperature region, thereby controlling wafer temperature uniformly.
This design improves etching rate and uniformity by maintaining the wafer edge at a lower temperature, meeting stringent critical dimension requirements and reducing system complexity and costs by using fewer heaters and components.