Semiconductor memory devices and control methods for semiconductor memory devices

The semiconductor memory device addresses NWI by adjusting threshold voltages using a weaker program pulse based on adjacent cell thresholds, maintaining a narrow distribution and reducing failure bits.

TWI934464BActive Publication Date: 2026-08-01KIOXIA CORP
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Patent Information

Application Number
TW114105209
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Priority Date
2024-03-21
Filing Date
2025-02-12
Publication Date
2026-08-01
Estimated Expiration
2045-02-11

AI Technical Summary

Technical Problem

NAND flash memory devices experience neighbor word-line interference (NWI) that widens the threshold voltage distribution and increases failure bit count, especially with increased memory density and multi-valued architectures.

Method used

A semiconductor memory device and control method that adjusts the threshold voltage of memory cells based on the threshold voltage level of adjacent cells, using a weaker program pulse to minimize the impact of NWI, thereby maintaining a narrower threshold voltage distribution and reducing failure bits.

Benefits of technology

The method effectively suppresses the expansion of threshold voltage distribution and maintains a sufficient margin between distributions, reducing the failure bit count without increasing the number of programming cycles.

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Abstract

This invention provides a semiconductor memory device that can suppress the expansion of the threshold value distribution even under the influence of NWI. One embodiment of the semiconductor memory device includes: a plurality of memory cell arrays; a plurality of memory cells included in a first memory cell array, which is one of the plurality of memory cell arrays; a plurality of word lines, each connected to a gate of the plurality of memory cells; a bit line connected to a first end of the first memory cell array; and a control circuit that executes at least one cycle in response to an instruction sequence for writing data to the first memory cell, which is one of the plurality of memory cells, connected to the first word line of the plurality of word lines, each cycle including writing data to the first memory cell, which is one of the plurality of memory cells. The first program operation for writing data to the first memory cell and the verification operation for verifying the data written to the first memory cell; and the instruction sequence includes threshold voltage information related to the threshold voltage level to be set in the second memory cell, the second memory cell being connected to the second word line adjacent to the first word line as one of the aforementioned plurality of word lines, and after exiting the aforementioned loop, the control circuit determines whether to perform the operation of adjusting the threshold voltage of the first memory cell based on the threshold voltage level set in the second memory cell.
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