Serpentine electrode for memory devices

Abstract

The present invention provides a bottom electrode with a serpentine pattern for a memory device, wherein the bottom electrode is positioned between an MTJ pillar and a first conductive structure.

Description

Technical Field

[0001] This application relates to a memory device, and more specifically, to a memory device comprising a bottom electrode with a serpentine pattern positioned below a magnetic tunneling junction (MTJ) post. Prior Technology

[0002] Magnetoresistive random access memory (MRAM) is a non-volatile random access memory technology in which data is stored by magnetic storage elements. These elements are typically formed by two ferromagnetic plates, each of which can be kept magnetized and separated by a thin dielectric layer (i.e., a tunnel barrier). One of the plates is a permanent magnet set to a specific polarity (i.e., a magnetic reference layer); the magnetization of the other plate can be changed to match the magnetization of an external field to store memory (i.e., a non-magnetic layer). This configuration is called MTJ-containing pillars. In leading-edge or neuromorphic computing systems, MTJ-containing pillars are typically embedded within back-end processing (BEOL) structures. Summary of the Invention

[0003] A bottom electrode with a serpentine pattern is provided for a memory device, wherein the bottom electrode is positioned between an MTJ pillar and a first conductive structure.

[0004] In one embodiment of this application, the memory device includes: a first conductive structure; a metal cap positioned on the first conductive structure; an MTJ-containing pillar positioned above the metal cap; a bottom electrode having a serpentine pattern positioned between the metal cap and the MTJ-containing pillar, wherein the bottom electrode has a bottom surface in contact with the metal cap and a top surface in contact with the MTJ-containing pillar; a top electrode positioned on the MTJ-containing pillar; and a second conductive structure electrically connected to the top electrode.

[0005] In another embodiment of this application, the memory device includes: a first conductive structure; a metal cap positioned on the first conductive structure; an MTJ-containing pillar positioned above the metal cap; a multi-layer bottom electrode structure having a serpentine pattern positioned between the metal cap and the MTJ-containing pillar, wherein the multi-layer bottom electrode structure has a bottommost bottom electrode in contact with the metal cap and a topmost bottom electrode in contact with the MTJ-containing pillar; a top electrode positioned on the MTJ-containing pillar; and a second conductive structure electrically connected to the top electrode. Simple Explanation of the Diagram

[0006] Figure 1 is a cross-sectional view of an exemplary structure that can be used in this application. The exemplary structure includes a first conductive structure embedded in a first interlayer dielectric (ILD) layer and a dielectric cap positioned on the first ILD layer and the first conductive structure.

[0007] Figure 2 is a cross-sectional view of the exemplary structure of Figure 1, in which a patterned dielectric cover exposes a first conductive structure in a solid form, and a metal cover adjacent to the patterned dielectric cover is formed on the solidly exposed first conductive structure.

[0008] Figure 3 is a cross-sectional view of the exemplary structure of Figure 2 after the second ILD layer is formed on the patterned dielectric cap and metal cap.

[0009] Figure 4 is a cross-sectional view of the exemplary structure of Figure 3 after the first patterned hard mask is formed on the second ILD layer.

[0010] Figure 5 is a cross-sectional view of the exemplary structure of Figure 4 after etching is performed to transfer the pattern provided by the first patterned hard mask to the second ILD layer and the first patterned hard mask is removed.

[0011] Figure 6 is a cross-sectional view of the exemplary structure of Figure 5 after a bottom electrode material layer with a serpentine pattern has been formed on the patterned second ILD layer.

[0012] Figure 7 is a cross-sectional view of the exemplary structure of Figure 6 after a gap-filled ILD layer is formed in the gap provided by the serpentine pattern of the bottom electrode layer.

[0013] Figure 8 is a cross-sectional view of the exemplary structure of Figure 7 after a second patterned hard mask is formed on a portion of the bottom electrode layer and on a gap-filled ILD layer located in the gaps provided by the serpentine pattern of the bottom electrode layer.

[0014] Figure 9 is a cross-sectional view of the exemplary structure of Figure 8 after the removal of the solid portion of the bottom electrode layer that is not protected by the second patterned hard mask, and the removal of the second patterned hard mask to reveal the bottom electrode with a serpentine pattern, wherein the gaps provided by the serpentine pattern are filled with a gap-filling ILD layer.

[0015] Figure 10 is a cross-sectional view of the exemplary structure of Figure 9 after a third ILD layer is formed on the second ILD layer to provide a multilayer ILD-containing region.

[0016] Figure 11 is a cross-sectional view of the exemplary structure of Figure 10 after forming an MTJ-containing stack including a blanket-covered bottom magnetic material layer, a blanket-covered tunnel barrier layer, and a blanket-covered top magnetic material layer.

[0017] Figure 12 is a cross-sectional view of the exemplary structure of Figure 11 after the top electrode material layer is formed on the MTJ stack.

[0018] Figure 13 is a cross-sectional view of the exemplary structure of Figure 12 after a third patterned hard mask is formed on the top electrode material layer.

[0019] Figure 14 is a cross-sectional view of the exemplary structure of Figure 13 after etching a top electrode material layer and an MTJ stack to provide a top electrode and an MTJ pillar, respectively, wherein the etching uses a third patterned hard mask as an etching mask, and the third patterned hard mask is removed.

[0020] Figure 15 is a cross-sectional view of the exemplary structure of Figure 14 after the encapsulation liner is formed on the top electrode and the sidewall containing the MTJ column.

[0021] Figure 16 is a cross-sectional view of the exemplary structure of Figure 15 after the fourth ILD layer adjacent to the liner is formed on the top of the top electrode.

[0022] Figure 17 is a cross-sectional view of the exemplary structure of Figure 16 after the formation of the second conductive structure in the fourth ILD layer that is in electrical contact with the top electrode.

[0023] Figure 18 is a cross-sectional view of the exemplary structure of Figure 5 after a first bottom electrode material layer with a serpentine pattern is formed on a patterned second ILD layer, and a second bottom electrode material layer with a serpentine pattern is formed on the first bottom electrode material layer.

[0024] Figure 19 is a cross-sectional view of the exemplary structure of Figure 18 after a gap-filled ILD layer is formed in the gap provided by the serpentine pattern of the second bottom electrode layer.

[0025] Figure 20 is a cross-sectional view of the exemplary structure of Figure 19 after a second patterned hard mask is formed on a portion of the second bottom electrode layer and on a gap-filled ILD layer located in the gaps provided by the serpentine pattern of the second bottom electrode layer.

[0026] Figure 21 is a cross-sectional view of the exemplary structure of Figure 20 after the following operations: removal of the solid exposed portion of the second bottom electrode layer not protected by the second patterned hard mask and the portion beneath the first bottom electrode layer; removal of the second patterned hard mask to expose the second bottom electrode with a serpentine pattern, wherein the gaps provided by the serpentine pattern are filled with a gap-filling ILD layer; and exposure of the first bottom electrode with a serpentine pattern positioned below the second bottom electrode; the first bottom electrode and the second bottom electrode together provide a multilayer bottom electrode structure with a serpentine pattern.

[0027] Figure 22 is a cross-sectional view of the exemplary structure of Figure 21 after a third ILD layer is formed on the second ILD layer to provide a multilayer ILD region.

[0028] Figure 23 is a cross-sectional view of the exemplary structure of Figure 22 after performing the processing steps of Figures 11 to 17. Implementation

[0029] This application will now be described in more detail with reference to the following discussion and the accompanying drawings. It should be noted that the drawings are provided for illustrative purposes only and are therefore not drawn to scale. It should also be noted that identical and corresponding elements are designated by the same element symbol.

[0030] In the following description, numerous specific details, such as particular structures, components, materials, dimensions, processing steps, and techniques, are set forth to provide an understanding of various embodiments of this application. However, those skilled in the art will understand that various embodiments of this application can be practiced without such specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring this application.

[0031] It should be understood that when a component, such as a layer, region, or substrate, is referred to as being "on" or "above" another component, it may be directly on the other component or an intervening component may be present. In contrast, when a component is referred to as being "directly on" or "directly above" another component, no intervening component is present. It should also be understood that when a component is referred to as being "below" or "under" another component, that component may be directly below or under the other component, or an intervening component may be present. In contrast, when a component is referred to as being "directly below" or "directly under" another component, no intervening component is present.

[0032] The terms substantially, substantially similar, approximately, or any other terms indicating functional equivalence or similarity refer to situations where differences in length, height, or orientation convey an explicit statement (e.g., a phrase without substantially similar terms) and substantially similar variants where there is no actual difference. In one embodiment, substantially (and its derivatives) means a difference in engineering or manufacturing tolerances that are generally acceptable for similar devices, such as a deviation of up to 10% or an angular deviation of 10°.

[0033] For high-performance MRAM devices based on vertical MTJ pillars, well-defined interfaces and interface control are essential. Embedded MTJ pillars are typically formed by patterning blanket-coated MTJ stacks using either reactive ion etching (RIE) or ion beam etching (IBE). Processing blanket-coated MTJ stacks into MTJ pillars using RIE and IBE presents significant challenges due to the short circuits caused by resputtered bottom electrode metal particles on the sidewalls of the MTJ pillars. A memory device is needed that does not have resputtered bottom electrode metal particles on the sidewalls of the MTJ pillars.

[0034] Referring first to FIG1, an exemplary structure for use in this application is illustrated, comprising a first conductive structure 14 embedded in a first ILD layer 10, and a dielectric cap 16 positioned on the first ILD layer 10 and the first conductive structure 14. In some embodiments, as illustrated in FIG1, a first diffusion barrier liner 12 may be present along the sidewalls and bottom surface of the first conductive structure 14. In other embodiments, the first diffusion barrier liner 12 may be omitted. Commonly, the first conductive structure 14, the optional first diffusion barrier liner 12, and the first ILD layer 10 provide a metal (or interconnect) level Mn, where n is any integer starting from 1; the upper limit of "n" may vary and may be predetermined by the manufacturer of a particular integrated circuit. Although FIG1 describes and illustrates a single first conductive structure 14 embedded in the first ILD layer 10, this application covers embodiments where more than one first conductive structure 14 is embedded in the first ILD layer 10. When more than one first conductive structure 14 is embedded in the first ILD layer 10, some or all of the first conductive structures may be processed to include the serpentine bottom electrode according to this application.

[0035] In some embodiments, the first conductive structure 14 may extend completely through the first ILD layer 10. In other embodiments, the first conductive structure 14 extends partially through the first ILD layer 10, and in these embodiments, the first conductive structure 14 may be connected to another conductive structure, such as (e.g.) a metal wire and / or a metal via, which may be located directly below and in contact with the first conductive structure 14.

[0036] Although not shown in any of the figures in this application, the substrate may be positioned below the metal layer Mn. The substrate may include: a front-end process (FEOL) layer comprising one or more semiconductor elements, such as, for example, field-effect transistors positioned on a semiconductor material; a mid-end process (MOL) layer comprising a plurality of metal contact structures embedded in the MOL dielectric material layer; at least one lower interconnect layer comprising a plurality of lower interconnect structures embedded in the lower interconnect dielectric material layer; or any combination thereof. In one example, the substrate includes both an FEOL layer and a MOL layer.

[0037] The metal layer Mn can be formed using techniques known to those skilled in the art. In one embodiment, a metal damascene process can be used when forming the metal layer Mn. The metal damascene process may include forming an opening to the first ILD layer 10, filling the opening with an optional diffusion barrier layer and a conductive material, and performing a planarization process, such as (e.g.) chemical mechanical polishing (CMP), if necessary, to remove the optional diffusion barrier layer and conductive material from the top surface of the first ILD layer 10. The diffusion barrier layer retained in the opening may be referred to herein as a first diffusion barrier liner 12, and the conductive material retained in the opening may be referred to herein as a first conductive structure 14. In some embodiments and as shown in FIG. 1, if the first conductive structure 14 is present, the first conductive structure 14 has a top surface that is substantially coplanar with the top surface of the first ILD layer 10 and the top surface of the first diffusion barrier liner 12.

[0038] The first ILD layer 10 may be composed of a dielectric material such as, for example, silicon dioxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), borosilicate silicate glass (BPSG), spin-coated low-k dielectric material, chemical vapor deposition (CVD) low-k dielectric material, or any combination thereof. The term "low-k" as used throughout this application refers to a dielectric material having a dielectric constant less than 4.0. Unless otherwise stated, all dielectric constants mentioned herein are measured in a vacuum. Illustrative low-k dielectric materials that may be used as the first ILD layer 10 include, but are not limited to, silsesquioxanes, C-doped oxides (i.e., organosilicones) comprising Si, C, O, and H atoms, thermosetting polyaryl ethers, or multilayers thereof. In this application, the term "polyaryl" is used to refer to an aryl moiety or an inertly substituted aryl moiety bonded together by bonds, fused rings, or inertly linked groups (such as, for example, oxygen, sulfur, ternary, ternary, carbonyl, and the like). Although not shown, the first ILD layer 10 may include a multilayer structure comprising at least two different dielectric materials stacked on top of each other. The first ILD layer 10 may be formed using deposition processes including, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), evaporation, or spin coating.

[0039] The diffusion barrier layer (and therefore the first diffusion barrier liner 12) used in this application may, as appropriate, include a diffusion barrier material (i.e., a material that acts as a barrier to prevent conductive materials such as copper from diffusing through it). Examples of diffusion barrier materials that may be used in providing the diffusion barrier layer (and therefore the first diffusion barrier liner 12) include, but are not limited to, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, or WN; in some cases in this application, chemical symbols found in the periodic table are used instead of the full names of elements or compounds. In some embodiments, the diffusion barrier material may comprise a stack of diffusion barrier materials. In one example, the diffusion barrier material may be composed of a stack of Ta / TaN. The diffusion barrier layer may be formed by a deposition process such as, for example, CVD, PECVD, or physical vapor deposition (PVD).

[0040] The conductive material providing the first conductive structure 14 may include conductive metals and / or conductive material alloys. Illustrative examples of conductive metals include, but are not limited to, Cu, W, Al, Co, or Ru. Illustrative examples of conductive metal alloys include Cu-Al alloys. The conductive material providing the first conductive structure 14 may be formed by a deposition process such as, for example, CVD, PECVD, PVD, sputtering, or electroplating. In some embodiments, reflow annealing may be performed after deposition of the conductive material providing the first conductive structure 14.

[0041] After forming the metal layer Mn, a dielectric cap 16 is formed. The dielectric cap 16 is composed of a dielectric cover material that is different in composition from the dielectric material providing the first ILD layer 10. The dielectric cover material providing the dielectric cap 16 may include, but is not limited to, silicon nitride (SiN), or a dielectric containing silicon, nitrogen, and carbon atoms (i.e., SiNC). The dielectric cap 16 may be formed by deposition processes including, but not limited to, atomic layer deposition (ALD), CVD, PECVD, or PVD.

[0042] Referring now to FIG. 2, an exemplary structure of FIG. 1 is illustrated, in which a patterned dielectric cap 16 substantially exposes a first conductive structure 14, and a metal cap 18 adjacent to the patterned dielectric cap 16 is formed on the substantially exposed first conductive structure 14. Patterning of the dielectric cap 16 includes photolithography. Photolithography includes forming a photoresist material on the layer / multilayer stack to be patterned, exposing the deposited photoresist material to the desired irradiation pattern, developing the photoresist material, and transferring the pattern from the developed photoresist material to the layer / multilayer stack to be patterned. The pattern transfer may include one or more etching processes. The one or more etching processes may include dry etching and / or wet etching. Dry etching may include reactive ion etching (RIE), plasma etching, or ion beam etching. Wet etching may include using a chemical etchant selectively removing the substantially exposed portion of the layer / multilayer stack to be patterned. The photoresist material is removed after a pattern transfer process utilizing a material removal process selectively removing the photoresist material. In this application, the patterning of the dielectric cap 16 forms an opening in the dielectric cap 16 that substantially exposes the first conductive structure 14. In some embodiments, if a first diffusion barrier liner 12 is present, the opening may also substantially expose the topmost surface of the first diffusion barrier liner 12. In other embodiments (not shown), the opening formed in the dielectric cap 16 does not substantially expose the first diffusion barrier liner 12.

[0043] The metal cap 18 is made of a metal that is inert compared to the conductive material present in the conductive structure 14. Illustrative examples of such inert metals include, but are not limited to, Ta, W, or Ru. The metal cap 18 may be formed in the opening formed in the dielectric cap 16 by a deposition process followed by planarization including CMP. The deposition process used in forming the metal cap 18 may include, for example, CVD, PECVD, PVD, sputtering, or electroplating. The metal cap 18 has a top surface that is substantially coplanar with the top surface of the patterned dielectric cap 16.

[0044] Referring now to FIG. 3, a cross-sectional view of the exemplary structure of FIG. 2 is shown after the second ILD layer 20 has been formed on the patterned dielectric cap 16 and metal cap 18. The second ILD layer 20 may include the dielectric material used for the first ILD layer 10 as mentioned above. The dielectric material providing the second ILD layer 20 may be the same in composition as the dielectric material providing the first ILD layer 10 or may be different in composition. However, the dielectric material providing the second ILD layer 20 may be different in composition from the dielectric cap material providing the dielectric cap 16. The second ILD layer 20 may be formed by a deposition process such as, for example, CVD, PECVD, vapor deposition, or spin coating. A planarization process such as, for example, CMP may be performed after the deposition of the dielectric material providing the second ILD layer 20.

[0045] Referring now to FIG. 4, an exemplary structure of FIG. 3 is illustrated after the formation of the first patterned hard mask 24 on the second ILD layer 20. In some embodiments, the first patterned hard mask 24 includes a plurality of openings formed therein. In another embodiment, a single opening may exist in the first patterned hard mask 24. The first patterned hard mask 24 is composed of a dielectric hard mask material including, for example, silicon dioxide, silicon nitride, and / or silicon oxynitride. The first patterned hard mask 24 may be formed by depositing a blanket-like hard mask material layer and subsequently performing photolithography patterning, in which transfer etching is selective in removing the dielectric hard mask material. Deposition of the blanket-like hard mask material layer includes, but is not limited to, CVD, PECVD, or PVD.

[0046] Referring now to FIG. 5, an illustrative structure of FIG. 4 is shown after etching is performed to transfer the pattern provided by the first patterned hard mask 24 to the second ILD layer 20, and after the first patterned hard mask 24 is removed. The etching to transfer the pattern provided by the first patterned hard mask 24 to the second ILD layer 20 is selective in removing the second ILD layer 20 which is not protected by the first patterned hard mask 24. The etching used in the pattern transfer step stops on the surface of the metal cap 18. After performing the pattern transfer etching by means of a material removal process that is selective in removing the first patterned hard mask 24, the first patterned hard mask 24 is removed. After the pattern transfer etching, the second ILD layer 20 is patterned to include at least one opening. Each opening in the second ILD layer 20 physically exposes a portion of the metal cap 18. At least one opening in the second ILD layer 20 will be used to form a bottom electrode with a serpentine pattern. The term "serpentine pattern" is used throughout this application to refer to a zigzag pattern comprising at least one hill and at least one valley.

[0047] Referring now to FIG. 6, an exemplary structure of FIG. 5 is illustrated after a bottom electrode material layer 26L with a serpentine pattern is formed on the previously patterned second ILD layer 20. The bottom electrode material layer 26L is composed of a conductive metal material such as, for example, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, or WN. The bottom electrode material layer 26L can be formed by depositing a conductive metal material. The deposition of the conductive metal material can include, but is not limited to, CVD, PECVD, ALD, or sputtering. In some embodiments, the bottom electrode material layer 26L is a conformal layer. As used herein, the term "conformal layer" means that the vertical thickness of the material layer along the horizontal surface is substantially the same as the lateral thickness along the vertical surface (i.e., within ±5%).

[0048] Referring now to Figure 7, an exemplary structure of Figure 6 is illustrated after a gap-filling ILD layer 28 is formed in the gaps (or single gaps) provided by the serpentine pattern of the bottom electrode layer 26L. The gap-filling ILD layer 28 is composed of the dielectric material used for the first ILD layer 10 as mentioned above. The dielectric material providing the gap-filling ILD layer 28 may be compositionally the same as or different from the dielectric material providing the first ILD layer 10 and / or the second ILD layer 20. The gap-filling ILD layer 28 may be formed by a deposition process such as, for example, CVD, PECVD, vapor deposition, or spin coating. A planarization process such as, for example, CMP may be performed after depositing the dielectric material providing the gap-filling ILD layer 28.

[0049] Referring now to Figure 8, an exemplary structure of Figure 7 is illustrated after a second patterned hard mask 30 is formed on a portion of the bottom electrode layer 26L and on a gap-filling ILD layer 28 positioned within the gaps provided by the serpentine pattern of the bottom electrode layer 26L. It should be noted that the second patterned hard mask 30 is formed directly over the serpentine pattern present in the bottom electrode layer 26L. The second patterned hard mask 30 is composed of a dielectric hard mask material including, for example, silicon dioxide, silicon nitride, and / or silicon oxynitride. The second patterned hard mask 30 can be formed by depositing a blanket-like hard mask material layer followed by photolithography patterning, in which transfer etching is selective in removing the dielectric hard mask material. Deposition of the blanket-like hard mask material layer includes, but is not limited to, CVD, PECVD, or PVD.

[0050] Referring now to FIG. 9, an exemplary structure of FIG. 8 is illustrated after removing the solid exposed portion of the bottom electrode layer 26L not protected by the second patterned hard mask 30, and removing the second patterned hard mask 30 to expose the bottom electrode 26 with a serpentine pattern, wherein the gaps provided by the serpentine pattern are filled with a gap-filling ILD layer 28. The solid exposed portion of the bottom electrode layer 26L is removed using a selective etching process when removing the bottom electrode layer 26L not protected by the second patterned hard mask 30. After removing the solid exposed portion of the bottom electrode layer 26L not protected by the second patterned hard mask 30, the second patterned hard mask 30 is removed using a selective material removal process when removing the second patterned hard mask 30. As shown in FIG. 9, the bottom electrode 26 has a top surface (represented by the "mounds" of the bottom electrode 26) that is substantially coplanar with the top surface of the gap-filling ILD layer 28. The bottom surface (represented by the "valleys" of the bottom electrode 26) is in electrical contact with the metal cover 18.

[0051] Referring now to Figure 10, an illustrative structure of Figure 9 is shown after a third ILD layer (not shown or labeled separately in Figure 10) is formed on the second ILD layer 20 to provide a multilayer ILD-containing region 21. The multilayer ILD-containing region 21 includes a combination of the third ILD layer and the second ILD layer 20. The third ILD layer is composed of the dielectric material used for the first ILD layer 10 as mentioned above. The dielectric material providing the third ILD layer may be compositionally the same as or different from the dielectric material providing the first ILD layer 10 and / or the second ILD layer 20 and / or the gap-filling ILD layer 28. The third ILD layer may be formed by a deposition process such as, for example, CVD, PECVD, vapor deposition, or spin coating. A planarization process such as, for example, CMP may be performed after depositing the dielectric material providing the third ILD layer. As shown in Figure 10, the multilayer ILD-containing region 21 has a top surface that is substantially coplanar with the top surface of the bottom electrode 26 (represented by each "mound" portion of the bottom electrode 26) and the top surface of the gap-filling ILD layer 28. It should be noted that the gap-filling ILD layer 28 is positioned above the bottom electrode 26 at each "valley" portion, and the second ILD layer 20 present in the multilayer ILD-containing region 21 is positioned below each "mound" portion of the bottom electrode 26.

[0052] Referring now to Figure 11, an exemplary structure of Figure 10 is illustrated after forming an MTJ-containing stack including a blanket-covered bottom magnetic material layer 32L, a blanket-covered tunnel barrier layer 34L, and a blanket-covered top magnetic material layer 36L. The blanket-covered bottom magnetic material layer 32L includes either a magnetically pinned (or reference) material or a non-magnetic material. The blanket-covered top magnetic material layer 36L includes the other of the magnetically pinned or non-magnetic materials not used in the blanket-covered bottom magnetic material layer 32L. In one example, the blanket-covered bottom magnetic material layer 32L includes a magnetically pinned (or reference) material, and the blanket-covered top magnetic material layer 36L includes a non-magnetic material. In another example, the blanket-covered bottom magnetic material layer 32L includes a non-magnetic material, and the blanket-covered top magnetic material layer 36L includes a magnetically pinned (or reference) material.

[0053] In embodiments in which the MTJ-containing stack includes a magnetically pinned (or reference) material as a blanket-covered bottom magnetic material layer 32L and a non-magnetic material as a blanket-covered upper magnetic material layer 36L, the MTJ-containing stack (and subsequently formed MTJ-containing pillars) may be referred to as a bottom-pinned MTJ-containing stack (or a bottom-pinned MTJ-containing pillar). In embodiments in which the MTJ-containing stack includes a non-magnetic material as a blanket-covered bottom magnetic material layer 32L and a magnetically pinned (or reference) material as a blanket-covered upper magnetic material layer 36L, the MTJ-containing stack (and subsequently formed MTJ-containing pillars) may be referred to as a top-pinned MTJ-containing stack (or a top-pinned MTJ-containing pillar).

[0054] In some embodiments, the bottom-pinned MTJ-containing stack may also include an optional blanket-coated metal seed material layer (not shown). In the bottom-pinned MTJ-containing stack, the optional blanket-coated metal seed material layer is formed directly below the blanket-coated bottom magnetic material layer 32L. In some embodiments, the top-pinned MTJ-containing stack may also include an optional blanket-coated metal seed material layer (not shown). In the top-pinned MTJ-containing stack, the optional blanket-coated metal seed material layer is formed directly below the blanket-coated upper magnetic material layer 36L. In some embodiments, the MTJ-containing stack may also include a blanket-coated MTJ capping material layer (not shown) positioned on the blanket-coated upper magnetic material layer 36L. In some embodiments, the non-magnetic material may consist of a single non-magnetic material or a multilayer stack of non-magnetic materials. In some embodiments, the non-magnetic material includes a non-magnetic spacer material positioned between a first non-magnetic material and a second non-magnetic material.

[0055] Magnetic pinning materials have fixed magnetization. Magnetic pinning materials may be composed of metals or metal alloys (or stacks thereof) including one or more metals exhibiting high spin polarization. In alternative embodiments, exemplary metals used to form the magnetic pinning material include iron, nickel, cobalt, chromium, boron, or manganese. Exemplary metal alloys may include the metals exemplified above. In another embodiment, the magnetic pinning material may be a multilayer configuration having (1) a high spin polarization region formed by metals and / or metal alloys using the metals mentioned above, and (2) a region composed of one or more materials exhibiting strong perpendicular magnetic anisotropy (strong PMA). Exemplary materials with strong PMA that can be used include metals such as cobalt, nickel, platinum, palladium, iridium, or ruthenium, and may be configured as alternating layers. The strong PMA region may also include alloys exhibiting strong PMA, wherein exemplary alloys include cobalt-iron-tungsten, cobalt-iron-tungsten, cobalt-chromium-platinum, cobalt-platinum, cobalt-palladium, iron-platinum, and / or iron-palladium. The alloy can be configured as alternating layers. In one embodiment, this combination of materials and regions can also be used as a magnetic pinning material.

[0056] The blanket-covered tunnel barrier layer 34L is made of an insulating material and is formed to provide adequate tunneling resistance. Exemplary materials used in the blanket-covered tunnel barrier layer 34L include magnesium oxide, aluminum oxide, and titanium oxide, or materials with high electrical tunneling conductivity, such as semiconductors or low bandgap insulators.

[0057] Non-magnetic materials may consist of magnetic materials (or stacks of magnetic materials) whose magnetization orientation can be altered relative to the magnetization orientation of the magnetic pinning layers. It should be noted that the term "non-magnetic material" indicates that the magnetic material, like magnetic pinning materials, generally does not have fixed magnetization, but instead, rotates freely after an applied voltage. Exemplary magnetic materials used in non-magnetic materials include alloys and / or multilayers of cobalt, iron, cobalt-iron alloys, nickel, nickel-iron alloys, and cobalt-iron-boron alloys.

[0058] If present, the nonmagnetic metallic spacer is composed of a nonmagnetic metal or metal alloy that allows the transmission of magnetic information and permits the two nonmagnetic layers to be magnetically coupled together, such that the first and second nonmagnetic layers remain parallel in equilibrium. The nonmagnetic metallic spacer allows for switching of spin torque between the first and second nonmagnetic materials. The first and second nonmagnetic materials may include any of the aforementioned nonmagnetic materials. The first and second nonmagnetic materials may be identical or different in composition from each other.

[0059] The optional blanket-type metal seed material layer may be composed of Pt, Pd, Ni, Rh, Ir, Re, or alloys thereof, or multiple layers. In one example, the optional blanket-type metal seed material layer is composed of Pt. If present, the blanket-type MTJ capping material layer may be composed of Nb, NbN, W, WN, Ta, TaN, Ti, TiN, Ru, Mo, Cr, V, Pd, Pt, Rh, Sc, Al, or other high-melting-point metals or conductive metal nitrides.

[0060] MTJ stacks can be formed by using one or more deposition processes such as sputtering, plasma-enhanced atomic layer deposition (PEALD), PECVD, or PVD.

[0061] Referring now to Figure 12, an exemplary structure of Figure 11 is illustrated after a top electrode material layer 38L is formed on the MTJ stack. The top electrode material layer 38L is composed of a conductive metal material such as, for example, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, or WN. The conductive metal material providing the top electrode material layer 38L may be compositionally the same as or different from the conductive metal material providing the top electrode material layer 26L. The top electrode material layer 38L may be formed by depositing the conductive metal material. The deposition of the conductive metal material may include, but is not limited to, CVD, PECVD, ALD, or sputtering.

[0062] Referring now to Figure 13, an exemplary structure of Figure 12 is illustrated after a third patterned hard mask 40 is formed on the top electrode-containing material layer 38L. The third patterned hard mask 40 is formed on the top electrode-containing material layer 38L and above the MTJ-containing stack positioned above the bottom electrode 26. The third patterned hard mask 40 is designed to have a width extending beyond the outermost wall of the bottom electrode 26. The third patterned hard mask 40 is composed of a dielectric hard mask material including, for example, silicon dioxide, silicon nitride, and / or silicon oxynitride. The third patterned hard mask 40 can be formed by depositing a blanket-like hard mask material layer followed by photolithography patterning, in which transfer etching is selective in removing the dielectric hard mask material. The deposition of the blanket-like hard mask material layer includes, but is not limited to, CVD, PECVD, or PVD.

[0063] Referring now to Figure 14, the exemplary structure of Figure 13 is illustrated after etching a top electrode-containing material layer 38L and an MTJ-containing stack to provide a top electrode 38 and an MTJ-containing pillar, respectively, where the etching uses a third patterned hard mask 40 as an etching mask, and the third patterned hard mask 40 is removed. The etching also patterns the multilayer ILD-containing region 21 shown in Figure 14. The etching may include a RIE or an IBE. It should be noted that because the bottom electrode 26 is embedded in the multilayer ILD-containing region 21 and because the third patterned hard mask 40 is designed to have a width extending beyond the outermost sidewall of the bottom electrode 26, the bottom electrode 26 is not etched, and therefore re-splattering of the bottom electrode metal particles on the sidewall of the MTJ-containing pillar does not occur. Because re-splattering of the bottom electrode metal particles on the sidewall of the MTJ-containing pillar is avoided, no short circuits were observed in the resulting memory device. The MTJ column includes at least the unetched portion of each of the following: a blanket-covered bottom magnetic material layer 32L, a blanket-covered tunnel barrier layer 34L, and a blanket-covered upper magnetic material layer 36L. The unetched portion of the blanket-covered bottom magnetic material layer 32L may be referred to herein as the bottom magnetic material layer 32, the unetched portion of the blanket-covered tunnel barrier layer 34L may be referred to herein as the tunnel barrier layer 34, and the unetched portion of the blanket-covered upper magnetic material layer 36L may be referred to herein as the upper magnetic material layer 36.

[0064] After etching, the third patterned hard mask 40 is removed from the top of the top electrode 38 using a selective material removal process that removes the third patterned hard mask 40 from the self-exemplary structure.

[0065] As shown in Figure 14, the top electrode 38 has sidewalls that are vertically aligned with the sidewalls of the MTJ-containing pillars (including the sidewalls of the bottom magnetic material layer 32, the tunnel barrier layer 34, and the upper magnetic material layer 36). The vertically aligned sidewalls of the top electrode 38 and the MTJ-containing pillars extend beyond the outermost sidewall of the bottom electrode 26. The vertically aligned sidewalls of the top electrode 38 and the MTJ-containing pillars are also vertically aligned with the sidewalls of the remaining multilayer ILD regions 21. In some embodiments, etching may form a stack of the top electrode 28 and the MTJ-containing pillars, wherein the sidewalls taper slightly inward or outward from the top electrode 28 to the bottom layer containing the MTJ-containing pillars.

[0066] Referring now to FIG. 15, an exemplary structure of FIG. 14 is illustrated after the encapsulation liner 42 is formed on the top electrode 38, the MTJ-containing pillars, and the remaining (i.e., patterned) multilayer ILD-containing sidewalls. The encapsulation liner 42 is composed of an encapsulation dielectric material that can provide passivation to the MTJ-containing pillars. In some embodiments, the encapsulation dielectric material providing the encapsulation liner 42 may be composed of silicon nitride. In other embodiments, the encapsulation dielectric material providing the encapsulation liner 42 contains atoms of silicon, carbon, and hydrogen. In some embodiments, in addition to atoms of carbon and hydrogen, the encapsulation dielectric material providing the encapsulation liner 42 may also include atoms of at least one of nitrogen and oxygen. In other embodiments, in addition to atoms of silicon, nitrogen, carbon, and hydrogen, the encapsulation dielectric material providing the encapsulation liner 42 may also include atoms of boron. In one example, the encapsulating dielectric material providing the encapsulation liner 42 may be composed of a SiNC dielectric material containing atoms of silicon, carbon, hydrogen, nitrogen, and oxygen. In an alternative example, the encapsulating dielectric material providing the encapsulation liner 42 may be composed of a SiBCN dielectric material containing atoms of silicon, boron, carbon, hydrogen, and nitrogen.

[0067] Encapsulation liner 42 can be formed by depositing a conformal layer of encapsulated dielectric material on the solid exposed surfaces of the top electrode 38, the MTJ pillars, the remaining (i.e., patterned) multilayer ILD-containing regions 21, and the dielectric cap 16. The conformal layer of encapsulated dielectric material can be formed by conformal deposition processes including, but not limited to, ALD, CVD, PECVD, or PVD. The formation of encapsulation liner 42 continues by removing the conformal layer of encapsulated dielectric material from all horizontal surfaces of the exemplary structure while maintaining the conformal layer of encapsulated dielectric material along the sidewalls of the top electrode 38, the MTJ pillars, and the remaining (i.e., patterned) multilayer ILD-containing regions 21. The remaining conformal layer of encapsulated dielectric material present along the sidewalls of the MTJ pillars can be referred to herein as encapsulation liner 42. Encapsulation liner 42 is columnar and laterally surrounds the sidewalls of the top electrode 38, the MTJ pillars, and the remaining (i.e., patterned) multilayer ILD-containing regions 21. Removing the conformal layer of the encapsulated dielectric material from all horizontal surfaces may include a dielectric etch-back process. As illustrated in Figure 15, the encapsulation liner 42 is positioned on the sidewalls of each of the bottom magnetic material layer 32, the tunnel barrier layer 34, and the upper magnetic material layer 36. The encapsulation liner 42 has a bottom surface that is in direct physical contact with the top surface of the dielectric cap 16, and a top surface that is substantially coplanar with the top surface of the top electrode 38.

[0068] Referring now to FIG. 16, an exemplary structure of FIG. 15 is illustrated, showing a fourth ILD layer 44 formed on top of the top electrode 38 adjacent to the encapsulation liner 42. The fourth ILD layer 44 may include the dielectric material used for the first ILD layer 10 as mentioned above. The dielectric material providing the fourth ILD layer 44 may be compositionally the same as or different from the dielectric material providing the first ILD layer 10 and / or the second ILD layer 20 and / or the third ILD layer. The fourth ILD layer 44 may be formed by a deposition process such as, for example, CVD, PECVD, vapor deposition, or spin coating. A planarization process such as, for example, CMP may be performed after depositing the dielectric material providing the fourth ILD layer 44.

[0069] Referring now to FIG. 17, an exemplary structure of FIG. 16 is illustrated after the formation of a second conductive structure 48 in the fourth ILD layer 44, which is in electrical contact with the top electrode 38. An optional second diffusion barrier liner 46 may be present along the sidewalls and bottom surface of the second conductive structure 48. The second conductive structure 48 is made of the conductive material used for the first conductive structure 14 as mentioned above. The optional second diffusion barrier liner 46 is made of the diffusion barrier material used for the optional first diffusion barrier liner 12 as mentioned above. The optional second diffusion barrier liner 46 and the second conductive structure 48 may be formed by a metal inlay process as mentioned above in the formation of the optional first diffusion barrier liner 12 and the first conductive structure 14. In this embodiment, the second conductive structure 48 is electrically connected (directly or indirectly) to the top electrode 38. Additionally, in this embodiment, the bottom electrode 26 is electrically connected to both the first conductive structure 14 (via the metal cap 18) and the MTJ-containing pillar. Compared to the flat bottom electrode commonly used in the prior art, the serpentine bottom electrode 26 has a reduced contact area with the MTJ-containing pillar. Even with the reduced contact area, the serpentine bottom electrode 26 still has a smoother top surface compared to the flat bottom electrode commonly used in the prior art. This smoother surface enables an enhanced interface between the bottom electrode 26 and the MTJ-containing pillar. [ ]

[0070] It is noteworthy that Figure 17 illustrates an exemplary memory device according to an embodiment of this application. The memory device illustrated in Figure 17 includes: a first conductive structure 14; a metal cap 18 positioned on the first conductive structure 14; an MTJ-containing pillar positioned above the metal cap 18; a bottom electrode 26 with a serpentine pattern positioned between the metal cap 18 and the MTJ-containing pillar, wherein the bottom electrode 26 has a bottom surface in contact with the metal cap 18 and a top surface in contact with the MTJ-containing pillar; a top electrode 38 positioned on the MTJ-containing pillar; and a second conductive structure 48 electrically connected to the top electrode 38. The presence of the serpentine-patterned bottom electrode 26 provides a bottom electrode top surface with reduced surface roughness or surface undulation by means of a reduced metal content in the bottom surface of the bottom electrode that interfaces with the bottom surface of the MTJ-containing pillar, thereby improving the magnetic performance of the memory device. [ ]

[0071] In some embodiments, the MTJ-containing column illustrated in FIG17 includes a bottom magnetic material layer 32, a tunnel barrier layer 34, and an upper magnetic material layer 36, wherein the bottom magnetic material layer 32 comprises a non-magnetic material, and the upper magnetic material layer 36 comprises a magnetic reference material. Such an MTJ-containing column is referred to as a top-pinned MTJ-containing column.

[0072] In some embodiments, the MTJ-containing post illustrated in FIG17 includes a bottom magnetic material layer 32, a tunnel barrier layer 34, and an upper magnetic material layer 36, wherein the bottom magnetic material layer 32 includes a magnetic reference material, and the upper magnetic material layer 36 includes a non-magnetic material. Such an MTJ-containing post is referred to as a bottom-pinned MTJ-containing post.

[0073] In some embodiments of this application, the top electrode 38 and the MTJ-containing pillar of the memory device illustrated in FIG17 are laterally surrounded by an encapsulation liner 42. The encapsulation liner 42 provides protection (i.e., electrical isolation) for the top electrode 38 and the MTJ-containing pillar, and in some embodiments, passivates the MTJ-containing pillar.

[0074] In some embodiments of this application, the memory device of FIG17 further includes a multilayer ILD-containing region 21 positioned adjacent to and embedded in the bottom electrode 26. This configuration, in which the bottom electrode 26 is embedded in the multilayer ILD-containing region 21, prevents bottom electrode metal particles from being re-sputtered onto the sidewalls containing the MTJ pillars during its formation. Therefore, this helps prevent potential short circuits in the memory device.

[0075] In some embodiments of this application, the memory device of FIG17 further includes a gap-filling ILD layer 28 positioned in the gaps created by the serpentine pattern of the bottom electrode 26. The presence of the gap-filling ILD layer 28 provides a surface on which MTJ pillars can be formed.

[0076] In some embodiments, the MTJ-containing pillar illustrated in FIG17 has a sidewall vertically aligned with the sidewall of the top electrode 38, and the vertically aligned sidewall of the MTJ-containing pillar and the top electrode 38 extends beyond the outermost sidewall of the bottom electrode 26. This configuration of the present application facilitates the formation of an MTJ-containing pillar free from resputtered bottom electrode particles.

[0077] In some embodiments, the bottom electrode 26 with a serpentine pattern shown in FIG17 includes a plurality of mounds and valleys, wherein each mound is in electrical contact with an MTJ-containing pillar and each valley is in electrical contact with a metal cap 18.

[0078] In some embodiments, the bottom electrode 26 with a serpentine pattern shown in FIG17 includes a single mound and a single valley, wherein the single mound is in electrical contact with the MTJ-containing pillar and the single valley is in electrical contact with the metal cap 18.

[0079] Compared to the entirely planar bottom electrode commonly used in the prior art, the bottom electrode 26, which has both mounds and valleys (or a single mound and valley), has a reduced contact area with the MTJ-containing pillar. Even with the reduced contact area, the bottom electrode 26 still has a smoother top surface compared to the entirely planar bottom electrode commonly used in the prior art. This smoother surface enables an enhanced interface between the bottom electrode 26 and the MTJ-containing pillar. [ ]

[0080] In some embodiments, the memory device of FIG17 further includes a diffusion barrier liner (i.e., a second diffusion barrier liner 46) positioned on the sidewall and bottom surface of the second conductive structure 48.

[0081] Referring now to FIG. 18, an exemplary structure of FIG. 5 is illustrated after a first bottom electrode material layer 25L with a serpentine pattern is formed on a previously patterned second ILD layer 20, and a second bottom electrode material layer 27L with a serpentine pattern is formed on the first bottom electrode material layer 25L. Although not shown, one or more additional bottom electrode material layers with serpentine patterns may be formed on top of the second bottom electrode material layer 27L. Therefore, this embodiment of the present application covers the formation of multiple (two or more) bottom electrode material layers, each with a serpentine pattern.

[0082] The first bottom electrode layer 25L is composed of a first conductive metal material, while the second bottom electrode layer 27L is composed of a second conductive metal material that is different in composition from the first conductive metal material. When an additional bottom electrode layer is formed, the first additional bottom electrode layer formed on the second bottom electrode layer 27L is composed of a conductive metal material that is different in composition from the second conductive metal material providing the second bottom electrode layer 27L, and each consecutive additional bottom electrode layer is composed of a conductive metal material that is different in composition from the aforementioned additional bottom electrode layers. The conductive metal material (including the first and second conductive metal materials mentioned above) includes, for example, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, or WN.

[0083] Each bottom electrode layer (including the first bottom electrode layer 25L and the second bottom electrode layer 27L) can be formed by a deposition process such as, for example, CVD, PECVD, ALD, or sputtering. It should be noted that each bottom electrode layer (including the first bottom electrode layer 25L and the second bottom electrode layer 27L) can be formed using the same or different deposition processes.

[0084] Referring now to FIG. 19, an exemplary structure of FIG. 18 is illustrated after a gap-filled ILD layer 28 is formed in the gaps provided by the serpentine pattern of the second bottom electrode layer 27L (in embodiments where more than two bottom electrode material layers are formed, the gap-filled ILD layer 28 is formed in the gaps provided by the serpentine pattern of the topmost bottom electrode layer). The gap-filled ILD layer 28 in this embodiment is the same as the gap-filled ILD layer 28 described above for providing the gap-filled ILD layer 28 for the exemplary structure shown in FIG. 7. Therefore, the description of the gap-filled ILD layer 28 provided in FIG. 7 applies here to FIG. 19.

[0085] Referring now to FIG. 20, the exemplary structure of FIG. 19 is illustrated after a second patterned hard mask 30 is formed on a portion of the second bottom electrode layer 27L (or the topmost bottom electrode layer) and on the gap-filling ILD layer 28 positioned in the gaps provided by the serpentine pattern of the second bottom electrode layer 27A (or the topmost bottom electrode layer). The second patterned hard mask 30 in this embodiment is the same as the second patterned hard mask 30 described above for providing the second patterned hard mask 30 for the exemplary structure shown in FIG. 8. Therefore, the description of the second patterned hard mask 30 provided in FIG. 8 applies herein to FIG. 20.

[0086] Referring now to FIG. 21, an exemplary structure of FIG. 20 is illustrated after the following operations: removal of the solid exposed portion of the second bottom electrode layer 27A, which is not protected by the second patterned hard mask 30, and the portion beneath the first bottom electrode layer 25A; removal of the second patterned hard mask 30 to expose the second bottom electrode 27 having a serpentine pattern, wherein the gaps provided by the serpentine pattern are filled with a gap-filling ILD layer 28; and exposure of the first bottom electrode 25 having a serpentine pattern positioned below the second bottom electrode 27; the first bottom electrode 25 and the second bottom electrode 27 together provide a multilayer bottom electrode structure having a serpentine pattern. In the illustrated embodiment, the multilayer bottom electrode structure includes the first bottom electrode 25 and the second bottom electrode 27. In other embodiments, the multilayer bottom electrode structure may contain three or more bottom electrodes, each having a serpentine pattern.

[0087] The solid exposed portions of the second electrode layer 27L and the first bottom electrode layer 25L are removed using one or more selective etching processes when removing the second electrode layer 27L and the first bottom electrode layer 25L which are not protected by the second patterned hard mask 30. After the solid exposed portions of the second electrode layer 27L and the first bottom electrode layer 25L which are not protected by the second patterned hard mask 30, the second patterned hard mask 30 is removed using a selective material removal process when removing the second patterned hard mask 30. As shown in FIG21, the second bottom electrode 27 has a top surface that is substantially coplanar with the top surface of the gap-filling ILD layer 28 (represented by the "mounds" of the second bottom electrode 27). The first bottom electrode 25 has a bottom surface that is in electrical contact with the metal cap 18 (represented by the "valleys" of the first bottom electrode 25). It should be noted that when more than two bottom electrodes are formed, the topmost bottom electrode of the multilayer bottom electrode structure will have a topmost surface that is substantially coplanar with the topmost surface of the gap-filled ILD layer 28.

[0088] Referring now to Figure 22, an exemplary structure of Figure 21 is illustrated after a third ILD layer (not shown or labeled separately in Figure 10) is formed on the second ILD layer 20 to provide a multilayer ILD-containing region 21. The multilayer ILD-containing region 21 includes a combination of the third ILD layer and the second ILD layer 20. The third ILD layer is composed of the dielectric material used for the first ILD layer 10 as mentioned above. The dielectric material providing the third ILD layer may be compositionally the same as or different from the dielectric material providing the first ILD layer 10 and / or the second ILD layer 20 and / or the gap-filling ILD layer 28. The third ILD layer may be formed by a deposition process such as, for example, CVD, PECVD, vapor deposition, or spin coating. A planarization process such as, for example, CMP may be performed after depositing the dielectric material providing the third ILD layer. As shown in Figure 22, the multilayer ILD-containing region 21 has a top surface that is substantially coplanar with the top surface of the second bottom electrode 27 (represented by the "mounds" of the second bottom electrode 27) and the top surface of the gap-filling ILD layer 28. It should be noted that when more than two bottom electrodes are formed, the multilayer ILD-containing region 21 has a top surface that is substantially coplanar with the top surface of the top bottom electrode of the multilayer bottom electrode structure and the top surface of the gap-filling ILD layer 28.

[0089] Referring now to FIG. 23, an exemplary structure of FIG. 22 is illustrated after performing the processing steps of FIG. 11 to FIG. 17. It is noteworthy that FIG. 23 illustrates the exemplary structure of FIG. 22 after forming the MTJ-containing pillar and top electrode 38, encapsulation liner 42, fourth ILD layer 44, optional second diffusion barrier liner 46, and second conductive structure 48. The MTJ-containing pillar includes at least a bottom magnetic material layer 32, a tunnel barrier layer 34, and an upper magnetic material layer 36. In this embodiment, the second conductive structure 48 is electrically connected (directly or indirectly) to the top electrode 38. Additionally, in this embodiment, the first bottom electrode 25 is electrically connected to the first conductive structure 14 (via the metal cap 18), and the topmost bottom electrode of the multi-layer bottom electrode structure (in the illustrated embodiment, the topmost bottom electrode is the second bottom electrode 27) is electrically connected to the MTJ-containing pillar. Compared to the entirely planar bottom electrode commonly used in the prior art, the contact area between the multi-layer bottom electrode structure with the serpentine pattern and the MTJ-containing pillar is reduced. Even with a reduced contact area, the multilayer bottom electrode structure with a serpentine pattern still has a smoother top surface compared to the full-plane bottom electrode typically used in prior art. This smoother surface enables a reinforced interface between the top bottom electrode of the multilayer bottom electrode structure and the MTJ-containing pillar. [ ]

[0090] It is noteworthy that Figure 23 illustrates an exemplary memory device according to another embodiment of this application. The memory device illustrated in Figure 23 includes: a first conductive structure 14; a metal cap 18 positioned on the first conductive structure 14; a MTJ-containing pillar positioned above the metal cap 18; a multi-layer bottom electrode structure with a serpentine pattern positioned between the metal cap 18 and the MTJ-containing pillar (e.g., a first bottom electrode 25 and a second bottom electrode 27), wherein the multi-layer bottom electrode structure has a bottom electrode (i.e., the first bottom electrode 25) in contact with the metal cap 18 and a bottom electrode (e.g., the second bottom electrode 27) in contact with the top of the MTJ-containing pillar; a top electrode 38 positioned on the MTJ-containing pillar; and a second conductive structure 48 electrically connected to the top electrode 38. The presence of a multi-layered bottom electrode structure with a serpentine pattern improves the magnetic performance of memory devices by reducing the metal content in the top surface of the bottom electrode, which interfaces with the bottom surface containing the MTJ pillar, thereby providing a bottom electrode top surface with reduced surface roughness or surface undulation. [ ]

[0091] In some embodiments, the MTJ-containing column illustrated in FIG23 includes a bottom magnetic material layer 32, a tunnel barrier layer 34, and an upper magnetic material layer 36, wherein the bottom magnetic material layer 32 comprises a non-magnetic material, and the upper magnetic material layer 36 comprises a magnetic reference material. Such an MTJ-containing column is referred to as a top-pinned MTJ-containing column.

[0092] In some embodiments, the MTJ-containing post illustrated in FIG23 includes a bottom magnetic material layer 32, a tunnel barrier layer 34, and an upper magnetic material layer 36, wherein the bottom magnetic material layer 32 includes a magnetic reference material, and the upper magnetic material layer 36 includes a non-magnetic material. Such an MTJ-containing post is referred to as a bottom-pinned MTJ-containing post.

[0093] In some embodiments of this application, the top electrode 38 and the MTJ-containing pillar of the memory device illustrated in FIG23 are laterally surrounded by an encapsulation liner 42. The encapsulation liner 42 provides protection (i.e., electrical isolation) for the top electrode 38 and the MTJ-containing pillar, and in some embodiments, passivates the MTJ-containing pillar.

[0094] In some embodiments of this application, the memory device of FIG23 further includes a multilayer ILD-containing region 21 positioned adjacent to and embedded in a multilayer bottom electrode structure (e.g., a first bottom electrode 25 and a second bottom electrode 27). This configuration, in which the multilayer bottom electrode structure is embedded in the multilayer ILD-containing region 21, prevents bottom electrode metal particles from being re-sputtered onto the sidewalls containing the MTJ pillars during their formation. Therefore, this helps prevent potential short circuits in the memory device.

[0095] In some embodiments of this application, the memory device of FIG23 further includes a gap-filling ILD layer 28 positioned in the gaps created by the serpentine pattern of the multilayer bottom electrode structure. The presence of the gap-filling ILD layer 28 provides a surface on which MTJ pillars can be formed.

[0096] In some embodiments, the MTJ-containing pillar illustrated in FIG23 has a sidewall vertically aligned with the sidewall of the top electrode, and the vertically aligned sidewall of the MTJ-containing pillar and the top electrode extends beyond the outermost sidewall of the multilayer bottom electrode structure. This configuration of the present application facilitates the formation of MTJ-containing pillars without resputtered bottom electrode particles.

[0097] In some embodiments of this application, the bottommost bottom electrode (i.e., the first bottom electrode 25) includes a plurality of mounds and valleys, wherein each valley of the bottommost bottom electrode (i.e., the first bottom electrode 25) is in electrical contact with the metal cap 18, and the topmost bottom electrode (e.g., the second bottom electrode 27) includes a plurality of mounds and valleys, wherein each mound of the topmost bottom electrode (e.g., the second bottom electrode 27) is in electrical contact with the MTJ-containing pillar.

[0098] In some embodiments of this application, the bottommost bottom electrode (i.e., the first bottom electrode 25) includes a single mound and a single valley, wherein the single valley of the bottommost bottom electrode (i.e., the first bottom electrode 25) is in electrical contact with the metal cap 18, and the topmost bottom electrode (e.g., the second bottom electrode 27) includes a single mound and a single valley, wherein the single mound of the topmost bottom electrode (e.g., the second bottom electrode 27) is in electrical contact with the MTJ-containing pillar.

[0099] Compared to the planar bottom electrode commonly used in prior art, the multilayer bottom electrode structure with mounds and valleys (or a single mound and valley) reduces the contact area with the MTJ-containing pillar. Even with the reduced contact area, the multilayer bottom electrode structure still has a smoother top surface compared to the planar bottom electrode commonly used in prior art. The smoother surface enables an enhanced interface between the top bottom electrode of the multilayer bottom electrode structure and the MTJ-containing pillar. [ ]

[0100] In some embodiments, the memory device of FIG23 further includes a diffusion barrier liner (i.e., a second diffusion barrier liner 46) positioned on the sidewall and bottom surface of the second conductive structure 48.

[0101] In some embodiments, the multilayer bottom electrode structure includes two bottom electrodes (e.g., a first bottom electrode 25 and a second bottom electrode 27) that are in close contact with each other.

[0102] In some embodiments, the two bottom electrodes (e.g., the first bottom electrode 25 and the second bottom electrode 27) are made of conductive metal materials with different compositions.

[0103] While this application has specifically shown and described with respect to its preferred embodiments, those skilled in the art will understand that changes in form and detail, as described above and others, can be made without departing from the spirit and scope of this application. Therefore, this application is intended to be limited to the exact form and details described and illustrated, but rather to fall within the scope of the appended claims.

[0104] 10: First ILD layer 12: First diffusion barrier liner 14: First conductive structure 16: Dielectric cap / Patterned dielectric cap 18: Metal Cap 20: Second ILD layer 21: Multilayer containing ILD region 24: First patterned hard mask 25: First bottom electrode 25L: First bottom electrode material layer / First bottom electrode layer 26: Bottom electrode 26L: Bottom layer containing electrode material / Bottom layer containing electrode material 27: Second bottom electrode 27L: Second bottom electrode layer / Second electrode layer / Second bottom electrode material layer 28: Gap-filling ILD layer 30: Second patterned hard mask 32: Bottom layer contains magnetic material 32L: Blanket-covered bottom with magnetic material layer 34:Tunnel barrier layer 34L: Blanket-covered tunnel barrier layer 36: Upper layer containing magnetic material 36L: Blanket-covered upper layer with magnetic material layer 38: Top electrode 38L: Top layer contains electrode material 40: Third Patterned Hard Mask 42: Bag lining 44: Fourth ILD layer 46: Second diffusion barrier liner 48: Second conductive structure

Claims

1. A memory device comprising: a first conductive structure; a metal cap positioned on the first conductive structure; a magnetic tunneling junction (MTJ) post positioned above the metal cap; a bottom electrode having a serpentine pattern positioned between the metal cap and the MTJ post, wherein the bottom electrode has a bottom surface in contact with the metal cap and a top surface in contact with the MTJ post; a gap-filling ILD layer positioned in one of the gaps created by the serpentine pattern of the bottom electrode; a top electrode positioned on the MTJ post; and a second conductive structure electrically connected to the top electrode.

2. The memory device of claim 1, wherein the MTJ pillar includes a bottom magnetic material layer, a tunnel barrier layer and an upper magnetic material layer, wherein the bottom magnetic material layer includes a non-magnetic material and the upper magnetic material layer includes a magnetic reference material.

3. The memory device of claim 1, wherein the MTJ pillar includes a bottom magnetic material layer, a tunnel barrier layer and an upper magnetic material layer, wherein the bottom magnetic material layer includes a magnetic reference material and the upper magnetic material layer includes a non-magnetic material.

4. The memory device of claim 1, wherein the top electrode and the MTJ-containing post are laterally surrounded by a capsule liner.

5. The memory device of claim 1, further comprising a multilayer ILD-containing region positioned adjacent to and embedded in the bottom electrode.

6. The memory device of claim 1, wherein the MTJ-containing pillar has a sidewall vertically aligned with one sidewall of the top electrode, and the MTJ-containing pillar and the top electrode extend beyond one outermost sidewall of the bottom electrode via the vertically aligned sidewall.

7. The memory device of claim 1, wherein the bottom electrode having the serpentine pattern comprises a plurality of mounds and valleys, wherein each mound is electrically contacted with the MTJ-containing pillar and each valley is electrically contacted with the metal cap.

8. The memory device of claim 1, wherein the bottom electrode having the serpentine pattern comprises a single mound and a single valley, wherein the single mound is in electrical contact with the MTJ-containing pillar and the single valley is in electrical contact with the metal cap.

9. The memory device of claim 1, further comprising a diffusion barrier liner located on one sidewall and one bottom surface of the second conductive structure.

10. A memory device comprising: a first conductive structure; a metal cap positioned on the first conductive structure; a magnetic tunneling junction (MTJ) post positioned above the metal cap; a multilayer bottom electrode structure having a serpentine pattern positioned between the metal cap and the MTJ post, wherein the multilayer bottom electrode structure has a bottom electrode at a very bottom contacting the metal cap and a top electrode at a very top contacting the MTJ post; a top electrode positioned on the MTJ post; and a second conductive structure electrically connected to the top electrode.

11. The memory device of claim 10, wherein the MTJ pillar includes a bottom magnetic material layer, a tunnel barrier layer and an upper magnetic material layer, wherein the bottom magnetic material layer includes a non-magnetic material and the upper magnetic material layer includes a magnetic reference material.

12. The memory device of claim 10, wherein the MTJ pillar comprises a bottom magnetic material layer, a tunnel barrier layer and an upper magnetic material layer, wherein the bottom magnetic material layer comprises a magnetic reference material and the upper magnetic material layer comprises a non-magnetic material.

13. The memory device of claim 10, wherein the top electrode and the MTJ-containing post are laterally surrounded by a capsule liner.

14. The memory device of claim 10, further comprising a multilayer ILD region positioned adjacent to and embedded in one of the multilayer bottom electrode structures.

15. The memory device of claim 10, further comprising a gap-filling ILD layer located in one of the gaps created by the serpentine pattern of the multilayer bottom electrode structure.

16. The memory device of claim 10, wherein the MTJ-containing pillar has a sidewall vertically aligned with one sidewall of the top electrode, and the MTJ-containing pillar and the top electrode extend beyond one of the outermost sidewalls of the multilayer bottom electrode structure.

17. The memory device of claim 10, wherein the bottommost bottom electrode comprises a plurality of mounds and valleys, wherein each valley of the plurality of mounds and valleys of the bottommost bottom electrode is in electrical contact with the metal cap, and the topmost bottom electrode comprises a plurality of mounds and valleys, wherein each mound of the plurality of mounds and valleys of the topmost bottom electrode is in electrical contact with the MTJ-containing pillar.

18. The memory device of claim 10, wherein the bottommost bottom electrode comprises a single mound and a single valley, wherein the single valley of the bottommost bottom electrode is in electrical contact with the metal cap, and the topmost bottom electrode comprises a single mound and a single valley, wherein the single mound of the topmost bottom electrode is in electrical contact with the MTJ-containing pillar.

19. The memory device of claim 10, further comprising a diffusion barrier liner positioned on one sidewall and one bottom surface of the second conductive structure.

20. The memory device of claim 10, wherein the multilayer bottom electrode structure includes two bottom electrodes that are in close contact with each other.

21. The memory device of claim 10, wherein the two bottom electrodes are made of conductive metal materials that are different in composition.

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