Embedded flash memory below 110nm and its fabrication method

A novel embedded flash memory structure with matched gate heights and simplified fabrication addresses miniaturization challenges, ensuring reliable and efficient flash memory operations by maintaining gate uniformity and reducing ion implantation risks.

TWI934885BActive Publication Date: 2026-08-01CHENGDU ANALOG CIRCUIT TECH INC
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Patent Information

Application Number
TW115113908
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Priority Date
2025-04-25
Filing Date
2026-04-09
Publication Date
2026-08-01
Estimated Expiration
2046-04-08

AI Technical Summary

Technical Problem

Existing embedded flash memory technologies face challenges in miniaturization below 110nm, particularly with the ESF3 and 2T structures, due to complex manufacturing processes, gate height incompatibility, and reliability issues from ion implantation, which affect the performance and stability of flash memory devices.

Method used

A novel embedded flash memory structure with a control gate height matching the logic gate height, utilizing a stacked gate and select gate with the same or similar height, and a simplified fabrication method involving simultaneous deposition and selective etching to ensure uniformity and reliability, with optional dielectric layers and vias for electrical connectivity.

Benefits of technology

The proposed structure and fabrication method result in a reliable, high-performance embedded flash memory with simplified manufacturing, ensuring consistent gate heights and reducing the risk of ion penetration, thereby enhancing the stability and efficiency of flash memory operations.

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Abstract

An embedded flash memory with a wavelength below 110nm and its fabrication method are disclosed. The embedded flash memory with a wavelength below 110nm includes: a substrate, a storage array region and a peripheral logic region on the substrate. The storage array region contains at least one storage cell. The storage cell includes: a common source located in the substrate; a common line located above and connected to the common source; a pair of stacked gates located on both sides of the common line, each stacked gate including a floating gate and a vertically stacked control gate above it; and a pair of select gates located next to the non-common line sides of the two stacked gates. The peripheral logic region contains at least one logic transistor, and the logic transistor includes a logic gate. The control gate in the storage cell has the same height as the logic gate of the logic transistor. This embedded flash memory exhibits good performance, stability, and reliability, and its fabrication method is simple, convenient, and low-cost.
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