Ohmic contacts for multiple channel fets and method of forming the same

Abstract

An ohmic contact for a multichannel FET includes a plurality of slit-shaped notches in a wafer on which a multichannel FET is disposed, wherein each notch has a depth at least equal to the depth of the lowest channel layer. Ohmic metal in and on the sidewalls of each notch provides ohmic contact to each of the plurality of channel layers. A linearly connected notch filled with ohmic metal may be provided adjacent to the outer edge of each notch, and an ohmic metal contact layer on the top surface of the wafer, the ohmic metal contact layer being above and contacting the ohmic metal in each of the notches. The ohmic contact of the present invention typically serves as a source and / or drain contact of the multichannel FET. The use of a regrown material for ohmic contact with the plurality of channels is also described, wherein the regrown material preferably has a corrugated structure.

Description

Technical Field

[0001] This invention relates generally to ohmic contacts, and more specifically to ohmic contacts for multichannel field-effect transistors (FETs). Prior Technology

[0002] Field-effect transistors (FETs) consisting of multiple (stacked) channel structures have recently attracted attention for their increased current density and reduced on-resistance in power amplifier and power switching applications. For single-channel FETs, conventional fused ohmic contacts are formed by annealing stacks of thin metal layers (such as Ti / Al / Mo / Au for GaN FETs and AuGe / Ni / Au for GaAs / InGaAs FETs); buried metal forms ohmic contacts to the channel layers. However, this method does not work well for multi-channel FET structures, where the distance between the top semiconductor surface and the stacked channels is large because the alloyed metal does not reach the deep channels. This results in higher contact resistance in multi-channel transistors.

[0003] "Regrown" ohmic contacts are another technique used to form low-resistance ohmic contacts. Low ohmic contact resistance has been demonstrated in laterally regrown n+ GaN over a single 2DEG (two-dimensional electron gas) channel. However, the contact resistance in multi-channel FETs can be higher than required. Summary of the Invention

[0004] An ohmic contact for a multichannel FET is presented. In one possible specific embodiment, the ohmic contact of the present invention comprises a plurality of slit-shaped notches in a wafer on which the multichannel FET resides, wherein each notch has a depth at least equal to the depth of the lowest channel layer of the FET. The notches are linearly aligned with each other, wherein this row of notches is oriented perpendicular to the current flow direction between the source and drain of the FET. Ohmic metal in and on the sidewalls of each slit-shaped notch provides ohmic contact to each of the plurality of channel layers. The sidewalls are preferably inclined, wherein the angle of the sidewalls is between 45° and 90°.

[0005] Each of the slit-shaped notches has an inner edge and an outer edge, to which current flows or from the inner edge. In a preferred embodiment, a linear connection notch is provided adjacent to the outer edge of each of the slit-shaped notches. Ohmic metal is also deposited in the linear connection notch, such that the ohmic metal interconnects the slit-shaped notches and the linear connection notches with a plurality of channel layers.

[0006] The ohmic contact of the present invention may also include an ohmic metal contact layer on the top surface of the wafer, the ohmic metal contact layer being above and in contact with the ohmic metal in each of the recesses in the row of recesses, and above the linear connection recesses (if present).

[0007] The ohmic contacts of this invention typically serve as source and / or drain contacts for a multichannel FET. The FET may be, for example, a GaN FET, wherein the ohmic metal comprises Ti, Al, Mo, and / or Au. Another example would be a GaAs / InGaAs FET, wherein the ohmic metal comprises AuGe, Ni, and / or Au. Additional examples are provided below.

[0008] The following figures, descriptions and claims will provide a better understanding of these and other features, aspects and advantages of the invention. Simple Explanation of the Diagram

[0009] [Figure 1] is a perspective view of a specific example of a multichannel FET employing ohmic contacts according to the present invention.

[0010] [Figure 2] is a perspective view of another possible specific example of a multichannel FET employing narrow ohmic contacts according to the present invention.

[0011] [Figure 3A] is a perspective view of a specific example of a multichannel FET employing ohmic contacts according to the present invention, and it depicts the cross-sectional lines A-A' and B-B' in the notch.

[0012] [Figures 3B and 3C] show two possible cross-sectional views of the notch, which are generated by the cross-sectional lines A-A' and B-B' in Figure 3A.

[0013] [Figures 4A and 4B] are plan views of two possible specific examples of a multichannel FET employing ohmic contacts according to the present invention, showing the potential and current paths between the contacts.

[0014] [Figure 5A] is a plan view of a possible specific example of a multichannel FET employing ohmic contacts according to the present invention.

[0015] [Figure 5B] is a plan view of another possible specific example of a multichannel FET employing ohmic contacts according to the present invention.

[0016] [Figure 6A] is a perspective view of a specific example of a multichannel FET employing regenerated ohmic contacts according to the present invention.

[0017] [Figure 6B] is a perspective view of another possible specific example of a multichannel FET employing regenerated ohmic contacts according to the present invention.

[0018] [Figure 7] is a flowchart illustrating a set of possible steps for forming an ohmic contact using the slit-shaped notch according to the present invention.

[0019] [Figure 8] is a flowchart illustrating a set of possible steps for forming an ohmic contact using the regenerated material according to the present invention. Implementation

[0020] As a summary, in a possible specific example, the ohmic contact of the present invention, intended for use with a FET having a multiple (stacked) channel structure, is formed by notching a small slit pattern prior to ohmic metal deposition. The notches become deeper than the depth of the underlying channel layer. Ohmic metal is deposited directly onto the sidewalls of each notch, thereby forming simultaneous contact with each channel. The length, width, and shape of the slit structure are preferably optimized based on the surface resistivity of the material and the lateral contact resistance between the metal and the channel, so as to minimize the total contact resistance.

[0021] A similar concept applied to the latest regrown ohmic contact technology is also described, in which the regrown material enables ohmic contact with the sidewalls of multiple channels. As described herein, the regrown material preferably has a corrugated structure that increases the contact area by enlarging the contact perimeter in two dimensions, thereby reducing the effective contact resistance. The length, width, and shape of the corrugated structure are preferably optimized based on the surface resistivity of the material and the lateral contact resistance between the metal and the channels to minimize the total contact resistance.

[0022] Figure 1 illustrates a possible specific example of the "slit pattern" method, in which ohmic contacts 10, 12 (source and drain) are provided for a multichannel FET 14. Each ohmic contact comprises a plurality of slit-shaped recesses 16 in a wafer 18 on which the multichannel FET resides. Each recess 16 has a depth at least equal to the depth of the lowest channel layer 20 of the FET, wherein the recesses are linearly aligned with each other. This row of recesses is oriented perpendicular to the current flow direction between the source and drain of the FET. Ohmic metal (unnumbered) is embedded in and on the sidewalls of each of the slit-shaped recesses, making ohmic contact with each of the plurality of channel layers, while also contacting the laterally formed channel layers. The width and spacing of the slits are preferably selected to optimize material conductivity and interfacial resistance.

[0023] The ohmic contact of the present invention may further include an ohmic metal contact layer 22 on the top surface of the wafer 18, the ohmic metal contact layer being above and in contact with the ohmic metal in each of the recesses 16. The ohmic metal contact layer 22 has an inner edge 24 and an outer edge 26; the recesses 16 are preferably located at a distance ≥ 0 µm receding from the inner edge 24 of the ohmic metal contact layer, such that each of the recesses is completely overlapped (covered) by the ohmic metal contact layer.

[0024] The ohmic metal contact layer 22 has an associated width W1, defined as the distance between the inner edge 24 and the outer edge 26. Each of the notches 16 also has an associated common width W2 defined in the same direction as W1. The minimum value of W1 is preferably equal to W2. W1 may be significantly larger than W2, as shown in FIG1. ​​Alternatively, as shown in FIG2, the ohmic metal contact layer 32 may be relatively narrow, wherein the width W1 is equal to or nearly equal to W2.

[0025] Figure 3A shows the multichannel FET 14 as described herein, where the cross-sectional views shown in Figures 3B and 3C (taken along section lines A-A' and B-B') illustrate the possible shapes of the sidewalls 40, 42 of the notch 16. As shown in Figure 3A, the sidewalls 40, 42 can be vertical. However, in Figure 3B, the sidewalls 40, 42 are inclined, with the angle of the sidewalls preferably between 45° and 90°.

[0026] When arranged as shown in Figure 1, a current path 50 is formed between ohmic contacts 10 and 12, with a slit-shaped recess 16 as described above, as shown in Figure 4A. Another possible specific example is shown in Figure 4B. As previously mentioned, a slit-shaped recess 60 is formed. Furthermore, a linear connection recess 62 is formed adjacent to the outer edge of each of the slit-shaped recesses 60. Both the linear connection recesses 62 and 60 are filled with ohmic metal, such that the slit-shaped recess and the linear connection recess of each ohmic contact are interconnected with multiple channel layers. Now, in addition to the current path 50, an additional current path 64 is also provided between the linear connection recesses 60.

[0027] It should be noted that at least two different specific instances are intended for ohmic contact with the linear connection notches shown in Figure 4B. For example, in the configuration shown in Figure 5A, the ohmic contact layer 66 is above and in contact with the ohmic metal in each of the notches 60 and 62. As previously mentioned, the notches 60 in this row are preferably located at a distance of ≥ 0 µm from the inner edge 68 of the ohmic metal contact layer, such that each of the notches is completely covered by the ohmic metal contact layer 66. Alternatively, as shown in Figure 5B, no ohmic metal contact layer is provided above the notches 60 and 62.

[0028] The ohmic contacts of this invention can be used with multichannel FETs made of various materials. For example, the multichannel FET can be an n-type AlGaN / GaN FET; suitable ohmic metals here include Ti, Al, Mo, and / or Au; for a p-type AlGaN / GaN FET, Pd, Ni, Pt, and / or Au are suitable ohmic metals. As another example, the multichannel FET can be a GaAs / InGaAs FET; suitable ohmic metals here include AuGe, Ni, and / or Au. Another example is an AlGa₂O₃ / Ga₂O₃ FET; suitable ohmic metals here include Ti and Au. Generally, the ohmic metal should be selected to provide the desired contact resistance; this is typically determined empirically.

[0029] It should be noted that although multichannel FETs are described primarily for use with ohmic contacts in this invention, they can be more generally applied to any FET having one or more channel layers. For example, ohmic contacts may be suitable for FETs with channel layers of a single thickness, such as large channels (rather than 2DEGs) uniformly doped with n-type or p-type dopants, where conventional alloyed ohmic contacts from the top surface cannot reach the entire channel layer. MESFETs (Metal-on-Semiconductor Field-Effect Transistors) are an example.

[0030] A similar method can be applied to the latest ohmic "regrown" ohmic contact technology. Here, instead of forming contacts by depositing metal, regrown materials such as n+ GaN are directly deposited on the sidewalls of the multichannel using methods such as MBE (molecular beam epitaxy) or MOCVD (metal-organic chemical vapor deposition). This is shown in Figures 6A and 6B. In Figure 6A, ohmic source contacts 70 and ohmic drain contacts 72 are formed on the multichannel FET 74 using regrown material 76 on a wafer 78 on which the multichannel FET resides. The regrown material 76 laterally contacts the sidewalls of each channel layer 79 of the multichannel FET.

[0031] A preferred embodiment of this concept is shown in Figure 6B. Here, the regrown material 82 has an inner edge 84 perpendicular to the top surface of the wafer 86 on which the FET resides, and the inner edge contacts the sidewall of each channel layer 88, wherein the inner edge 84 has a corrugated shape. The corrugated structure increases the total contact perimeter in two dimensions, thereby reducing the contact resistance of the gate width of each transistor. The length, width, and shape of the corrugated structure are preferably optimized based on the surface resistance of the material and the lateral contact resistance between the regrown material and the channel to minimize the total contact resistance.

[0032] Examples of suitable regeneration materials for various FET types are as follows: - n-type AlGaN / GaN FET: n+ GaN - p-type AlGaN / GaN FET: p+ GaN - n-type AlGaO3 / Ga2 O3 FET:n+ Ga2 O3

[0033] As mentioned above, for the slit notch method, the regenerated material method described in this paper can be more generally applied to any FET with one or more channel layers.

[0034] Compared to previous techniques, the "slit" and "regeneration" methods provide significantly reduced contact resistance for multiple channels by (1) allowing ohmic metal or regenerated material to directly contact multiple channels simultaneously and (2) increasing the contact periphery by introducing slit / corrugated structures.

[0035] A possible method for forming ohmic contacts using slit-shaped notches as described herein is shown in Figure 7. In step 90, slit-shaped notches are etched in a wafer on which a multi-channel FET is fabricated. Each notch is etched to a depth at least equal to the depth of the lowest channel layer of the FET. The notches are linearly aligned with each other, and this row of notches is oriented perpendicular to the current flow direction between the source and drain of the FET. In step 92, ohmic metal is deposited in and on the sidewalls of each of the slit-shaped notches, thereby making ohmic contact with each of the multiple channel layers.

[0036] As appropriate, in step 94, a linear connection notch adjacent to the outer edge of each of the slit-shaped notches (as shown in Figures 4B, 5A, and 5B) is etched. If the linear connection notch has been etched, ohmic metal is also deposited in the linear connection notch, such that the ohmic metal interconnects the slit-shaped notch and the linear connection notch with the multiple channel layers (step 96).

[0037] Another optional step is shown in step 98: an ohmic metal contact layer is deposited on the top surface of the wafer, the ohmic metal contact layer being above and in contact with the ohmic metal in each of the notches (as shown in Figures 1 and 2). According to the invention, any one of steps 94 / 96 or step 98 may be performed, both of them may be performed, or neither may be performed.

[0038] The etching step is preferably performed by dry etching, such as reactive ion etching (RIE) or inductively coupled plasma etching (ICP-RIE). Ohmic metal deposition is preferably included in a single process step by sequentially vaporizing or sputtering the ohmic metal. As previously noted, the sidewalls of the notch may be tilted, with the angle between 45° and 90°. The etching and metal deposition steps are preferably performed before the formation of the FET's gate.

[0039] A possible method for forming ohmic contacts using a regenerated material as described herein is illustrated in Figure 8. In step 100, a multichannel FET is etched to expose the sidewalls of each channel layer. In step 102, a regenerated material, such as n+ GaN, is directly deposited such that the regenerated material is laterally deposited toward the sidewalls of each of the contact channel layers. Optionally (and preferably), in step 104, the inner edge of the regenerated material is set to a corrugated shape. As noted above, the regenerated material is preferably deposited using MBE or MOVCD.

[0040] The ohmic contacts of this invention in multichannel FETs can be used in a variety of applications. For example, power amplifier MMICs with high output power, low-noise amplifier MMICs with high linearity, RF switch MMICs with low insertion loss and high isolation, and power switching transistors with low dynamic on-resistance and breakdown voltage are just some of the possible applications.

[0041] The specific examples of the invention described herein are illustrative, and many modifications, variations, and rearrangements can be readily conceived to achieve substantially equivalent results, all of which are intended to be embodied within the spirit and scope of the invention as defined in the appended claims.

[0042] 10, 12: Ohmic contacts 14,74: Multichannel FET 16,60: Slit-shaped notch / notch 18,78,86: Wafers 20: Lowest Channel Layer 22, 32, 66: Ohmic metal contact layer 24,68,84: Inner edge 26: Outer edge 40, 42: Sidewall 50: Current path 62: Linear connection notch 64: Additional Current Path 70: Ohmic source contact 72: Ohmic drain contact 76,82: Regeneration materials 79, 88: Channel Layer 90: Steps 92: Steps 94: Steps 96: Steps 98: Steps 100: Steps 102: Steps 104: Steps A-A', B-B': Cross-section lines W1: Associated width W2: Associated common width

Claims

1. An ohmic contact for a FET, comprising: a regenerated material on a wafer on which a FET is disposed, the FET having one or more channel layers, the regenerated material laterally contacting the sidewalls of each channel layer of the FET.

2. The ohmic contact of claim 1, wherein the regrown material has an inner edge perpendicular to the top surface of the wafer and in contact with the sidewalls of the one or more channel layers, the inner edge having a corrugated shape.

3. An ohmic contact for a multichannel FET, comprising: a regenerated material on a wafer on which a multichannel FET is disposed, the regenerated material laterally contacting the sidewalls of each channel layer of the multichannel FET.

4. The ohmic contact of claim 3, wherein the regrown material has an inner edge perpendicular to the top surface of the wafer and in contact with the sidewall of the channel layer, the inner edge having a corrugated shape.

5. The ohmic contact of claim 3, wherein the multichannel FET is an n-type AlGaN / GaN FET and the regrown material is n+GaN, or the multichannel FET is a p-type AlGaN / GaN FET and the regrown material is p+GaN, or the multichannel FET is an n-type AlGaO3 / Ga2O3 FET and the regrown material is n+Ga2O3.

6. A method of forming an ohmic contact for a multichannel FET, comprising: etching layers of the multichannel FET to expose the sidewalls of each channel layer; and directly depositing a regenerated material such that the regenerated material laterally contacts the sidewall of each of the channel layers.

7. The method of claim 6, wherein the regenerated material has an inner edge perpendicular to the top surface of the wafer and in contact with the sidewall, the inner edge having a corrugated shape.

8. The method of claim 6, wherein the direct deposition step is performed using molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOVCD).

9. The method of claim 6, wherein the multichannel FET is an n-type AlGaN / GaN FET and the regrown material is n+GaN, or the multichannel FET is a p-type AlGaN / GaN FET and the regrown material is p+GaN, or the multichannel FET is an n-type AlGaO3 / Ga2O3 FET and the regrown material is n+Ga2O3.

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