Electronic circuit and method of operating electronic circuit

Abstract

This invention provides an electronic circuit and method. The electronic circuit includes: an in-phase (I) quadrature (Q) amplifier, comprising an I-series branch and a Q-series branch, the IQ amplifier being configured to receive differential input and control signals, controlling the gate voltages in the I-series branch and the Q-series branch based on the control signals, generating an I output signal using the I-series branch and a Q output signal using the Q-series branch; and a quadrature coupler, configured to perform quadrature summation of the I output signal and the Q output signal and generate a final phase-shifted output.

Description

Technical Field

[0001] This disclosure is generally related to active phase shifters with reduced power consumption. [Priority]

[0002] This application is based on and claims the priority of U.S. Provisional Patent Application No. 63 / 033,488, filed on June 2, 2020, with the United States Patent and Trademark Office, the entire content of which is incorporated herein by reference.

Background Art

[0003] Directional communication at millimeter-wave (mm-wave) frequencies is a key enabling technology for deploying fifth generation (5G) cellular technology. Phased arrays are used to implement these directional links.

[0004] Antennas in a phased array can steer the direction of a radiation beam when driven with a specific combination of amplitude and phase. One of the key blocks for implementing such systems is a phase shifter. The goal of a phase shifter is to produce a digitally programmable output phase for a fixed-phase input signal while ensuring that the gain variation in these different phase states is as low as possible. Phase shifter designs can be broadly classified as active and passive phase shifter designs. As the number of antenna elements increases and the phase resolution becomes lower, active phase shifters offer area / integration and loss advantages over passive phase shifters, corresponding to, at the same time, the disadvantage of increased power consumption.

Summary of the Invention

[0005] According to one embodiment, an electronic circuit includes: an in-phase (I) quadrature (Q) amplifier including an I stacked branch and a Q stacked branch, the IQ amplifier configured to receive a differential input and a control signal, control a gate voltage in the I stacked branch and a gate voltage in the Q stacked branch based on the control signal, generate an I output signal using the I stacked branch, and generate a Q output signal using the Q stacked branch; and a quadrature coupler configured to perform a quadrature summation of the I output signal and the Q output signal and generate a final phase-shifted output.

[0006] According to one embodiment, a method includes: receiving a differential input and a control signal using an IQ amplifier including an I stacked branch and a Q stacked branch, controlling a gate voltage in the I stacked branch and a gate voltage in the Q stacked branch based on the control signal, generating an I output signal using the I stacked branch, generating a Q output signal using the Q stacked branch, performing a quadrature summation of the I output signal and the Q output signal using a quadrature coupler, and generating a final phase-shifted output using the quadrature coupler.

Embodiments

[0008] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same elements will be denoted by the same reference numerals in different drawings. In the following description, only specific details such as detailed configurations and components are provided to assist in the overall understanding of the embodiments of the present disclosure. Therefore, it will be apparent to those skilled in the art that various changes and modifications can be made to the embodiments described herein without departing from the scope of the present disclosure. In addition, descriptions of well-known functions and structures are omitted for clarity and conciseness. The terms described below are defined in consideration of the functions in the present disclosure and may vary according to the user, the user's intention, or habit. Therefore, the definitions of the terms should be determined based on the content throughout this specification.

[0009] The present disclosure can have various modifications and various embodiments, and embodiments among the various embodiments will be described in detail below with reference to the accompanying drawings. However, it should be understood that the present disclosure is not limited to the embodiments, but the present disclosure includes all modifications, equivalents, and alternatives within the scope of the present disclosure.

[0010] Although ordinal terms such as first, second, etc. may be used to describe various elements, the structural elements are not limited by such terms. The terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, a first structural element may be referred to as a second structural element. Similarly, a second structural element may also be referred to as a first structural element. As used herein, the term "and / or" includes any and all combinations of one or more related items.

[0011] The terms used herein are only used to describe the various embodiments of the present disclosure, but are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, the singular forms are intended to include the plural forms. In the present disclosure, it should be understood that the terms "comprises" or "has" indicate the presence of features, numbers, steps, operations, structural elements, components, or combinations thereof, and do not exclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, structural elements, components, or combinations thereof.

[0012] Unless otherwise defined, all terms used herein have the same meaning as those understood by those skilled in the art to which the present disclosure pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having the same meaning as the content in the relevant technical field, and should not be interpreted as having an ideal or overly formalized meaning, unless clearly defined in the present disclosure.

[0013] An electronic device according to an embodiment may be one of various types of electronic devices. The electronic device may include, for example, a portable communication device (e.g., a smartphone), a computer, a portable multimedia device, a portable medical device, a camera, a wearable device, or a household appliance. According to an embodiment of the present disclosure, the electronic device is not limited to the electronic devices described above.

[0014] The terms used in the present disclosure are not intended to limit the present disclosure, but are intended to include various changes, equivalents, or substitutions of the corresponding embodiments. Regarding the description of the drawings, like reference numerals may be used to refer to like or related elements. Unless the relevant context clearly indicates otherwise, the singular form of the noun corresponding to an item may include one or more of the things. As used herein, each of the phrases such as "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" may include all possible combinations of the items enumerated together in the corresponding one of the phrases. As used herein, terms such as "first", "second", "primary", and "secondary" may be used to distinguish a corresponding component from another component, but are not intended to limit the component in other aspects (e.g., importance or order). It is intended that, with or without the terms "operatively" or "communicatively", if one element (e.g., a first element) is referred to as "coupled with", "coupled to", "connected with", or "connected to" another element (e.g., a second element), it indicates that the element may be directly (e.g., wired), wirelessly, or via a third element coupled with the other element.

[0015] As used herein, the term "module" may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with other terms, such as "logic", "logic block", "component", and "circuit". A module may be a single integrated component suitable for performing one or more functions, or the smallest unit or part thereof. For example, according to an embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0016] FIG. 1 illustrates a diagram of a conventional active phase shifter 100. The active phase shifter 100 includes an in-phase (I) variable gain amplifier (VGA) “AI” 102, a corresponding impedance matching network (MN) 104, a quadrature (Q) VGA “AQ” 106, a corresponding impedance MN 108, and an I / Q generator summing circuit 110 that receives the outputs of MN 104 and MN 108 and performs quadrature addition.

[0017] Based on the phase range and phase step, different AI:AQ ratios should be implemented to feed into the I / Q generator 110 for quadrature vector summation. There are two requirements for the AI:AQ ratio: (1) 『Arctan (AQ / AI)』 should be close to the target phase value to be generated (i.e., different from the target phase value lower than the phase error target); (2) 『(AI^2 + AQ^2) ^0.5』 should be almost constant in all phase states (i.e., much smaller than the gain error target). Therefore, as shown in FIG. 1, the I VGA 102 and the Q VGA 106 are the same.

[0018] Current systems, methods, and circuits can be implemented in an active phase shifter to reduce power consumption. FIG. 2 illustrates a diagram of an active phase shifter 200 according to an embodiment. The active phase shifter 200 includes a single combined IQ amplifier 202, an MN 204 for the I output, an MN 206 for the Q output, and an I / Q generator summing circuit 208. The IQ amplifier 202 can include a single differential transconductor instead of two separate differential transconductors in the conventional situation as shown in FIG. 1 to generate currents that are wired to separate digitally programmable cascaded branches, thereby generating the required AI:AQ ratio.

[0019] The active phase shifter 200 offers various advantages. The active phase shifter 200 uses a single differential transconductor to generate signal currents that are wired to separate digitally programmable cascaded branches, and the outputs of the digitally programmable cascaded branches serve as inputs to the I / Q generator summing circuit. Since the conventional active phase shifter uses separate amplifiers with two differential transconductors, this topology has lower current consumption while generating the same output amplitude. The cascaded device is segmented and then weighted to achieve 4-bit phase shift in the active phase shifter 200. The conventional active phase shifter is non-segmented, and thus only 3-bit phase shift is achievable.

[0020] The active phase shifter 200 provides reduced power consumption compared to conventional phase shifters. Due to the use of a single differential transconductor, the active phase shifter 200 also has a reduced input gate load / capacitance compared to architectures in which both the I-path and the Q-path are implemented by separate amplifiers. The reduced load results in higher gain / less power consumption during the driving stage. This advantage is significant at mm-wave frequencies, where the gate capacitance can have significant resistive losses due to low-loss lower-level metal / polysilicon gate wiring, especially for larger-width devices. The area required to implement the active phase shifter 200 core is at least 30% smaller than that of a conventional active phase shifter, resulting in a more compact layout and thus improved integration ease.

[0021] The active phase shifter is implemented as a 4-bit 360-degree phase shifter (i.e., 360 / 2^4 = 22.5-degree phase steps). Independent of the choice of architecture for the phase shifter, the I:Q amplitude ratios required for 4-bit phase shifting are 1:0 (0 degrees), 1:0.4 (22.5 degrees), 0.7:0.7 (45 degrees), 0.4:1 (67.5 degrees), and 0:1 (90 degrees).

[0022] For the most efficient use of DC current, the power consumption can be defined by Equation (1) over all different phase states (i.e., (I,Q) pairs, where Imax and Qmax are the maximum amplitudes required for the I-path and Q-path over all phase states). max (abs(I / Imax) + abs(Q / Qmax)) (1)

[0023] For the 4-bit phase shift case, as shown in Table 1, if the I amplitudes and Q amplitudes are summed for 0 / 22.5 / 45 / 67.5 / 90, it can be seen that Equation (1) is 1.4. Table 1 Phase Shift Normalized AI Normalized AQ Arctan(AQ / AI) (AI^2 + AQ^2)^0.5 Normalized(AI + AQ) 0 1 0 0 1 1 22.5 1 0.4 21.8 1.07 1.4 45 0.7 0.7 45 .98 1.4 67.5 0.4 1 68.2 1.07 1.4 90 0 1 90 1 1

[0024] Therefore, if the I current and the Q current are generated via a single differential transconductor and then rewired to two separate I / Q converters based on the desired relative ratio, power reduction is achieved. The current consumption of the active phase shifter 200 can be limited to 1.4X compared to 2X in the case of a conventional design using two separate amplifiers, without sacrificing any gain and still generating the desired phase steps.

[0025] FIG. 3 illustrates a diagram of a 4-bit active phase shifter 300 according to an embodiment. The active phase shifter 300 includes a digital logic block 302 that generates four sets of control signals: I<3:0>, Ibar<3:0>, Q<3:0>, and Qbar<3:0>. I<3:0> and Ibar<3:0> are control signals (e.g., I-based control signals) for the cascaded devices in the I signal path, and Q<3:0> and Qbar<3:0> are control signals (e.g., Q-based control signals) for the cascaded devices in the Q signal path. The active phase shifter 300 includes a single differential transconductor that receives a differential voltage input 303. The I cascade branch 304 generates an I signal output 332, and the Q cascade branch 306 generates a Q signal output 334. The I cascade branch 304 includes a first cascade arm 308 and a second cascade arm 310. The first cascade arm 308 includes a first segmented and weighted cascade transistor 316 and a second segmented and weighted cascade transistor 318. The second cascade arm 310 includes a third segmented and weighted cascade transistor 320 and a fourth segmented and weighted cascade transistor 322. The Q cascade branch 306 includes a first cascade arm 312 and a second cascade arm 314. The first cascade arm 312 includes a first segmented and weighted cascade transistor 324 and a second segmented and weighted cascade transistor 326. The second cascade arm 314 includes a third segmented and weighted cascade transistor 328 and a fourth segmented and weighted cascade transistor 330. In addition, the drain outputs of the segmented and weighted cascade transistor 318 and the segmented and weighted cascade transistor 320 are connected to the differential side of an I output balun having a flipped polarity relative to the segmented and weighted cascade transistor 316 and the segmented and weighted cascade transistor 322. Similarly, the drain outputs of the segmented and weighted cascade transistor 326 and the segmented and weighted cascade transistor 328 are connected to the differential side of a Q output balun having a flipped polarity relative to the segmented and weighted cascade transistor 324 and the segmented and weighted cascade transistor 330. The I cascade branch 304 generates a differential output that is converted into a single-ended I output 332 using a balun, and the Q cascade branch 306 generates a differential output that is converted into a single-ended Q output 334 using a balun. The I output 332 and the Q output 334 are processed by a tuned quadrature coupler 336 that performs a quadrature vector summation to generate a final phase-shifted output.

[0026] As shown in FIG. 3, the active phase shifter 300 receives a differential input signal 303 and a single 4-bit digital control signal PS<3:0> that selects one of 16 possible phase shift states. The digital logic block 302 is used to generate four sets of 4-bit control signals to control the gates of the I-stack transistors and the Q-stack transistors according to the desired phase shift state to be generated. The digital logic block 302 may include a look-up table that contains on / off settings for each of the stack transistors for each of the phase states.

[0027] In each of the I / Q differential stack arms (arms 308 and 310 of the I-stack branch 304 and arms 312 and 314 of the Q-stack branch 306), there are two sets of segmented and weighted stack transistors controlled by I<3:0> / Q<3:0> and Ibar / Qbar<3:0> respectively. For example, the stack transistor 316 is controlled by I<3:0>, the stack transistor 318 is controlled by Ibar<3:0>, the stack transistor 320 is controlled by Ibar<3:0>, and the stack transistor 322 is controlled by I<3:0>. Similarly, the stack transistor 324 is controlled by Q<3:0>, the stack transistor 326 is controlled by Qbar<3:0>, the stack transistor 328 is controlled by Qbar<3:0>, and the stack transistor 330 is controlled by Q<3:0>. Due to the need to generate relative polarity I / Q outputs to achieve a full 360-degree phase shift capability, these two sets of control signals (i.e., I / Ibar and Q / Qbar) are used.

[0028] Each of the stack transistors can be segmented and weighted (4:3:2:1) to generate the required relative I:Q ratio. If, at the same time, the same number of two sets of stacked devices controlled by I / Q and Ibar / Qbar are turned on, then there is no net output signal because the signal currents are canceled in the primary winding of the transformer connected to the drains of the stack transistors. This cancellation of a portion of the signal current is used for the 0 / 90 / 180 / 270-degree phase states, where only I or Q (or I or Q with inverted polarity) signals are required at the output.

[0029] FIG. 4 illustrates a flowchart 400 of a 4-bit active phase shifter according to an embodiment. At step 402, the active phase shifter receives a differential input and four control signals. The active phase shifter can receive the differential input as a differential voltage input (which is converted to a current by a differential transconductor) and the 4-bit control signal. The differential voltage input can be converted to a current by a differential transconductor, and the 4-bit control signal can be converted (e.g., by the digital block 302) into a derived set of four 4-bit control signals I<3:0>, Ibar<3:0>, Q<3:0>, and Qbar<3:0>, as described above.

[0030] At step 404, the active phase shifter sets a control signal to control the cascode transistors in the cascode arms. The control signal can control the gates of the cascode transistors in the I / Q differential cascode arms. The gates are controlled according to the desired phase shift setting given by a 4-bit control input. Each of the I / Q cascode branches has two arms, and each of the two arms can include two cascode transistors that can be further segmented and weighted. In the first cascode arm of the I cascode branch, the gate of the first segmented and weighted cascode transistor can be set by I<3:0>, and the gate of the second segmented and weighted cascode transistor can be set by Ibar<3:0>. In the second cascode arm of the I cascode branch, the gate of the third segmented and weighted cascode transistor can be set by Ibar<3:0>, and the gate of the fourth segmented and weighted cascode transistor can be set by I<3:0>. The drain outputs of the second segmented and weighted cascode transistor and the third segmented and weighted cascode transistor can be connected to the differential side of the I output balun that has a reversed polarity relative to the drain outputs of the first segmented and weighted cascode transistor and the fourth segmented and weighted cascode transistor. In the first cascode arm of the Q cascode branch, the gate of the first segmented and weighted cascode transistor can be set by Q<3:0>, and the gate of the second segmented and weighted cascode transistor can be set by Qbar<3:0>. In the second cascode arm of the Q cascode branch, the gate of the third segmented and weighted cascode transistor can be set by Qbar<3:0>, and the gate of the fourth segmented and weighted cascode transistor can be set by Q<3:0>. The drain outputs of the second segmented and weighted cascode transistor and the third segmented and weighted cascode transistor can be connected to the differential side of the Q output balun that has a reversed polarity relative to the drain outputs of the first segmented and weighted cascode transistor and the fourth segmented and weighted cascode transistor.

[0031] At step 406, the active phase shifter generates an I output signal using the I cascode branch and a Q output signal using the Q cascode branch based on the outputs from the cascode transistors. At step 408, the active phase shifter performs an orthogonal vector summation of the I output signal and the Q output signal (using an I / Q generator / summing circuit) to generate the final desired phase-shifted output signal. At step 410, the active phase shifter generates the final phase-shifted output using an orthogonal coupler.

[0032] As an additional or alternative embodiment, given the phase shifter step size, different relative weightings of the cascode transistors are possible, resulting in slightly different systematic phase errors in the phase states.

[0033] Another additional or alternative embodiment includes different segmentation and weighting of the cascaded transistors based on different target I:Q weighting ratios required to achieve higher or lower phase step sizes. The concept of using a single combined I / Q amplifier core is possible, but the power saving advantages may be different from those of a 4-bit active phase shifter.

[0034] FIG. 5 illustrates a block diagram of an electronic device 501 in a network environment 500 according to an embodiment. Referring to FIG. 5, the electronic device 501 in the network environment 500 may communicate with another electronic device 502 via a first network 598 (e.g., a short-range wireless communication network), or communicate with another electronic device 504 or a server 508 via a second network 599 (e.g., a long-range wireless communication network). The electronic device 501 may also communicate with the electronic device 504 via the server 508. The electronic device 501 may include a processor 520, a memory 530, an input device 550, a sound output device 555, a display device 560, an audio module 570, a sensor module 576, an interface 577, a haptic module 579, a camera module 580, a power management module 588, a battery 589, a communication module 590, a subscriber identification module (SIM) 596, or an antenna module 597. In one embodiment, at least one of the components (e.g., the display device 560 or the camera module 580) may be omitted from the electronic device 501, or one or more other components may be added to the electronic device 501. In one embodiment, some of the components may be implemented as a single integrated circuit (IC). For example, the sensor module 576 (e.g., a fingerprint sensor, an iris sensor, or an illuminance sensor) may be embedded in the display device 560 (e.g., a display).

[0035] The processor 520 may execute software (e.g., program 540) to control at least one other component (e.g., a hardware or software component) of the electronic device 501 coupled to the processor 520, and may perform various data processing or calculations. As at least part of the data processing or calculation, the processor 520 may load commands or data received from another component (e.g., the sensor module 576 or the communication module 590) in the volatile memory 532, process the commands or data stored in the volatile memory 532, and store the resulting data in the non-volatile memory 534. The processor 520 may include a main processor 521 (e.g., a central processing unit (CPU) or an application processor (AP)) and an auxiliary processor 523 (e.g., a graphics processing unit (GPU), an image signal processor (ISP), a sensor aggregator processor, or a communication processor (CP)), and the auxiliary processor 523 may operate independently of the main processor 521 or in combination with the main processor 521. Additionally or alternatively, the auxiliary processor 523 may be adapted to consume less power than the main processor 521, or to perform specific functions. The auxiliary processor 523 may be implemented separately from the main processor 521, or implemented as part of the main processor 521.

[0036] The auxiliary processor 523 may replace the main processor 521 when the main processor 521 is in a non-active (e.g., sleep) state or may control at least some of the functions or states related to at least one of the components of the electronic device 501 (e.g., the display device 560, the sensor module 576, or the communication module 590) together with the main processor 521 when the main processor 521 is in an active state (e.g., executing an application). According to one embodiment, the auxiliary processor 523 (e.g., ISP or CP) may be implemented as part of another component (e.g., the camera module 580 or the communication module 590) that is functionally related to the auxiliary processor 523.

[0037] The memory 530 may store various data used by at least one component of the electronic device 501 (e.g., the processor 520 or the sensor module 576). The various data may include, for example, software (e.g., program 540) and input data or output data for commands related thereto. The memory 530 may include the volatile memory 532 or the non-volatile memory 534.

[0038] The program 540 can be stored as software in the memory 530 and can include, for example, an operating system (OS) 542, middleware 544, or an application program 546.

[0039] The input device 550 can receive commands or data to be used by another component (such as the processor 520) of the electronic device 501 from the outside of the electronic device 501 (such as a user). The input device 550 can include, for example, a microphone, a mouse, or a keyboard.

[0040] The sound output device 555 can output a sound signal to the outside of the electronic device 501. The sound output device 555 can include, for example, a speaker or a receiver. The speaker can be used for general purposes, such as playing multimedia or recording, and the receiver can be used for receiving incoming calls. According to one embodiment, the receiver can be implemented separately from the speaker or implemented as a part of the speaker.

[0041] The display device 560 can visually provide information to the outside of the electronic device 501 (such as a user). The display device 560 can include, for example, a display, a holographic device, or a projector, and control circuitry for controlling the corresponding one of the display, the holographic device, and the projector. According to one embodiment, the display device 560 can include a touch circuit suitable for detecting a touch or a sensor circuit (such as a pressure sensor) suitable for measuring the intensity of a force caused by the touch.

[0042] The audio module 570 can convert sound into an electrical signal and vice versa. According to one embodiment, the audio module 570 can obtain sound via the input device 550 or output sound via the sound output device 555 or headphones of an external electronic device 502, which is directly (such as wired) or wirelessly coupled to the electronic device 501.

[0043] The sensor module 576 can detect the operating state of the electronic device 501 (such as power or temperature) or the environmental state outside the electronic device 501 (such as the state of a user), and then generate an electrical signal or data value corresponding to the detected state. The sensor module 576 can include, for example, a posture sensor, a gyroscope sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0044] The interface 577 may support one or more specified protocols of the electronic device 501 that is to be used to be directly (e.g., wired) or wirelessly coupled to the external electronic device 502. According to one embodiment, the interface 577 may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, a secure digital (SD) card interface, or an audio interface.

[0045] The connection terminal 578 may include a connector through which the electronic device 501 may be physically connected to the external electronic device 502. According to one embodiment, the connection terminal 578 may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0046] The haptic module 579 may convert an electrical signal into a mechanical stimulus (e.g., vibration or movement) or an electrical stimulus that may be recognized by the user via tactile or kinesthetic senses. According to one embodiment, the haptic module 579 may include, for example, a motor, a piezoelectric element, or an electrical stimulator.

[0047] The camera module 580 may capture still images or moving images. According to one embodiment, the camera module 580 may include one or more lenses, an image sensor, an ISP, or a flash.

[0048] The power management module 588 may manage the power supplied to the electronic device 501. The power management module 588 may be implemented as at least part of, for example, a power management integrated circuit (PMIC).

[0049] The battery 589 may supply power to at least one component of the electronic device 501. According to one embodiment, the battery 589 may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0050] The communication module 590 can support establishing a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device 501 and an external electronic device (e.g., the electronic device 502, the electronic device 504, or the server 508), and communicate via the established communication channel. The communication module 590 can include one or more CPs, and the one or more CPs can operate independently of the processor 520 (e.g., the AP) and support direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module 590 can include a wireless communication module 592 (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module 594 (e.g., a local area network (LAN) communication module or a power line communication (PLC) module). The corresponding one of these communication modules can communicate with the external electronic device via the first network 598 (e.g., a short-range communication network, such as BluetoothTM, Wi-Fi Direct, or the Infrared Data Association (IrDA) standard) or the second network 599 (e.g., a long-range communication network, such as a cellular network, the Internet, or a computer network (e.g., a LAN or a wide area network (WAN))). These various types of communication modules can be implemented as a single component (e.g., a single IC), or can be implemented as multiple components (e.g., multiple ICs) separated from each other. The wireless communication module 592 can use the user information (e.g., the international mobile subscriber identity (IMSI)) stored in the user identification module 596 to identify and authenticate the electronic device 501 in a communication network (such as the first network 598 or the second network 599).

[0051] The antenna module 597 can transmit signals or power to the outside of the electronic device 501 (e.g., an external electronic device) or receive signals or power from the outside of the electronic device 501. According to one embodiment, the antenna module 597 can include one or more antennas, and can select at least one antenna suitable for the communication scheme used in the communication network (such as the first network 598 or the second network 599) from them, for example, by the communication module 590 (e.g., the wireless communication module 592). Signals or power can then be transmitted or received between the communication module 590 and the external electronic device via the selected at least one antenna.

[0052] At least some of the components described above may be coupled to each other and communicate signals (e.g., commands or data) therebetween via a peripheral communication scheme (e.g., a bus, general purpose input and output (GPIO), serial peripheral interface (SPI), or mobile industry processor interface (MIPI)).

[0053] According to one embodiment, commands or data may be transmitted or received between the electronic device 501 and the external electronic device 504 via the server 508 coupled to the second network 599. Each of the electronic devices 502 and 504 may be a device of the same type or a different type as the electronic device 501. All or some of the operations to be performed at the electronic device 501 may be performed at one or more of the external electronic device 502, the external electronic device 504, or the external electronic device 508. For example, if the electronic device 501 is to perform a function or service automatically or in response to a request from a user or another device, then instead of or in addition to the electronic device 501 performing the function or service, the electronic device 501 may request that one or more external electronic devices perform at least a part of the function or service. The one or more external electronic devices that receive the request may perform at least a part of the requested function or service or additional functions or additional services related to the request, and pass the result of the performance to the electronic device 501. The electronic device 501 may provide the result as at least part of a reply to the request with or without further processing the result. To this end, techniques such as cloud computing, distributed computing, or master-slave computing may be used.

[0054] An embodiment can be implemented as software (e.g., program 540) including one or more instructions stored in a storage medium (e.g., internal memory 536 or external memory 538) readable by a machine (e.g., electronic device 501). For example, a processor of electronic device 501 can invoke at least one of the one or more instructions stored in the storage medium and execute at least one of the one or more instructions under the control of the processor with or without using one or more other components. Thus, the machine can be operable to perform at least one function according to the at least one invoked instruction. The one or more instructions can include code generated by a compiler or code executable by an interpreter. The machine-readable storage medium can be provided in the form of a non-transitory storage medium. The term "non-transitory" indicates that the storage medium is a tangible device and does not include signals (e.g., electromagnetic waves), but this term does not distinguish between the case where data is stored semi-permanently in the storage medium and the case where data is stored temporarily in the storage medium.

[0055] According to one embodiment, the method of the present disclosure can be included in and provided in a computer program product. The computer program product can be traded between a seller and a buyer as a product. The computer program product can be distributed in the form of a machine-readable storage medium (e.g., compact disc read only memory (CD-ROM)), or distributed online (e.g., downloaded or uploaded) via an application store (e.g., Play StoreTM), or directly distributed between two user devices (e.g., smart phones). If distributed online, at least a part of the computer program product can be temporarily generated or at least temporarily stored in a machine-readable storage medium such as the memory of a manufacturer's server, the server of an application store, or a relay server.

[0056] According to one embodiment, each of the components (e.g., modules or programs) described above can include a single entity or multiple entities. One or more of the components described above can be omitted, or one or more other components can be added. Alternatively or additionally, multiple components (e.g., modules or programs) can be integrated into a single component. In this case, the integrated component can still perform one or more functions of each of the multiple components in the same or similar manner as each of the multiple components performed one or more functions by the corresponding one of the multiple components before integration. Operations performed by a module, program, or another component can be sequential, parallel, repeated, or exploratory, or one or more of the operations can be executed in a different order or omitted, or one or more other operations can be added.

[0057] Although certain embodiments of the present disclosure have been described in the detailed description of the present disclosure, the present disclosure can be modified in various forms without departing from the scope of the present disclosure. Therefore, the scope of the present disclosure should not be determined solely based on the described embodiments, but based on the appended claims and their equivalents.

Brief Description of the Drawings

[0007] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following detailed description in conjunction with the accompanying drawings, in which: FIG. 1 illustrates a diagram of a conventional active phase shifter. FIG. 2 illustrates a diagram of an active phase shifter according to an embodiment. FIG. 3 illustrates a diagram of a 4-bit active phase shifter according to an embodiment. FIG. 4 illustrates a flowchart of a 4-bit active phase shifter according to an embodiment. FIG. 5 illustrates a block diagram of an electronic device in a network environment according to an embodiment.

Claims

1. An electronic circuit, comprising: A digital logic block is configured to generate control signals by querying a lookup table based on a 4-bit digital input. The lookup table contains on / off settings for each of a plurality of cascaded transistors for each phase state. A non-inverting (I) quadrature (Q) amplifier includes an inverting cascade branch and a quadrature cascade branch, each containing the plurality of cascaded transistors. Each of the plurality of cascaded transistors is segmented and weighted to generate a relative inverting:quadrature ratio. The inverting quadrature amplifier is configured to: receive differential input and control signals; control the gate voltages in the inverting cascade branch and the quadrature cascade branch based on the control signals; generate an inverting output signal using the inverting cascade branch; and generate a quadrature output signal using the quadrature cascade branch. And an orthogonal coupler, configured to: perform orthogonal summation of the in-phase output signal and the quadrature output signal; And to generate the final phase-shifted output.

2. The electronic circuit as claimed in claim 1, wherein the in-phase stacked branch comprises a first stacked arm and a second stacked arm.

3. The electronic circuit as claimed in claim 2, wherein the first stacked arm comprises a first stacked transistor and a second stacked transistor, and the second stacked arm comprises a third stacked transistor and a fourth stacked transistor.

4. The electronic circuit of claim 3, wherein the first tandem crystal, the second tandem crystal, the third tandem crystal, and the fourth tandem crystal process the received control signal as an in-phase control signal.

5. The electronic circuit of claim 3, wherein the first tandem transistor, the second tandem transistor, the third tandem transistor, and the fourth tandem transistor are segmented and weighted to produce the relative in-phase:orthogonal ratio.

6. The electronic circuit of claim 1, wherein the orthogonal stacked branch comprises a first stacked arm and a second stacked arm.

7. The electronic circuit of claim 6, wherein the first stacked arm comprises a first stacked transistor and a second stacked transistor, and the second stacked arm comprises a third stacked transistor and a fourth stacked transistor.

8. The electronic circuit of claim 7, wherein the first tandem crystal, the second tandem crystal, the third tandem crystal, and the fourth tandem crystal process the received control signal as an orthogonal control signal.

9. The electronic circuit of claim 7, wherein the first tandem transistor, the second tandem transistor, the third tandem transistor, and the fourth tandem transistor are segmented and weighted to produce the relative in-phase:orthogonal ratio.

10. A method of operating an electronic circuit, the method comprising: A control signal is generated using a digital logic block based on a 4-bit digital input lookup table containing on / off settings for each of a plurality of cascaded transistors for each of the phase states; differential input and control signals are received using a non-inverting (I)-quadrature (Q) amplifier comprising in-phase and quadrature cascade branches, wherein the in-phase and quadrature cascade branches each comprise the plurality of cascaded transistors, each of which is segmented and weighted to generate a relative in-phase:quadrature ratio; gate voltages in the in-phase and quadrature cascade branches are controlled based on the control signals; an in-phase output signal is generated using the in-phase cascade branches; a quadrature output signal is generated using the quadrature cascade branches; a quadrature summation of the in-phase and quadrature output signals is performed using a quadrature coupler; and a final phase-shifted output is generated using the quadrature coupler.

11. The method of claim 10, wherein the in-phase stacked branch comprises a first stacked arm and a second stacked arm.

12. The method of claim 11, wherein the first stacked arm comprises a first stacked transistor and a second stacked transistor, and the second stacked arm comprises a third stacked transistor and a fourth stacked transistor.

13. The method of claim 12, wherein processing the control signal further comprises processing the received control signal as an in-phase control signal using the first tandem crystal, the second tandem crystal, the third tandem crystal, and the fourth tandem crystal.

14. The method of claim 12, wherein the first tandem crystal, the second tandem crystal, the third tandem crystal, and the fourth tandem crystal are segmented and weighted to produce the relative in-phase:orthogonal ratio.

15. The method of claim 10, wherein the orthogonal stacked branch comprises a first stacked arm and a second stacked arm.

16. The method of claim 15, wherein the first stacked arm comprises a first stacked transistor and a second stacked transistor, and the second stacked arm comprises a third stacked transistor and a fourth stacked transistor.

17. The method of claim 16, wherein processing the control signal further comprises processing the received control signal based on orthogonality using the first tandem crystal, the second tandem crystal, the third tandem crystal, and the fourth tandem crystal.

18. The method of claim 16, wherein the first tandem crystal, the second tandem crystal, the third tandem crystal, and the fourth tandem crystal are segmented and weighted to produce the relative in-phase:orthogonal ratio.

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