Method, sturcture, and system for threshold voltage control

Abstract

Methods and systems for depositing a threshold voltage shift layer on a substrate surface are disclosed, as well as structures and apparatus formed by the methods. An exemplary method involves depositing a threshold voltage shift layer on the surface of a substrate using a cyclic deposition process. Threshold voltage shift layers are particularly suitable for metal-oxide-semiconductor field-effect transistors.

Description

Technical Field

[0001] This disclosure generally relates to methods and systems suitable for forming layers on the surface of a substrate, and to structures including layers. More specifically, this disclosure relates to methods and systems for forming a threshold voltage layer that allows control of a metal-oxide-semiconductor field-effect transistor (MOSFET), and the structures formed using such methods and systems. Prior Technology

[0002] Scaling of semiconductor devices (such as complementary metal-oxide-semiconductor (CMOS) devices) has led to significant improvements in the speed and density of integrated circuits. However, conventional device scaling techniques face significant challenges for future technology nodes. For example, one challenge is finding suitable dielectric stacks to form isolation barriers between the gates and channels of field-effect transistors (FETs). A specific problem in this regard is controlling the threshold voltage of the FET.

[0003] The following prior art has been filed: JP3589954 describes an electromagnetic wave detector and an image detector. US9773818 describes a display device having a transparent conductive film and a metal film. US20200052056 describes an organic light-emitting diode (OLED) display device and a method of manufacturing an OLED display device. US8823672 describes a touch panel display device. WO2017171739 describes a transistor gate-channel configuration. WO2006055226 describes a nitrogen-containing field-effect transistor gate stack containing a threshold voltage control layer formed by metal oxide deposition. US2012161126 describes a semiconductor device and a method of manufacturing the same. US9780225 describes a semiconductor device and a method of manufacturing the same.

[0004] Any discussion presented in this section (including discussions of problems and solutions) is included in this disclosure solely for the purpose of providing background context. Such discussion should not be construed as an admission that any or all of the information was known at the time of making this invention or otherwise constitutes prior art. Summary of the Invention

[0005] The present invention can be simplified to describe a series of concepts that will be further detailed below. The present invention is not intended to necessarily identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0006] The various embodiments disclosed herein relate to methods for forming structures including threshold voltage shift layers, to structures and apparatus formed using such methods, and to equipment for performing the methods and / or for forming the structures and / or apparatus. Threshold voltage shift layers can be used in various applications, including work function adjustment layers. Alternatively or concurrently, they can be used as threshold voltage adjustment layers or p-type diode shift layers.

[0007] Cyclic deposition processes may include one or more of an atomic layer deposition process and a cyclic chemical vapor deposition process. Cyclic deposition processes may include thermal processes, i.e., processes that do not use plasma-activated species. In some cases, oxygen reactants may be exposed to a plasma to form activated oxygen reactant species, such as free radicals and / or ions.

[0008] In one embodiment, this document describes a method for depositing a layer for controlling the threshold voltage of a metal-oxide-semiconductor field-effect transistor (MOSFET), the method comprising the steps of: providing a substrate in a reactor chamber, the substrate comprising a surface, the surface comprising a silicon oxide surface and / or a high-k dielectric surface; depositing a threshold voltage shifting layer on the silicon oxide surface and / or the high-k dielectric surface using a cyclic deposition process; wherein the threshold voltage shifting layer comprises gallium and oxygen; wherein the cyclic deposition process comprises: providing a gallium precursor to the reactor chamber; and providing an oxygen reactant to the reactor chamber.

[0009] In some embodiments, the oxygen reactants are selected from the list of the following components: O2, O3, H2O, H2O2, and N2O.

[0010] In some embodiments, the gallium precursor system is selected from the following: gallium diketoates, gallium alkoxides, alkyl gallium, alkyl amide gallium, gallium halide, and gallium hydride.

[0011] In some embodiments, the gallium precursor system is selected from the list of tris(dimethylamine)gallium, gallium(III) acetylacetonate, dimethylgallium isopropanol, gallium chloride, and trimethylgallium.

[0012] In some embodiments, the cyclic deposition process includes a sequence of a water pulse, a gallium precursor pulse, and an ozone pulse.

[0013] In some embodiments, the cyclic deposition process includes a sequence of a water pulse, a gallium precursor pulse, and an oxygen pulse.

[0014] In some embodiments, the cyclic deposition process includes a sequence of an ozone pulse, a gallium precursor pulse, and a water pulse.

[0015] In some embodiments, the cyclic deposition process includes a sequence of an oxygen pulse, a gallium precursor pulse, and a water pulse.

[0016] In some embodiments, the cyclic deposition process includes a sequence of an ozone pulse, a gallium precursor pulse, and an oxygen pulse.

[0017] In some embodiments, the cyclic deposition process includes a sequence of an oxygen pulse, a gallium precursor pulse, and an ozone pulse.

[0018] In some embodiments, the threshold voltage shift layer further comprises indium, and the cyclic deposition process further comprises the step of providing an indium precursor to the reaction chamber.

[0019] In some embodiments, the cyclic deposition process includes a plurality of pulses, each pulse comprising one or more gallium precursor pulses, one or more indium precursor pulses, and one or more oxygen reactant pulses; wherein the gallium precursor is provided to the reaction chamber in one or more gallium precursor pulses, wherein the indium precursor is provided to the reaction chamber in an indium precursor pulse, and wherein the oxygen reactant is provided to the reaction chamber in an oxygen reactant pulse; and wherein the pulses are provided in any of the following sequence: gallium precursor pulse, indium precursor pulse, oxygen reactant pulse; or, indium precursor pulse, gallium precursor pulse, oxygen reactant pulse.

[0020] In some embodiments, the indium precursor system is selected from alkyl indium, indium halide, beta-diketone indium, indium alkoxide, and alkylamide indium.

[0021] In some embodiments, the indium precursor system is selected from the following list: trimethylindium, tri(dimethylamine)indium, triethylindium (TEIn), cyclopentadienylindium, InCl3, 3-(dimethylamine)propyl[dimethylindium], hexafluoroacetoacetone indium, and acetoacetone indium.

[0022] In some embodiments, the threshold voltage shift layer further comprises zinc, and the cyclic deposition process further comprises the step of providing a zinc precursor to the reaction chamber.

[0023] In some embodiments, the zinc precursor system is selected from alkyl zinc compounds, zinc halides, zinc betahidone salts, zinc alkoxides, and zinc alkylamides.

[0024] In some embodiments, the threshold voltage shift layer further comprises tin, and the cyclic deposition process further comprises the step of providing a tin precursor to the reaction chamber.

[0025] In some embodiments, the tin precursor system is selected from alkyltin, tin halide, beta-diketone tin, alkyltin oxide, and alkylamide tin.

[0026] The document further describes a method for depositing a layer for controlling the threshold voltage of a metal-oxide-semiconductor field-effect transistor (MOSFET). The method includes the following steps: providing a substrate in a reactor chamber, the substrate including a surface, the surface including a silicon oxide surface and / or a high-k dielectric surface; depositing a threshold voltage shifting layer on the silicon oxide surface and / or the high-k dielectric surface using a cyclic deposition process; wherein the threshold voltage shifting layer includes tin and oxygen; wherein the cyclic deposition process includes: providing a tin precursor to the reactor chamber; and providing an oxygen reactant to the reactor chamber.

[0027] In some embodiments, the oxygen reactant is selected from the list of the following components: O2, O3, H2O, H2O2, and N2O.

[0028] In some embodiments, the tin precursor system is selected from the following list: beta-diketoxin tin, alkoxide tin, alkyl tin, alkylamide tin, tin halide, organotin alkylane and tin alkylane.

[0029] In some embodiments, the cyclic deposition process includes a sequence of a water pulse, a tin precursor pulse, and an ozone pulse.

[0030] In some embodiments, the cyclic deposition process includes a sequence of a water pulse, a tin precursor pulse, and an oxygen pulse.

[0031] In some embodiments, the cyclic deposition process includes a sequence of an ozone pulse, a tin precursor pulse, and a water pulse.

[0032] In some embodiments, the cyclic deposition process includes a sequence of an oxygen pulse, a tin precursor pulse, and a water pulse.

[0033] In some embodiments, the cyclic deposition process includes a sequence of an ozone pulse, a tin precursor pulse, and an oxygen pulse.

[0034] In some embodiments, the cyclic deposition process includes a sequence of an oxygen pulse, a tin precursor pulse, and an ozone pulse.

[0035] A method for depositing a layer for controlling the threshold voltage of a metal-oxide-semiconductor field-effect transistor (MOSFET) is further described. The method includes the following steps: providing a substrate in a reactor chamber, the substrate including a surface, the surface including a silicon oxide surface and / or a high-k dielectric surface; depositing a threshold voltage shift layer on the silicon oxide surface and / or the high-k dielectric surface using a cyclic deposition process; wherein the threshold voltage shift layer includes zinc and oxygen; and wherein the cyclic deposition process includes: providing a zinc precursor to the reactor chamber; and providing an oxygen reactant to the reactor chamber.

[0036] In some embodiments, the oxygen reactant is selected from the list of the following components: O2, O3, H2O, H2O2, and N2O.

[0037] In some embodiments, the zinc precursor system is selected from the following list: zinc beta-diketoate, zinc alkoxide, alkyl zinc, alkylamide zinc, zinc halide, and zinc hydride.

[0038] In some embodiments, the cyclic deposition process includes a sequence of a water pulse, a zinc precursor pulse, and an ozone pulse.

[0039] In some embodiments, the cyclic deposition process includes a sequence of a water pulse, a zinc precursor pulse, and an oxygen pulse.

[0040] In some embodiments, the cyclic deposition process includes a sequence of an ozone pulse, a zinc precursor pulse, and a water pulse.

[0041] In some embodiments, the cyclic deposition process includes a sequence of an oxygen pulse, a zinc precursor pulse, and a water pulse.

[0042] In some embodiments, the cyclic deposition process includes a sequence of an ozone pulse, a zinc precursor pulse, and an oxygen pulse.

[0043] In some embodiments, the cyclic deposition process includes a sequence of an oxygen pulse, a zinc precursor pulse, and an ozone pulse.

[0044] In some embodiments, the cyclic deposition process includes the step of contacting a substrate with a surface modifier, the surface modifier comprising an alcohol or anhydride.

[0045] In some embodiments, the surface modifier comprises an alcohol selected from methanol, ethanol, and isopropanol.

[0046] In some embodiments, the surface modifier comprises an anhydride selected from formic anhydride and acetic anhydride.

[0047] In some embodiments, the threshold voltage shift layer has a thickness ranging from at least 0.03 nm to at most 1.0 nm.

[0048] In some embodiments, the threshold voltage shift layer is deposited at a temperature of at least 80°C to a maximum of 300°C.

[0049] In some embodiments, the threshold voltage moving layer is deposited under a pressure of at least 1.0 Torr to a maximum of 10.0 Torr.

[0050] In some embodiments, the cyclic deposition process includes a cyclic chemical vapor deposition process.

[0051] In some embodiments, the cyclic deposition process includes a thermal process.

[0052] This paper further describes a structure comprising a threshold voltage shift layer formed according to the method described herein.

[0053] In some embodiments, the structure includes a high-k dielectric layer between the threshold voltage shift layer and the substrate.

[0054] In some embodiments, the threshold voltage shift layer is positioned between the high-k dielectric layer and the substrate.

[0055] In some embodiments, the thickness of the threshold voltage shift layer ranges from at least 0.03 nm to at most 1.0 nm.

[0056] Further, a gate-all-around metal-oxide-semiconductor field-effect transistor comprising the structure described herein is described.

[0057] A system is further described, comprising one or more reaction chambers; a precursor gas source containing a gallium precursor; an oxygen reactant gas source containing an oxygen reactant; an exhaust source; and a controller, wherein the controller is configured to control the flow of gas into at least one of the one or more reaction chambers to form a layer for controlling the threshold voltage of a MOSFET according to the method described herein.

[0058] According to a further exemplary embodiment of the present invention, a structure is formed using the method described herein. The structure may include a substrate and a threshold voltage shift layer formed over one surface of the substrate. The exemplary structure may further include one or more additional layers, such as an additional metal or conductive layer overlying the threshold voltage shift layer and / or one or more insulating or dielectric layers below the threshold voltage shift layer. The structure may be or can form part of a CMOS structure (such as one or more PMOS and NMOS structures) or other device structure.

[0059] According to further embodiments of this disclosure, a device or a portion thereof can be formed using the methods and / or structures described herein. The device may include a substrate, an insulating or dielectric layer, a threshold voltage shift layer overlying the insulating or dielectric layer, and optionally an additional metal layer overlying the threshold voltage shift layer. The device may be, or may form, a portion of, for example, a CMOS device.

[0060] According to further embodiments of this disclosure, a device or a portion thereof can be formed using the methods and / or structures described herein. The device may include a substrate, an interface layer (such as a silicon oxide layer), a threshold voltage shift layer overlying the interface layer, a high-k dielectric layer overlying the threshold voltage shift layer, and optionally an additional metal layer overlying the threshold voltage shift layer. The device may be, or may form, a portion of, for example, a CMOS device.

[0061] Based on further examples of this disclosure, a system for performing the methods described herein and / or for forming a structure, apparatus, or part thereof is disclosed.

[0062] Those skilled in the art will readily understand these and other embodiments from the following detailed description, which has been accompanied by reference to some of the embodiments, and the accompanying drawings. The invention is not limited to any of the specific embodiments disclosed. Simple Explanation of the Diagram

[0063] A more complete understanding of the embodiments disclosed herein can be obtained by referring to the embodiments and the claims when considering the following illustrative drawings. Figure 1 illustrates a method according to an exemplary embodiment of the present disclosure. Figures 2 to 4 illustrate exemplary structures according to embodiments of the present disclosure. Figure 5 illustrates a reactor system according to an additional exemplary embodiment of this disclosure. It should be understood that the elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be exaggerated relative to other elements to help improve the understanding of the illustrated embodiments of the invention. Implementation

[0064] The illustrative descriptions of the methods, structures, apparatuses, and systems provided below are merely illustrative and intended for purposes of explanation only; the following descriptions are not intended to limit the scope of this disclosure or the claims. Furthermore, the listing of multiple embodiments having the stated features is not intended to exclude other embodiments having additional features or other embodiments incorporating different combinations of the stated features. For example, various embodiments are presented as illustrative examples and may be enumerated in the appendix. Unless otherwise noted, the illustrative embodiments or components thereof may be combined or used separately.

[0065] As described in more detail below, various embodiments of this disclosure provide methods for forming structures (such as gate dielectrics or portions thereof) for field-calibrated transistors. For example, exemplary methods can be used to form CMOS devices or portions thereof. However, unless otherwise stated, the invention is not necessarily limited to such examples.

[0066] In this disclosure, "gas" can include materials that are gases, vaporized solids, and / or vaporized liquids at ambient temperature and atmospheric pressure (NTP), and may consist of a single gas or a mixture of gases, depending on the context. Gases other than process gases (i.e., gases not introduced through a gas distribution assembly, other gas distribution device, or the like) can be used, for example, to seal reaction spaces, and may include sealing gases such as rare or inert gases. In some cases, the term "precursor" can refer to a compound that participates in a chemical reaction to form another compound, and in some cases, to a compound that constitutes the membrane matrix or the main framework of the membrane; the term "reactant" may be used interchangeably with the term "precursor." The term "oxygen reactant" can be used to refer to a reactant containing oxygen. The term "inert gas" can refer to a gas that does not participate in a chemical reaction and / or become part of the membrane matrix to a perceptible degree. Exemplary inert gases include helium, argon, and any combination thereof. In some cases, inert gases may include nitrogen and / or hydrogen.

[0067] As used herein, the term "substrate" can refer to any underlying material(s) on which a device, circuit, or film can be formed or on which a film(s) can be formed. A substrate can include bulk materials (such as silicon (e.g., single-crystal silicon)), other group IV materials (such as germanium) or other semiconductor materials (such as group II-VI or III-V semiconductor materials), and can include one or more layers overlying or underlying the bulk material. Further, a substrate can include various features, such as recesses, protrusions, and the like formed within or on at least a portion of a layer of the substrate. For example, a substrate can include a bulk semiconductor material and an insulating or dielectric material layer overlying at least a portion of the bulk semiconductor material. In some embodiments, the surface of the substrate can simultaneously include several materials.

[0068] As used herein, the terms "film" and / or "layer" can refer to any continuous or discontinuous structure and material (such as materials deposited by the methods disclosed herein). For example, films and / or layers can include two-dimensional materials, three-dimensional materials, nanoparticles, or even partial or complete molecular layers, partial or complete atomic layers, or clusters of atoms and / or molecules, or layers composed of isolated atoms and / or molecules. Films or layers may contain materials or layers with pinholes and may be at least partially continuous.

[0069] As used herein, the term "gate all around transistor" can refer to a device including a gate stack, which comprises a gate dielectric and a conductive material surrounding a semiconductor channel region. As used herein, the term "gate all around transistor" can also refer to various device architectures, such as nanosheet devices, fork-shaped devices, vertical field-effect transistors, and stacked device architectures.

[0070] The term "cyclic deposition process" can refer to the process of sequentially introducing precursors (and / or reactants) into a reaction chamber to deposit a layer over a substrate, and includes processing techniques such as atomic layer deposition (ALD), cyclic chemical vapor deposition (cyclic CVD), and hybrid cyclic deposition processes that include ALD components and cyclic CVD components.

[0071] The term "atomic layer deposition" can refer to a vapor deposition process in which deposition cycles (typically multiple consecutive deposition cycles) are performed in a process chamber. When performed using alternating pulses of (multiple) precursor / (multiple) reactive gases and (multiple) purging (e.g., inert carrier) gases, the term atomic layer deposition, as used herein, also refers to processes specified by related terms, such as chemical vapor deposition, atomic layer epitaxy (ALE), molecular beam epitaxy (MBE), gas source MBE, organometallic MBE, and chemical beam epitaxy.

[0072] Typically, in an ALD process, during each cycle, a precursor is introduced into the reaction chamber and chemisorbed onto the deposition surface (e.g., a substrate surface from a previous ALD cycle, consisting of previously deposited material or other materials), forming a monolayer or sub-monolayer of material that is not readily reacting with additional precursors (i.e., a self-limiting reaction). Subsequently, in some cases, reactants (e.g., another precursor or reactive gas) may be introduced into the process chamber to convert the chemisorbed precursor into the desired material on the deposition surface. The reactants may be able to further react with the precursor. Any excess precursor may be removed from the process chamber and / or any excess reactants and / or reaction byproducts may be removed from the reaction chamber during one or more cycles (e.g., during each step of each cycle). Note that, as used herein, an ALD process does not necessarily consist of a series of self-limiting surface reactions.

[0073] As used herein, "gallium precursor" includes gases or materials that can be converted into a gaseous state and can be represented by a chemical formula including gallium.

[0074] As used herein, "indium precursor" includes gases or materials that can be converted into a gaseous state and can be represented by a chemical formula including indium.

[0075] As used herein, "tin precursor" includes gases or materials that can be converted into a gaseous state and can be represented by a chemical formula including tin.

[0076] As used herein, "zinc precursor" includes gases or materials that can be converted into a gaseous state and can be represented by a chemical formula including zinc.

[0077] As used herein, the term "reactant" includes gases or materials that can be converted into a gaseous state and can be used together with one or more of the precursors mentioned herein to form a layer on a substrate. Specifically, this document utilizes oxygen-containing reactants, also known as oxygen reactants. The term "oxygen reactant" can refer to gases or materials that can be converted into a gaseous state and can be represented by a chemical formula including oxygen. In some cases, the chemical formula includes both oxygen and hydrogen. In some cases, the oxygen reactant does not include diatomic oxygen. Exemplary oxygen reactants include H₂O₂, H₂O, O₂, O₃, and N₂O.

[0078] As used in this article, "threshold voltage" refers to the minimum gate voltage required to establish a conductive path between the source and drain terminals of a field-effect transistor.

[0079] The term "threshold voltage shift layer" refers to a layer that can be used in the gate stack of a field-effect transistor (FET) and can change the threshold voltage of the FET. In this document, the term "threshold voltage shift layer" may be equated with similar terms such as threshold voltage adjustment layer, work function adjustment layer, work function shift layer, tunable threshold voltage layer, flat-band voltage adjustment layer, flat-band voltage shift layer, or simply "layer".

[0080] Furthermore, in this disclosure, any two values ​​of a variable may constitute a feasible range of the variable, and any indicated range may include or exclude endpoints. Additionally, any indicated value of the variable (regardless of whether the value is indicated as "about") may refer to an exact value or an approximate value and include equivalent values, and may refer to an average, median, representative value, multiple values, or the like. Further, in some embodiments of this invention, the terms "including," "constituted by," and "having" independently mean "typically or broadly comprising," "comprising," "consisting essentially of," or "consisting of." In some embodiments of this invention, any defined meaning does not necessarily exclude ordinary and conventional meanings.

[0081] The methods and apparatus described herein are applicable to controlling the threshold voltage of field-effect transistors (FETs). Specifically, the methods and apparatus of this invention are particularly applicable to controlling the threshold voltage of n-channel or p-channel FETs, such as n-channel or p-channel metal-oxide-semiconductor (MOSFETs) and n-channel or p-channel gate-all-around (GEO) MOSFETs. Specifically, the methods and apparatus of this invention are particularly applicable to inducing a positive flat-band voltage shift for p-channel MOSFETs. Furthermore, the methods and apparatus of this invention are particularly applicable to inducing a negative flat-band voltage shift for n-channel MOSFETs. Therefore, the methods and apparatus of this invention are particularly applicable to increasing the gate voltage at which a conductive channel is created between the source and drain of a p-MOSFET. Furthermore, the methods and apparatus of this invention are particularly applicable to decreasing the gate voltage at which a conductive channel is created between the source and drain of an n-MOSFET. n-MOSFETs and / or p-MOSFETs may, for example, be included in CMOS-based integrated circuits. In other words, the methods and apparatus of the present invention are particularly suitable for increasing voltage (where a p-MOSFET switches from an off state to an on state at a given voltage) and for decreasing voltage (where an n-MOSFET switches from an off state to an on state at a given voltage). The methods and apparatus of the present invention are particularly suitable for fabricating n- or p-MOSFETs with an all-around gate architecture or similar architecture. Additionally or alternatively, the methods and apparatus of the present invention are particularly useful in the context of systems-on-chip. Advantageously, the currently disclosed method allows for the deposition of a threshold shift layer that contributes only minimally to the equivalent oxide thickness of the gate dielectric stack, while providing a low growth rate and a significant positive threshold voltage shift. Advantageously, the currently disclosed method allows for the deposition of a threshold shift layer with a low impurity content.

[0082] Therefore, this paper describes a method for depositing a layer. The method includes providing a substrate in a reactor chamber. The substrate includes a surface, which comprises a silicon oxide surface and / or a high-k dielectric surface. A threshold voltage shift layer is then deposited on the silicon oxide surface and / or the high-k dielectric surface. Advantageously, the threshold voltage shift layer can be deposited by a cyclic deposition process.

[0083] In some embodiments, the cyclic deposition process includes a plurality of precursor pulses and a plurality of oxygen reactant pulses. It should be understood that precursor pulses and oxygen reactant pulses may be provided alternately. During the precursor pulses, one or more of a gallium precursor, indium precursor, zinc precursor, and tin precursor are provided to the reaction chamber. During the oxygen reactant pulses, oxygen reactant is provided to the reaction chamber.

[0084] In some embodiments, the threshold voltage shift layer comprises gallium and oxygen. In other words, in these embodiments, the threshold voltage shift layer comprises gallium oxide. Furthermore, in these embodiments, the cyclic deposition process includes providing a gallium precursor to the reaction chamber and providing an oxygen reactant to the reaction chamber.

[0085] In one particular embodiment, gallium oxide is deposited by a cyclic deposition process comprising one or more cycles, the cycles including an oxygen reactant pulse, an oxygen reactant flush, a gallium precursor pulse, and a precursor flush. A suitable oxygen reactant includes ozone. A suitable gallium precursor includes tris(dimethylamino)gallium(III) (TDMAGa). The cyclic deposition process can occur at a temperature of at least 150°C to at most 250°C (e.g., at about 200°C). The cyclic deposition process occurs, for example, at a pressure of at least 1.0 Torrile pressure to at most 8.0 Torrile pressure (e.g., at about 4.0 Torrile pressure). Suitably, a continuous flow of inert gas, such as N2, such as, for example, a 325 sccm N2 flow, can be maintained through one or more precursor tubes connected to the reaction chamber. Thus, the inert gas can suitably serve as a purge gas. A precursor tube can refer to a line that delivers one or more precursors or reactants from a precursor or reactant source to the reaction chamber. The oxygen reactant pulse may, for example, last from at least 0.1 s to at most 10.0 s or about 2.0 s. The oxygen reactant rinse may, for example, last from at least 1.0 s to at most 6.0 s, such as about 3.0 s. The gallium precursor pulse may, for example, last from at least 0.5 s to at most 5.0 s, such as about 1.5 s. The precursor rinse may, for example, last from at least 1.0 s to at most 10.0 s, such as about 5.0 s. A cyclic deposition process preferably includes an oxygen reactant pulse as its first step, which may have a different duration than subsequent oxygen reactant pulses. In an exemplary embodiment, such a first oxygen reactant pulse lasts from at least 0.1 s to at most 10.0 s, or about 3.0 s. A first oxygen reactant rinse following the first oxygen reactant pulse may, for example, last from at least 1.0 s to at most 6.0 s.

[0086] The oxygen reactant may comprise an oxygen-containing compound, an oxygen radical, or elemental oxygen. Exemplary oxygen reactants include O₂, H₂O, O₃, H₂O₂, and N₂O. In some embodiments, the method uses a cyclic deposition sequence involving a plurality of alternating precursor pulses and oxygen reactant pulses, wherein the oxygen reactant may vary from pulse to pulse. For example, in some pulses, H₂O may be used as the oxygen reactant, in other pulses, O₂ may be used as the oxygen reactant, and in still other pulses, O₃ may be used as the oxygen reactant. In some embodiments, the oxygen reactant is selected from a list of oxygen, ozone, and water compositions. In some embodiments, the resulting growth rate is less than 1.0 nm per cycle, or less than 0.5 nm per cycle, or less than 0.4 nm per cycle, or less than 0.3 nm per cycle, or less than 0.2 nm per cycle, or less than 0.1 nm per cycle.

[0087] Suitable gallium precursors may be selected from gallium beta diketonates (such as gallium triacetate and tris(2,2,6,6-tetramethyl-3,5-heptadienic acid)gallium(III)), gallium alkoxides, alkyl gallium (such as trimethylgallium or triethylgallium), alkyl acetylamine gallium (such as tri(dimethylacetylamine)gallium, i.e., TDMAGa), gallium halides, and gallium hydrides. For example, gallium precursors may include tri(dimethylacetylamine)gallium, gallium(III)acetate (Ga(acac)3), gallium alkoxides (such as isopropanol dimethylgallium), gallium halides (such as gallium chloride, gallium tribromide, and gallium triiodide), and / or alkyl gallium (such as trimethylgallium (TMGa)). In some embodiments, gallium carboxylates may be used as precursors, such as gallium triacetate or gallium tripropionate.

[0088] In some embodiments, the gallium precursor comprises tris(dimethylamino)gallium dimer and the oxygen reactant comprises O2, H2O, O3, and H2O2 and / or N2O. In some embodiments, the precursor comprises tris(dimethylamino)gallium and the oxygen reactant comprises ozone.

[0089] In some embodiments, the cyclic deposition process includes one to six, one to five, or one to four cycles of a pulse sequence having the following order: water pulse, gallium precursor pulse, ozone pulse, gallium precursor pulse. The gallium precursor may comprise any precursor mentioned herein, such as tris(dimethylamino)gallium.

[0090] In some embodiments, gallium carboxylate, such as gallium triacetate, is used as a gallium precursor, and the co-reactants are selected from a list of components consisting of H₂O, NH₃, O₂, O₃, and H₂O₂.

[0091] In some embodiments, the cyclic deposition process includes one or more cycles of the following pulse sequences in any order: water pulse, gallium precursor pulse, ozone pulse, gallium precursor pulse.

[0092] In some embodiments, the method of forming a threshold voltage shift layer includes one or more of the following pulse sequences: gallium precursor pulse, first oxygen reactant pulse, gallium precursor pulse, and second oxygen reactant pulse. Thus, a gallium oxide threshold voltage shift layer is formed on a substrate. Suitably, the substrate on which the threshold voltage shift layer is deposited includes an interface layer, such as silicon oxide, and the gallium oxide layer is deposited on the interface layer. Suitably, the gallium oxide threshold voltage shift layer may be deposited directly on the interface layer. A high-k dielectric layer may subsequently be deposited on the gallium oxide threshold voltage shift layer. Suitably, the method of forming the threshold voltage shift layer comprises 1 to 16 cycles, 1 to 8 cycles, 1 to 4 cycles, or 1 to 2 cycles of the following pulse sequence: gallium precursor pulse, first oxygen reactant pulse, gallium precursor pulse, and second oxygen reactant pulse. The gallium precursor used for the gallium precursor pulse may comprise alkyl amide gallium, such as tris(dimethylamide)gallium(III). Please note that tris(dimethylamino)gallium(III) can be provided in a dimer form. The first oxygen reactant pulse and / or the second oxygen reactant pulse may use an oxygen-containing oxidant, such as water, ozone, or oxygen. Suitablely, water may be used for the first oxygen reactant pulse. Suitablely, ozone may be used for the second oxygen reactant pulse.

[0093] The threshold voltage shift layer may further comprise indium. Therefore, and in some embodiments, the threshold voltage shift layer further comprises indium. In such embodiments, the cyclic deposition process further includes the step of providing an indium precursor to the reaction chamber. Therefore, an indium gallium oxide-based threshold voltage shift layer can be deposited.

[0094] In some embodiments, the cyclic deposition process includes a plurality of pulses. Each pulse includes one or more gallium precursor pulses, one or more indium precursor pulses, and one or more oxygen reactant pulses. Gallium precursor is supplied to the reaction chamber during one or more gallium precursor pulses, indium precursor is supplied to the reaction chamber during indium precursor pulses, and oxygen reactant is supplied to the reaction chamber during oxygen reactant pulses. The aforementioned pulses may be supplied in any of the following sequences: gallium precursor pulse, indium precursor pulse, oxygen reactant pulse; or indium precursor pulse, gallium precursor pulse, oxygen reactant pulse; or indium precursor pulse, oxygen reactant pulse; gallium precursor pulse, oxygen reactant pulse; or gallium precursor pulse, oxygen reactant pulse, indium precursor pulse, oxygen reactant pulse. In other words, the aforementioned pulses may be supplied to the reaction chamber in any of the following order. A particularly advantageous critical shift layer can be obtained by sequentially feeding gallium and indium precursors into the reaction chamber in any order, followed by a pulse of oxygen reactant into the reaction chamber. This sequence can be performed once, or repeated, for example, 2, 3, 4, 5, 6, or more times to form the critical shift layer. In this invention, which is not limited to theory or any particular mode of operation, it is believed that the improved properties result from a more uniform surface coverage, achieved by interleaving gallium and indium precursors of different sizes, for example, by interleaving larger gallium precursors with smaller indium precursors.

[0095] In some embodiments, the indium precursor is selected from alkyl indium (such as trimethyl indium and triethyl indium), indium halide (such as indium chloride, indium dichloride and indium trichloride), beta-diketone indium (such as indium triacetyl acetone), indium alkoxides and alkylamide indium. Exemplary indium precursors include trimethyl indium (TMIn), TDMAIn, triethyl indium (TEIn), cyclopentadienyl indium (Cp-In), InCl3, 3-(dimethylamine)propyl]dimethyl-indium, indium hexafluoroacetyl acetone (In(hfac)3), and indium acetyl acetone (In(acac)3).

[0096] In some embodiments, the indium precursor comprises trimethylindium and the gallium precursor comprises tri(dimethylamino)gallium.

[0097] In some embodiments, the indium precursor comprises an alkyl indium such as trimethylindium and the gallium precursor comprises a gallium carboxylate such as gallium triacetate. In these embodiments, the cyclic deposition process may suitably comprise a gallium precursor pulse, an oxygen reactant pulse, an indium precursor pulse, and an oxygen reactant pulse in that order. Alternatively or alternatively, such a cyclic deposition process may comprise an oxygen reactant pulse, a gallium precursor pulse, an oxygen reactant pulse, and an indium precursor pulse in that order. Alternatively or alternatively, such a cyclic deposition process may comprise an indium precursor pulse immediately following a gallium precursor pulse, or directly an indium precursor pulse immediately following a gallium precursor pulse, followed by an oxygen reactant pulse.

[0098] In a particular embodiment, InGaOx is deposited by a cyclic deposition process comprising one or more cycles, the cycles including an oxygen reactant pulse, an oxygen reactant flush, a gallium precursor pulse, an indium precursor pulse, and a precursor flush. A suitable oxygen reactant includes ozone. A suitable gallium precursor includes tris(dimethylamino)gallium(III). A suitable indium precursor includes trimethylindium. The cyclic deposition process can be performed at at least 200°C to at most 250°C (e.g., at an environment of about 225°C). The cyclic deposition process can occur, for example, at at least 1.0 Torrile pressure to at most 8.0 Torrile pressure (e.g., at about 4.0 Torrile pressure). Suitably, a continuous inert gas flow, such as an N2 flow, such as, for example, 325 sccm, can be maintained through one or more precursor tubes connected to the reaction chamber. Thus, the inert gas can suitably serve as a purge gas. A precursor tube can refer to a pipeline that transports one or more precursors or reactants from a precursor or reactant source to the reaction chamber. An oxygen reactant pulse can, for example, last from at least 0.1 s to at most 10.0 s, or about 2.0 s. An oxygen reactant flush can, for example, last from at least 1.0 s to at most 6.0 s, or about 3.0 s. A gallium precursor pulse can, for example, last from at least 0.5 s to at most 5.0 s, or about 1.5 s. For example, a precursor pulse can, for example, last from at least 0.5 s to at most 5.0 s, or about 2.0 s. A precursor flush can, for example, last from at least 1.0 s to at most 10.0 s, or about 3.0 s. Preferably, the gallium precursor pulse and the indium precursor pulse follow each other directly without intermediate flushing or oxygen reactant pulses. This can improve the quality of the deposited layer. Furthermore, the cyclic deposition process preferably includes an oxygen reactant pulse as its first step, which may have a duration different from subsequent oxygen reactant pulses. In an exemplary embodiment, such a first oxygen reactant pulse lasts from at least 0.1 s to at most 10.0 s, or about 3.0 s. A first oxygen reactant rinse following the first oxygen reactant pulse may, for example, last from at least 1.0 s to at most 6.0 s.

[0099] In some embodiments, the threshold voltage shift layer further comprises zinc. In these embodiments, the cyclic deposition process further includes the step of providing a zinc precursor to the reaction chamber. Thus, a threshold voltage shift layer containing a GaZnOx layer or an InGaZnOx layer can be formed. In some embodiments, the zinc precursor is selected from alkyl zinc derivatives, zinc halides, zinc betahyaconate derivatives, zinc alkoxide derivatives, and alkylamide derivatives.

[0100] In some embodiments, the threshold voltage shift layer comprises indium, zinc, and oxygen. In other words, in these embodiments, the threshold voltage shift layer comprises indium zinc oxide. Furthermore, in these embodiments, the cyclic deposition process includes providing an indium precursor to the reaction chamber, providing a zinc precursor to the reaction chamber, and providing an oxygen reactant to the reaction chamber. Advantageously, such a layer can be deposited in a cyclic deposition process comprising alternating sequences of precursor pulses and reactant pulses. The precursor pulses comprise providing both zinc and indium precursors to the reaction chamber. The reaction pulses comprise providing reactants to the reaction chamber. Optionally, the precursor pulses and reactant pulses are separated by a rinsing step.

[0101] In some embodiments, a threshold voltage shift layer comprising indium, zinc, and oxygen is deposited using a cyclic deposition process comprising an indium precursor pulse, an oxygen precursor pulse, a zinc precursor pulse, and an oxygen precursor pulse in that order.

[0102] In some embodiments, a threshold voltage shift layer comprising indium, zinc, and oxygen is deposited using a cyclic deposition process comprising the following sequence: a zinc precursor pulse, an oxygen precursor pulse, an indium precursor pulse, and an oxygen precursor pulse.

[0103] In some embodiments, the threshold voltage shift layer further comprises tin. Therefore, indium gallium zinc oxide, indium gallium tin oxide, or gallium tin oxide threshold voltage shift layers can be deposited. In these embodiments, the cyclic deposition process further includes the step of providing a tin precursor to the reaction chamber. In some embodiments, the tin precursor is selected from tin alkyl groups, tin halides, beta-diketone tin groups, alkyltin oxides, and alkylamide tin groups. Exemplary tin precursors include alkylamide tin groups such as tetramethyl(dimethylamide)tin (TDMASn), and tin alkylamine groups such as N,N-tri-butyl-1,1-dimethylethylenediaminestannous(II).

[0104] In some embodiments, the method of the present invention is used to grow an indium gallium zinc oxide threshold voltage shift layer, wherein the indium precursor comprises trimethylindium, the zinc precursor comprises diethylzinc, and the gallium precursor comprises tris(dimethylamino)gallium.

[0105] In some embodiments, the cyclic deposition process includes a sequence of a water pulse, a gallium precursor pulse, and an ozone pulse in a given order. In some embodiments, the cyclic deposition process further includes a tin precursor pulse, a zinc precursor pulse, and / or an indium precursor pulse between the water pulse and the ozone pulse.

[0106] In some embodiments, the cyclic deposition process includes a sequence of a water pulse, a gallium precursor pulse, and an oxygen pulse in a given order. In some embodiments, the cyclic deposition process further includes a tin precursor pulse, a zinc precursor pulse, and / or an indium precursor pulse between the water pulse and the oxygen pulse.

[0107] In some embodiments, the cyclic deposition process includes a sequence of an ozone pulse, a gallium precursor pulse, and a water pulse in a given order. In some embodiments, the cyclic deposition process further includes a tin precursor pulse, a zinc precursor pulse, and / or an indium precursor pulse between the ozone pulse and the water-oxygen pulse.

[0108] In some embodiments, the cyclic deposition process includes a sequence of an oxygen pulse, a gallium precursor pulse, and a water pulse in a given order. In some embodiments, the cyclic deposition process further includes a tin precursor pulse, a zinc precursor pulse, and / or an indium precursor pulse between the oxygen pulse and the water pulse.

[0109] In some embodiments, the cyclic deposition process includes a sequence of ozone pulses, a gallium precursor pulse, and an oxygen pulse in a given order. In some embodiments, the cyclic deposition process further includes a tin precursor pulse, a zinc precursor pulse, and / or an indium precursor pulse between the ozone pulse and the oxygen pulse.

[0110] In some embodiments, the cyclic deposition process includes a sequence of an oxygen pulse, a gallium precursor pulse, and an ozone pulse in a given order. In some embodiments, the cyclic deposition process further includes a tin precursor pulse, a zinc precursor pulse, and / or an indium precursor pulse between the oxygen pulse and the ozone pulse.

[0111] Tin oxide is another material that can be used as a threshold voltage shifting layer. Therefore, another method for depositing a layer for controlling the threshold voltage of a metal-oxide-semiconductor field-effect transistor (MOSFET) is further described. This method includes the step of providing a substrate in a reactor chamber. The substrate includes a surface. The surface includes a silicon oxide surface and / or a high-k dielectric surface. Using a cyclic deposition process, a threshold voltage shifting layer is deposited on the silicon oxide surface and / or the high-k dielectric surface. The threshold voltage shifting layer comprises tin and oxygen. The cyclic deposition process includes providing a tin precursor to the reaction chamber and providing a nitrogen reactant to the reaction chamber.

[0112] In some embodiments, the oxygen reactants are selected from the list of the following compositions: O2, O3, and H2O.

[0113] In some embodiments, the tin precursor system is selected from the following list: beta-diketoxin tin, alkoxide tin, alkyl tin, alkylamide tin, tin halide, organotin alkylane and tin alkylane.

[0114] In some embodiments, the cyclic deposition process includes a sequence of a water pulse, a tin precursor pulse, and an ozone pulse. In some embodiments, the cyclic deposition process includes a sequence of a water pulse, a tin precursor pulse, and an oxygen pulse. In some embodiments, the cyclic deposition process includes a sequence of an ozone pulse, a tin precursor pulse, and a water pulse. In some embodiments, the cyclic deposition process includes a sequence of an oxygen pulse, a tin precursor pulse, and a water pulse. In some embodiments, the cyclic deposition process includes a sequence of an ozone pulse, a tin precursor pulse, and an oxygen pulse. In some embodiments, the cyclic deposition process includes a sequence of an oxygen pulse, a tin precursor pulse, and an ozone pulse.

[0115] In some embodiments, the threshold voltage shift layer comprises indium, tin, and oxygen. In other words, in these embodiments, the threshold voltage shift layer comprises indium tin oxide. Furthermore, in these embodiments, the cyclic deposition process includes providing an indium precursor to the reaction chamber, providing a tin precursor to the reaction chamber, and providing an oxygen reactant to the reaction chamber. Advantageously, such a layer can be deposited in a cyclic deposition process comprising alternating sequences of precursor pulses and reagent pulses. The precursor pulses comprise providing tin and indium precursors to the reaction chamber. The reagent pulses comprise providing reagents to the reaction chamber. Optionally, the precursor pulses and reagent pulses are separated by a rinsing step.

[0116] Zinc oxide is another suitable material for use as a threshold voltage shifting layer. Therefore, another method for depositing a layer for controlling the threshold voltage of a metal-oxide-semiconductor field-effect transistor (MOSFET) is further described. The method includes providing a substrate in a reactor chamber. The substrate includes a surface. The surface includes a silicon oxide surface and / or a high-k dielectric surface. Using a cyclic deposition process, a threshold voltage shifting layer is deposited on the silicon oxide surface and / or the high-k dielectric surface. The threshold voltage shifting layer comprises zinc and oxygen. The cyclic deposition process may include providing a zinc precursor to the reaction chamber and providing a nitrogen reactant to the reaction chamber.

[0117] In some embodiments, the oxygen reactants are selected from the list of the following compositions: O2, O3, and H2O.

[0118] In some embodiments, the zinc precursor system is selected from the following list: zinc beta-diketoate, zinc alkoxide, alkyl zinc, alkylamide zinc, zinc halide, and zinc hydride.

[0119] In some embodiments, the cyclic deposition process includes a sequence of a water pulse, a zinc precursor pulse, and an ozone pulse. In some embodiments, the cyclic deposition process includes a sequence of a water pulse, a zinc precursor pulse, and an oxygen pulse. In some embodiments, the cyclic deposition process includes a sequence of an ozone pulse, a zinc precursor pulse, and a water pulse. In some embodiments, the cyclic deposition process includes a sequence of an oxygen pulse, a zinc precursor pulse, and a water pulse. In some embodiments, the cyclic deposition process includes a sequence of an ozone pulse, a zinc precursor pulse, and an oxygen pulse. In some embodiments, the cyclic deposition process includes a sequence of an oxygen pulse, a zinc precursor pulse, and an ozone pulse.

[0120] In some embodiments, the threshold voltage shift layer comprises tin, zinc, and oxygen. In other words, in these embodiments, the threshold voltage shift layer comprises zinc tin oxide. Furthermore, in these embodiments, the cyclic deposition process includes providing a zinc precursor to the reaction chamber, providing a tin precursor to the reaction chamber, and providing an oxygen reactant to the reaction chamber. Advantageously, such a layer can be deposited in a cyclic deposition process comprising alternating sequences of precursor pulses and reagent pulses. In these embodiments, the precursor pulses comprise providing tin and zinc precursors to the reaction chamber. In such embodiments, the reagent pulses comprise providing reagents to the reaction chamber. Optionally, the precursor pulses and reagent pulses are separated by a rinsing step.

[0121] In some embodiments, the threshold voltage shift layer comprises indium, tin, zinc, and oxygen. In other words, in these embodiments, the threshold voltage shift layer comprises indium tin zinc oxide. Furthermore, in these embodiments, the cyclic deposition process includes providing an indium precursor, providing a zinc precursor to the reaction chamber, providing a tin precursor to the reaction chamber, and providing an oxygen reactant to the reaction chamber. Advantageously, such a layer can be deposited in a cyclic deposition process comprising alternating sequences of precursor pulses and reagent pulses. The precursor pulses comprise providing indium, tin, and zinc precursors to the reaction chamber. The reagent pulses comprise providing reagents to the reaction chamber. Optionally, the precursor pulses and reagent pulses are separated by a rinsing step.

[0122] In some embodiments, the steps of providing precursors to the reaction chamber are performed prior to a surface modification step, in which the substrate is contacted with a surface modifier. Surface modification can activate or deactivate surface states on the substrate, thereby affecting the amount of precursor chemisorbed onto the substrate in subsequent steps of providing the precursor. The surface modification step can be performed at any suitable time, i.e., before any precursor pulse. For example, the surface modification step can be performed before at least one gallium precursor pulse. For example, the surface modification step can be performed before at least one indium precursor pulse. For example, the surface modification step can be performed before at least one zinc precursor pulse. For example, the surface modification step can be performed before at least one tin precursor pulse. This can advantageously reduce the amount of material deposited on the substrate in any given pulse. Therefore, the growth rate of the layer can be reduced, which can lead to improved thickness control in the growth direction and / or reduced compositional variation. Furthermore, performing the surface modification step before some pulses but not before others can be advantageously used for compositional control.

[0123] Therefore, in some embodiments, the process described herein uses a surface modification step, wherein the substrate is contacted with a surface modifier before contacting the substrate with the vapor indium precursor, before contacting the substrate with the gallium precursor, before contacting the substrate with the zinc precursor, and / or before contacting the substrate with the tin precursor. Thus, the active surface states on the substrate are deactivated to form deactivated surface states. It should be understood that the active surface states readily react with the indium precursor, gallium precursor, zinc precursor, and / or one or more tin precursors. Conversely, it should be understood that the deactivated surface states substantially do not react with, or at least to a lesser extent react with, the indium precursor, gallium precursor, zinc precursor, and / or tin precursor.

[0124] In some embodiments, the surface modification step is performed before the substrate is contacted with each precursor. In other words, in some embodiments, the substrate is contacted with a surface modifier before contacting the indium precursor, and before contacting the gallium precursor, the substrate is contacted with a surface modifier before contacting the zinc precursor, and before contacting the tin precursor.

[0125] In some embodiments, the surface modifier may react with OH groups on the substrate surface. Exemplary surface modifiers include alcohols and acid anhydrides. Suitable alcohols include methanol, ethanol, and / or isopropanol. Suitable acid anhydrides include formic anhydride and acetic anhydride.

[0126] In one exemplary embodiment, the method described herein includes forming a layer by cyclically performing the following first sub-cycle, which includes: exposing a substrate having surfaces capped with reactive surface terminals (e.g., having OH-capped surfaces) to a surface modifier that deactivates a portion of the reactive surface terminals. Optionally, the reaction chamber containing the substrate is then rinsed. Next, the surface is exposed to a first precursor (e.g., a zinc precursor, gallium precursor, zinc precursor, or indium precursor). The first precursor reacts substantially only with the active (i.e., non-deactivating) reactive surface terminals. Optionally, the reaction chamber containing the substrate is then rinsed. Subsequently, the substrate is exposed to an oxygen reactant (such as H₂O or O₃), which leads to the regeneration of the reactive surface terminals. Optionally, the reaction chamber containing the substrate is then rinsed. Thus, a layer comprising an oxide of a first element (e.g., zinc oxide, gallium oxide, zinc oxide, or indium oxide) is formed, and its growth rate can be controlled (i.e. reduced) in a suitable manner by the surface modifier. The first sub-loop can be repeated any number of times to achieve the desired layer thickness.

[0127] In another exemplary embodiment, the supercycle further includes a second sub-cycle comprising exposing the substrate to a surface modifier again, which reactivates a portion of the reactive surface terminals. The surface is then exposed to a second precursor (e.g., a zinc precursor, gallium precursor, tin precursor, or indium precursor), which essentially reacts only with the active reactive surface terminals. Optionally, the reaction chamber containing the substrate is then rinsed. Subsequently, the substrate is exposed to a co-reactant (such as H₂O or O₃), which leads to the regeneration of the reactive surface terminals. Optionally, the reaction chamber containing the substrate is then rinsed. This forms a layer comprising a mixture of a first oxide and a second oxide, the growth rate of which can be controlled (i.e., reduced) in a suitable manner by the surface modifier. The composition of the layer can be effectively controlled when the use of the surface modifier is omitted from either the first or second sub-cycle. The first and second sub-cycles can be repeated any number of times to achieve the desired layer thickness. The composition of the layer can be effectively controlled when the use of the surface modifier is omitted from either the first or second sub-cycle.

[0128] In another exemplary embodiment, the cyclic deposition process further includes a third sub-cycle that involves exposing the substrate to a surface modifier, which then deactivates a portion of the reactive surface terminals. The surface is then exposed to a third precursor (e.g., a zinc precursor, gallium precursor, tin precursor, or indium precursor), which reacts only with the activated reactive surface terminals. Optionally, the reaction chamber containing the substrate is then rinsed. Subsequently, the substrate is exposed to a co-reactant (such as H₂O or O₃), which leads to the regeneration of the reactive surface terminals. Optionally, the reaction chamber containing the substrate is then rinsed. Thus, a layer comprising a mixture of a first oxide, a second oxide, and a third oxide is formed, and its growth rate can be controlled (i.e., reduced) in a suitable manner by the surface modifier. The composition of the layer can be effectively controlled when the use of the surface modifier is omitted from one or two sub-cycles selected from the first, second, and third sub-cycles.

[0129] In another exemplary embodiment, the cyclic deposition process further includes a fourth sub-cycle that involves exposing the substrate to a surface modifier, which then deactivates a portion of the reactive surface terminals. The surface is then exposed to a fourth precursor (e.g., a zinc precursor, gallium precursor, tin precursor, or indium precursor), which essentially reacts only with the activated reactive surface terminals. Optionally, the reaction chamber containing the substrate is then rinsed. Subsequently, the substrate is exposed to a co-reactant (such as H₂O or O₃), which leads to the regeneration of the reactive surface terminals. Optionally, the reaction chamber containing the substrate is then rinsed. Thus, a layer comprising a mixture of a first oxide, a second oxide, a third oxide, and a fourth oxide is formed, and its growth rate can be controlled (i.e., reduced) in a suitable manner by the surface modifier. The composition of the layer can be effectively controlled when the use of the surface modifier is omitted from one, two, or three sub-cycles selected from the first, second, third, and fourth sub-cycles.

[0130] In some embodiments, after the substrate has been exposed to the surface modifier, the substrate is simultaneously exposed to two or more precursors.

[0131] In some embodiments, the first sub-loop, the second sub-loop, the third sub-loop, and / or the fourth sub-loop are repeated one or more times before the next sub-loop occurs. In some embodiments, the threshold voltage shift layer has a thickness of at least 0.03 nm to at most 1.0 nm, or at least 0.05 nm to at most 0.5 nm, or at least 0.1 nm to at most 0.2 nm, or at least 0.5 nm to at most 1.0 nm, or at least 0.2 nm to at most 0.5 nm, or at least 0.1 nm to at most 0.2 nm, or at least 0.05 nm to at most 0.1 nm, or at least 0.03 nm to at most 0.05 nm. In some embodiments, the threshold voltage shift layer has a thickness of less than 3.0 nm. In some embodiments, the threshold voltage shift layer has a thickness of less than 2.0 nm. In some embodiments, the threshold voltage shift layer has a thickness of less than 1.0 nm. In some embodiments, the threshold voltage shift layer has a thickness of less than 0.5 nm. In some embodiments, the threshold voltage shift layer has a thickness of less than 0.4 nm. In some embodiments, the threshold voltage shift layer has a thickness of less than 0.3 nm. In some embodiments, the threshold voltage shift layer has a thickness of less than 0.2 nm. In some embodiments, the threshold voltage shift layer has a thickness of less than 0.1 nm. In some embodiments, the threshold voltage shift layer has a thickness of less than 0.05 nm.

[0132] In some embodiments, the threshold voltage shift layer is deposited at a temperature of at least 30°C to at most 450°C, or at least 50°C to at most 400°C, or at least 80°C to at most 300°C, or at least 80°C to at most 150°C, or at least 150°C to at most 200°C, or at least 200°C to at most 250°C, or at least 250°C to at most 300°C.

[0133] In some embodiments, the threshold voltage shift layer is deposited under a pressure of at least 0.1 Torr to a maximum of 20.0 Torr, or at least 1.0 Torr to a maximum of 10.0 Torr, or at least 2.0 Torr to a maximum of 6.0 Torr, or at least 3.0 Torr to a maximum of 5.0 Torr.

[0134] In some embodiments, the MOSFET includes a gate-around structure.

[0135] In some embodiments, the all-around gate includes a semiconductor material covered with a silicon oxide layer. A threshold voltage shift layer is deposited on the silicon oxide layer. The threshold voltage shift layer may be suitably covered by a high-k dielectric layer.

[0136] In some embodiments, the all-around gate structure includes a semiconductor material covered with a silicon oxide layer. The silicon oxide layer is covered by a high-k dielectric layer. A threshold voltage shift layer is deposited on the high-k dielectric layer.

[0137] In some embodiments, the cyclic deposition process includes a cyclic chemical vapor deposition process.

[0138] In some embodiments, the cyclic deposition process includes a thermal process.

[0139] In some embodiments, the cyclic deposition process uses plasma-enhanced deposition techniques. For example, the cyclic deposition process may include plasma-enhanced atomic layer deposition and / or plasma-enhanced chemical vapor deposition.

[0140] A structure is further described, comprising a threshold voltage shift layer formed according to the method disclosed herein.

[0141] In some embodiments, the structure includes a high-k dielectric layer between the threshold voltage shift layer and the substrate. In some embodiments, the structure includes the following layer sequence in the following order: silicon oxide / threshold voltage shift layer / hafnium oxide / titanium nitride. As an alternative to hafnium oxide, another high-k dielectric, such as aluminum oxide or niobium oxide, may also be used. In this configuration, the threshold voltage shift layer may have a thickness, for example, from 0.03 nm to 1.0 nm, for example, from 0.05 nm to 0.5 nm, for example, from about 0.1 nm to 0.2 nm. This configuration is particularly suitable for inducing positive threshold voltage shifts in p-MOSFETs. Furthermore, this configuration is particularly suitable for inducing negative threshold voltage shifts in n-MOSFETs.

[0142] In some embodiments, the structure includes a threshold voltage shift layer between a high-k dielectric layer and a substrate. In some embodiments, the structure includes the following layer sequence in the following order: silicon oxide, hafnium oxide, threshold voltage shift layer, and titanium nitride. The silicon oxide layer may be an interfacial silicon oxide layer formed on a silicon substrate, for example, as a chemical oxide. As an alternative to hafnium oxide, another high-k dielectric, such as aluminum oxide or niobium oxide, may also be used. In this configuration, the threshold voltage shift layer may have a thickness of, for example, 0.03 nm to 1.0 nm, for example, 0.05 nm to 0.5 nm, for example, 0.1 nm to 0.2 nm. This configuration is particularly suitable for inducing positive threshold voltage shifts in p-MOSFETs. Furthermore, this configuration is particularly suitable for inducing negative threshold voltage shifts in n-MOSFETs.

[0143] In some embodiments, the gallium oxide layer has a thickness of less than 0.3 nm.

[0144] A p-channel all-around gate metal-oxide-semiconductor field-effect transistor is further described, comprising the structure according to the present disclosure.

[0145] A further description is provided of an n-channel all-around gate metal-oxide-semiconductor field-effect transistor comprising the structure according to the present disclosure.

[0146] A system is further described, comprising one or more reaction chambers; a precursor gas source containing a gallium precursor; an oxygen reactant gas source containing an oxygen reactant; an exhaust source; and a controller. The controller is configured to control the flow of gas into at least one of the one or more reaction chambers to form a layer for controlling the threshold voltage of a MOSFET (such as an n-channel MOSFET or a p-channel MOSFET) according to the method described herein. The n-channel MOSFET or p-channel MOSFET may, for example, be included in a CMOS-based integrated circuit.

[0147] Referring now to FIG1, a method 100 according to an exemplary embodiment of the present disclosure is illustrated. For example, method 100 can be used to form gate electrode structures suitable for PMOS, NMOS, and / or CMOS devices (such as for use as threshold voltage shift layers in CMOS devices). These layers are particularly suitable as threshold voltage control layers in n-channel or p-channel MOSFETs. However, unless otherwise noted, the method is not limited to such applications.

[0148] Method 100 includes the following steps: providing a substrate in the reaction chamber of a reactor (step 102); and depositing a layer comprising one or more of gallium oxide, tin oxide, indium gallium oxide, and zinc oxide onto the surface of the substrate using a cyclic deposition process (step 104).

[0149] During step 102, a substrate is provided in the reaction chamber. The reaction chamber used during step 102 may be or may include the reaction chamber of a chemical vapor deposition reactor system configured to perform a cyclic deposition process. Alternatively, the reaction chamber used during step 102 may be or may include the reaction chamber of an atomic layer deposition reactor system configured to perform a cyclic deposition process. The reaction chamber may be a stand-alone reaction chamber or part of a clustered device.

[0150] Step 102 may include heating the substrate to a desired deposition temperature within the reaction chamber. In some embodiments disclosed herein, step 102 includes heating the substrate to a temperature of at least 50°C to at most 400°C, or at least 80°C to at most 300°C, or at least 80°C to at most 150°C, or at least 150°C to at most 200°C, or at least 200°C to at most 250°C, or at least 250°C to at most 300°C.

[0151] In addition to controlling the substrate temperature, the pressure inside the reaction chamber can also be adjusted. For example, in some embodiments disclosed herein, the pressure inside the reaction chamber during step 102 can be at least 1.0 Torr to at most 10.0 Torr, or at least 2.0 Torr to at most 6.0 Torr, or at least 3.0 Torr to at most 5.0 Torr.

[0152] During step 104, a layer comprising gallium oxide, tin oxide, indium gallium oxide, and / or zinc oxide is deposited onto the surface of a substrate using a cyclic deposition process. The cyclic deposition process may include cyclic CVD, ALD, or a hybrid cyclic CVD / ALD process. For example, in some embodiments, the growth rate of a particular ALD process may be lower than that of a CVD process. One method to increase the growth rate may be to operate at a deposition temperature higher than that typically used in ALD processes, resulting in certain portions of the chemical vapor deposition process, but still utilizing the sequential introduction of precursors and reactants. This process may be referred to as cyclic CVD. In some embodiments, the cyclic CVD process may include introducing two or more precursors and reactants into a reaction chamber, wherein overlapping time periods may exist between the two or more precursors and reactants in the reaction chamber, resulting in both deposited ALD components and deposited CVD components simultaneously. This is referred to as a hybrid process. According to a further example, a cyclic deposition process may include a continuous flow of reactants / precursors and periodic pulses of precursors or reactants into the reaction chamber. However, preferably, the current method is carried out in ALD mode, i.e., in a mode where precursor pulses and oxygen reactants are separated from each other by rinsing. This minimizes gas-phase reactions. Note that when the precursors under discussion do not readily react with each other in the gas phase, the different precursor pulses do not necessarily need to be separated by rinsing.

[0153] According to some examples disclosed herein, the cyclic deposition process is a thermal deposition process. In such cases, the cyclic deposition process does not include the use of plasma to form activated species for use in the cyclic deposition process.

[0154] Cyclic deposition processes may include (e.g., separately and sequentially) supplying gallium, indium, tin, and / or zinc precursors to the reaction chamber and supplying oxygen reactants to the reaction chamber. Gallium, indium, tin, and / or zinc precursors may include one or more of the precursors mentioned elsewhere herein.

[0155] In the case of a thermal cycling deposition process, the duration of the step of providing oxygen reactants to the reaction chamber can be relatively long to allow the oxygen reactants to react with the precursors or their derivatives. For example, the duration can be greater than or equal to 5 seconds or greater than or equal to 10 seconds, or from at least 1.0 second to at most 50.0 seconds, or from at least 2.0 seconds to at most 20.0 seconds, or from at least 5.0 seconds to at most 15.0 seconds.

[0156] As part of step 104, the reaction chamber may be flushed with a vacuum and / or an inert gas to mitigate the gas-phase reaction between the precursor and reactants and enable partially or fully self-saturated surface reactions (e.g., in the case of ALD). Alternatively or concurrently, the substrate may be moved to contact the first gas-phase oxygen reactant (e.g., the precursor) and the second gas-phase oxygen reactant (e.g., oxygen-containing gas), respectively. Before contacting the substrate with the next reactive chemical, residual chemicals and reaction byproducts (if any) may be removed from the substrate surface or the reaction chamber, such as by flushing the reaction space or by moving the substrate. The reaction chamber may be flushed after the step of providing the precursor to the reaction chamber and / or after the step of providing the oxygen reactant to the reaction chamber.

[0157] In some embodiments of this disclosure, method 100 includes repeating a unit deposition cycle, which includes (1) providing one or more of an indium precursor, a gallium precursor, a tin precursor, and a zinc precursor to a reaction chamber and (2) providing an oxygen reactant to a reaction chamber, wherein a rinsing or moving step may optionally be performed after step (1) and / or step (2). The deposition cycle may be repeated one or more times based on, for example, the desired thickness of the threshold voltage shift layer. For example, if the thickness of the threshold voltage shift layer is less than that desired for a particular application, the steps of providing the precursor to the reaction chamber and providing the oxygen reactant to the reaction chamber may be repeated one or more times. Once the threshold voltage shift layer has been deposited to the desired thickness, the substrate can be subjected to additional processes to form a device structure and / or device.

[0158] In some embodiments, in / above a structure having an aspect ratio (height / width) of more than about 2, more than about 5, more than about 10, more than about 25, more than about 50, more than about 100, or between about 10 and 100 or between about 5 and about 25, the step coverage of layers containing gallium oxide, indium oxide, tin oxide and / or zinc oxide (i.e., threshold voltage shift layers) is equal to or greater than about 50%, or greater than about 80%, or greater than about 90%, or about 95%, or about 98%, or about 99% or greater.

[0159] Figure 2, block a) illustrates a portion 200 of a structure / device according to an additional example of this disclosure. The device or structure 200 includes a substrate 202, a dielectric or insulating material 205, and a layer 208 containing gallium oxide, indium oxide, tin oxide, and / or zinc oxide. In the illustrated example, structure 200 also includes an additional conductive layer 210.

[0160] Substrate 202 may be or may include any of the substrate materials described herein. Dielectric or insulating material 205 may include one or more dielectric or insulating material layers. For example, dielectric or insulating material 205 may include interface layer 204 and a high-k material 206 deposited over interface layer 204. In some cases, interface layer 204 may be absent or may be imperceptibly present. Interface layer 204 may include oxides (such as silicon oxide) that may be formed on, for example, a single-crystal silicon surface of substrate 202 using, for example, a chemical oxidation process or an oxide deposition process. High-k material 206 may be or may include, for example, a metal oxide having a dielectric constant greater than about 7. In some embodiments, the high-k material has a higher dielectric constant than silicon oxide. Exemplary high-k materials include hafnium oxide (HfO 2), tantalum oxide (Ta 2O 5), zirconium oxide (ZrO 2), titanium oxide (TiO 2), hafnium silicate (HfSiOx), aluminum oxide (Al 2O 3) or lanthanum oxide (La 2O 3), or mixtures thereof, and their laminates.

[0161] Figure 2, region b), illustrates part 200 of a structure / apparatus according to an additional example of this disclosure. It is similar to the structure shown in Figure 2, region a), except that the threshold voltage shift layer 208 is located between the interface layer 204 and the high-k material 206.

[0162] The threshold voltage shift layer 208 can be formed according to the method described herein. Since the threshold voltage shift layer 208 is formed using a cyclic deposition process, the concentrations of gallium oxide, indium oxide, tin oxide, and / or zinc oxide and / or other components in the threshold voltage shift layer 208 can vary from the bottom to the top of the threshold voltage shift layer 208, for example, by controlling the amount of gallium, indium, tin, and / or zinc precursors and / or oxygen reactants and / or individual pulse times during one or more deposition cycles. In some cases, the threshold voltage shift layer 208 may have a stoichiometric composition. The effective work function and other properties of the gate stack containing the threshold voltage shift layer 208 can be altered by changing the amount of gallium, indium, tin, zinc, and / or other compounds in the layer or during the deposition cycle.

[0163] The threshold voltage shift layer 208 may include impurities, such as halides, hydrogen, carbon or the like, in amounts alone or in combination, for example, less than 10.0 atomic percent, less than 6.0 atomic percent, less than 4.0 atomic percent, less than 2.0 atomic percent, less than 1.0 atomic percent, less than 0.2 atomic percent, or less than 0.1 atomic percent, or less than 0.05 atomic percent.

[0164] When used to replace layers that may be other than gallium, indium, zinc, and / or tin-aluminum, the threshold voltage shift layer 208 may be relatively thin, for example, less than 0.5 nm thick, or less than 0.4 nm thick, or less than 0.3 nm thick, or less than 0.2 nm thick, or less than 0.1 nm thick, which may be desirable for many applications, including, for example, work function and / or threshold voltage adjustment layers in the gate stack of n-channel or p-channel MOSFETs.

[0165] The effective work function of the gate stack including the threshold voltage shift layer 208 can be > 4.6 eV, > 4.7 eV, > 4.8 eV, > 4.9 eV, > 4.95 eV, or > 5.0 eV. The effective work function of the gate stack can be shifted from about 30 meV to about 400 meV, or from about 30 meV to about 200 meV, or from about 50 meV to about 100 meV using layers containing gallium oxide, indium oxide, tin oxide, and / or zinc oxide as described herein.

[0166] The threshold voltage shift layer 208 can form a continuous film—for example, using method 100—with a thickness of less than < 5 nm, < 4 nm, < 3 nm, < 2 nm, < 1.5 nm, < 1.2 nm, < 1.0 nm, or < 0.9 nm. The layer 208 containing gallium oxide, indium oxide, tin oxide, and / or zinc oxide can be relatively smooth with relatively low particle boundary formation. In some cases, the layer 208 containing gallium oxide, indium oxide, tin oxide, and / or zinc oxide can be amorphous, with a relatively low columnar crystal structure (compared to, for example, TiN). For thicknesses less than 10 nm, the RMS roughness of an example indicative layer 208 containing gallium oxide, indium oxide, tin oxide, and / or zinc oxide can be <1.0 nm, <0.7 nm, <0.5 nm, <0.4 nm, <0.35 nm, or <0.3 nm, or <0.25 nm, or <0.20 nm, or <0.15 nm, or <0.1 nm.

[0167] Alternatively, the threshold voltage shift layer 208 may be thinner and discontinuous than, for example, 1.0 nm, 0.5 nm, 0.3 nm, 0.2 nm, or 0.1 nm. For example, the layer may contain separated islands, gaps, and / or pores. The threshold voltage shift layer 208 may even consist entirely of a plurality of separated atoms and / or atomic clusters.

[0168] The additional conductive layer 212 may include, for example, a metal, such as a refractory metal or the like.

[0169] Figure 3 illustrates another exemplary structure 300 according to an example of the present disclosure. The device or structure 300 includes a substrate 302, a dielectric or insulating material 304, and a threshold voltage shift layer 306. The dielectric or insulating material comprises an interface layer 308 and a high-k dielectric layer 310. Suitable interface layers include silicon oxide. In the illustrated example, structure 300 also includes an additional conductive layer 312. In the illustrated example, the threshold voltage shift layer 306 is deposited on top of the high-k dielectric layer 310. Alternatively, the threshold voltage shift layer 306 may be deposited on top of the interface layer 308, and the high-k dielectric layer 310 may be deposited on top of the threshold voltage shift layer 306.

[0170] In the illustrated example, substrate 302 includes source region 314, drain region 316, and channel region 318. Although illustrated as a horizontal structure, structures and devices according to embodiments of this disclosure may include vertical and / or three-dimensional structures and devices (such as finned FET devices, all-around field-effect transistors, and stacked device architectures).

[0171] Figure 4 illustrates another structure 400 according to an example of this disclosure. Structure 400 is suitable for gate-all-around field-effect transistor (GAA FET) (also known as a side-mounted nanowire FET) device and the like.

[0172] In the illustrated example, structure 400 includes a semiconductor material 402, a dielectric material 404, a threshold voltage shifting layer 406, and a conductive layer 408. The dielectric material suitably comprises an interface layer (e.g., silicon oxide) and a high-k dielectric layer, similar to the layer sequence illustrated in Figures 2 and 3. Structure 400 may be formed over a substrate, including any substrate material described herein.

[0173] In the illustrated example, the threshold voltage shifting layer 406 is deposited on top of the dielectric layer. Alternatively (an embodiment not shown in FIG4), the threshold voltage shifting layer 406 may be deposited on top of the interface layer, and a high-k dielectric layer may be deposited on the threshold voltage shifting layer 406.

[0174] Semiconductor material 402 may include any suitable semiconductor material. For example, semiconductor material 402 may include group IV, group III-V, or group II-VI semiconductor materials. For instance, semiconductor material 402 includes silicon, or more specifically, monocrystalline silicon.

[0175] Figure 5 illustrates a system 500 with additional exemplary embodiments according to this disclosure. System 500 can be used to perform the methods as described herein and / or form structural or apparatus portions as described herein.

[0176] In the illustrated example, system 500 includes one or more reaction chambers 502, precursor gas source 504, oxygen reactant gas source 506, flushing gas source 508, exhaust source 510, and controller 512.

[0177] Reaction chamber 502 may include any suitable reaction chamber (such as an ALD or CVD reaction chamber).

[0178] Precursor gas source 504 may include a container and one or more precursors, alone or mixed with one or more carrier gases (e.g., inert gases), as described herein. Oxygen reactant gas source 506 may include a container and one or more oxygen reactants, alone or mixed with one or more carrier gases, as described herein. As described herein, purge gas source 508 may include one or more inert gases. Although illustrated as having three gas sources 504 to 508, system 500 may include any suitable number of gas sources. Gas sources 504 to 508 may be coupled to reaction chamber 502 via lines 514, 516, 518, each line potentially including a flow controller, valve, heater, and the like.

[0179] The exhaust source 510 may include one or more vacuum pumps.

[0180] Controller 512 includes electronic circuitry and software to selectively operate valves, manifolds, heaters, pumps, and other components included in system 500. Such circuitry and components operate to introduce precursors, oxygen reactants, and purge gases from individual sources 504 through 508. Controller 512 can control the timing of gas pulse sequences, the temperature of the substrate and / or reaction chamber, the pressure within the reaction chamber, and various other operations to provide appropriate operation of system 500. Controller 512 may include control software to electrically or pneumatically control valves to control the flow of precursors, oxygen reactants, and purge gases into and out of reaction chamber 502. Controller 512 may include modules (such as software or hardware components, e.g., FPGAs or ASICs) performing certain tasks. Modules can be advantageously configured to reside on addressable storage media of the control system and configured to perform one or more processes.

[0181] Other configurations of system 500 are possible, including different numbers and types of precursor and oxygen reactant sources and purge gas sources. Furthermore, it will be understood that there are many configurations of valves, conduits, precursor sources, and purge gas sources, which can be used to achieve the objective of selectively feeding gases into reaction chamber 502. Further, as a system schematic, many components have been omitted for ease of illustration, and such components may include, for example, various valves, manifolds, purifiers, heaters, containers, vents, and / or bypasses.

[0182] During operation of reactor system 500, substrates (such as semiconductor wafers (not shown)) are transferred from, for example, a substrate transport system to reaction chamber 502. Once the substrates are transferred to reaction chamber 502, one or more gases (such as precursors, oxygen reactants, carrier gases and / or flushing gases) from gas sources 504 to 508 are introduced into reaction chamber 502.

[0183] The foregoing exemplary embodiments disclosed herein do not limit the scope of the invention, as these embodiments are merely examples of numerous embodiments of the invention, the scope of which is defined by the appended claims and their legal equivalents. Any equivalent embodiments are intended to be within the scope of the invention. In fact, in addition to what is shown and described herein, various modifications to the invention (such as alternatives to the described elements) will be apparent to those skilled in the art from this specification. Such modifications and embodiments are also intended to fall within the scope of the appended claims.

[0184] 100: Method 102, 104: Steps 200: Device or structure 202: Substrate 204: Interface Layer 205: Dielectric or insulating material 206: High-k materials 208: Threshold Voltage Shift Layer 210: Conductive layer 300: Device or structure 302: Substrate 304: Dielectric or insulating material 306: Threshold Voltage Shift Layer 308: Interface Layer 310: High-k dielectric layer 312: Conductive layer 314: Source Region 316: Drainage Zone 318: Passage Area 400: Structure 402: Semiconductor Materials 404: Dielectric material 406: Threshold Voltage Shift Layer 408: Conductive layer 500: System 502: Reaction Chamber 504: Precursor gas source 506: Oxygen reactant gas source 508: Flushing Gas Source 510: Exhaust source 512: Controller 514, 516, 518: Pipelines

Claims

1. A method for depositing a layer for controlling a threshold voltage of a metal-oxide-semiconductor field-effect transistor (MOSFET), the method comprising the steps of: providing a substrate in a reaction chamber, the substrate comprising a surface comprising a silicon oxide surface and / or a high-k dielectric surface; depositing a threshold voltage shifting layer on the silicon oxide surface and / or the high-k dielectric surface using a cyclic deposition process; wherein the threshold voltage shifting layer comprises gallium and oxygen; wherein the cyclic deposition process comprises providing, in the following sequence: providing a first pulse of a gallium precursor to the reaction chamber; providing an oxygen reactant to the reaction chamber; and providing a second pulse of the gallium precursor to the reaction chamber; wherein the gallium precursor is selected from the list of gallium beta-diketones, gallium alkoxides, alkyl gallium, alkylamide gallium, gallium halides, and gallium hydrides, and the oxygen reactant is selected from the list consisting of O2, O3, H2O, H2O2, and N2O.

2. The method as described in claim 1, wherein the gallium precursor system is selected from the list of tris(dimethylamine) gallium, acetoacetone gallium(III), isopropanol dimethyl gallium, gallium chloride and trimethyl gallium.

3. The method as described in claim 1, wherein, The threshold voltage shift layer further comprises indium, and the cyclic deposition process further comprises a step of providing an indium precursor to the reaction chamber.

4. The method of claim 3, wherein the cyclic deposition process includes a plurality of pulses, the pulses comprising one or more gallium precursor pulses, one or more indium precursor pulses, and one or more oxygen reactant pulses; wherein the gallium precursor is provided to the reaction chamber in the one or more gallium precursor pulses, wherein the indium precursor is provided to the reaction chamber in the one or more indium precursor pulses, wherein the oxygen reactant is provided to the reaction chamber in the one or more oxygen reactant pulses; and wherein the pulses are provided in the form of any of the following sequence: - the one or more gallium precursor pulses, the one or more indium precursor pulses, and the one or more oxygen reactant pulses; or - the one or more indium precursor pulses, the one or more gallium precursor pulses, and the one or more oxygen reactant pulses.

5. The method as described in claim 3 or 4, wherein the indium precursor is selected from alkyl indium, indium halide, indium beta-diketoate, indium alkoxide, and indium alkylamide.

6. The method as described in any one of claims 1 to 4, wherein the threshold voltage shift layer further comprises zinc, and wherein the cyclic deposition process further comprises a step of providing a zinc precursor to the reaction chamber.

7. The method as described in claim 6, wherein the zinc precursor is selected from alkyl zinc derivatives, zinc halides, zinc betahyaconate derivatives, zinc alkoxide derivatives, and zinc alkylamide derivatives.

8. The method as described in any one of claims 1 to 4, wherein the threshold voltage shift layer further comprises tin, and wherein the cyclic deposition process further comprises a step of providing a tin precursor to the reaction chamber.

9. The method as described in claim 8, wherein the tin precursor is selected from alkyltin, tin halide, beta-diketoate tin, alkoxide tin, and alkylamide tin.

10. The method as described in any one of claims 1 to 4, wherein the threshold voltage shift layer has a thickness from at least 0.03 nm to at most 1.0 nm.

11. The method as described in any one of claims 1 to 4, wherein the threshold voltage shift layer is deposited at a temperature of at least 80°C to at most 300°C.

12. The method as described in any one of claims 1 to 4, wherein the threshold voltage shift layer is deposited under a pressure of at least 1.0 Torr to at most 10.0 Torr.

13. The method as described in any one of claims 1 to 4, wherein the cyclic deposition process includes a cyclic chemical vapor deposition process.

14. The method as described in any one of claims 1 to 4, wherein the deposition process includes a thermal process.

15. A structure for threshold voltage control comprising a threshold voltage shift layer formed according to the method described in any one of claims 1 to 14.

16. The structure as described in claim 15, comprising a high-k dielectric layer between the threshold voltage shift layer and a substrate.

17. The structure as described in claim 15, wherein the threshold voltage shift layer is located between a high-k dielectric layer and a substrate.

18. A system for threshold voltage control, comprising: one or more reaction chambers; a precursor gas source comprising a gallium precursor; an oxygen reactant gas source comprising an oxygen reactant; an exhaust source; and a controller, wherein the controller is configured to control gas flow into at least one of the one or more reaction chambers to form a layer for controlling a threshold voltage of a MOSFET according to the method described in any one of claims 1 to 14.

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