Progressive envelope tracking with delay compensation

Abstract

This invention discloses an asymptotic envelope tracking (ET) with delay compensation, comprising an ET integrated circuit (IC) (ETIC) that switches between different driver amplifiers with different associated offset voltages based on a tracking signal (e.g., a Vramp) from a baseband transceiver. To ensure that the desired change in offset voltage occurs simultaneously with an input signal at one of the driver amplifiers, a delay can be added to that input signal. By adding this delay to the input of the driver amplifiers and controlling this delay, changes in offset voltage will track changes in the input signal at the driver amplifiers, thus improving the overall efficiency of the ETIC.

Description

Technical Field

[0001] The technology of this invention is generally related to an envelope tracking (ET) radio frequency (RF) front-end circuit. Prior Technology

[0002] Mobile communication devices are becoming increasingly prevalent in providing wireless communication services in today's society. The popularity of these mobile communication devices is partly driven by the numerous functions now implemented on them. The increased processing power in these devices means that mobile communication devices have evolved from mere communication tools into sophisticated mobile multimedia hubs capable of enhancing the user experience.

[0003] Fifth-generation new radio (5G-NR) wireless communication systems are widely regarded as a technological advancement, achieving significantly higher data throughput, improved coverage, enhanced signaling efficiency, and reduced latency compared to existing third-generation (3G) and fourth-generation (4G) communication systems. A 5G-NR mobile communication device typically transmits and receives an RF signal in millimeter-wave (mmWave) radio frequency (RF) spectrum, typically above 6 GHz. It should be noted that RF signals transmitted in the mmWave RF spectrum may be more susceptible to propagation attenuation and interference, which can lead to a significant reduction in data throughput. To help mitigate propagation attenuation and maintain the desired data throughput, 5G-NR mobile communication devices can be configured to use spatial multiplexing schemes such as multiple-input multiple-output (MIMO) and RF beamforming to simultaneously transmit RF signals from multiple antennas. Therefore, 5G-NR mobile communication devices require the use of multiple RF power amplifiers in an RF front-end module (FEM) to amplify the RF signal before feeding it to multiple antennas.

[0004] Envelope tracking (ET) is a power management technique designed to improve the operating efficiency of RF power amplifiers. Specifically, a power amplifier simultaneously amplifies the RF signal based on multiple ET voltages that track a time-varying power envelope. Understandably, the better the ET voltages can track the time-varying power envelope, the higher the operating efficiency of the power amplifier.

[0005] When a small number of resource blocks exist in the FEM, from a power usage perspective, a very robust ET circuit can be over-engineered and inefficient. Various methods have been proposed to improve efficiency, including modulating an offset voltage within one of the conditioning circuits that generates the control signal for the RF power amplifier. There is still room for improvement in this offset voltage modulation. Summary of the Invention

[0006] Embodiments of the present invention relate to asymptotic envelope tracking (ET) with delay compensation. In one exemplary embodiment, an ET integrated circuit (IC) (ETIC) switches between different driver amplifiers with different associated offset voltages based on a tracking signal (e.g., Vramp) from a baseband transceiver. To ensure that the desired change in the offset voltage occurs simultaneously with an input signal at one of the driver amplifiers, a delay can be added to that input signal at the driver amplifiers. By adding this delay to the inputs of the driver amplifiers and controlling this delay, the change in the offset voltage will track the change in the input signal at the driver amplifiers, thereby improving the overall efficiency of the ETIC.

[0007] In one embodiment, an ETIC is provided. The ETIC includes an input configured to receive a VRamp signal from a baseband transceiver. The ETIC also includes a first driver amplifier coupled to a first offset capacitor and a first variable feedback circuit. The ETIC also includes a second driver amplifier coupled to a second offset capacitor, the first variable feedback circuit, and a second variable feedback circuit. The ETIC also includes a controller circuit configured to switch between the first driver amplifier and the second driver amplifier. The controller circuit is also configured to adjust a first delay of a first path extending from a node to the second driver amplifier through the second variable feedback circuit to match a second delay of a second path extending from the node to the second driver amplifier through the controller circuit.

[0008] In another embodiment, a wireless device is provided. The wireless device includes a baseband transceiver configured to generate a VRamp signal. The wireless device also includes an ETIC coupled to the baseband transceiver. The ETIC includes an input configured to receive the VRamp signal. The ETIC also includes a first driver amplifier coupled to a first offset capacitor and a first variable feedback circuit. The ETIC also includes a second driver amplifier coupled to a second offset capacitor, the first variable feedback circuit, and a second variable feedback circuit. The ETIC also includes a controller circuit. The controller circuit is configured to switch between the first driver amplifier and the second driver amplifier. The controller circuit is also configured to adjust a first delay of a first path extending from a node to the second driver amplifier through the second variable feedback circuit to match a second delay of a second path extending from the node to the second driver amplifier through the controller circuit.

[0009] Those skilled in the art will understand the scope of this disclosure and implement its additional forms after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings. Simple Explanation of the Diagram

[0010] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the invention and, together with the description, explain the principles of the invention.

[0011] Figure 1 is a schematic diagram of an exemplary ET radio frequency (RF) front-end circuit having a power amplifier array controlled by an envelope tracking (ET) integrated circuit (IC) (ETIC);

[0012] Figure 2 is a schematic diagram of a wireless device that includes the number of ET RF front-end circuits shown in Figure 1;

[0013] Figure 3 is a block diagram of an asymptotic ETIC that switches between power amplifiers and is based on the input signal vramp offset, while also showing the delay path of the signal affecting Vcc;

[0014] Figure 4 provides a comparison of the contribution of the Vcc control signal from one of the driver amplifiers and one of the RF power amplifiers with one of the offset voltages in an asymptotic ETIC; and

[0015] Figure 5 is a block diagram containing an asymptotic ETIC for a delay element in a driver amplifier, wherein the delay element causes a change in the input of the driver amplifier to align with a change in an offset voltage. Implementation

[0016] Related applications This application claims the right of U.S. Provisional Patent Application No. 63 / 114,200, filed November 16, 2020, the entire contents of which are incorporated herein by reference.

[0017] The embodiments described below illustrate essential information necessary for those skilled in the art to practice these embodiments and depict the best mode of practice. After reading the following description in conjunction with the accompanying drawings, those skilled in the art will understand the concepts of the invention and recognize applications of these concepts not specifically discussed herein. It should be understood that these concepts and applications fall within the scope of the invention and the appended claims.

[0018] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, such elements should not be limited by such terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated items.

[0019] It should be understood that when an element (such as a layer, region, or substrate) is referred to as "located on" or "extending to" another element, the element may be directly located on or directly extended to the other element, or an intermediate element may be present. In contrast, when an element is referred to as "directly located on" or "directly extended to" another element, no intermediate element is present. Similarly, it should be understood that when an element (such as a layer, region, or substrate) is referred to as "located above" or "extending above" another element, it may be directly located above or directly extended above the other element, or an intermediate element may be present. In contrast, when an element is referred to as "directly located above" or "directly extended above" another element, no intermediate element is present. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or an intermediate element may be present. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate element is present.

[0020] Relative terms (such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical") may be used herein to describe the relationship between one element, layer, or region and another element, layer, or region as illustrated in the figures. It should be understood that these terms, as well as those discussed above, are intended to cover different orientations of the device other than those depicted in the figures.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms "a / an" and "the" are intended to include the plural forms as well, unless clearly indicated otherwise. It should be further understood that when the terms "comprises / comprising" and / or "includes / including" are used herein, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0022] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should be further understood that the terms used herein shall be interpreted as having the same meaning as they have in the context of this specification and in the related art, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0023] Embodiments of this invention relate to asymptotic envelope tracking (ET) with delay compensation. In one exemplary embodiment, an ET integrated circuit (IC) (ETIC) switches between different driver amplifiers with different associated offset voltages based on a tracking signal (e.g., a Vramp) from a baseband transceiver. To ensure that the desired change in the offset voltage occurs simultaneously with an input signal at one of the driver amplifiers, a delay can be added to that input signal of the driver amplifiers. By adding this delay to the input of the driver amplifiers and controlling this delay, the change in the offset voltage will track the change in the input signal at the driver amplifiers, and the overall efficiency of the ETIC can be improved.

[0024] Before addressing specific aspects of the present invention, an overview of a transmitter having a radio frequency (RF) front-end circuit is provided in Figures 1 and 2, and a discussion of a conventional progressive ETIC is provided in Figures 3 and 4. An exemplary aspect of the present invention will now be discussed with reference to Figure 5.

[0025] In this regard, FIG1 is a schematic diagram of an exemplary ET RF front-end circuit 10 according to one configuration of the present invention. For example, the ET RF front-end circuit 10 is self-contained in a single-chip system (SoC) or system-in-package (SiP) to provide all the basic functions of an RF front-end module (FEM). Specifically, the ET RF front-end circuit 10 is configured to include an ETIC 12, a target voltage circuit 14, a local transceiver circuit 16, and a number of power amplifiers 18A(1) to 18A(N). The ET RF front-end circuit 10 may also include a number of second power amplifiers 18B(1) to 18B(N). By encapsulating the ETIC 12, the target voltage circuit 14, the local transceiver circuit 16, the power amplifiers 18A(1) to 18A(N) and the second power amplifiers 18B(1) to 18B(N) into an ET RF front-end circuit 10, distance-related distortion in the conventional embodiments described above can be reduced, thus helping to improve the operating efficiency and linearity of the power amplifiers 18A(1) to 18A(N) and 18B(1) to 18B(N).

[0026] ETIC 12 is configured to generate a number of first ET voltages VCCOA-1 to VCCOA-N at a number of first output nodes NA1-1 to NA1-N. ETIC 12 is also configured to generate a second ET voltage VCCDA at a second output node NA2. ETIC 12 generates both the first ET voltages VCCOA-1 to VCCOA-N and the second ET voltage VCCDA based on a time-varying ET target voltage VTGTA (sometimes also referred to as Vramp). For a detailed description of one specific embodiment of ETIC 12 that generates the first ET voltages VCCOA-1 to VCCOA-N and the second ET voltage VCCDA based on the time-varying ET target voltage VTGTA, please refer to U.S. Patent Application No. 17 / 142,507 entitled "ENVELOPE TRACKING POWER MANAGEMENT APPARATUS INCORPORATING MULTIPLE POWER AMPLIFIERS".

[0027] The target voltage circuit 14 is configured to generate a time-varying ET target voltage VTGTA based on an input signal 20, which may be a modulated carrier signal at a millimeter-wave (mmWave) frequency, intermediate frequency (IF), or in-phase / quadrature (I / Q) baseband frequency. In a non-limiting example, the target voltage circuit 14 includes an amplitude detection circuit 22 and an analog lookup table (LUT) 24. The amplitude detection circuit 22 is configured to detect a number of time-varying amplitudes 26 of the input signal 20, and the analog LUT 24 is configured to generate the time-varying ET target voltage VTGTA based on the time-varying amplitudes 26.

[0028] Local transceiver circuit 16 further generates RF signals 62A(1) to 62A(N) and 62B(1) to 62B(N) provided to power amplifiers 18A(1) to 18A(N), 18B(1) to 18B(N), which are controlled by various Vcc signals from ETIC 12. Power amplifiers 18A(1) to 18A(N) may comprise an array of well-known amplifiers 66 and 68. Similarly, power amplifiers 18B(1) to 18B(N) may comprise an array of well-known amplifiers 70 and 72. A coupler circuit 76 may be used to provide a feedback signal 78 to a calibration circuit 74, which helps analog LUT 24 determine a correct VTGTA.

[0029] One or more of the ET RF front-end circuits 10 of Figure 1 can be incorporated into a wireless device (e.g., a smartphone) to help enhance RF performance and user experience. In this regard, Figure 2 is a schematic diagram of a wireless device 100 comprising a number of ET RF front-end circuits 102(1) to 102(K) (which may be any of the ET RF front-end circuits 10 of Figure 1). Common elements between Figures 1 and 2 are shown herein by common element symbols and will not be described again herein.

[0030] The wireless device 100 includes a baseband transceiver 104 separate from any of the ET RF front-end circuits 102(1) to 102(K). The baseband transceiver 104 is configured to generate an input signal 20.

[0031] Each of the ET RF front-end circuits 102(1) to 102(K) is coupled to a first antenna array 106 and a second antenna array 108. The first antenna array 106 includes a number of first antennas 110(1) to 110(N), each coupled to one of antenna ports 64A(1) to 64A(N) and configured to radiate one of RF signals 62A(1) to 62A(N) according to a first polarization (e.g., horizontal polarization). The second antenna array 108 includes a number of second antennas 112(1) to 112(N), each coupled to one of second antenna ports 64B(1) to 64B(N) and configured to radiate one of second RF signals 62B(1) to 62B(N) according to a second polarization (e.g., vertical polarization).

[0032] The ET RF front-end circuits 102(1) to 102(K) can be placed in different locations within the wireless device 100 to help enhance RF performance and improve user experience. For example, some of the ET RF front-end circuits 102(1) to 102(K) can be located on the top edge of one of the wireless devices 100, while some of the ET RF front-end circuits 102(1) to 102(K) can be located on the bottom edge of one of the wireless devices 100.

[0033] It should be understood that the ET RF front-end circuit is used to improve the efficiency of the main power amplifier array used for signal transmission. That is, by providing the power amplifier with "just enough" voltage (Vcc) when it needs it, the power amplifier does not "waste" unnecessary power in the worst case (static Vcc level). For example, if the power amplifier only needs 3 volts (3V) to boost the transmit signal to the required level, but Vcc is 5V, then the power amplifier is being supplied with unused and wasted excess voltage. By using ET, Vcc is controlled and the efficiency of the power amplifier is improved.

[0034] While using an ET does improve system efficiency by increasing the efficiency of the power amplifier, an ETIC may introduce some inefficiencies. Improving transceiver efficiency is generally considered desirable to aid in battery management for mobile computing devices. One method to improve the efficiency of an ETIC is through the use of a progressive ET, as better explained with reference to Figures 3 and 4.

[0035] In this regard, Figure 3 is a block diagram of ETIC 12 using a progressive ET. A target voltage (V TGTA, also referred to as Vramp) is provided to ETIC 12 and received by a multiplexer 130. The target voltage may initially be a differential signal, but the multiplexer 130 may convert the signal into a single-ended signal as desired. The multiplexer 130 may be coupled to a bandpass filter 132, which blocks signals at frequencies other than the desired frequency. The bandpass filter 132 is coupled to an anti-aliasing filter (AAF) 134 that generates the Vcc target. The Vcc target is provided to a first driver amplifier 136 (sometimes referred to as a horizontal amplifier H). The output of the first driver amplifier 136 may be coupled to a ground 140 through a switch 138. When the switch 138 is open (i.e., not grounded), the first driver amplifier 136 outputs an amplified signal V parampH and is coupled to a first offset capacitor 142. The first offset capacitor 142 also acts as a DC block, allowing only AC signals to pass through. The first offset capacitor 142 is coupled to an output node 144. The first offset capacitor 142 can be quite large, for example, approximately 2 to 3 microfarads. A control signal Vcc is obtained at the output node 144. The output node 144 is also coupled to a first feedback circuit 146, which is coupled to a first driver amplifier 136. The control signal Vcc is similar to the signals VCCOA-1 to VCCOA-N in Figure 1.

[0036] Continuing to refer to FIG. 3, the band-pass filter 132 is also coupled to a multiplier 148 that multiplies Vcc target by a factor K, where 0 < K < 1. K determines the percentage of Vcc derived from the first driver amplifier 136 relative to the voltage provided at the first offset capacitor 142, as will be better explained below. The value K*Vcc target is provided to an adder 150, which adds K*Vcc target to a signal Voffset0Target from a digital-to-analog converter (DAC) 152 to form a signal Voffset Target. The adder 150 is coupled to a controller circuit 154. The controller circuit 154 has additional inputs from multiplexers 156, 158, 160 and provides an output to a multi-level boost charge pump 162. The multi-level boost charge pump 162 can use one or more capacitors 164(1) to 164(M) to provide charge boosts at different levels. The multi-level boost charge pump 162 can be connected to a voltage source such as Vbat. The multi-level boost charge pump 162 can also receive a signal V batampH (voltage battery amplifier level) and a feedback signal Vccfb from the output node 144. The multi-level boost charge pump 162 can be coupled to a power inductor 166 through a switching circuit 168. The power inductor 166 is coupled to the output node 144 to provide a basic DC power level (although with some ripple) at the output node 144. The multiplexer 158 receives the voltage signals V parampH and V parampL and selects between them. The multiplexer 160 receives the current signals I paramp_sense_H and I paramp_sense_L and selects between them. The respective voltage and current values can be manipulated within the controller circuit 154 to help estimate a load seen at the output node 144.

[0037] Continuing to refer to FIG. 3, the AAF 134 is also coupled to a second driver amplifier 170 (sometimes referred to as a vertical amplifier, although the L is used because V might be confused with voltage). The second driver amplifier 170 includes an output coupled to ground 140 through a switch 172. When the switch 172 is open (e.g., not grounded), the second driver amplifier 170 generates a signal VparampL. In use, only one of the switches 138 or 172 is open at a time. The second driver amplifier 170 is coupled to a second offset capacitor 174, which is coupled to the output node 144. The output node 144 is also coupled to a second feedback circuit 176, which is coupled to an input of the second driver amplifier 170. The second offset capacitor 174 is relatively smaller than the first offset capacitor 142 and can be (e.g.) about 20 to 40 nanofarads, and thus CoffsetL << CoffsetH. The reduced capacitance of the second offset capacitor 174 may cause an increase in the ripple voltage, but this can be offset by using a lower Vbatamp voltage. Both the first and second driver amplifiers 136, 170 receive the input signals Vbatamp1 and Vbatamp2.

[0038] In operation, the controller circuit 154 uses the switches 138, 172 to control a signal path from the AAF 134 through one or the other of the driver amplifiers 136, 170 to the output node 144. It should be understood that the Vcc at the output node 144 is the sum of an offset voltage generated by the offset capacitors 142, 174 and the Vparamp from the respective driver amplifiers 136, 170. This sum is preferably illustrated in FIG. 4, where an output 400 of the second driver amplifier 170 is added to an offset voltage 402 from the second offset capacitor 174 to generate the Vcc signal 404. Thus, different values of the offset capacitors 142, 174 generate different offset voltages. Additionally, the choice of a particular K allows the selection of the ratio of the voltage provided by the driver amplifiers 136, 170 relative to the offset capacitors 142, 174. A progressive ETIC 12 takes advantage of this difference by switching between the driver amplifiers 136, 170 based on which is more effective. For more details on a progressive ETIC, the interested reader may refer to U.S. Patent No. 11,018,627, which is incorporated herein by reference in its entirety.

[0039] While the ability to tune Vcc by varying the offset voltage helps improve the efficiency of the power amplifiers 18A(1) to 18A(N) and 18B(1) to 18B(N), this solution introduces other problems. Specifically, the signal entering AAF 134 drives both driver amplifiers 136 and 170 and is also supplied to the controller circuit 154. As illustrated in Figure 3, these two paths do not have the same length and therefore have different delays associated with them. The delay through driver amplifiers 136 and 170 is shown in Figure 3 as Vcc_to_Vcctargetv_delay. Therefore, the change in Vcc target from bandpass filter 132 propagates to output node 144 relatively quickly because only three components (AAF 134, driver amplifiers 136 and 170, and offset capacitors 142 and 174) are located between bandpass filter 132 and output node 144. In contrast, an offset loop delay (shown by the dashed line in Figure 3) passes through multiplier 148, adder 150, controller circuit 154, multi-bit quasi-boost charge pump 162, power inductor 166, and returns to controller circuit 154. The relatively large number of components this signal must pass through before switches 138 and 172 are controlled means that the offset loop delay is substantially greater than Vcc_to_Vcctargetv_delay. This difference means that driver amplifiers 136 and 170 will be very fast and will carry most of the load current instead of power inductor 166, resulting in degraded operation.

[0040] In summary, despite the two main categories, there are various ways to align the delay between the two paths. The first type of solution is to increase the bandwidth of the slow path as much as possible to speed up data exchange. This acceleration can be achieved by using a baseband controller instead of or attached to a pulse-width modulation (PWM) controller in controller circuit 154. While this method increases bandwidth, such an increase is insufficient to offset the overall path delay. Alternatively, this acceleration can be achieved by reducing the value of power inductor 166. However, variations in power inductor 166 introduce additional branches to the ripple. Another option is to reduce the value of the second offset capacitor 174. Size limitations prevent the second offset capacitor 174 from being much smaller than the aforementioned 20 to 40 NFarad. Similarly, reducing the capacitance of the second offset capacitor 174 also introduces ripple branches. Another option is to increase the bandwidth within controller circuit 154 by using a lower zero frequency for the loop filter. Again, this reduces delay, but is still insufficient. As another option, controller circuit 154 may attempt to obtain a timing advance equivalent to Vccfb by using Vcc target instead of Vccfb. However, since Vcc target is a target rather than a feedback signal, it creates an open loop that may not produce the desired value. It should be understood that these feasible methods for increasing the bandwidth of the slow path come with trade-offs that are unacceptable under current design realities.

[0041] A second type of solution to the alignment delay is to reduce the bandwidth of AAF 134 and driver amplifiers 136, 170. This method has proven to provide a more acceptable trade-off. Therefore, an exemplary embodiment of the present invention provides time alignment between paths by adding a feedback capacitor and also adjusting AAF to increase the delay from the self-bandpass filter to the driver amplifier. These changes also reduce the output impedance of the amplifier and aid in ripple absorption. The feedback capacitor also acts as a pole in the driver amplifier's transfer function.

[0042] In this regard, Figure 5 illustrates a progressive ETIC 200. The progressive ETIC 200 is largely structurally similar to the ETIC 12, with several important modifications to provide delay compensation. A target voltage (VTGTA, also referred to as Vramp) is provided to the ETIC 200 and received by a multiplexer 202. The target voltage may initially be a differential signal, but the multiplexer 202 can convert the signal to a single-ended signal as desired. The multiplexer 202 can be coupled to a bandpass filter 204, which blocks signals at frequencies other than the desired frequency. The bandpass filter 204 is coupled to an AAF 206, with a node 208 in between. The Vcc target exists at node 208, and the AAF 206 generates the Vcc target. The Vcc target is provided to a first driver amplifier 210 (sometimes referred to as a horizontal amplifier H). The output of the first driver amplifier 210 can be coupled to ground 214 via a switch 212. When switch 212 is open (i.e., not grounded), the first driver amplifier 210 outputs an amplified signal VparampH, which is coupled to a first offset capacitor 216. The first offset capacitor 216 also acts as a DC block, allowing only AC signals to pass through. The first offset capacitor 216 is coupled to an output node 218. The first offset capacitor 216 can be quite large, for example, about 2 to 3 microfarads. A control signal Vcc can be obtained at the output node 218. The output node 218 is also coupled to a first variable feedback circuit 220, which is coupled to the first driver amplifier 210 and a second driver amplifier 222.

[0043] Continuing to refer to FIG. 5, a band-pass filter 204 provides a derivative of Vramp to a baseband controller (BBC) 224A portion of a controller 224 circuit. The controller circuit 224 may further include a PWM controller 224B, a Voffset loop controller 224C (which allows for the programming of a bandwidth), and a dither circuit 224D. The band-pass filter 204 is also coupled to a multiplier 226 that multiplies Vcc target by a factor K (where 0 < K < 1). K determines the percentage of Vcc derived from the driver amplifier 210 or 222 relative to the voltage provided at the first offset capacitor 216, as will be better explained below. The value K*Vcc target is provided to an adder 228, which adds K*Vcc target to a signal Voffset0Target from a DAC 230 to form a signal Voffset Target. The value from the DAC 230 is a DC offset value. The adder 228 is coupled to the dither circuit 224D of the controller circuit 224. The controller circuit 224 has an additional input from a multiplexer 232 that selects between V parampH from the first driver amplifier 210 and V parampL from the second driver amplifier 222. The controller circuit 224 also receives a sense current signal Iparamp_sense from one of the driver amplifiers 210, 222. The PWM controller 224B and the BBC 224A output signals selected by a multiplexer 234. The output of the multiplexer 234 is coupled to a multi-level boost charge pump 236. The multi-level boost charge pump 236 can use one or more capacitors 238(1) to 238(P) to provide different levels of charge boosting. The multi-level boost charge pump 236 can be coupled to a voltage source such as Vbat. The multi-level boost charge pump 236 can also receive a signal V batampH (voltage battery amplifier level). The multi-level boost charge pump 236 is coupled to a power inductor 240 through a switching circuit 242. The power inductor 240 is coupled to the output node 218 to provide a basic DC power level at the output node 218. Voltage and current values can be manipulated within the controller circuit 224 to assist in estimating a load seen at the output node 218.

[0044] Continuing to refer to FIG. 5, the AAF 206 is also coupled to a second variable feedback circuit 244, which in turn is coupled to a second driver amplifier 222 (sometimes referred to as a vertical amplifier, although the L is used because V might be confused with voltage). The second driver amplifier 222 generates the signal V parampL. Although not shown in the figure, there may be a switch (similar to switch 172 in FIG. 3) that couples the output of the second driver amplifier 222 to ground. Similar to the ETIC 12, these switches are used to switch between the driver amplifiers 210, 222 as needed. The second driver amplifier 222 is coupled to a second offset capacitor 246, which is coupled to the output node 218. The second offset capacitor 246 is relatively smaller than the first offset capacitor 216 and can be (for example) about 20 to 40 nanofarads, and thus C offsetL << C offsetH. Delay paths 250, 252 are also shown in FIG. 5. As previously explained, it is these different delay paths 250, 252 that can cause misalignment of the control signal at the driver amplifier 222.

[0045] Exemplary aspects of the present invention control the AAF 206 and the second variable feedback circuit 244 to control the delay of the Vcc_toVcctargetv_delay delay path 250. Specifically, the controller circuit 224 can store, for example, in a look-up table or the like, a modification to the second variable feedback circuit 244 based on frequency, voltage level, and / or other parameters. Then, when the controller circuit 224 receives the dVramp signal, the controller circuit 224 can send a signal to the second variable feedback circuit 244 to adjust one or more delay elements within the second variable feedback circuit 244 to cause the delay between node 208 and the input of the second driver amplifier 222 (i.e., path 250) to be equal to the delay between node 208 and the changing signal that causes the use of the second offset capacitor 246 (i.e., path 252). It should be further noted that the controller circuit 224 can also adjust the AAF 206 to introduce a delay in path 250.

[0046] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present invention. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the following claims for patents.

[0047] 10: Envelope Tracking (ET) Radio Frequency (RF) Front-End Circuit 12: ET Integrated Circuit (IC) (ETIC) 14: Target Voltage Circuit 16: Local Transceiver Circuit 18A(1) to 18A(N): Power Amplifier 18B(1) to 18B(N): Second power amplifier 20: Input signal 22: Amplitude Detection Circuit 24: Analogy Lookup Table (LUT) 26: Time-varying amplitude 62A(1) to 62A(N): RF signals 62B(1) to 62B(N): RF signals 64A(1) to 64A(N): Antenna Port 64B(1) to 64B(N): Second day line port 66: Amplifier 68: Amplifier 70: Amplifier 72: Amplifier 74: Calibration Circuit 76: Coupler Circuit 78: Feedback Signal 100: Wireless devices 102(1) to 102(K): ET RF front-end circuit 104: Baseband transceiver 106: First antenna array 108: Second day linear array 110(1) to 110(N): First antenna 112(1) to 112(N): Second line 130: Multiplexer 132: Bandpass filter 134: Anti-aliasing filter (AAF) 136: First driver amplifier 138: Switch 140: Grounding 142: First offset capacitor 144: Output Node 146: First Feedback Circuit 148: Multiplier 150: Adder 152: Digital-to-Analog Converter (DAC) 154: Controller Circuit 156: Multiplexer 158: Multiplexer 160: Multiplexer 162: Multi-position Quasi-boost Charge Pump 164(1) to 164(M): Capacitors 166: Power Inductor 168: Switching Circuit 170: Second driver amplifier 172: Switch 174: Second offset capacitor 176: Second Feedback Circuit 200: Progressive ETIC 202: Multiplexer 204: Bandpass filter 206: AAF 208: Node 210: First driver amplifier 212: Switch 214: Grounding 216: First offset capacitor 218: Output Node 220: First Variable Feedback Circuit 222: Second driver amplifier 224: Controller Circuit 224A: Baseband Controller (BBC) 224B: Pulse Width Modulation (PWM) Controller 224C: Voffset Loop Controller 224D: Flickering Circuit 226: Multiplier 228: Adder 230:DAC 232: Multiplexer 234: Multiplexer 236: Multi-position Quasi-boost Charge Pump 238(1) to 238(P): Capacitors 240: Power Inductor 242: Switching Circuit 244: Second Variable Feedback Circuit 246: Second offset capacitor 250: Delay Path 252: Delay Path 400: Output 402: Offset Voltage 404: Vcc signal dVramp: signal I paramp_sense: Sensing current signal I paramp_sense_H: Current signal I paramp_sense_L: Current signal K*Vcc target: value NA1-1 to NA1-N: First output node N A2: Second output node Vbat: Voltage source Vbatamp1: Input signal Vbatamp2: Input signal Vbatam pH: Signal VCC: Control signal Vcc_to_Vcctargetv_delay: Delay VCCDA: Second ET voltage V CCFB: Feedback Signal VCCOA-1 to VCCOA-N: First ET voltage Voffset Target: Signal Voffset0Target: Signal V parampH: Amplified signal V parampL: signal VRAMP: Target Voltage V TGTA: Time-varying ET target voltage

Claims

1. An envelope tracking (ET) integrated circuit (IC) (ETIC), comprising: One input, configured to receive a vramp signal from a baseband transceiver; A first driver amplifier coupled to a first offset capacitor and a first variable feedback circuit; a second driver amplifier coupled to a second offset capacitor, the first variable feedback circuit, and a second variable delay circuit; and a controller circuit configured to: switch between the first driver amplifier and the second driver amplifier; and adjust a first delay of a first path extending from a node to the second driver amplifier through the second variable delay circuit to match a second delay of a second path extending from the node to the second driver amplifier through the controller circuit.

2. As in Request 1's ETIC, wherein the first offset capacitor is coupled to an output node.

3. The ETIC of claim 2, wherein the second offset capacitor is coupled to the output node, and wherein the second offset capacitor is located in series between the second driver amplifier and the output node.

4. The ETIC of request item 1 further includes a bandpass filter coupled to the input and the node.

5. The ETIC of claim 1 further includes an anti-aliasing filter (AAF) coupled to the node and the first driver amplifier.

6. As in Request 1, the second offset capacitor is smaller than the first offset capacitor.

7. The ETIC of claim 1, wherein the controller circuit is configured to adjust the first delay by adjusting the second variable delay circuit to increase a delay.

8. ETIC as requested in item 5, wherein the controller circuit is configured to adjust the first delay by adjusting the AAF to increase a delay.

9. The ETIC of claim 1 further includes selectively coupling the first driver amplifier to a switch grounded, wherein the controller circuitry is configured to operate the switch to switch between the first driver amplifier and the second driver amplifier.

10. The ETIC of claim 1 further includes a scaling circuit coupled to one of the nodes.

11. A wireless device comprising: A baseband transceiver configured to generate a vramp signal; An envelope tracking (ET) integrated circuit (IC) (ETIC) coupled to the baseband transceiver, the ETIC including: an input configured to receive the vramp signal; A first driver amplifier coupled to a first offset capacitor and a first variable feedback circuit; a second driver amplifier coupled to a second offset capacitor, the first variable feedback circuit, and a second variable delay circuit; and a controller circuit configured to: switch between the first driver amplifier and the second driver amplifier; and adjust a first delay of a first path extending from a node to the second driver amplifier through the second variable delay circuit to match a second delay of a second path extending from the node to the second driver amplifier through the controller circuit.

12. The wireless device of claim 11, wherein the first offset capacitor is coupled to an output node.

13. The wireless device of claim 12, wherein the second offset capacitor is coupled to the output node.

14. The wireless device of claim 13 further includes a power amplifier coupled to the output node.

15. The wireless device of claim 11 further includes an anti-aliasing filter (AAF) coupled to the node and the first driver amplifier.

16. The wireless device of claim 11, wherein the controller circuit is configured to adjust the first delay by adjusting the second variable delay circuit to increase a delay.

17. The wireless device of claim 15, wherein the controller circuit is configured to adjust the first delay by adjusting the AAF to increase a delay.

18. The wireless device of claim 11 further includes selectively coupling the first driver amplifier to a grounded switch, wherein the controller circuitry is configured to operate the switch to switch between the first driver amplifier and the second driver amplifier.

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