Variable current drive for isolated gate drivers

Abstract

A method for driving a high-power drive device includes providing a signal having a first predetermined signal level to an output node during a first stage of a multi-stage transition process. The method includes generating a first indication of a first parameter associated with the signal provided to the output node. The method includes generating a second indication of a second parameter associated with the signal provided to the output node. In the first stage, the second parameter is a time elapsed since the start of the first stage. The method includes providing the signal having a second predetermined signal level to the output node during a second stage of the multi-stage transition process. The method includes transitioning from the first stage to the second stage based on the first indication and the second indication.

Description

Technical Field

[0001] This invention relates to circuits, and more particularly to control circuits for high-power applications. Prior Technology

[0002] In a typical control application, a processor system provides control signals for controlling one or more load systems. During normal operation, a large DC or transient voltage difference may exist between one domain of the processor system and one domain of the load system, thus requiring an isolation barrier between the processor system and the load system. For example, a domain may be grounded at a voltage of hundreds or thousands of volts relative to ground. Therefore, an intermediate system includes isolation to prevent damaging currents from flowing between the processor system and the load system. Although isolation prevents the processor system from coupling to the load system via a direct conductive path, an isolated communication channel allows communication between the two systems using optical (optical isolators), capacitive, inductive (transformer), or electromagnetic techniques. In at least one embodiment, the isolated communication channel blocks DC signals and allows only AC signals to pass through. The intermediate system typically uses a voltage converter and output driver to provide control signals at a voltage level suitable for the load system.

[0003] Referring to Figure 1, in an exemplary motor control application, processor 100 (which may be a microprocessor, microcontroller, or other suitable processing device) operates in a first domain (i.e., VDD1, e.g., 5 volts (V)) and provides one or more signals to a high-power load system operating in a second domain (i.e., VDD3, e.g., 800 V). Systems 102 each include an isolation barrier 130 and an isolated communication channel for securely transmitting control signals from processor 100 to driver 106, which drives high-power drive devices 108 and 109 for delivering three-phase power to a three-phase inverter of motor 120. Exemplary high-power drive devices include power metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), gallium nitride (GaN) MOSFETs, silicon carbide power MOSFETs, or other suitable devices capable of delivering high current over short periods of time.

[0004] Voltage converter 104 converts an available supply voltage from VDD1 or VDD3 to a voltage level (i.e., VDD2, for example, about 15 V) usable by the high-voltage side of system 102 and driver 106. It should be noted that in other embodiments, a single voltage converter 104 converts a supply voltage from a first voltage level (e.g., VDD3) to multiple other voltage levels (e.g., VDD1 and VDD2) and / or provides multiple outputs of a specific voltage (e.g., multiple VDD2 outputs corresponding to multiple systems 102). Driver 106 provides switching control signals at the levels required by the corresponding high-power drive devices 108 or 109 of the three inverters. The load motor requires three-phase power at a high-power level. System 102 corresponding to the high-power device (high-side inverter device) coupled to VDD3 is grounded at a voltage corresponding to the high-voltage level of VDD3, switched relative to ground. Typical high-power drive devices 108 and 109 used for the three inverters driving motor 120 require a substantial turn-on voltage (e.g., in the range of tens of volts) and are susceptible to fault conditions that can damage such devices.

[0005] Exemplary isolated gate drivers are used in industrial and automotive applications. Conventional embodiments of gate drivers use a fixed resistor to determine a fixed drive strength during the normal turn-on and normal turn-off procedures of a high-power drive. The fixed drive strength determination represents a trade-off between maximizing efficiency, minimizing radiated and conducted emissions (i.e., electromagnetic interference (EMI)), and limiting voltage stress on external high-power drive devices. Therefore, improved techniques for controlling high-power drive devices are desired. Simple Explanation of the Diagram

[0006] The invention will be better understood by referring to the accompanying drawings, and those skilled in the art will understand several objectives, features and advantages of the invention.

[0007] Figure 1 shows a functional block diagram of a typical motor control system.

[0008] Figure 2 shows a functional block diagram of one part of the motor control system in Figure 1, including an exemplary fault detection circuit system and a driver control circuit.

[0009] Figure 3 shows a simplified illustration of one part of the motor control system in Figure 2.

[0010] Figure 4 illustrates timing waveforms and switching parameter definitions consistent with at least one embodiment of the present invention.

[0011] Figure 5 illustrates a functional block diagram of a portion of a packaged driver integrated circuit product that includes a variable strength gate driver circuit, consistent with at least one embodiment of the present invention.

[0012] Figure 6 illustrates a circuit diagram of an exemplary embodiment of a variable current driver circuit consistent with at least one embodiment of the present invention.

[0013] Figure 7 illustrates an exemplary variable current driver operating register and parameter values ​​consistent with at least one embodiment of the present invention.

[0014] Figure 8 illustrates a functional block diagram of an exemplary package of a driver product for a low-power system, consistent with at least one embodiment of the present invention.

[0015] Figure 9 illustrates a functional block diagram of an exemplary package of a driver product for a medium-power system, consistent with at least one embodiment of the present invention.

[0016] Figure 10 illustrates a functional block diagram of an exemplary package of a driver product for a high-power system, consistent with at least one embodiment of the present invention.

[0017] Figure 11 illustrates a functional block diagram of an exemplary package for a driver product of a high-power system with redundancy, consistent with at least one embodiment of the present invention.

[0018] The use of the same reference symbol in different diagrams indicates similar or identical items. Implementation

[0019] Referring to Figure 2, in an exemplary motor control application, processor 100 receives a voltage (i.e., VDD1, for example, 5 V) and provides one or more signals to a high-power load system operating in a second domain (i.e., VDD3, for example, several hundred volts). Driver product 200 includes an isolation barrier 230 and a communication channel for securely transmitting control signals from processor 100 across the isolation barrier 230 to drive a high-power drive device for delivering three-phase power to a three-phase inverter of motor 120. In an exemplary embodiment, driver product 200 includes multiple integrated circuits configured as a multi-chip module in a single package. For example, driver product 200 includes primary-side integrated circuit 201 and secondary-side integrated circuit 203. Primary-side integrated circuit 201 receives a control signal from processor 100 and transmits the signal across isolation barrier 230 to secondary-side integrated circuit 203. In these embodiments, terminals 250, 252, 254, ..., 270 are pins of one of the multi-chip modules and are coupled to external components (e.g., discrete resistors and capacitors) and processor 100.

[0020] Driver product 200 includes an isolation barrier 230 that isolates a first side (e.g., primary-side integrated circuit 201) of driver product 200 operating using VDD1 (e.g., a voltage less than 10 volts) and a second side (e.g., secondary-side integrated circuit 203) of driver product 200 operating using VDD2 (e.g., a voltage of tens of volts). An isolated communication channel facilitates communication between primary-side integrated circuit 201 and secondary-side integrated circuit 203. Any suitable communication technology that does not use a conductive path between the two sides can be used, such as optical, capacitive, inductive, or electromagnetic technologies. The isolated communication channel facilitates communication of a control signal from processor 100 via primary-side integrated circuit 201 to secondary-side integrated circuit 203.

[0021] An example of an isolated communication channel uses digital modulation (e.g., on-off keying modulation) to transmit one or more digital signals between primary-side integrated circuit 201 and secondary-side integrated circuit 203, but other communication protocols may be used. Generally, on-off keying modulation is a form of amplitude shift keying that represents digital data as the presence or absence of a carrier or oscillation signal with a carrier frequency fc (e.g., 500 MHz to 1 GHz). The presence of the carrier for a specified duration represents a binary 1, and its absence for the same duration represents a binary 0. This type of transmission is robust for isolated applications because a logic "0" state sends the same signal as when the primary side loses power (e.g., nothing), and the device readily exhibits its preset state. This behavior is advantageous in driver applications because it does not accidentally turn on a driven load device, even when the primary side loses power. However, isolated communication channels can use other types of signals (e.g., pulse width modulation signals or other types of amplitude shift keying modulation signals). The digital modulation scheme used can be determined based on the performance specifications of the target application (e.g., signal resolution) and the environment (e.g., probability of transient events).

[0022] Secondary-side accelerator circuit 203 includes driver 221, which generates one or more output control signals based on a received control signal CTL received from primary-side accelerator circuit 201, which receives a control signal IN from processor 100 at terminal 254. Driver 221 provides corresponding signals to terminals 264 and 266. Buffer 219 generates control signals CTLH and CTLL at appropriate signal levels to control the pull-up and pull-down mechanisms of driver 221, respectively. Buffer 219 may generate one control signal or two separate control signals for the pull-up and pull-down mechanisms based on the received control signal CTL. An external resistor RH adjusts the pull-up strength by 1 / RH, independent of the external resistor RL that adjusts the pull-down strength by 1 / RL. Although the received control signal CTL is illustrated as a single-ended signal based on an input control signal IN received from processor 100 at terminal 254, it should be noted that in other embodiments, the input control signal IN and the received control signal CTL are differential signals. Generally speaking, signals illustrated herein as single-ended signals may be implemented as differential signals in other embodiments, and signals illustrated herein as differential signals may be implemented as single-ended signals in other embodiments.

[0023] One or more passive components can be used to independently adjust the pull-up and pull-down strengths of the output control signal provided to the control terminal of the high-power drive device 108 from the on-resistance RDS(ON) of the integrated pull-up output device coupled to terminal 264. For example, resistor RH adjusts the pull-up strength. Resistor RL adjusts the pull-down strength of the signal provided to the gate of the high-power drive device 108 via terminal 266 to have a different strength than the pull-up strength of the signal provided to the gate of the high-power drive device 108. In a typical configuration, the pull-up time is slower than the pull-down time, and resistors RH and RL will vary depending on the specifications of the device used as the high-power drive device 108 (e.g., power MOSFET, IGBT, GaN MOSFET, silicon carbide power MOSFET, etc.).

[0024] In at least one embodiment, an isolated communication channel feeds voltage or fault information from the secondary-side integrated circuit 203 back to the primary-side integrated circuit 201. The primary-side integrated circuit 201 or the processor 100 uses this information to adjust operating parameters or generate one or more fault indicators, which can be used to automatically handle faults by correspondingly controlling the output driver 221. For example, the secondary-side integrated circuit 203 includes a module for detecting fault conditions associated with high-power drives, such as a desaturation detector 214, and can also detect user-initiated faults received from the processor 100. The secondary-side integrated circuit 203 can use the fault indicators(s) to prevent damage to the high-power drives, load systems, or users of the load systems. Additionally, the secondary-side integrated circuit 203 can send an indication of a fault or associated diagnostic information to the primary-side integrated circuit 201 and / or the processor 100.

[0025] In at least one embodiment, the secondary-side integrated circuit 203 includes desaturation fault protection for high-power semiconductor devices, preventing short-circuit current events that could damage the high-power drive device 108. This fault can be caused by malfunctioning inverter gate driver behavior, drive supply voltage problems, a short circuit in one of the power stages, or insufficient gate drive signal due to other excessive current or power dissipation in the high-power drive device. These events can substantially increase power consumption, leading to rapid overheating and damage to the corresponding high-power drive device. For example, when a short-circuit current condition occurs in the illustrative motor drive application of Figures 1 and 2 (e.g., both devices of an individual inverter phase of a three-phase inverter are turned on), high current flows through the high-power drive devices 108 and 109, potentially damaging them. Therefore, a fault detection technique detects this desaturation condition. The driver product 200 can send one of its indicators to the processor 100.

[0026] In at least one embodiment of driver product 200, after a fault condition is detected, a desaturation fault protection shuts off the high-power drive device 108. In a typical application, terminal 262 is coupled to an external resistor and diode, which are coupled to a terminal of the high-power drive device 108 (e.g., the collector of an IGBT or the drain of a MOSFET). In at least one embodiment of driver product 200, desaturation detection circuit 214 is enabled only when the high-power drive device 108 is turned on. Desaturation detection circuit 214 senses when the collector-emitter voltage (or drain-to-source voltage, as appropriate) of the high-power drive device 108 exceeds a predetermined threshold level (e.g., 7 V). It should be noted that the predetermined threshold level of desaturation detection circuit 214 can be externally adjusted based on the forward voltage of one or more diodes coupled to the desaturation resistor coupled to terminal 262 or based on the resistance of the desaturation resistor. Alternatively, a delay time can be introduced by coupling a capacitor between terminal 262 and an external power supply node.

[0027] Generally speaking, the undervoltage lockout detector 212 prevents insufficient voltage from being applied to the control terminals of the high-power drive device 108 by forcing the output at terminal 264 low during the power-on period of the drive product 200. The undervoltage lockout detector 212 detects when the supply voltage (e.g., VDD2 sensed using terminal 260) exceeds a first predetermined undervoltage lockout threshold voltage and generates an indication thereof, which can be used to disable the lockout condition. The undervoltage lockout detector 212 also detects when the supply voltage falls below a second predetermined undervoltage lockout threshold (which may differ from the first undervoltage lockout threshold voltage) to provide noise margin for undervoltage lockout voltage detection. The indication generated by the undervoltage lockout detector 212 can be provided to the processor 100 using terminal 252. In at least one embodiment, the drive product 200 includes a similar mechanism for an overvoltage condition.

[0028] The Miller clamp 220 reduces the parasitic turn-on effect of the high-power drive device 108 caused by the charging of Miller capacitors (e.g., in other embodiments of the high-power device 108, the collector-to-gate parasitic capacitor of an IGBT device or the drain-to-gate parasitic capacitor of a MOSFET). This gate-to-collector coupling can respond to a high transient voltage (e.g., a gate voltage surge) generated when the high-power drive device 108 is turned off, causing a parasitic turn-on of device 108. A gate voltage surge is generated when another high-power drive device coupled to the high-power drive device 108 is turned on.

[0029] For example, when the upper high-power drive 109 is turned on, a corresponding lower high-power drive 108 coupled to the upper high-power drive 109 experiences a voltage change dV CE / dt, causing current to flow to the gate drive terminal coupled to the lower high-power drive 108. In the absence of Miller clamp 220, this current will generate a voltage drop across the external resistor RL and will increase the gate-to-emitter voltage of the corresponding lower high-power drive 108. If the gate-to-emitter voltage exceeds the device threshold voltage (e.g., 2 V), the high-power drive 108 is turned on. A parasitic turn-on event occurs when the high-power drive 108 is turned on and the corresponding upper high-power drive 109 is in a turn-off state. Miller clamp 220 prevents parasitic turn-on by coupling terminal 268 to ground via a low-resistance switch that prevents or inhibits the Miller capacitor current from generating a voltage sufficient to turn on the high-power drive.

[0030] In some embodiments of driver product 200, Miller clamp 220 is not required because a sufficiently large gate capacitor coupled between the gate and emitter of each high-power drive device 108 shunts any Miller current and raises the transient level required for parasitic turn-on. However, these embodiments increase the gate charge voltage required to reach the threshold voltage of the high-power drive device 108, increasing driver power and switching losses of the high-power drive device 108. In other embodiments of driver product 200 that do not use a Miller clamp circuit, the supply voltage is coupled to a negative voltage (e.g., -5 V) instead of ground. This configuration provides additional voltage margin to increase the likelihood that parasitic turn-on transients do not raise the control terminals of the high-power drive device 108 above their threshold voltage. However, this configuration increases cost by requiring an additional pin on the package and generating a negative voltage.

[0031] After a fault condition is detected by the module on the secondary-side integrated circuit 203, fault logic 216 generates a control signal FAULT, which can initiate the shutdown of the high-power drive 108. Fault logic 216 reports the fault condition to processor 100 via primary-side integrated circuit 201. Alternatively, fault logic 216 reports the fault condition only to primary-side integrated circuit 201, and the high-power drive 108 continues to operate. Primary-side integrated circuit 201 then reports the fault condition to processor 100. Since a system may contain multiple high-power drives (e.g., six high-power drives in the exemplary motor control application described herein), shutting down only one of these drives could damage the high-power drive or the load. Therefore, in response to the detection of a fault, processor 100 may initiate the shutdown of one of the high-power drives 108 only after detecting a predetermined number of faults within a specific time period or after other conditions are met. In at least one embodiment, the processor 100 initiates the shutdown of the high-power drive 108 independently of any fault detection of the drive product 200 (e.g., based on a fault detection from another drive product 200 associated with another high-power drive 108 or 109).

[0032] A sudden shutdown of one of the high-power drive devices 108 can result in a large di / dt induced voltage. Such voltage surges can damage the high-power drive device 108 or the load. Therefore, in response to a fault condition, the processor 100 or driver product 200 initiates a soft shutdown of one of the high-power drive devices 108, which causes the control terminals of the high-power drive device 108 to discharge slowly at a rate having a longer shutdown time than the normal shutdown time of the output control signal. For example, fault logic 216 receives an indicator from desaturation detection circuit 214 and generates a control signal FAULT to initiate a soft shutdown based on this. In other embodiments, fault logic 216 receives an indicator from one or more other fault detection circuits. A typical implementation of a soft shutdown function in a driver product may use an additional terminal or at least one additional external resistor coupled to terminal 264 or terminal 266.

[0033] A variable current drive technique divides a transition (e.g., on or off) of a state (e.g., on or off) of a high-power drive into multiple stages (i.e., time intervals) with different characteristics. The use of a variable current drive reduces or eliminates the need for an external gate resistor to control the transition of the high-power drive. Compared to conventional methods, using multiple current settings for an output gate driver current (e.g., a gate current of the high-power drive) during a transition of the output signal improves the state transition of the high-power drive and the corresponding system efficiency level (i.e., the ratio of useful work performed by the system to the total energy consumed by the system, which, in an exemplary electric vehicle application, affects the range of a battery charge per charge of an electric vehicle), reduces EMI, and reduces voltage stress on the high-power drive.

[0034] In at least one embodiment of the variable current drive technology, a change in the target current level during a state transition of a high-power drive device is based on an indication of a control voltage of the high-power drive device (e.g., a gate-to-source voltage VGS sensed by the output node of a gate driver product) and a corresponding time constraint. For example, in response to the gate-to-source voltage VGS of the high-power drive device reaching or exceeding a Miller plateau, a target current level changes from a first predetermined current level to a second predetermined current level. The Miller plateau refers to a region of gate-to-source voltage time response in which the gate-to-source voltage VGS is nearly constant and is a region in which the state of the high-power drive device switches between a first state (e.g., an off state) and a second state (e.g., an on state). The Miller plateau is defined by the gate-to-source voltage level VPLAT_ON and the gate-to-source voltage level VPLAT_OFF, which are equivalent to inflection points in the response of the gate-to-source voltage VGS. In at least one embodiment, one objective of the variable current drive technique is to reach the Miller plateau voltage as quickly as possible. However, to limit electromagnetic interference caused by the current of the variable current driver, the variable current drive technique drives a high current level only for a finite period of time and reduces the current after reaching the Miller plateau voltage or after a corresponding time limit has expired. Therefore, the variable current driver initially drives a high gate current level (e.g., 12 A) to reduce the time required to charge the gate of the high-power drive device to the Miller plateau voltage (or discharge the gate of the high-power drive device to the Miller plateau voltage, as appropriate), and then the variable current driver drives another current level (e.g., 6 A) to the gate of the high-power drive device to achieve a drain-to-source (or collector-to-emitter) voltage change over time (e.g., dV DS / dt ON or dV DS / dT OFF) for the remainder of the state transition of the high-power drive device. Compared to conventional gate driver implementations, variable current drive technology offers improved capabilities to optimize the trade-offs between faster switching speeds for efficiency, lower dV DS / dt for reduced EMI, and reduced drive output voltage overshoot.

[0035] In at least one embodiment of the variable current drive technology, in addition to a threshold voltage criterion for triggering a change in a target output current level, or instead of a threshold voltage criterion, a change in the target output current level based on a time constraint may also be used. In at least one embodiment, the variable current drive technology uses a combination of a threshold voltage criterion and a time constraint (e.g., changing a target current level based on a threshold voltage or based on a time constraint, whichever is achieved first) to provide more reliable operation in high-noise environments where incorrect switching might otherwise occur due to noise. In at least one embodiment, the variable current drive technology uses a digital counter to measure elapsed time. In at least one embodiment, the variable current drive technology uses an RC-based system to measure elapsed time. For example, one or more timers generate an indicator of the time elapsed since the start of one stage of a multi-stage transition procedure. Even if a target voltage level is not achieved at the output node, the variable current drive technology still responds to the expiration of a predetermined amount of time (e.g., to reduce EMI) or responds to the expiration of a predetermined amount of time and another condition (e.g., a sensed current level or a sensed voltage level exceeds a predetermined threshold level) to change the target current level and enter the next stage of the multi-stage transition process.

[0036] Figures 3 and 4 illustrate an exemplary implementation of a variable current drive technology that includes a multi-stage turn-on procedure and a multi-stage turn-off procedure. An exemplary high-power gate driver using a +15 V and -4 V power supply drives a high-power drive device 304. An inductor 306, having an initial condition of IL = 20 A and coupled in parallel with a diode, represents an exemplary load. Exemplary waveforms of the gate current IGATE, drain-to-source voltage VDS, drain current ID, gate-to-source voltage VGS, and control signal CTL driven by the gate driver 302 illustrate an exemplary multi-stage turn-on procedure and an exemplary multi-stage turn-off procedure for the high-power drive device 304. The target set current ISET illustrates an exemplary target current level (i.e., a predetermined target current setpoint) used to program the actual gate current IGATE flowing into the gate of the high-power drive device 304. The resulting drain current ID and associated voltages of the high-power drive 304 (e.g., drain-to-source voltage VDS and gate-to-source voltage VGS) represent a response to an exemplary variable current drive profile using a combination of parameters such as Miller plateau voltage, Miller clamp voltage, and time limits for each stage of a multi-stage switching procedure. Although the embodiments described herein use the Miller plateau voltage as a voltage threshold for triggering a change in the target gate current level for one stage of a multi-stage turn-on procedure or a multi-stage turn-off procedure of the high-power drive 304, other embodiments use other voltages, multiple switching voltages, current levels, or combinations thereof.

[0037] In at least one embodiment of the variable current drive technology, the characteristics of a multi-stage switching procedure of a high-power drive device are defined by parameters of a normal turn-on setting (e.g., a target current setpoint, a gate-to-source threshold voltage, and a time limit for one stage of the multi-stage switching procedure). The normal turn-on procedure comprises two stages: stage P TON1 and stage P TON2. Each stage of the normal turn-on procedure has a corresponding, individually programmed outflow current level. For example, stage P TON1 has a target current setpoint I ON1_SET. In at least one embodiment of the normal turn-on procedure, the Miller plateau voltage V PLAT_ON is used as a threshold voltage to trigger a transition from stage P TON1 to stage P TON2. In at least one embodiment of the normal turn-on procedure, the target current setpoint ION1_SET is greater than the target current setpoint ION_SET2 (i.e., ION1_SET > ION2_SET), and time limit tON1 triggers a transition from stage PTON1 to stage PTON2 to limit the amount of time that the higher current level of the target current setpoint ION1_SET is used to limit EMI. In response to the expiration of time limit tON1, the normal turn-on procedure enters stage PTON2, even if the gate-to-source voltage VGS has not reached the Miller plateau voltage VPLAT_ON. Therefore, in response to the gate-to-source voltage VGS of the high-power drive device 304 exceeding the Miller plateau voltage VPLAT_ON or in response to the time elapsed in stage PTON1 exceeding time limit tON1 (whichever occurs first), the normal turn-on procedure continues from stage PTON1 to stage PTON2. Once in stage PTON2, the normal turn-on procedure does not return to stage PTON1.

[0038] Stage P TON2 has a target current setpoint I ON2_SET. Another set of variable current drive turn-on settings also controls stage P TON2 of the normal turn-on procedure. For example, the current setpoint I ON2_SET specifies the target outflow current level of stage P TON2 of the normal turn-on procedure. The time limit t ON2 specifies the time during which the desired gate-to-source voltage VGS is higher than the undervoltage threshold VGSON_UV. In at least one embodiment, if the time limit t ON2 expires before the gate-to-source voltage VGS exceeds the undervoltage threshold VGSON_UV, the control circuitry triggers a fault. In at least one embodiment of the variable current drive technology, after the gate-to-source voltage VGS reaches the voltage level VPOS, the high-power drive device 304 remains on and the drain current ID increases at a rate of VDC_Link / L until a transition of the control signal CTL triggers another multi-stage transition procedure, causing the gate-to-source voltage VGS to exceed (i.e., fall below) the Miller plateau voltage VPLAT_OFF.

[0039] In at least one embodiment of the variable current drive technology, the characteristics of a multi-stage turnaround procedure are defined by parameters of a normal shutdown setting (e.g., a target current setpoint, a threshold voltage, and a time limit for one stage of the multi-stage turnaround procedure). The normal shutdown procedure comprises three stages: stage PTOFF1, stage PTOFF2, and stage PTOFF3. Each stage has a corresponding, individually programmed draw-in current level. For example, stages PTOFF1, PTOFF2, and PTOFF3 have target current setpoints IOFF1_SET, IOFF2_SET, and IMC_SET, respectively. In at least one embodiment, the target current setpoint I OFF1_SET is greater than the target current setpoint I OFF2_SET (i.e., I OFF1_SET > I OFF2_SET), and the target current setpoint I MC_SET is greater than or equal to the target current setpoint I OFF1_SET and greater than the target current setpoint I OFF2_SET (i.e., I MC_SET ≥ I OFF1_SET and I MC_SET > I OFF2_SET).

[0040] The normal shutdown setting parameters control stage PTOFF1 include a current level parameter, a threshold voltage parameter, and a time parameter (e.g., target current setpoint I OFF1_SET, threshold voltage V PLAT_OFF, and time limit t OFF1). The target current setpoint I OFF1_SET specifies the target draw-in current level for stage PTOFF1, and the threshold voltage V PLAT_OFF specifies the threshold voltage used to trigger a transition from stage PTOFF1 to stage PTOFF2 in the normal shutdown procedure. The time parameter t OFF1 specifies the time limit for stage PTOFF1 in the normal shutdown procedure. The variable current drives the normal shutdown setting parameters (e.g., target current setpoint I OFF2_SET, threshold voltage V MC, and time limit t OFF2) to control stage PTOFF2. The current parameter specifies the target draw-in current level for stage PTOFF2 in the normal shutdown procedure. The voltage parameter, Miller clamp voltage VMC, specifies the threshold voltage used to trigger a transition to stage PTOFF3, thereby triggering the internal Miller clamp function of the variable strength driver. The time parameter specifies the time limit tOFF2 of stage PTOFF2 to trigger a transition to stage PTOFF3 in the normal shutdown procedure.

[0041] The normal shutdown procedure phase PTOFF3 is controlled by the normal shutdown setting parameters current setpoint IMC_SET and time limit tOFF3. Current IMC_SET specifies the target current draw-in level for phase PTOFF3 of the normal shutdown procedure. Time limit tOFF3 specifies the time during which the desired gate-to-source voltage VGS is below the overvoltage threshold VGSOFF_OV, representing the overvoltage limit of the gate-to-source voltage VGS during the shutdown period. In at least one embodiment, if time limit tOFF3 expires before the gate-to-source voltage VGS falls below the overvoltage threshold VGSOFF_OV, the control circuitry triggers a fault.

[0042] In at least one embodiment, in response to changes in the state of the received control signal CTL, the variable current drive technique introduces a small dead time (e.g., a time delay tDT) before initiating a corresponding multi-stage transition procedure (e.g., an on procedure or a off procedure) to reduce or eliminate breakdown between the pull-up and pull-down circuits of the gate driver. The multi-stage transition profiles (including parameters and the number of stages) described herein are merely illustrative. Compared to conventional methods, transition profiles can be optimized for different objectives or operating conditions to improve efficiency, reduce EMI, and reduce drain-to-source voltage VDS (or collector-to-emitter voltage VCE) voltage stress. In at least one embodiment, a soft-shutdown profile implements a multi-stage soft-shutdown procedure initiated by the gate driver 302 in response to the detection of a fault (e.g., a short-circuit load of the power switch). In at least one embodiment, the soft-shutdown procedure uses the same shutdown procedure as a normal shutdown procedure but with different parameters. For example, the target current setpoint I SS2_SET parameter (which corresponds to the target current setpoint I OFF2_SET of the normal shutdown setting) is set to a value lower than that used for normal load current under short-circuit load conditions to slow down the shutdown procedure and reduce or eliminate any resulting overshoot that could damage the drain-source voltage VDS (or collector-emitter voltage VCE) of a high-power drive device. In at least one embodiment of a multi-stage switching setting, a time limit in one or more stages of an on-progress or a shutdown procedure triggers a measurement for fault detection.

[0043] Referring to Figure 5, in at least one embodiment, the driver product 400 includes a primary-side integrated circuit, an isolation barrier and an isolated communication channel (not shown in Figure 5, but described above), and a secondary-side integrated circuit 403. In at least one embodiment, the secondary-side integrated circuit 403 of the driver product 400 includes a gate driver 420 coupled to terminal VO, which in some embodiments is the only terminal of the driver product 400 coupled to the gate terminal of the high-power drive device 108. In at least one embodiment, the gate driver 420 integrates a Miller clamping function and eliminates the external resistor coupled to the high-power drive device 108 described above. In at least one embodiment, the gate driver 420 integrates other fault detection circuitry described above (not shown).

[0044] In at least one embodiment of the gate driver 420, the driver controller 404 configures the variable intensity driver 402 to flow current according to a normal on setting in response to a change in the control signal CTL from a first value to a second value; configures the variable intensity driver 402 to draw current according to a normal off setting in response to a change in the control signal CTL from a second value to a first value; or configures the variable intensity driver 402 to implement a soft shutdown setting in response to a control signal CTL having a second value and in response to a fault condition (e.g., a desaturation fault condition indicated by the control signal FAULT). The above describes exemplary on, off, and soft shutdown settings, but other settings are used in other embodiments. The settings are independently determined by the values ​​used by the driver controller 404 to generate control signals using predetermined digital codes. The predetermined digital code and other configuration parameters can be preloaded into memory 410, received from a serial interface of one of the driver products 400, or provided to the working register of gate driver 420 or memory 410 using other technologies.

[0045] In at least one embodiment, the driver controller 404 receives a control signal CTL across an isolation barrier from a primary-side integrated circuit and a feedback signal from a comparator 406, which in some embodiments is a hysteresis comparator. In at least one embodiment, the comparator 406 receives a predetermined signal level from a digital-to-analog converter 412. In at least one embodiment, the predetermined signal level code is digitally stored as part of an on or off setting in memory 410 and subsequently converted to an analog signal for use by the comparator 406. In other embodiments, instead of using an analog comparator, an analog-to-digital converter digitizes a level of a signal on terminal VO, and the digital comparison logic or driver controller 404 generates a feedback signal FB indicating a comparison between the gate-to-source voltage VGS of the high-power drive device 108 and a predetermined threshold voltage of an on or off setting. In at least one embodiment of the secondary-side circuit 403, at least one set of digital codes retrieved from memory 410 corresponds to a target current setpoint of a variable current drive profile. Driver controller 404 accesses these digital codes to set the output current (gate current I GATE) provided by variable intensity driver 402 to the gate of high-power drive device 108 according to the variable current drive profile.

[0046] Referring to Figure 6, in at least one embodiment of the gate driver 420, the variable intensity driver 402 is a variable current driver that includes a current source that generates the gate current IGATE and the corresponding voltage described above. In at least one embodiment, a current digital-to-analog converter (DAC) 421 and a current DAC 422 are used to implement the current source. The current DAC 421, which flows current to terminal VO during the turn-on procedure, is implemented using a p-type transistor. The current DAC 422, which draws current from terminal VO during the turn-off procedure, is implemented using an n-type transistor. Both current DAC 421 and current DAC 422 include a current mirror structure with a fixed current input leg (e.g., transistors MP and MPC of current DAC 421 and MN and MNC of current DAC 422) and an output stage including binary weighted branches or thermometer weighted branches (e.g., branches including transistors MP0 and MPC0, branches including transistors MP1 and MPC1, ..., branches including transistors MPn and MPCn of current DAC 421, branches including transistors MN0 and MNC0, branches including transistors MN1 and MNC1, ..., branches including transistors MNn and MNCn of current DAC 422). Corresponding switches (e.g., switches SOFF_P0, SON_P0, SOFF_P1, SON_P1, ..., SOFF_Pn and SON_Pn of current DAC 421 and switches SOFF_N0, SON_N0, SOFF_N1, SON_N1, ..., SOFF_Nn and SON_Nn of current DAC 422) selectively enable a branch of an output stage based on a target current ISET. An exemplary manufacturing process provides transistors with different breakdown voltages by forming gate terminals using oxide layers of varying thicknesses. An exemplary high-voltage device has a thicker gate oxide layer and therefore a higher breakdown voltage compared to a low-voltage device with a thinner gate oxide layer. In at least one embodiment of the variable intensity driver 402, a low-voltage transistor is used to increase the accuracy of the current supplied to terminal VO, rather than using a high-voltage transistor to interface to the high-voltage domain. The low-voltage devices M P0, ..., M PN and MN0, ..., MNn are protected from the high voltage on terminal VO by corresponding stacked devices, and provide a precise output current to the gate of the high-power drive device 108 independently of a wide range of voltages on terminal VO. Although each branch of the output stage includes a transistor and a selectively enabled stacked transistor, in other embodiments, different numbers of transistors and branch topologies are used.

[0047] In an exemplary embodiment of the variable intensity driver 402, a maximum output current requirement is 12.4 A, generated by a 5-bit (i.e., n=0, 1, 2, ..., 4) current mirror digital-to-analog converter circuit with an input bias current IBIAS of 1.24 mA and a current gain of 10,000. The least significant bit of the binary weighted digital-to-analog converter circuit corresponds to a current of 0.4 A. Whenever the digital input control code is updated, a transistor of a predetermined size that generates this high output current produces a large transient on the diode-connected input reference transistor MP or MN, which generates reference voltages VOHF and VOLF for each digital-to-analog converter circuit. Therefore, the variable intensity driver 402 includes storage capacitors CHF and CLF, respectively, coupled in parallel to the diode-connected transistor MP of DAC 421 and the diode-connected transistor MN of DAC 422, to reduce or eliminate short-time glitch interference in the DAC voltage reference during output current transitions. In at least one embodiment of the variable intensity driver 402, the binary weighted or thermometer-weighted branches of DACs 421 and DAC 422 are composed of a plurality of smaller individual devices totaling up to the size of a target output device. This structure reduces the impact of semiconductor manufacturing defects on the overall functionality of the output stage. In at least one embodiment, the DAC structure and least significant bit size of the output stage are selected to reduce the impact of a single defect.

[0048] In at least one embodiment, the variable intensity driver 402 is coupled to a driver controller 404 and memory 410 or other control logic and associated memory storing a variable current drive working register. In at least one embodiment, the driver controller 404 controls the on / off procedure based on the contents of memory 410 and parameter inputs. For example, the driver controller circuitry generates digital control signals to configure the variable intensity driver 402 according to a target current level and associated contents of the working register for an active stage of a multi-stage transition procedure. In at least one embodiment, the driver controller 404 executes a state machine that updates the digital control signals to configure or reconfigure the variable intensity driver 402 to implement various stages of the multi-stage transition procedure based on parameter indicators (e.g., a sensor output indicating a voltage level or a current level, a timer output indicating elapsed time, or another parameter indicator) and predetermined parameter values ​​stored in memory (e.g., a target signal level, a threshold voltage, or a time limit value). In at least one embodiment, a fast voltage comparator is located outside a driver controller circuit and provides a parameter indicator, such as a feedback signal indicating a comparison between the gate-to-source voltage VGS and a predetermined threshold voltage. In at least one embodiment, a high-resolution counter in a timer circuit 414 external to the driver controller circuit 404 provides timing information.

[0049] Variable current drive technology divides a switching process into multiple stages with independent characteristics (such as current level, threshold voltage, and time limit). In at least one embodiment, during operation, parameter values ​​stored in a working register are used to control a multi-stage switching process of a high-power drive device. In at least one embodiment, each parameter value is assigned an index to one of a lookup tables corresponding to parameter values ​​(e.g., voltage, current, or time values).

[0050] Figure 7 illustrates exemplary variable current drive parameters for the one- or two-stage turn-on procedure, one- or three-stage turn-off procedure, and one- or three-stage soft-shutdown procedure described above. However, other embodiments use a different number of stages for turn-on, turn-off, or soft-shutdown. In at least one embodiment, a working register specifies the variable current drive parameter values ​​for operating the gate driver in an exemplary automotive traction inverter application. For example, stage P_TON1 of the multi-stage turn-on procedure described above is controlled by parameters stored in register ON_P1 (e.g., register bits I_ON1, t_ON1, and V_PLAT_ON). Stage P_TON2 of the multi-stage turn-on procedure described above is controlled by parameters stored in register ON_P2 (e.g., register bits I_ON2, t_ON2, and V_GSON_UV). The stage PTOFF1 of the multi-stage shutdown procedure described above is controlled by parameters stored in register OFF_P1 and register bits I OFF1, t OFF1, and V PLAT_OFF. The stage PTOFF2 of the multi-stage shutdown procedure described above is controlled by parameters stored in register OFF_P2 (e.g., register bits t OFF2 and V MC). The stage PTOFF3 of the multi-stage shutdown procedure described above is controlled by parameters stored in register OFF_P3 (register bits t OFF3 and V GSOFF_OV). In at least one embodiment, a multi-stage soft shutdown procedure reuses the shutdown registers. In at least one embodiment, stage P SS1 of the soft shutdown procedure is controlled by parameters stored in register SS_P1 (e.g., register bit t SS1 and register bit V PLAT_SS), and stage P SS2 of the shutdown procedure is controlled by parameters stored in register SS_P2 (e.g., register bit I SS2 and register bit t SS2). In at least one embodiment, stage three and its associated registers, as well as the register V MC of stage two, are not used by the exemplary soft shutdown procedure. In one exemplary embodiment, the registers corresponding to each parameter store 3-bit index values ​​pointing to parameter values ​​in the associated parameter value table. As mentioned herein, a configuration component is a set of parameter values ​​(e.g., ON_P1 or OFF_P3) stored in one stage of a multi-stage transition procedure. A variable current drive setting profile is a complete set of setting profile components for all multi-stage transitions in one embodiment of variable current drive technology, representing the values ​​of ON_P1, ON_P2, OFF_P1, OFF_P2, OFF_P3, SS_P1, and SS_P2 in an exemplary embodiment.

[0051] Generally speaking, one example of an isolated gate driver product is packaged to maintain an isolation barrier between two voltage domains and to transfer heat generated by the encapsulated die to the circuit board or surrounding air. A conventional isolated gate driver coupled to an external gate resistor uses both the external gate resistor and the internal resistance of the gate driver to dissipate power generated during the turn-on or turn-off processes of a high-power drive. The internal resistance of a conventional isolated gate driver is typically substantially smaller than the external gate resistor, resulting in the external gate resistor dissipating most of the power. In at least one embodiment of a driver product, the elimination of the external gate resistor increases the amount of power dissipated by a gate driver integrated circuit. The isolation barrier requires increasing the distance between the pins on the opposite side of the isolation barrier and an exposed die pad (e.g., a thermal pad or metal plate outside the package) or other heat sink structure. Therefore, the isolation barrier or power dissipation specification may require a custom-designed package, which increases cost. In the absence of an external gate resistor, or with the use of a small external gate resistor, the gate driver integrated circuit dissipates most of the power required to turn on or off high-power drives. When driving high-power drives, the power dissipation capability of the gate driver integrated circuit can limit package options to packages that include enhanced power dissipation features (e.g., with exposed die pads). Using enhanced power dissipation features on a package that also maintains an isolation barrier increases package size, may require a custom-designed package, and thus increases the cost of the driver product.

[0052] A multi-die distributed packaging technology addresses the power dissipation requirements of a driver product based on the size and associated power dissipation needs of the high-power drive device used in the target application. In at least one embodiment of a driver product, multiple dies are distributed across multiple packages; for example, one package provides current isolation, and at least one other package dissipates power for variable-intensity driver circuitry. Figures 8, 9, and 10 illustrate exemplary embodiments of the multi-die distributed packaging technology.

[0053] In at least one embodiment of a low-power driver product, two integrated circuit chips implement low-voltage control and current isolation, and a third integrated circuit chip includes a variable-intensity driver. All three chips reside in the same package, and the appropriate thermal conductivity requirements for low-power driver applications are achieved without exposing the chip pad package. Referring to FIG8, in at least one embodiment, driver product 700 includes package 702 that houses a primary-side integrated circuit chip 704, an isolation barrier 706, a secondary-side integrated circuit chip 708, and a variable-current driver integrated circuit chip 710. The primary-side integrated circuit chip 704 is isolated from the secondary-side integrated circuit chip 708 by the isolation barrier 706. The primary-side integrated circuit chip 704 receives a control signal CTL (e.g., a pulse width modulation control signal) and transmits the received control signal across the isolation barrier 706 to the secondary-side integrated circuit chip 708. The variable current driver chip 710 drives the low-power system 712 according to the control signal.

[0054] The low-power system 712 includes a small high-power drive, for example, a high-power drive used in low-power applications. Therefore, in the low-power system 712, a single package is sufficient to maintain an isolation barrier and dissipate power generated by the low-voltage control function of the gate driver and the variable current drive of the gate driver. The relatively small high-power drive has a low input capacitance CGATE. The power dissipated by the variable current driver die 710 is relatively low, and a low-cost package containing standard power dissipation characteristics is sufficient to provide an isolation barrier and power dissipation for the primary-side integrated circuit die 704, the secondary-side integrated circuit die 708, and the variable-intensity driver die 710. Communication between the secondary-side integrated circuit die 708 and the variable current driver die 710 includes PWM signals indicating the target on or off state of the external high-power drive and additional configuration, status, and control communication required between the secondary-side integrated circuit die 708 and the variable current driver die 710. In at least one embodiment of the driver product 700, these signal connections are maintained within the package.

[0055] In at least one embodiment, a driver product uses two packages to house an integrated circuit die that provides isolation and drive capability to a medium-sized high-power drive device in an application that consumes more power than a low-power application. A first package houses the integrated circuit die providing isolation and low-voltage control functionality. The first package maintains an isolation barrier and does not have stringent thermal conductivity requirements. A second package with enhanced power dissipation characteristics (e.g., with exposed die pads or external metal pads) houses the variable current driver die. Referring to FIG9, a medium-power system 816 includes a medium-sized high-power drive device with a medium-sized input capacitance C GATE. In this embodiment, a significant amount of power is dissipated by the variable current driver die 710 and may not be properly conducted by a package that does not have enhanced power dissipation characteristics. In at least one embodiment of driver product 800, package 802 is a low-power package with standard power dissipation characteristics and houses an isolation barrier 706, a primary-side integrated circuit die 704, and a secondary-side integrated circuit die 708. Package 810 includes enhanced power dissipation features and houses a variable current driver die 710. In this dual-package embodiment, the received control signals CTL and configuration, status, and control transmission CTRL between the secondary-side integrated circuit die 708 and the variable current driver die 710 utilize external package pins and external coupling. In at least one embodiment of driver product 800, transmission uses parallel logic signals, serial communication protocols (e.g., SPI bus), or combinations thereof. In at least one embodiment of driver product 800, differential transmission is used for inter-package transmission to improve conducted and radiated immunity and reduce conducted and radiated emissions, but single-ended transmission may be used in other embodiments.

[0056] In at least one embodiment, a driver product uses a first package of an integrated circuit die that provides isolation and low-voltage control functions, and two or more power dissipation enhancement packages that enclose a corresponding variable-strength driver stage coupled in parallel, to drive a large high-power drive device. Referring to FIG10, driver product 900 includes a high-power system 916 that includes a relatively large high-power drive device with a relatively large input capacitance C GATE. The power dissipated by the variable current driver die 710 may exceed the capacity of package 810, which includes a chip pad 814 to enhance power dissipation. At least one additional package including chip pad 914 encloses the variable current driver die 910 (which is another embodiment of the variable current driver die). The variable current driver die 710 and the variable current driver die 910 are configured in parallel to drive one of the high-power drive devices in the high-power system 916. Referring to Figure 11, the configuration of variable current driver dies 810 and 910 provides redundancy in the event of one of the variable current driver dies being shorted to ground, rather than by coupling variable current driver dies 810 and 910 in parallel. Redundancy is provided by using two or more variable intensity driver dies in a separate package, which can operate at a reduced system power level in response to a failure of one of the high-power drives in the high-power system 916. Referring to Figures 10 and 11, in addition to enhanced power dissipation, separating the variable current driver dies into separate high-power packages located closer to the corresponding high-power drive also reduces gate current loops. The use of multi-die distributed packaging technology in two or more packages reduces system cost while providing a variable intensity drive solution for different levels of system power requirements.

[0057] Therefore, a variable current drive technique is disclosed that uses a variable intensity driver and associated control to divide a switching process (i.e., a turn-on or turn-off process) of a high-power drive into a multi-stage switching process with multiple stages that can have different driver settings. The use of variable current drive reduces or eliminates the need for external gate resistors for controlling the turn-on and turn-off transitions. Compared to a conventional gate driver method, using multiple current settings during the turn-on or turn-off of a high-power drive improves the turn-on and turn-off process (e.g., improves efficiency, reduces EMI, or reduces drain-to-source voltage VDS and gate-to-source voltage VGS voltage stress). The reduction or elimination of external gate resistors allows the gate driver circuitry to be positioned closer to the high-power drive, thereby reducing the inductance and area of ​​a gate loop (i.e., the area enclosed by the gate current loop). Reducing the inductance of the gate loop reduces ringing of the gate signal. Reducing the area of ​​the gate current loop reduces radiated emissions and improves the radiated immunity of the circuit. Compared to other technologies that use a gate driver with multiple outputs for turning on high-power drives and multiple outputs for turning off high-power drives, variable current drive technology and scalable packaging solutions use fewer pins and fewer external components.

[0058] In at least one embodiment, a method for controlling a high-power drive device includes providing a signal having a first predetermined signal level to an output node during a first stage of a multi-stage transition procedure. The method includes generating a first indication of a first parameter associated with the signal provided to the output node. The method includes generating a second indication of a second parameter associated with the signal provided to the output node. In the first stage, the second parameter is a time elapsed since the start of the first stage. The method includes providing the signal having a second predetermined signal level to the output node during a second stage of the multi-stage transition procedure. The method includes transitioning from the first stage to the second stage based on the first indication and the second indication.

[0059] In at least one embodiment, a system for controlling a high-power drive device includes a driver circuit. The driver circuit includes an output node and a variable intensity driver circuit coupled to the output node. The variable intensity driver circuit is configured to provide a signal to the output node. The signal has an intensity based on a multi-bit digital control signal. The driver circuit includes an indicator circuit configured to generate a first indication of a first parameter associated with the signal. The driver circuit includes a timer circuit configured to generate a second indication of a second parameter associated with the signal. The driver circuit includes a driver controller circuit that generates the multi-bit digital control signal in response to a received control signal and a predetermined setting of a multi-stage transition procedure, the first indication, and the second indication.

[0060] In at least one embodiment, a system for controlling a high-power drive device includes: an output node; a variable intensity driver circuit configured to provide a signal having a signal level based on a multi-bit digital control signal to the output node; and a control circuit configured to generate the multi-bit digital control signal based on a received control signal, a fault indicator signal, a predetermined setting of a multi-stage transition procedure, an indication of a first parameter associated with the signal, and an indication of a second parameter associated with the signal.

[0061] The description of the invention set forth herein is illustrative and not intended to limit the scope of the invention as set forth in the following claims. For example, although the invention has been described in one embodiment of a driver product used in a motor application with one of two on-phase and three off-phases, those skilled in the art will understand that the teachings herein can be utilized in other applications and in other numbers of on-phase or off-phases. Furthermore, although the invention has been described in one embodiment of a variable intensity driver 402 using a current DAC, those skilled in the art will understand that the teachings herein can be utilized in conjunction with other variable intensity driver topologies (e.g., variable intensity drivers including digitally controllable inverter segments). Variations and modifications to the embodiments disclosed herein can be made based on the description set forth herein without departing from the scope of the invention as set forth in the following claims.

[0062] 100: Processor 102: System 104: Voltage Converter 106: Driver 108: High-power drive unit 109: High-power drive unit 120: Motor 130:Isolation barrier 200: Drive Products 201: Primary-side PCB circuit 203: Secondary side accelerator circuit 212: Undervoltage lockout detector 214: Desaturation Detector 216: Fault Logic 219: Buffer 220: Miller Clamp 221: Driver 230:Isolation barrier 250:Terminal 252:Terminal 254:Terminal 256:Terminal 258:Terminal 260:Terminal 262:Terminal 264:Terminal 266:Terminal 268:Terminal 270:Terminal 302: Gate Driver 304: High-power drive unit 306: Inductor 400: Drive Products 402: Variable Intensity Driver 403: Secondary-side integrated circuit 404: Drive controller 406: Comparator 410: Memory 412: Digital to Analog Converter 414: Timer Circuit 420: Gate Driver 421: Current-to-Digital-to-Analog Converter (DAC) 422: Current-to-Digital-to-Analog Converter (DAC) 700: Drive Products 702: Package 704: Primary-side integrated circuit die 706:Isolation barrier 708: Secondary-side integrated circuit die 710: Variable Current Driver Diode 712: Low-power system 800: Drive Products 802: Package 810: Package 814: Crystal Pad 816: Medium Power System 900: Drive Products 910: Variable Current Driver Chip 914: Crystal Pad 916: High-Power System

Claims

1. A method for controlling a high-power drive device, the method comprising: During a first stage of a multi-stage transition procedure, a signal having a first predetermined signal level is provided to an output node; a first indication of a first parameter associated with the signal provided to the output node is generated; a second indication of a second parameter associated with the signal provided to the output node is generated, wherein the second parameter is a time elapsed since the start of the first stage; during a second stage of the multi-stage transition procedure, the signal having a second predetermined signal level is provided to the output node; and a transition from the first stage to the second stage is made based on the first indication and the second indication.

2. The method of claim 1, further comprising the first stage of the multi-stage transition procedure in response to a received control signal changing from a first signal level to a second signal level and entering the multi-stage transition procedure in the absence of a fault condition.

3. The method of claim 2, further comprising delaying the transition from a state providing a signal having a third predetermined signal level to the first stage of the multi-stage transition procedure.

4. The method of claim 1, wherein the signal is a current and the first predetermined signal level is greater than the second predetermined signal level.

5. The method of request item 1, wherein the transition from the first stage to the second stage is in response to the first parameter exceeding a first threshold or the second parameter exceeding a second threshold.

6. The method of claim 5, wherein the multi-stage transition procedure is coupled to a turn-on procedure of the high-power drive device of the output node, wherein in the first stage, the first parameter is a sensed voltage level on the output node, and the first threshold corresponds to a Miller plateau turn-on voltage of the high-power drive device, and the second threshold corresponds to a time limit of the first stage.

7. The method of claim 5, wherein the multi-stage transition procedure is coupled to a shutdown procedure of the high-power drive device of the output node, wherein in the first stage, the first parameter is a sensed voltage level on the output node and the first threshold value corresponds to a Miller plateau shutdown voltage of the high-power drive device, and in the second stage, a third threshold value corresponds to a Miller clamping voltage of the high-power drive device.

8. The method of claim 7, further comprising: During the third stage of one of the multi-stage transition procedures, the signal having a third predetermined signal level is provided to the output node based on the first instruction or the second instruction; and in response to the first parameter being lower than a third predetermined threshold level, the transition from the second stage to the third stage is initiated, wherein the second predetermined signal level is lower than the third predetermined signal level.

9. The method of claim 1, wherein the signal is a current and the method further includes converting a multi-bit digital control signal into the current having the first predetermined signal level, and the conversion includes updating the multi-bit digital control signal from a first value corresponding to the first predetermined signal level to a second value corresponding to the second predetermined signal level.

10. The method of claim 1, wherein the multi-stage transition procedure is an on-state procedure of the high-power drive device or an off-state procedure of the high-power drive device.

11. A system for controlling a high-power drive device, the system comprising: An output node of a driver circuit; a variable intensity driver circuit of the driver circuit coupled to and configured to provide a signal to the output node, the signal having an intensity based on a multi-bit digital control signal; an indicator circuit of the driver circuit configured to generate a first indication of a first parameter associated with the signal; a timer circuit of the driver circuit configured to generate a second indication of a second parameter associated with the signal; and a driver controller circuit of the driver circuit that generates the multi-bit digital control signal in response to a received control signal and a predetermined setting of a multi-stage transition procedure, the first indication, and the second indication.

12. The system of claim 11, wherein the driver controller circuitry further responds to a fault indication signal.

13. The system of claim 11, wherein the signal is a current and the variable intensity driver circuit includes: A first current-to-analog converter circuit configured to generate an on-state voltage includes a first current mirror having a fixed input stage and a first selectively configured output stage, and a first storage capacitor coupled in parallel with a first diode-coupled input device of the fixed input stage, the first storage capacitor being coupled to ground; and a second current-to-analog converter circuit configured to generate an off-state voltage includes a second current mirror having a second fixed input stage and a second selectively configured output stage, and a second storage capacitor coupled in parallel with a second diode-coupled input device of the fixed input stage, the second storage capacitor being coupled to a power node.

14. The system of claim 11 further includes a storage element configured to store a predetermined profile of the multi-stage transition procedure, the predetermined profile including a first control value corresponding to a first target signal level of a first stage of the multi-stage transition procedure, a second control value corresponding to a second target signal level of the multi-stage transition procedure, a first predetermined threshold value and a second predetermined threshold value.

15. The system of claim 14, wherein the multi-stage transition procedure is coupled to a turn-on procedure of the high-power drive device of the output node, and in the first stage of the multi-stage transition procedure, the first parameter is a sensed voltage level on the output node and the second parameter is a time from the start of the first stage, the signal is an output current, the first target signal level is greater than the second target signal level, the first predetermined threshold corresponds to a Miller plateau turn-on voltage of the high-power drive device, and the second predetermined threshold corresponds to a time limit of the first stage.

16. The system of claim 14, wherein the multi-stage transition procedure is coupled to a shutdown procedure of the high-power drive device of the output node, and in the first stage of the multi-stage transition procedure, the first parameter is a sensed voltage level on the output node and the second parameter is a time from the start of the first stage, the signal is an output current and the first target signal level is greater than the second target signal level, the first predetermined threshold corresponds to a Miller plateau shutdown voltage of the high-power drive device, and the second predetermined threshold corresponds to a time limit of the first stage.

17. The system of claim 16, wherein the multi-stage transition procedure includes a third stage, the predetermined setting includes a third control value corresponding to a third target signal level and includes a third predetermined threshold value, the third target signal level being greater than the first target signal level and greater than the second target signal level, and the third predetermined threshold value corresponding to a Miller clamping voltage of the high-power drive device.

18. The system of claim 11, further comprising: A first integrated circuit die and a second integrated circuit die, which implement low-voltage control and isolation features; a third integrated circuit die including the output node, the variable intensity driver circuit and the indicator circuit; and a package that houses the first integrated circuit die, the second integrated circuit die and the third integrated circuit die.

19. The system of claim 11, further comprising: A first integrated circuit die and a second integrated circuit die, which implement low-voltage control and isolation features; a third integrated circuit die, which includes the output node, the variable intensity driver circuit and the indicator circuit; a first package that houses the first integrated circuit die and the second integrated circuit die; and a second package that houses the third integrated circuit die, the first package including standard power dissipation features and the second package including enhanced power dissipation features.

20. The system of claim 11, further comprising: A first integrated circuit die and a second integrated circuit die, which implement low-voltage control and isolation features; a third integrated circuit die, which includes the output node, the variable intensity driver circuit, and the indicator circuit; a fourth integrated circuit die, which includes a second output node, a second variable intensity driver circuit, and a second indicator circuit; a first package that houses the first integrated circuit die and the second integrated circuit die; a second package that houses the third integrated circuit die; and a third package that houses the fourth integrated circuit die, wherein the first package includes standard power dissipation features and the second package and the third package each include enhanced power dissipation features, and the output node is coupled to the high-power drive device, and the second output node is coupled to the high-power drive device or a second high-power drive device.

21. A system for controlling a high-power drive device, the system comprising: One output node; A variable intensity driver circuit configured to provide a signal having a signal level based on a multi-bit digital control signal to the output node; and a control circuit configured to generate the multi-bit digital control signal based on a received control signal, a fault indicator signal, a predetermined setting of a multi-stage transition program, a first indication of a first parameter associated with the signal, and a second indication of a second parameter associated with the signal.

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