Semiconductor memory devices

Abstract

The purpose of this disclosure is to provide a semiconductor memory device that responds to testing of memory that does not rely on the pass / fail determination of all bits. The semiconductor memory device disclosed herein includes: a memory cell array comprising a plurality of memory cells; a readout data output unit that outputs data read from the memory cell array to the outside with an unchanging bit width of m bits; and a defect information acquisition unit that acquires defect information indicating the defect when a defect is detected in the data read from the memory cell array. The defect information acquisition unit outputs defect information using two or more but no more than n bit values, where each bit value is a value used to output to the outside that represents 1 bit of information for each defect number of the data read from the memory cell array, ranging from 0 to n bits (n < m).

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor memory device. [Previous Technology]

[0002] Consider a scenario where a test operation is performed in a semiconductor device having multiple memory groups to detect defects in multiple memory cell groups within each memory group. In this test operation, if multiple test data corresponding to multiple memory cell groups of each memory group are directly output to the outside of the semiconductor device via a data output terminal, the test time increases due to the number of multiple memory cell groups selected for outputting the test data.

[0003] To shorten the testing time, Patent Document 1 proposes a configuration that includes a determination circuit for judging whether the data read from the memory cells is pass / fail, and a circuit for synthesizing the determination data as the result of the inversion circuit and outputting it as test data as the test result. According to the configuration proposed in Patent Document 1, by compressing the test data for each group of memory cells and then synthesizing the determination data for each group, the output test data can be suppressed to below the number of memory cells, thus shortening the testing time. [Prior Art Documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2013-137843 [Summary of the Invention]

[0005] [The problem the invention aims to solve]

[0006] In the configuration described in Patent Document 1, the test data initially read from the memory cell is judged as either having more than one unqualified bit or all bits being qualified (0 / 1), and the result of this judgment is compressed. However, in the configuration described in Patent Document 1, since all bits are judged as unqualified except when all bits are judged as qualified, the number of defects cannot be counted. Therefore, it is difficult to apply to memory where the qualification of all bits is not a prerequisite.

[0007] The purpose of this disclosure is to provide a semiconductor memory device that responds to tests of memory that do not rely on the pass / fail determination of all bits. [Technical Means for Solving the Problem]

[0008] The semiconductor memory device disclosed herein includes: a memory cell array comprising a plurality of memory cells; a readout data output unit that outputs data read from the memory cell array to the outside with an unchanging bit width of m bits; and a defect information acquisition unit that acquires defect information indicating the defect when a defect is detected in the data read from the memory cell array; and the defect information acquisition unit outputs defect information using two or more but less than n bit values, wherein the bit values ​​are values ​​used to output to the outside that the number of defects in the data read from the memory cell array is 0 to n bits (n < m), and varies depending on the number of defects, and each represents 1 bit of information.

Implementation Method

[0010] Hereinafter, embodiments of the present disclosure will be described in detail based on the drawings. In addition, in the following embodiments, repeated descriptions are omitted by marking the same parts with the same symbols.

[0011] Hereinafter, embodiments of the present disclosure will be described in the following order: 1. Overview of the present disclosure 2. Regarding the prior art 3. Regarding embodiments of the present disclosure 4. First variation of the embodiment 4-1. First example of the first variation of the embodiment 4-2. Second example of the first variation of the embodiment 5. Second variation of the embodiment

[0012] [1. Overview of the Disclosure] First, the technology disclosed herein will be described in a general manner. Figure 1 is a schematic diagram showing a memory inspection system to which the technology disclosed herein can be applied.

[0013] As shown in Figure 1, the memory 10 disclosed herein, which is the object of inspection, comprises a plurality of memory cells that serve as units for writing and reading data, and a specific number of each memory cell in the plurality of memory cells constitute a cell array. The memory 10 reads and writes data to the cell array with a data width of m bits. For example, the memory 10 can read and write data with a data width of 16 bits (m=16), 32 bits (m=32), or 64 bits (m=64).

[0014] Connect the tester 20 to the memory 10. The tester 20 is connected to the memory 10, for example, by contacting the terminals (pads) of the memory 10 with probes. The tester 20 sends a write or read instruction, along with the address for the write or read operation, to the memory 10. The memory 10 measures the number of defective data (defective bits) read according to the instruction and address sent by the tester 20.

[0015] Memory 10 outputs defect information indicating defects to tester 20 based on the measurement result of the number of defective data. The defect information is information that the number of defective data read is n (n < m) bits and varies depending on the number of defects. The defect information is sent to tester 20 as two or more but less than m defect information signals, each representing 1 bit of information.

[0016] Thus, the memory 10 disclosed herein outputs defective information as a value that varies for each defective number using n bits, which is smaller than the data width (m bits) for reading and writing data. Therefore, defective numbers up to a number that can be represented by n bits can be detected, and responses can be made to tests of memory that do not rely on the pass / fail determination of all bits.

[0017] [2. Regarding the prior art] Next, prior to the description of the embodiments disclosed herein, the prior art will be described for ease of understanding.

[0018] Figure 2A is a schematic diagram illustrating a method for testing memory using existing technology. In Figure 2A, a plurality of memory modules 10a, each being tested, are connected to a tester 20. Here, each memory module 10a is a DRAM (Dynamic Random Access Memory). In the example of Figure 2A, each memory module 10a has a terminal group 50 containing a plurality of terminals corresponding to IO (Input / Output) with a data width of 16 bits for reading and writing data. Furthermore, each memory module 10a has a 1-bit test terminal 51 for outputting test results.

[0019] The tester 20 sends the instruction to read out, along with the read out address, which is sequentially specified in the address unit of a 16-bit quantity corresponding to the data width of IO, to each memory 10a. Each memory 10a outputs the test result to the test terminal 51 according to the instruction sent by the tester 20, which is "0" when all bits in the memory are passable and "1" when even 1 bit is failable.

[0020] The tester 20 reads the 1-bit output of the test terminal 51 of each memory 10a. By reading the 1-bit output of the tester 20, the pass / fail status of each memory 10a can be determined. Thus, in the prior art, the test result data of all bits of the memory is compressed into 1-bit data, and the pass / fail status of the memory is determined, thereby obtaining the test result of the tester 20.

[0021] Figure 2B is a schematic diagram illustrating a method for inspecting a memory using existing technology, in which a memory 10b, which utilizes existing technology as DRAM, and a logic circuit 40 that uses the memory 10b for processing are co-packaged in a single package, called a mixed memory 30. In the case of a mixed memory 30, since the memory 10b and the logic circuit 40 are directly connected within the package, the data width of the memory 10b10 relative to the IO60 of the logic circuit 40 is, for example, 128 bits.

[0022] Thus, in the hybrid memory 30, since the data width of IO60 of the built-in memory 10b can be set to be very large, the number of terminals required to connect the tester 20 becomes extremely large in order to check all bits of the data width of IO60. Therefore, in the hybrid memory 30, the test result data must be compressed. In the example of FIG2B, the configuration is such that the test result data compressed to 1 bit in memory 10b is output to one terminal provided in the hybrid memory 30.

[0023] However, in recent years, MRAM (Magnetoresistive Random Access Memory) or ReRAM (Resistive Random Access Memory) has attracted attention due to its high operating speed or non-volatility.

[0024] Figure 3 is a schematic diagram showing the macroscopic structure of an MRAM as a semiconductor memory device using the prior art. Furthermore, unless otherwise specified, the macroscopically structured MRAM will be described as an MRAM in the following description. Also, since ReRAM can also adopt the same structure, its description here is omitted.

[0025] In Figure 3, the MRAM 100 includes a plurality of cell arrays 110 arranged in a grid pattern, and a compression circuit 120 for compressing test result data. In the example of Figure 3, the two cell arrays 110 on the left and the two cell arrays 110 on the right are connected to terminals (not shown) via I / O pins 130a and 130b, which have a data width of multiple bits (e.g., 32 bits). Furthermore, in Figure 3, signal lines and terminals indicating commands and addresses by the tester 20 are omitted.

[0026] Buses 130a and 130b are also connected to compression circuit 120. Compression circuit 120 performs an AND or NAND check on each bit of the 64-bit data width (32 bits of bus 130a and 32 bits of bus 130b), outputting a 1-bit test result data. More specifically, compression circuit 120 outputs a "fail" result as test result data when the 64-bit data contains even a 1-bit failure, and outputs a "pass" result as test result data when the 64-bit data does not contain any failures. The 1-bit test result data output from compression circuit 120 is output to the outside of MRAM 100 via a signal line 140 with a 1-bit data width.

[0027] MRAM100 or ReRAM is randomly defective, and the probability that all bits of a plurality of bits at a specified address will become a specific bit value is low. Therefore, it is difficult to compress the test data in the same way as DRAM during the testing of MRAM100 or ReRAM.

[0028] That is, in the configuration shown in Figure 3 above, even if only one cell in each of the plurality of cell arrays 110 is defective, the test result data will still show as unqualified. Therefore, in the randomly generated defective MRAM 100 or ReRAM, the probability of the test result data being qualified is extremely low, and it is difficult to perform proper checks. For example, the MRAM 100 or ReRAM is actually equipped with an error correction circuit that performs error correction according to ECC (Error Correction Code), and the defective digital bits can be corrected by the error correction circuit. Therefore, the test result data is preferably configured to allow the defective digital bits to be set as qualified.

[0029] [3. Regarding the Embodiments of this Disclosure] Next, embodiments of this disclosure will be described. FIG4 is a block diagram showing an example of the configuration of an MRAM (macroscopic structure) semiconductor memory device as an embodiment. The MRAM 100a of the embodiment shown in FIG4, compared with the configuration of the prior art MRAM 100 shown in FIG3, replaces the compression circuit 120 with a defect counter 200. In addition, in FIG4, the signal lines and terminals for indicating instructions and addresses by the tester 20 are omitted.

[0030] Alternatively, the MRAM100a can have an internal error correction circuit for ECC-based error correction. The error correction circuit can be located externally to the MRAM100a. The error correction circuit stops functioning during testing.

[0031] In the example of Figure 4, similar to Figure 3 above, the two cell arrays 110 on the left and the two cell arrays 110 on the right are connected to terminals (not shown) via I / O pins 130a and 130b, which have a data width of multiple bits (e.g., 32 bits). The data read from each cell array 110 is output from these terminals without modification. These terminals and I / O pins function as readout data output units that output the data read from each cell array 110 to an external readout data output unit. Buses 130a and 130b are also connected to the defect counter 200.

[0032] The defect counter 200 counts the number of defective bits for a total data width of 64 bits, for example, the 32-bit data width of bus 130a and the 32-bit data width of bus 130b. The defect counter 200 obtains defect information (defect count) of the counted defective bits. More specifically, the defect counter 200 obtains defect information of signals that are 2 bits or more and n bits or less, which are values ​​that vary depending on the number of defective bits per cell array 110, and are of 0 bits or more and n bits or less. Here, the value n is the value m (e.g., m = 32 × 2 = 64) relative to the total number of bits of the data width of the display buses 130a and 130b, and is a value of [n < m].

[0033] Furthermore, when the number of defective bits is above a threshold, the defect counter 200 acquires overflow information as a discrimination signal to determine that the number of defective bits is above the threshold. As a more specific example, when the number of defective bits exceeds the number that can be represented by n bits, the defect counter 200 acquires a display overflow value (e.g., value [1]) as overflow information. The defect counter 200 includes the acquired overflow information in the defect information and outputs it as test result data.

[0034] As a specific example, if the value n=2, the defect counter 200 can count 0 to 3 defective bits. When the number of defective bits is 0 to 3, the defect counter 200 obtains defect information including a 2-bit value that displays the number of defective bits. The overflow information is set to display a value that does not overflow (e.g., value [0]). On the other hand, when the number of defective bits exceeds 3, the defect counter 200 obtains overflow information that displays an overflow value.

[0035] Thus, the defect counter 200 functions as a defect information acquisition unit that acquires defect information to display defects when defects are detected in the data read from the cell array 110. Furthermore, the defect counter 200 acquires the defect number from the defect information as a bit value from LSB (Least Significant Bit) to n bits.

[0036] Figure 5 is a schematic diagram showing an example of test result data output by corresponding the defect counter 200 of the embodiment with the number of non-conforming items, and comparing it with test result data using the compression circuit 120 of the prior art. In the example of Figure 5, the value n is set to 2, and the threshold for overflow of defective bits is set to 4. That is, the number of defective bits is 4 or more, and overflow is set.

[0037] In Figure 5, row A shows an example of test result data using the prior art, and row B shows an example of test result data in the implementation mode. In the prior art example shown in row A, for a non-conforming number of 0, the test result data is set as qualified, and for non-conforming numbers other than 0, all test result data are set as unqualified.

[0038] In contrast, in the example of the implementation shown in line B, for the number of nonconformities = 0, the defect information in the test result data is qualified (e.g., value [0]); for the number of nonconformities = 1 to 3, the defect information in the test result data is the value indicating the number of nonconformities. If the number of nonconformities is 4 or more, the overflow information in the test result data is the value indicating overflow [overflow].

[0039] That is, the defect counter 200 in the implementation form obtains defect information corresponding to the number of defects = 0 to 2n-1 using n bits of data. Furthermore, when the number of defects is above the threshold (=2n), the defect counter 200 sets the overflow information to the value of the overflow [overflow].

[0040] In the example where n=2, the defect counter 200 obtains the defect number corresponding to the defect number = 0 to 3 using 2 bits of data. When the defect number is above the threshold (=4), the overflow information is set to the overflow value [overflow]. When the overflow information is expressed using 1 bit of data, the defect information is 3 bits of test result data and is output to the outside via a signal line 141 with a data width of 3 bits.

[0041] Thus, by using the defect counter 200 in the application implementation, a response can be made to the testing of memory that does not require the pass / fail determination of all bits. Furthermore, when the value n=2, only 3 signal lines 141 are needed to output the test result data, and the same number of measurements can be obtained from the tester 20.

[0042] Furthermore, the value n can be appropriately set, for example, according to the specifications of the MRAM100a. For example, the value n can be set according to the error correction capability of the ECC applied to the MRAM100a.

[0043] Figure 6 is a circuit diagram showing an example of the configuration of a defect counter 200 in an embodiment. The defect counter 200 shown in Figure 6 is an example with a data width of m bits and a threshold value of [4] relative to the overflow.

[0044] In Figure 6, the defect counter 200 includes, for example, a number of cells 2101, 2102, 2103, ..., 210x, ..., 210m with the same configuration as the number of bits corresponding to the data width (=m bits) in the IO of the MRAM 100a. That is, the defect counter 200 is constructed by repeatedly connecting the cells 2101 to 210m of the pattern of each bit of data read from the cell array 110.

[0045] Therefore, when there is no need to specifically distinguish between each unit 2101 to 210m, unit 210x shall be appropriately described as any unit among each unit 2101 to 210m. Also, when there is no need to specifically distinguish between each unit 2101 to 210m, each unit 2101 to 210m shall sometimes be representatively described as unit 210. Furthermore, in FIG6, the direction on the right side of the figure is designated as the rear segment, and the direction on the left side is designated as the front segment. In addition, in the following, the value [1] shall correspond to the high state of the signal, and the value [0] shall correspond to the low state of the signal.

[0046] Unit 210x includes 3 XOR circuits 220, 221 and 222, 2 AND circuits 230 and 231, and 1 OR circuit 240.

[0047] The XOR circuit 220 inputs data (Data)[x] of bit position x of each bit of bus 130a and 130b at one input terminal, and inputs the expected value [x] corresponding to the data [x] at the other input terminal.

[0048] Here, the expected value [x] of the embodiment shows the expected value of the data [x] at that bit position x. For example, prior to the counting of defective numbers by the defective number counter 200, a specific value (e.g., value [1]) is written to each memory cell contained in the cell array 110 of the MRAM 100a. In this case, the data expected to be read from each memory cell is equal to the specific value. The specific value in this case is the expected value [x]. That is, the expected value in the embodiment is a value with a different concept from the expected value in probability.

[0049] Figure 7 is a schematic diagram showing the truth value table of expected value and data in the implementation mode. As shown in Figure 7, it is considered acceptable when the expected value and data are consistent, and unacceptable when the expected value and data are different. The output value [0] of the XOR circuit 220 is used to display the acceptable value, and the output value [1] is used to display the unacceptable value.

[0050] In unit 210x, the XOR circuit 220 outputs a value [0] when the expected value [x] matches the data [x], and outputs a value [1] when they differ. Thus, the XOR circuit 220 functions as a comparator comparing the data [x] read from the cell array 110 with the expected value [x] set for that data [x]. When the output of the XOR circuit 220 displays a value [1], it can be determined that the memory cell in the memory cell of the object being inspected that corresponds to the data [x] is defective. Thus, when the expected value [x] differs from the data [x], the XOR circuit 220 sets the output to the value [1] and enables a signal indicating that the data [x] is defective.

[0051] The output of XOR circuit 220 in unit 210x is input to one input terminal of XOR circuit 221 and AND circuit 230 in unit 210x. The output of XOR circuit 221 in unit 210x-1 is input to the other input terminal of XOR circuit 221 and AND circuit 230. In addition, in FIG6, in unit 2101 of the first segment, the value [0] is input from terminal 2501 to the other input terminal of XOR circuit 221. Similarly, in unit 2101, the value [0] is input from terminal 2502 to the other input terminal of XOR circuit 222 described later.

[0052] The output of the XOR circuit 221 in unit 210x is input to another input terminal of the XOR circuit 221 in the subsequent unit 201x+1. Also, when unit 210x is the last unit 210m, the output of the XOR circuit 221 is output from the defective number counter 200 as the value of the 0th bit (bit[0]) of the defective number counter 200.

[0053] The output of the XOR circuit 221 in unit 210x is as follows: (1) If the expected value [x] is consistent with the data [x], and the output of the XOR circuit 221 in the preceding unit 210x-1 (terminal 2501 in unit 2101) is [0], then the output value is [0]. (2) If the expected value [x] is consistent with the data [x], and the output of the XOR circuit 221 in the preceding unit 210x-1 (other than unit 2101) is [1], then the output value is [1]. (3) If the expected value [x] is different from the data [x], and the output of the XOR circuit 221 in the preceding unit 210x-1 is [0], then the output value is [1]. (4) If the expected value [x] of the XOR circuit 221 is different from the data [x], and the output of the XOR circuit 221 in the previous unit 210x-1 is the value [1], then the output value is [0].

[0054] The output of the AND circuit 230 in unit 210x is as follows: (1) If the expected value [x] is consistent with the data [x], and the output of the XOR circuit 221 in the preceding unit 210x-1 (terminal 2501 in unit 2101) is [0], then the output value of the AND circuit 230 is [0]. (2) If the expected value [x] is consistent with the data [x], and the output of the XOR circuit 221 in the preceding unit 210x-1 (other than unit 2101) is [1], then the output value of the AND circuit 230 is [0]. (3) If the expected value [x] is different from the data [x], and the output of the XOR circuit 221 in the preceding unit 210x-1 is [0], then the output value of the AND circuit 230 is [0]. (4) If the expected value [x] of AND circuit 230 is different from the data [x], and the output of XOR circuit 221 in the front unit 210x-1 is the value [1], then the output value is [1].

[0055] The output of the AND circuit 230 in unit 210x is input to one of the input terminals of the XOR circuit 222 and the AND circuit 231 in unit 210x. The output of the XOR circuit 222 in the previous unit 210x-1 is input to the other input terminal of the XOR circuit 222 and the AND circuit 231. In addition, in FIG6, in the first unit 2101, the value [0] is input from terminal 2501 to the other input terminal of the XOR circuit.

[0056] The XOR circuit 222 and AND circuit 231 in unit 210x take the output of AND circuit 230 and the output of XOR circuit 222 in the previous unit 210x-1 as inputs, and operate in the same way as the XOR circuit 221 and AND circuit 230 mentioned above.

[0057] That is, the output of the XOR circuit 222 in unit 210x is input to another input terminal of the XOR circuit 222 in the subsequent unit 201x+1. Also, when unit 210x is the last unit 210m, the output of the XOR circuit 222 is output from the defective number counter 200 as the value of the first bit (bit[1]) of the defective number counter 200.

[0058] In the defective number counter 200, when the AND circuit 230 in unit 210x is different from the expected value [x] and the data [x], and when the expected value is different from the data in any unit 210 preceding unit 210x, the output value is [1]. Furthermore, when the output of the AND circuit 231 in unit 210x is the value [1], and when the output of the AND circuit 230 in any unit 210 preceding unit 210x is different from the output of the XOR circuit 222, the output value is [1].

[0059] That is, in unit 210x, the number of cases where the expected value differs from the data in each unit 210 preceding unit 210x, i.e., the defect number, is added together. The added defect number is output from XOR circuit 221 with the value of the 0th bit and from XOR circuit 222 with the value of the 1st bit, respectively, as a binary value.

[0060] The output of the AND circuit 231 in unit 210x is input to one input terminal of the OR circuit 240. The output of the OR circuit 240 in the previous unit 210x-1 is input to the other input terminal of the OR circuit 240. Here, in Figure 6, in the first unit 2101, the value [0] is input from terminal 2503 to the other input terminal of the OR circuit 240. Also, when unit 210x is the last unit 210m, the output of the OR circuit 240 is output from the defective number counter 200 as overflow information [overflow].

[0061] That is, if the output of the AND circuit 231 is the value [1] in at least one of the units 210 in each of the units 2101 to 210m, then the OR circuit 240 of the last unit 210m outputs the overflow information [overflow] of the value [1].

[0062] Thus, the overflow information [overflow] is the value [1] when a bit overflow occurs in the AND circuits 230 and 231 in at least one of the units 2101 to 210m. Therefore, the output of the OR circuit 240 in the last unit 210m can be considered as the second bit (topmost bit) of the test result data together with the 0th bit (bit [0]) and the 1st bit (bit [1]). Since the value of the topmost bit is output by the OR circuit 240 connected in series through the units 2101 to 210m, once it increases to the value [1], it will not be reversed even if it is added due to a fault.

[0063] Figure 8 is a schematic diagram showing the result of an example of the operation of the defect counter 200 in the configuration shown in Figure 6. Figure 8 also shows an example with values ​​m=5, n=2, and the threshold relative to the overflow set to [4]. That is, Figure 8 shows an example of the simulation result when five units 210 are connected in the configuration of Figure 6. In each waveform of Figure 8, the high state displays the value [1], and the low state displays the value [0]. Furthermore, the expected value [0] (Low) is input to each unit 210.

[0064] The symbols a to f in the figure show the status corresponding to the combination of data (Data) [0] to [4] input to the 5 units 210. Symbol a shows that any one of the data [0] to [4] is the value [0] (Low), which is a qualified status. Symbols b to f show that 1 to 4 of the data [1] to [4] are the value [1], which is a disqualified status.

[0065] The defect counter 200 counts the number of defects when the value read from each memory cell (data [0] to [4]) is different from the expected value [0], and outputs the count result in binary from the 0th bit (bit [0]) and the 1st bit (bit [1]). It can be seen that when the number of defects is the threshold, that is, 4 or more, the overflow information [overflow] is the value [1]. That is, when the overflow information [overflow] is set to the 2nd bit relative to the 0th and 1st bits, when there are 4 or more defects, the count result is fixed at the threshold [4].

[0066] Thus, the defect counter 200 as a whole is configured as an adder that adds the defect numbers in each bit read simultaneously from the data width (=m bits) of the IO of the MRAM 100a. Furthermore, when the added defect number is 0 or has not reached the threshold, the adder outputs a value that varies for each defect number, and when the defect number is above the threshold, the result of adding the defect numbers is fixed at the threshold.

[0067] Thus, by using the defect counter 200 in the application embodiment, the number of defects can be counted during the testing of memory such as MRAM or ReRAM where the pass / fail status of all bits is not a prerequisite. Since the defect counter 200 in the application embodiment can output defect information in fewer bits than the data width of the memory's I / O, the test count can be obtained, and the test time can be shortened. Furthermore, therefore, while the number of defects can be counted, the number of terminals used to output test result data to the tester 20 can be reduced.

[0068] Furthermore, since the defect counter 200 in the embodiment is composed of a repeating pattern of cell 210 repeated on each IO (each bit), it is easy to expand the data width of the IO accordingly. In addition, in cell 210, the defect count and threshold can be changed by adding a combination circuit of XOR circuit 221 and AND circuit 230.

[0069] [4. First variation of the implementation] Next, the first variation of the implementation disclosed herein will be described. The first variation of the implementation is an example of grouping memory I / O and setting expected values ​​in the fault count counter 200 according to the grouped groups.

[0070] (4-1. First example of the first variation of the implementation) First, the first example of the first variation of the implementation will be explained. Figure 9 is a schematic diagram used to explain the first example of the first variation of the implementation. In Figure 9, a configuration example is shown in which the defect counter 200 has a value m=5, a value n=2, and the threshold relative to the overflow is set to [4].

[0071] In the example of Figure 9, in this configuration, each bit of IO is grouped into two groups: group 260a of data [0] to [2] and group 260b of data [3] and [4].

[0072] In the example of FIG9, the XOR circuit 220 corresponding to units 2101 to 2103 of group 260a is input with an expected value [X0] (e.g., value [0]). On the other hand, the XOR circuit 220 corresponding to units 2104 and 2105 of group 260b is input with an expected value [X1] (e.g., value [1]) that is different from the expected value [X0].

[0073] In the example of Figure 9, adjacent bits of IO are grouped together, but this is not limited to this example. For example, in IO, it can be grouped into groups of odd-numbered bits and groups of even-numbered bits. It is not limited to this, and it can also be grouped according to any combination of bits in IO.

[0074] (4-2. Second Example of the First Variation of the Implementation) Next, the second example of the first variation of the implementation will be explained. In the first example of the first variation of the above-described implementation, the bits of the IO are grouped based on the hardware configuration. In contrast, in the second example of the first variation of the implementation, the bits of the IO are grouped based on the logic configuration of the memory, and the expected value is set according to the group.

[0075] Figure 10 is a schematic diagram illustrating the second example of the first variation of the implementation. In Figure 10, the MRAM100b (macrostructure) serves as the logical constituent unit of the memory region, comprising four groups 150(A1), 150(A2), 150(A3), and 150(A4). These groups 150(A1), 150(A2), 150(A3), and 150(A4) can be considered as groups of the cell array 110 based on logical structure. In this second example, each of the groups 150(A1), 150(A2), 150(A3), and 150(A4) is treated as a group, and an expected value is set according to the group.

[0076] In the example of Figure 10, the expected value [A1] is set for the group of IOs corresponding to group 150 (A1), and the expected value [A2] is set for the group of IOs corresponding to group 150 (A2). Also, the expected value [A3] is set for the group of IOs corresponding to group 150 (A3), and the expected value [A4] is set for the group of IOs corresponding to group 150 (A4). In this case, as an example, various combinations of expected values ​​corresponding to each group are considered, with expected values ​​[A1] and [A3] being values ​​[0] and expected values ​​[A2] and [A4] being values ​​[1].

[0077] As described in the first and second examples of the first variation of the implementation, in the defect counter 200, more detailed testing can be performed by setting the expected value according to the grouping of each bit of IO.

[0078] [5. Second Variation of Embodiment] Next, a second variation of the embodiment will be described. In the above embodiment, the memory I / O terminals and the terminal for outputting test result data of the defect counter 200 are separately provided in the MRAM 100a. In contrast, in the second variation of the embodiment, the memory I / O terminals and the terminal for outputting test result data are shared.

[0079] Figure 11 is a schematic diagram illustrating the second variation of the embodiment. In Figure 11, the MRAM 100c shares a terminal group 160 containing a plurality of terminals with the IOs corresponding to buses 130a and 130b and the signal line 141 for the test result data of the output defect counter 200. For example, the MRAM 100c connects each bit of the IO to each of the plurality of terminals contained in the terminal group 160, and connects each bit of the signal line 141 to any terminal among the plurality of terminals contained in the terminal group 160.

[0080] In this way, by sharing the I / O terminals of the memory and the test result output terminals, the overall number of terminals of the MRAM100c can be reduced.

[0081] Furthermore, although the application of the technology of the embodiment to a single semiconductor memory device has been described above, the technology of the embodiment can also be applied to semiconductor memory devices with other configurations. For example, the technology of the embodiment can be applied to the hybrid memory 30 described using FIG2B. In this case, the defect counter 200 described in the embodiment is provided on the memory 10b mounted on the hybrid memory 30.

[0082] Furthermore, although it has been explained above that the technology of the embodiment is applied to semiconductor memory devices such as MRAM or ReRAM, which are not based on the premise that all bits are qualified, this is not limited to this example. That is, the technology of the embodiment can also be applied to semiconductor memory devices such as DRAM, which are based on the premise that all bits are qualified.

[0083] Furthermore, the effects described in this instruction manual are for illustrative purposes only and are not limited to other effects.

[0084] Alternatively, the present technology may also be configured as follows. (1) A semiconductor memory device comprising: a memory cell array including a plurality of memory cells; a readout data output unit that outputs data read from the memory cell array to the outside with an unchanging bit width of m bits; and a defect information acquisition unit that, when a defect is detected in the data read from the memory cell array, acquires defect information representing the defect; and the defect information acquisition unit outputs defect information by means of two or more and n or fewer bit values, wherein the bit values ​​are used to output to the outside a defect number of data read from the memory cell array that is 0 to n bits (n < m) bits, and varies depending on the defect number, and each bit represents 1 bit of information. (2) The semiconductor memory device described in (1) above, wherein the defect information acquisition unit acquires bit values ​​representing the number of defects from LSB (Least Significant Bit) to the number of bits of n bits. (3) In the semiconductor memory device described in (2) above, the defect information acquisition unit outputs a discrimination signal when the number of defects exceeds the number that can be expressed in n bits. (4) In the semiconductor memory device described in any one of (1) to (3) above, the defect information acquisition unit does not reverse the value of the topmost bit when detecting a defect while the value of the topmost bit in the defect information is increasing. (5) In the semiconductor memory device described in any one of (1) to (4) above, the defect information acquisition unit includes an adder that counts the defects contained in the data read simultaneously from the memory cell array. (6) In the semiconductor memory device described in (5) above, the adder is configured by repeating the pattern of each bit of the data read from the memory cell array. (7) The semiconductor memory device described in any one of (1) to (6) above, wherein the defective information acquisition unit includes: a comparator that compares the data read from the memory cell array with a pre-set expected value for the read data; and when the comparison result of the comparator shows that the read data is different from the expected value, a signal indicating that the read data is defective is activated. (8) The semiconductor memory device described in (7) above, wherein the defective information acquisition unit sets the expected value corresponding to each of the plurality of groups after the data read simultaneously from the memory cell array is grouped. (9) The semiconductor memory device described in (7) above, wherein the defective information acquisition unit sets the expected value corresponding to each of the plurality of groups after the memory cell array is grouped based on logic configuration. (10) The semiconductor memory device described in any one of (1) to (9) above, wherein the output terminal of the defective information acquisition unit for outputting the defective information is shared with the output terminal of the read data output unit for outputting data.(11) The semiconductor memory device described in any one of (1) to (10) above further includes: a logic circuit connected to the readout data output unit. (12) The semiconductor memory device described in any one of (1) to (11) above, wherein the memory cell uses a resistance-changing element as a memory element for storing data. (13) The semiconductor memory device described in any one of (1) to (12) above, wherein the memory cell uses a magnetic resistive element as a memory element for storing data. [Simplified Explanation of the Diagram]

[0009] Figure 1 is a schematic diagram showing a memory inspection system to which the technology disclosed herein can be applied. Figure 2A is a schematic diagram illustrating a memory inspection method using the prior art. Figure 2B is a schematic diagram illustrating a memory inspection method for mixed-load memory using the prior art. Figure 3 is a schematic diagram showing the macroscopic structure of MRAM using the prior art. Figure 4 is a block diagram showing an example of the configuration of an MRAM (macroscopic structure) in a semiconductor memory device as an embodiment. Figure 5 is a schematic diagram showing an example of test result data output by a defective counter based on the number of defective items in the embodiment, compared with test result data from a compression circuit using the prior art. Figure 6 is a circuit diagram showing an example of the configuration of a defective counter in the embodiment. Figure 7 is a schematic diagram showing a table of expected values ​​and true values ​​of data in the embodiment. Figure 8 is a schematic diagram showing the result of an example of the operation of a defective counter in the embodiment. Figure 9 is a schematic diagram illustrating the first example of the first variation of the implementation. Figure 10 is a schematic diagram illustrating the second example of the first variation of the implementation. Figure 11 is a schematic diagram illustrating the second example of the implementation.

Claims

1. A semiconductor memory device comprising: a memory including a memory cell array, wherein the memory cell array includes a plurality of memory cells, and the memory is configured to read data from the memory cell array; a read data output unit configured to output the read data without modification, wherein the read data has a bit width of m bits; and a defect information acquisition unit configured to: detect at least one of the defects in the read data; acquire defect information representing the at least one of the defects; and output the defect information, wherein the defect information acquisition unit includes an adder configured to: determine the number of defects in the read data; and control the number of defects such that the number of defects is less than or equal to a threshold, wherein the number of defects in the read data is 0 to n bits, n is less than m, and the defect information includes individual values ​​of each of the defects. Each of the aforementioned defects corresponds to 2 to n bit values, and each of the 2 to n bit values ​​represents 1 bit of information of each of the aforementioned defects.

2. The semiconductor memory device of claim 1, wherein the defect information acquisition unit is further configured to acquire a plurality of bit values ​​representing the number of defects from LSB (Least Significant Bit) to the nth bit value.

3. The semiconductor memory device of claim 2, wherein the defect information acquisition unit is further configured to output a discrimination signal based on the number of defects exceeding the threshold, and the threshold is associated with the n bits.

4. The semiconductor memory device of claim 1, wherein the defect information acquisition unit is further configured to: detect at least one of the defects according to the increment of the value of the top-order bit, wherein the defect information includes the value of the top-order bit; and maintain the value of the top-order bit according to the increment of the value of the top-order bit.

5. The semiconductor memory device of claim 1, wherein the adder is further configured to: determine the number of defects contained in the readout data simultaneously read from the memory cell array.

6. The semiconductor memory device of claim 5, wherein the adder comprises: a repeating pattern for each bit of the readout data from the memory cell array.

7. The semiconductor memory device of claim 1, wherein the defect information acquisition unit further includes: a comparator configured to: set an expected value for the read data; compare the read data with the expected value for the read data; generate a comparison result representing the difference between the read data and the expected value based on the comparison; and enable a signal indicating that the read data is defective based on the comparison result showing that the read data is different from the expected value.

8. The semiconductor memory device of claim 7, wherein the aforementioned defective information acquisition unit is further configured to: set the aforementioned expectation value based on each of the plurality of groups of the aforementioned readout data, and the aforementioned readout data is read simultaneously from the aforementioned memory cell array.

9. The semiconductor memory device of claim 7, wherein the aforementioned defective information acquisition unit is further configured to: set the aforementioned expectation value according to each of the plurality of groups of the read data, and the read data is grouped into the plurality of groups based on logical configuration.

10. The semiconductor memory device of claim 1, wherein the output terminal of the aforementioned defective information acquisition unit is shared with the output terminal of the aforementioned readout data output unit, the aforementioned defective information acquisition unit is further configured to output the aforementioned defective information via the aforementioned output terminal of the aforementioned defective information acquisition unit, and the aforementioned readout data output unit is further configured to output the aforementioned output data via the aforementioned output terminal of the aforementioned readout data output unit.

11. The semiconductor memory device of claim 1 further includes: a logic circuit connected to the readout data output unit described above.

12. The semiconductor memory device of claim 1, wherein each of the plurality of memory cells is configured such that the read data is stored in a resistance-changing element that serves as a memory element.

13. The semiconductor memory device of claim 1, wherein each of the plurality of memory cells is configured such that the read data is stored in a magnetic resistive element serving as a memory element.

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