Glass package core with planar structures

Abstract

The embodiments described herein may relate to equipment, processes, and techniques associated with glass interposers or substrates that can be formed using glass etching processes to achieve highly integrated modules. Planar structures, which may be vertical plane structures, created within the glass interposer can be used to provide shielding for conductive vias in the glass interposer, thereby increasing signal density within the glass substrate and reducing crosstalk. Other embodiments may be described and / or claimed.

Description

[Technical Field]

[0001] The embodiments disclosed herein generally relate to the field of semiconductor packaging, and in particular to planar structures within the core of a semiconductor package. [Previous Technology]

[0002] The continued growth of virtual machines and cloud computing will continue to increase the demand for high-speed input / output (I / O) between the package and the substrate. [Summary of the Invention]

[0003] and

Implementation Method

[0014] The embodiments described herein may relate to equipment, processes, and techniques for manufacturing glass substrates including through-holes and planes. In embodiments, the glass substrate may be a thin glass substrate and may have fine-pitch through-holes and planes of any shape formed in the substrate. In embodiments, the substrate is used as part of an encapsulation to achieve a structure in which the silicon grains can be closely proximate each other. In embodiments, silicon grains may be directly mounted onto the glass substrate, and in these embodiments the glass substrate may also be referred to as a glass interposer to also enable fine-pitch integration with the silicon grains.

[0015] Embodiments may include a glass interposer layer, which can be used as a core or interposer layer in a highly integrated system within a module. The glass core may include a plurality of vias and planes formed using the laser-assisted etching technique described herein. In embodiments, the vias may be separated by vertical planes and / or trench vias for signal isolation. In embodiments, the vias may have a high aspect ratio, for example, a diameter as small as 5 µm on a 100 µm thick substrate. As described elsewhere herein, a high via density within the core or interposer layer can further enable a structure in which grains are assembled on different sides of the glass core or interposer layer.

[0016] Compared to legacy packages, these embodiments can produce packages with a smaller overall form factor, higher bandwidth density, higher signal isolation, and limited crosstalk. Furthermore, these embodiments can facilitate chip de-assembly and re-connection. Therefore, highly integrated modules can be achieved on glass core packages with vertical and / or planar structures. These implementations may be particularly useful for client devices, handheld devices, wearable devices, and portable devices.

[0017] Three-dimensional (3D) heterogeneous integration enables various grains to be close to each other within a module or on a package substrate. In legacy structures, an interposer is required to achieve dense interconnection between different grains, where the legacy interposer may contain silicon as the substrate material. In legacy implementations, the liner capacitance associated with doped silicon limits frequency bandwidth and significantly increases electrical or signal loss in modules using silicon as the interposer. In legacy implementations, low-doped silicon is not affected by the liner capacitance, but can exhibit excessive crosstalk or coupling between signals carried by silicon vias.

[0018] The embodiments described herein are applicable to glass interposers for achieving highly integrated modules using the glass etching process described herein. The glass etching process described herein can be used to create planar structures, which can be vertical plane structures within a glass substrate, to increase density integration within the glass substrate and reduce crosstalk, improve signal integrity, power delivery, and EMI.

[0019] Compared to laser-assisted etching processes, one or more laser sources followed by wet etching can be used to create through-holes or trenches in glass panels or glass wafers. Using these laser techniques, vias with small diameters, such as on the order of less than 10 µm, can be created and spaced apart with a pitch of approximately 50 µm or less. Other vias with different diameters can be created. These vias can later be electroplated or filled to create electrical paths through the bridge. These techniques can be used to create vias with high aspect ratios (e.g., 10:1, 20:1, 40:1, or 50:1) in glass wafers or panels. These techniques can also be used to create vertical plane structures within glass substrates. Due to the fine pitch of the vias, more signals can pass through the BGA field and package core at a higher density, and the frequency range can be expanded, enabling higher bandwidth communications. Furthermore, these techniques can reduce or eliminate impedance mismatch, which in older implementations might have limited the frequency bandwidth of signals transmitted through the package BGA interface.

[0020] Reference is made in the following detailed description to the accompanying drawings, which form part of this document, wherein similar numerals denote similar parts, and wherein the subject matter of the invention can be achieved by way of illustration of embodiments. It should be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the invention. Therefore, the following detailed description should not be considered limiting, and the scope of the embodiments is defined by the appended claims and their equivalents.

[0021] For the purposes of this invention, the term "A and / or B" means (A), (B), or (A and B). For the purposes of this invention, the term "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0022] The description may use perspective-based descriptions, such as top / bottom, inside / outside, above / below, etc. These descriptions are only used to facilitate discussion and are not intended to limit the application of the embodiments described herein to any particular orientation.

[0023] The description may use the terms "in one embodiment" or "in an embodiment," which may refer to one or more identical or different embodiments. In addition, the terms "comprising," "including," and "having" are synonymous in their use in the embodiments of the present invention.

[0024] The term "coupled with" and its derivatives may be used herein. "Coupled" may mean one or more of the following: "Coupled" may mean two or more elements in direct physical or electrical contact. However, "coupled" may also mean two or more elements in indirect contact with each other, but still cooperating or interacting with each other, and may mean one or more other elements coupled or connected between the mutually coupled elements. The term "directly coupled" may mean two or more elements in direct contact.

[0025] The various operations can be described sequentially as a plurality of discrete operations in a manner that best facilitates understanding of the requested object. However, the order of description should not be interpreted as implying that these operations necessarily depend on the order.

[0026] As used herein, the term "module" may refer to, be a part of, or include the following: ASIC, electronic circuitry, processor (common, dedicated, or grouped) and / or memory (common, dedicated, or grouped) executing one or more software or firmware programs, combinational logic circuitry and / or other suitable components providing the described functionality.

[0027] The various figures herein may depict one or more layers of one or more package components. The layers described herein are examples of the relative positions of layers of different package components. These layers are depicted for illustrative purposes and are not drawn to scale. Therefore, the relative sizes of the layers should not be assumed from the figures, and sizes, thicknesses, or dimensions may be assumed only in some embodiments specifically pointed out or discussed.

[0028] Figure 1 illustrates several examples of laser-assisted etching (referred to herein as "LEGIT") in a glass interconnect process according to an embodiment. One application of LEGIT technology is to provide alternative substrate core materials for legacy copper foil substrates (CCLs) used in semiconductor packages for implementing products such as servers, graphics, clients, and 5G. Hollow shapes can be formed in a glass substrate by using laser-assisted etching, crack-free, high-density through-hole drilling. In the embodiments, different process parameters can be adjusted to achieve drilling of various shapes and depths, thereby opening the door to innovative devices, structures, processes, and designs in glass. Embodiments, such as the bridge discussed herein, can also utilize these techniques.

[0029] Figure 100 illustrates a high-order process flow for creating through-holes or blind vias (or trenches) in a microelectronic packaging substrate (e.g., glass) using LEGIT. The resulting glass volume / shape with laser-induced morphological variations is then selectively etched to create trenches, through-holes, or voids that can be filled with conductive material. Through-holes 112 are created by laser pulses from two laser sources 102, 104 on opposite sides of a glass wafer 106. As used herein, through-holes and through-vias refer to holes or vias that begin on one side of the glass / substrate and end on the other. Blind holes and blind vias refer to holes or vias that begin on the substrate surface and partially stop inside the substrate. In an embodiment, laser pulses from the two laser sources 102, 104 are applied vertically to the glass wafer 106 to induce morphological variations 108 in the glass upon encountering the laser pulses, which may also be referred to as structural variations. This morphological variation 108 includes variations in the glass molecular structure to make it easier to etch away (remove a portion of the glass). In an embodiment, a wet etching process can be used.

[0030] Figure 120 shows the advanced process flow for a double-blind shape. The double-blind shapes 132, 133 can be established by laser pulses from two laser sources 122, 124, which are similar to laser sources 102, 104, located on opposite sides of a glass wafer 126, which is similar to glass wafer 106. In this example, the laser pulse energy and / or laser pulse exposure time from the two laser sources 122, 124 can be adjusted. This may result in morphological variations 128, 129 in the glass 126, making it easier to etch away portions of the glass. In this embodiment, a wet etching process can be used.

[0031] Figure 140 illustrates a high-order process flow for a single-blind shape, which may also be referred to as a trench. In this example, a single laser source 142 delivers laser pulses to a glass wafer 146 to create morphological variations 148 in the glass 146. As described above, these morphological variations make it easier to etch away a portion of the glass 152. In this embodiment, a wet etching process may be used.

[0032] Figure 160 illustrates an advanced process flow for a through-hole shape. In this example, a single laser source 162 applies a laser pulse to glass 166 to create a morphological variation 168 in glass 166, which makes it easier to etch away a portion of glass 172. As shown here, the laser pulse energy and / or laser pulse exposure time from laser source 162 are adjusted to create an etched portion 172 that fully extends through glass 166.

[0033] As shown in Figure 1, although the embodiments show laser sources 102, 104, 122, 124, 142, and 162 as perpendicular to the surfaces of glass 106, 126, 146, and 166, in these embodiments, the laser sources can be positioned at an angle to the glass surface, with varying pulse energy and / or pulse exposure time, to form diagonal through-holes or trenches, or to shape through-holes, such as 112 and 172, for example, making them cylindrical, conical, or incorporating other features. Furthermore, since the etching of glass largely depends on its chemical composition, changing the glass type may also result in different features appearing within the through-holes or trenches.

[0034] In an embodiment using the process described in FIG. 1, through-hole vias 112, 172 with diameters less than 10 µm can be created, and can have an aspect ratio of 40:1 to 50:1. This allows for a higher density of vias within the glass, configured close to each other with fine pitch. In an embodiment, the pitch can be 50 µm or less. After creating the vias or trenches, a metallization process can be applied to create conductive paths through the vias or trenches, for example, plated vias (PTH). Using these techniques, finer-pitch vias will produce better signal strength, allowing more input / output signals to pass through the glass wafer and other coupling components, such as the substrate.

[0035] FIG2 illustrates a side view of a package having a glass core with multiple planar structures according to various embodiments, wherein a die is attached to the glass core. Package 200 is a side view having a glass core 202, the glass core 202 including a plane 204 established within the glass core 202. In embodiments, plane 204 extends from a first side to a second side opposite to the first side of the glass core 202 and may extend through the width of the glass core 202. In embodiments, plane 204 may be a vertical plane. In embodiments, plane 204 may be filled with a conductive material to provide electromagnetic interference (EMI) isolation from other electrical features within the glass core 202, particularly the conductive via 206, which will be discussed in more detail below. In embodiments, the conductive material may comprise copper, gold, tin, aluminum, or some other suitable conductive material.

[0036] The glass core 202 may include one or more conductive vias 206 to electrically couple a first side and a second side of the glass core 202. In an embodiment, the one or more vias 206 may be located between two planes 204 to provide shielding for the vias 206. In an embodiment, the planes 204 may be electrically coupled to a ground in the package 200 to enhance the shielding properties of the planes 204. In an embodiment, some planes 204 may be used for power transmission to supply power, for example, to supply power to one or more dies.

[0037] In an embodiment, one or more wires 208 may be coupled to the surface of the glass core 202. In an embodiment, the wires 208 may be disposed in trenches (not shown) on the surface of the glass core 202 such that the top of the wires 208 is uniformly horizontal with respect to the surface of the glass core 202. In an embodiment, the wires 208 may be used as a redistribution layer or as an interconnection between grains (e.g., grains 220, 222) on the same or opposite sides of the glass core 202 (as shown in FIG. 5). In an embodiment, the grains 220, 222 may be computing grains, computing grain complexes, patterning grains, storage grains, communication grains, etc.

[0038] In an embodiment, the first RDL 210 may be coupled to a first side of the glass core 202, and the second RDL 212 may be coupled to a second side of the glass core 202 opposite to the first side. RDLs 210 and 212 may comprise multiple layers of metal, wherein different layers may be separated by a non-conductive dielectric material. These metal layers may serve as redistribution layers for signal and power transmission. Electrical features within RDLs 210 and 212 may be electrically coupled to the plane 204 and the conductive via 206. In an embodiment, RDL 212 may include interconnects, such as solder balls 214 on one side of RDL 212, for electrical and physical coupling to a substrate or some other device (not shown).

[0039] In an embodiment, one or more grains 218, 220, 222 may be coupled to the glass core 202. Grain 218 may be electrically and physically coupled to the surface of RDL 210 on the first side of the glass core 202. Grains 220, 222 may be electrically and physically coupled to the glass core 202 within cavities 224, 226 of RDL 210. In an embodiment, grains 220, 222 may be electrically coupled to one or more vias 206 and / or planes 204.

[0040] FIG3 illustrates a side view of a package having a glass core with multiple planar structures according to various embodiments, with wiring features on the surface of the glass core. Package 300 may be similar to package 200 of FIG2, including glass core 302, planar surface 304, conductive via 306 and RDL 310, 312, which may be similar to glass core 202, planar surface 204, conductive via 206 and RDL 210, 212 of FIG2.

[0041] Package 300 illustrates the connection between dies 320 and 322 on the same side of the glass core 302. Signals can be routed on the glass core 302 using conductive vias 306 and through wires 307, which may be similar to wire 208 in Figure 2, to electrically couple the dies 320 and 322 on both sides of the glass core 302. In an embodiment, the horizontal ground plane 311 in RDL 310 and the horizontal ground plane 313 in RDL 312 can be used in conjunction with plane 304 to provide shielding and impedance control.

[0042] In the embodiments, RDL 310, 312 can be formed using semiconductor manufacturing processes such as chemical vapor deposition (CVD), which are then spin-coated followed by electroplating. Using these techniques, the dielectric layers of RDL 310, 312 can be on the order of 100 nanometers (nm) to 5 µm.

[0043] In other embodiments, the dielectric layers of RDL 310, 312 may be formed using lamination or spin coating methods applicable to typical multilayer organic packaging substrates. The dielectric layers of RDL 310, 312 may also be referred to as stacked layers and may have a thickness of approximately a few micrometers to tens of micrometers, for example, from 2 µm to 50 µm.

[0044] Figure 4 illustrates a side view of a package with a glass core having multiple planar structures according to various embodiments. Wiring features are present on the surface of the glass core, and multiple dies are attached to both sides of the glass core. The package 400 may be similar to the package 300 of Figure 3, including a glass core 402, a planar surface 404, a conductive via 406, a wire 407, and RDLs 410 and 412, which may be similar to the glass core 302, planar surface 304, conductive via 306, wire 307, and RDLs 310 and 312 of Figure 3.

[0045] The dies 430 and 432 are physically and electrically coupled to the first side of the glass core 402, and physically and electrically coupled to the plane 404 and the conductive via 406. Furthermore, the dies 430 and 432 are electrically coupled using wires 407. As shown, the wires 407 may be located between the planes 404, which can provide shielding for the wires 407 and other conductive vias 406 between the conductive planes 404.

[0046] As shown, dies 434 and 436 are electrically and physically coupled to a second side of the glass core 402 opposite to dies 430 and 432. Dies 434 and 436 are also electrically coupled to conductive vias 406 and plane 404. In an embodiment, plane 404 may be filled with a conductive material and is also coupled to ground of package 400 to provide shielding within a portion of package 400. In an embodiment, plane 404 can be used for power transmission, which can result in reduced inductance and low series resistance. In an embodiment, plane 404 can also be used as a reference for signal lines, particularly when control impedance is important.

[0047] Figure 5 illustrates a side view of a package with a glass core having multiple planar structures according to various embodiments, wherein wiring features are present on the surface of the glass core and planar structures are present within the RDL to shield the wiring features. Package 500 may be similar to package 400 of Figure 4, including glass core 502, conductive via 506, planar surface 504, high-speed horizontal bus (wire) 507, 509, RDL 510, 512 and horizontal ground plane 511, 513. These may be similar to glass core 402, conductive via 406, planar surface 404, wire 407 and RDL 410, 412 of Figure 4, and horizontal ground plane 311, 313 of Figure 3.

[0048] As shown, all dies 530, 532, 534, and 536 can be similar to dies 430, 432, 434, and 436 in FIG. 4, physically and electrically coupled to the glass core 502. Dies 530 and 532 can be coupled to a high-speed horizontal bus 507 contained within a conductor, and dies 534 and 536 can be coupled to a high-speed horizontal bus 509 contained within a conductor. In an embodiment, in addition to the plane 504 surrounding the high-speed horizontal buses 507 and 509, horizontal ground planes 511 and 513 can provide shielding during operation of the package 500. In an embodiment, plane 504 can also be used as a ground reference for signals on the high-speed horizontal buses 507 and 509.

[0049] FIG6 illustrates a side view of a package having a glass core with multiple planar structures according to various embodiments, wherein wiring features are present on the surface of the glass core and an RDL is present on the side of the wiring features of the glass core. Package 600 may be similar to package 500 of FIG5, including glass core 602, conductive via 606, planar surface 604, wire 607 and RDL 610. These may be similar to glass core 502, conductive via 506, planar surface 504, wire 507 and RDL 510 of FIG5.

[0050] Package 600 includes dies 630, 632, 634, and 636, which may be similar to dies 530, 532, 534, and 536 in Figure 5, and are physically and electrically coupled to the glass core 602. It should be noted that there is only one RDL 610 on one side of the glass core 602, which contains dies 630 and 632 located within cavities 624 and 626, which may be similar to cavities 224 and 226 in Figure 2, within RDL 610.

[0051] On the other side of the glass core 602, solder balls 614 may be placed, allowing dies 634, 636 to be coupled to the glass core 602 after the solder balls 614 are attached to the substrate or another device (not shown). In an embodiment, the solder balls 614 are of sufficient size to not interfere with the operation of dies 634, 636.

[0052] FIG7 illustrates a side view of a package having a glass core with multiple planar structures according to various embodiments, wherein wiring features are present on the surface of the glass core, and an RDL is present on the side of the glass core opposite to the wiring features. The package 700 may include a glass core 702, a conductive via 706, a plane 704, a conductor 707, and an RDL 712. These may be similar to the glass core 602, conductive via 606, plane 604, conductor 607, and RDL 610 of FIG6.

[0053] Package 700 includes dies 730, 732, 734, and 736, which may be similar to dies 630, 632, 634, and 636 in Figure 6, and are physically and electrically coupled to the glass core 702. Note that there is only one RDL 712 on one side of the glass core 702, which contains dies 734 and 736 located in cavities 743 and 745, respectively, within RDL 712.

[0054] Figure 8 illustrates a side view of a package with a multi-planar structure of glass cores according to various embodiments, wherein wiring features are present on both surfaces of the glass cores, and conductive vias electrically coupled to one or more chips are present on opposite sides of the glass cores. Package 800 illustrates an embodiment using an extended architecture of stacked chips.

[0055] Package 800 may include a glass core 802, a conductive via 806, a plane 804, and conductive wires 807 and 809. These may be similar to the glass core 702, conductive via 706, plane 704, and conductive wire 707 in FIG. 7. Package 800 includes dies 830, 832, 840, and 842, which may be similar to the dies 730, 732, 734, and 736 in FIG. 7.

[0056] The molding layer 846 coupled to one side of the glass core 802 may have a cavity into which the dies 830, 832 can be inserted and electrically coupled to the glass core 802. In an embodiment, the dies 830, 832 may be electrically coupled to the other side of the glass core 802 using a conductive via 806 and a wire 809. In an embodiment, the dies 830, 832 may be electrically coupled to the die 840 using a wire 809. In an embodiment, the dies 830, 832 may be electrically coupled to the die 840 using a wire 807 coupled to the dies 830, 832, and electrically coupled to the die 840 using a conductive via 806 as shown.

[0057] In an embodiment, die 842 may be stacked on top of and electrically coupled to dies 830, 832. In an embodiment, die 842 may be stacked on top of molding layer 846. In an embodiment, another die 844 may be coupled to molding layer 846 and electrically coupled to some other die or device (not shown). Solder balls 814 may be similar to solder balls 714 of FIG. 7 and may be used to electrically and physically couple package 802 to a substrate or another device (not shown). In an embodiment, the height of solder balls 814 is high enough to allow die 840 to be positioned between solder balls 814 after assembly and to operate normally during operation of package 800.

[0058] It should be understood that the various structures and components shown in Figures 2-8 may encompass multiple paradigms of embodiments, which may be mixed and / or matched to create a variety of 3D heterogeneous integrated packages, including planar structures through the glass core to provide shielding for conductive features within the glass core. It should also be understood that when the die is directly coupled to the glass layer, the joint may be a solder joint or a metal-to-metal joint. Furthermore, the die and glass may be coupled using advanced bonding techniques.

[0059] Figure 9 illustrates an exemplary process for creating planar structures and conductive vias within a glass core, according to various embodiments. Process 900 can be implemented using the processes, techniques, equipment, and / or systems described herein with reference to Figures 1-8.

[0060] At block 902, this process may include identifying a glass core having a first side and a second side opposite to the first side. In embodiments, the glass core may be similar to glass cores 106, 126, 146, and 166 of FIG. 1, glass core 202 of FIG. 2, 302 of FIG. 3, 402 of FIG. 4, 502 of FIG. 5, 602 of FIG. 6, 702 of FIG. 7, and 802 of FIG. 8.

[0061] In block 904, this process may further include forming a first plane and a second plane extending from a first side of the glass core to a second side of the glass core. This process may include one or more techniques as shown in FIG. 1 above. In embodiments, the first plane and the second plane may be similar to plane 304 of FIG. 3, 404 of FIG. 4, 504 of FIG. 5, 604 of FIG. 6, 704 of FIG. 7, or 804 of FIG. 8.

[0062] In block 906, this process may further include forming one or more through-holes extending from a first side of the glass core to a second side of the glass core, wherein the one or more through-holes are between the first plane and the second plane. This process may include one or more techniques as shown in FIG. 1 above. In embodiments, the one or more through-holes may be similar to through-hole 306 of FIG. 3, 406 of FIG. 4, 506 of FIG. 5, 606 of FIG. 6, 706 of FIG. 7, or 806 of FIG. 8.

[0063] FIG10 schematically illustrates a computing device according to an embodiment. According to any of the several disclosed embodiments and their equivalents set forth in this disclosure, the depicted computer system 1000 (also referred to as electronic system 1000) may embody all or part of a glass-encapsulated core with a planar structure. The computer system 1000 may be a mobile device such as a network-connected laptop. The computer system 1000 may be a mobile device such as a wireless smartphone. The computer system 1000 may be a desktop computer. The computer system 1000 may be a handheld reader. The computer system 1000 may be a server system. The computer system 1000 may be a supercomputer or a high-performance computing system.

[0064] In one embodiment, electronic system 1000 is a computer system that includes a system bus 1020 electrically coupled to various components of electronic system 1000. According to various embodiments, system bus 1020 is a single bus or any combination of buses. Electronic system 1000 includes a voltage source 1030 supplying power to integrated circuit 1010. In some embodiments, voltage source 1030 supplies current to integrated circuit 1010 through system bus 1020.

[0065] According to an embodiment, the integrated circuit 1010 is electrically coupled to the system bus 1020 and includes any circuitry or combination of circuits. In one embodiment, the integrated circuit 1010 includes a processor 1012, which may be of any type. As used herein, processor 1012 may refer to any type of circuitry, such as, but not limited to, a microprocessor, microcontroller, graphics processor, digital signal processor, or other processor. In one embodiment, processor 1012 includes or is coupled to all or part of a high-speed bridge between the package and the component, as disclosed herein. In one embodiment, an SRAM embodiment is present in the processor's memory cache. Other types of circuitry that may be included in the integrated circuit 1010 are custom circuitry or application-specific integrated circuits (ASICs), such as communication circuitry 1014 for wireless devices such as mobile phones, smartphones, pagers, portable computers, two-way radios, and similar electronic systems, or communication circuitry for servers. In one embodiment, the integrated circuit 1010 includes memory-on-die 1016, such as static random access memory (SRAM). In one embodiment, the integrated circuit 1010 includes embedded on-die memory 1016, such as embedded dynamic random access memory (eDRAM).

[0066] In one embodiment, the integrated circuit 1010 is supplemented by a subsequent integrated circuit 1011. Useful embodiments include a dual processor 1013 and dual communication circuits 1015, as well as dual on-die memory 1017, such as SRAM. In one embodiment, the dual integrated circuit 1010 includes embedded on-die memory 1017, such as eDRAM.

[0067] In one embodiment, the electronic system 1000 further includes external memory 1040, which may include one or more memory elements suitable for a particular application, such as main memory 1042 in the form of RAM, one or more hard disks 1044, and / or one or more drives for processing removable media 1046, such as magnetic disks, optical discs (CDs), digital multifunction hard disks (DVDs), flash memory drives, and other removable media known in the art. According to one embodiment, external memory 1040 may also be embedded memory 1048, such as the first die in a die stack.

[0068] In one embodiment, the electronic system 1000 further includes a display device 1050 and an audio output 1060. In one embodiment, the electronic system 1000 includes an input device, such as a controller 1070, which may be a keyboard, mouse, trackball, game controller, microphone, voice recognition device, or any other input device that inputs information into the electronic system 1000. In one embodiment, the input device 1070 is a camera. In one embodiment, the input device 1070 is a digital recorder. In one embodiment, the input device 1070 is both a camera and a digital recorder.

[0069] As shown herein, the integrated circuit 1010 can be implemented in several different embodiments, including all or part of a glass package core with a planar structure according to any of the disclosed embodiments and their equivalents, an electronic system, a computer system, one or more methods of manufacturing an integrated circuit, and one or more methods of manufacturing an electronic component including a package substrate that implements all or part of the glass package core with a planar structure, according to any of the disclosed embodiments described herein, such as the various embodiments herein and their recognized equivalents in the art. According to any of the disclosed processes for a glass package core with a planar structure and its equivalents, the elements, materials, geometries, dimensions, and operating sequences can vary to accommodate specific input / output coupling requirements, including the number of array contacts and the array contact configuration of the microelectronic die embedded in the processor mounting substrate. A base substrate may be included, as shown by the dashed line in FIG10. Passive devices may also be included, as shown in FIG10.

[0070] Multiple embodiments may include any suitable combination of the embodiments described above, including alternative (or) embodiments of the embodiments described above in combination (and) (e.g., "and" can be "and / or"). In addition, some embodiments may include one or more articles of manufacture having instructions stored thereon (e.g., a non-volatile computer-readable medium) that, when executed, cause the operation of any of the embodiments described above. Furthermore, some embodiments may include a device or system having any suitable means for performing the various operations of the embodiments described above.

[0071] The above description of the embodiments, including the description in the abstract, is not intended to be exhaustive or to limit the embodiments to the precise aspects disclosed. The precise embodiments described herein are for illustrative purposes, and thus those skilled in the art will recognize that various equivalent modifications may fall within the scope of the embodiments.

[0072] These modifications can be made to the embodiments based on the above detailed description. The terminology used in the following claims should not be construed as limiting the specific implementations disclosed in the specification and claims. Rather, the scope of the invention is determined entirely by the following claims and is interpreted in accordance with established principles of the interpretation of the claims.

[0073] The following paragraphs describe examples of various embodiments.

[0074] Example

[0075] Example 1 is an interposer layer comprising: a glass core having a first side and a second side opposite to the first side; a plurality of planar structures within the glass core extending from the first side of the glass core to the second side of the glass core; and one or more conductive vias extending from the first side of the glass core to the second side of the glass core, wherein one of the one or more conductive vias is between the first and the second of the plurality of planar structures.

[0076] Example 2 may include an interposer layer as in Example 1, wherein the plurality of planar structures are filled with a conductive material for shielding the one or more conductive vias.

[0077] Example 3 may include an intermediate layer as in Example 2, wherein at least some of the plurality of planar structures are electrically coupled to ground.

[0078] Example 4 may include an interlayer as in Example 2, wherein the conductive material comprises one or more of copper, tin, gold, and aluminum.

[0079] Example 5 may include an intermediate layer as in Example 1, wherein the plurality of planar structures are substantially parallel to each other.

[0080] Example 6 may include an interposer layer as in Example 1, and further include one or more routing structures on the first side of the glass core or the second side of the glass core for coupling with at least one of the one or more conductive vias.

[0081] Example 7 may include an intermediary layer as in Example 6, wherein the one or more routing structures are recessed into the surface of the first side or the second side of the glass core.

[0082] Example 8 may include an interposer layer as in Example 1, wherein the one or more conductive vias have an aspect ratio of 20:1.

[0083] Example 9 may include an interposer layer as in Example 1, further including a third and a fourth of the plurality of planar structures in the glass core; and wherein at least one of the one or more conductive vias is between the third and the fourth of the plurality of planar structures.

[0084] Example 10 may include an intermediary layer such as any of Examples 1-9, wherein one of the planar structures is perpendicular to the other planar structure.

[0085] Example 11 is a package comprising: an interposer including: a glass core having a first side and a second side opposite to the first side; a plurality of planar structures within the glass core extending from the first side of the glass core to the second side of the glass core; and one or more conductive vias extending from the first side of the glass core to the second side of the glass core, wherein one of the one or more conductive vias is between a first and a second of the plurality of planar structures, wherein the plurality of planar structures are filled with a conductive material for shielding the one or more conductive vias; and a redistribution layer (RDL) coupled to the first side or the second side of the glass core, the RDL including electrical traces electrically coupled to at least one of the one or more conductive vias.

[0086] Example 12 may include a package as in Example 11, further including a die physically coupled to the first side or the second side of the glass core, the die being electrically coupled to one of the one or more conductive vias.

[0087] Example 13 may include a package as in Example 12, wherein the die is a first die; and further includes: a second die, which is physically coupled to the first side or the second side of the glass core on the same side as the first die; and a bus that electrically couples the connector on the first die to the connector on the second die, wherein the bus is on the surface of the glass core.

[0088] Example 14 may include a package as in Example 13, wherein the bus is recessed in the surface of the glass core.

[0089] Example 15 may include a package as in Example 13, further including a portion of the RDL between the first die and the second die, wherein the RDL includes a plane filled with conductive material and level with the surface of the glass core, and wherein the bus is between the plane filled with conductive material in the RDL and the surface of the glass core.

[0090] Example 16 may include a package as in any of Examples 13-15, wherein the bus is electrically coupled to one or more conductive vias.

[0091] Example 17 is a method comprising: identifying a glass core having a first side and a second side opposite to the first side; forming a first plane and a second plane extending from the first side of the glass core to the second side of the glass core; and forming one or more through holes extending from the first side of the glass core to the second side of the glass core, wherein the one or more through holes are between the first plane and the second plane.

[0092] Example 18 may include the method of Example 17, further including embedding conductive material into the first plane, the second plane or the one or more through holes.

[0093] Example 19 may include the method of Example 18, wherein embedding the conductive material further includes one of the following options: conformal electroplating or filling.

[0094] Example 20 may include a method as in any of Examples 18-19, wherein the conductive material comprises one or more of copper, gold, tin or aluminum. [Simplified Explanation of the Diagram]

[0004] [Figure 1] illustrates several examples of laser-assisted etching in a glass interconnect process according to an embodiment.

[0005] [Figure 2] illustrates a side view of a package having a glass core with multiple planar structures according to various embodiments, wherein the grains are attached to the glass core.

[0006] [Figure 3] illustrates a side view of a package having a glass core with multiple planar structures according to various embodiments, with wiring features on the surface of the glass core.

[0007] [Figure 4] illustrates a side view of a package having a glass core with multiple planar structures according to various embodiments, having wiring features on the surface of the glass core, and having multiple grains attached to both sides of the glass core.

[0008] [Figure 5] illustrates a side view of a package having a glass core with multiple planar structures according to various embodiments, having wiring features on the surface of the glass core, and having planar structures within the redistribution layer (RDL) to shield the wiring features.

[0009] [Figure 6] illustrates a side view of a package having a glass core with multiple planar structures according to various embodiments, having wiring features on the surface of the glass core and having an RDL on the wiring feature side of the glass core.

[0010] [Figure 7] illustrates a side view of a package having a glass core with multiple planar structures according to various embodiments, having wiring features on the surface of the glass core and having an RDL on the side of the glass core opposite to the wiring features.

[0011] [Figure 8] illustrates a side view of a package having a glass core with multiple planar structures according to various embodiments, wherein wiring features are present on both surfaces of the glass core, and conductive vias electrically coupled to one or more grains are present on opposite sides of the glass core.

[0012] [Figure 9] illustrates an exemplary process for creating planar structures and conductive vias within a glass core, according to various embodiments.

[0013] [Figure 10] schematically illustrates a computing device according to an embodiment.

Claims

1. An intermediary layer, comprising: A glass core having a first side and a second side opposite to the first side; The glass core contains a plurality of planar structures extending from the first side of the glass core to the second side of the glass core; one or more conductive vias extending from the first side of the glass core to the second side of the glass core, wherein one of the one or more conductive vias is located between the first and the second of the plurality of planar structures; and one or more routing structures on the first side or the second side of the glass core for coupling with at least one of the one or more conductive vias, wherein the one or more routing structures are recessed into the surface of the first side or the second side of the glass core.

2. As in the intermediary layer of request item 1, where, The plurality of planar structures are filled with conductive material for shielding the one or more conductive vias.

3. As in the intermediary layer of request item 2, where, At least some of the plurality of planar structures are electrically coupled to ground.

4. As in the intermediary layer of request item 2, where, The conductive material comprises one or more of copper, tin, gold, and aluminum.

5. As in the intermediary layer of request item 1, where, The multiple planar structures are essentially parallel to each other.

6. As in the intermediary layer of request item 1, where, The one or more conductive vias have an aspect ratio of 20:

1.

7. The interlayer of claim 1 further includes a third and a fourth of the plurality of planar structures in the glass core; and wherein at least one of the one or more conductive vias is between the third and the fourth of the plurality of planar structures.

8. An intermediary layer as described in any of requests 1 to 7, wherein, One of the planar structures is perpendicular to the other planar structure.

9. A package, comprising: An interposer layer includes: a glass core having a first side and a second side opposite to the first side; a plurality of planar structures within the glass core extending from the first side of the glass core to the second side of the glass core; and one or more conductive vias extending from the first side of the glass core to the second side of the glass core, wherein one of the one or more conductive vias is between a first and a second of the plurality of planar structures, wherein the plurality of planar structures are filled with a conductive material for shielding the one or more conductive vias; and a redistribution layer (RDL) coupled to the first side or the second side of the glass core, the RDL including electrical traces electrically coupled to at least one of the one or more conductive vias; and a grain physically coupled to the first side or the second side of the glass core, the grain being electrically coupled to one of the one or more conductive vias, wherein the grain is a first grain; and further includes: The second grain is physically coupled to the first or second side of the glass core on the same side as the first grain; and the busbar electrically couples the connector on the first grain to the connector on the second grain, wherein the busbar is recessed in the surface of the glass core.

10. The package as claimed in claim 9, further including a portion of the RDL between the first die and the second die, wherein, The RDL includes a plane filled with conductive material and level with the surface of the glass core, wherein the busbar is located between the plane filled with conductive material in the RDL and the surface of the glass core.

11. As in the encapsulation of request item 9 or 10, where, The bus is electrically coupled to one or more conductive vias.

12. A method for manufacturing a packaged core, comprising: Identify a glass core having a first side and a second side opposite to the first side; A first plane and a second plane are formed extending from the first side of the glass core to the second side of the glass core; one or more through holes are formed extending from the first side of the glass core to the second side of the glass core, wherein the one or more through holes are between the first plane and the second plane; and one or more routing structures are formed on the first side or the second side of the glass core to couple with at least one of the one or more through holes, wherein the one or more routing structures are recessed in the surface of the first side or the second side of the glass core.

13. The method of claim 12 further includes embedding a conductive material into the first plane, the second plane, or the one or more through holes.

14. As in request item 13, where, Embedded conductive materials further include one of the following options: conformal plating or filling.

15. As in request item 13 or 14, wherein, The conductive material comprises one or more of copper, gold, tin or aluminum.

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