Interconnection structures and methods for forming the same

Abstract

An interconnect structure includes: a first dielectric layer; a first conductive layer disposed in the first dielectric layer; a second dielectric layer disposed above the first dielectric layer; a second conductive layer disposed in the second dielectric layer and electrically contacting the first conductive layer; a third dielectric layer disposed above the second dielectric layer, wherein the third dielectric layer comprises a silicon carbide (SiCN) based material; and a resistive device disposed in the third dielectric layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for forming the same, and particularly to an interconnect structure and a method for forming the same. Prior Technology

[0002] As the semiconductor industry introduces new generations of integrated circuits (ICs) with higher performance and more functionality, the component density forming ICs increases, while the size, dimensions, and spacing between components or elements decrease. The semiconductor industry continuously increases the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the smallest component size, thereby allowing more components to be integrated into a given area.

[0003] However, when embedding high-resistivity elements in a semiconductor structure, the low thermal conductivity of the dielectric material in the interconnect structure can lead to heat dissipation problems. For example, when forming resistors in a back-end of the line (BEOL) structure, the low thermal conductivity of the interlayer dielectric (ILD) layer may prevent the resistor from dissipating heat and cause device damage. Therefore, there is a need in the art to provide improved devices or methods that can solve the above problems. Summary of the Invention

[0004] Some embodiments of the present invention provide an interconnect structure, including: a first dielectric layer; a first conductive layer disposed in the first dielectric layer; a second dielectric layer disposed above the first dielectric layer; a second conductive layer disposed in the second dielectric layer and electrically contacting the first conductive layer; a third dielectric layer disposed above the second dielectric layer, wherein the third dielectric layer comprises a silicon carbide (SiCN) based material; and a resistive device disposed in the third dielectric layer.

[0005] Other embodiments of the present invention provide an interconnect structure comprising: a first dielectric layer; a first conductive layer disposed in the first dielectric layer; a second dielectric layer disposed above the first dielectric layer; a second conductive layer disposed in the second dielectric layer and electrically contacting the first conductive layer; a third dielectric layer disposed above the second dielectric layer, wherein the third dielectric layer comprises a material based on crystalline silicon oxide (SiOC); and a resistive device disposed in the third dielectric layer.

[0006] Some embodiments of the present invention provide a method for forming an interconnect structure, comprising: forming a first dielectric layer on a semiconductor substrate; forming a first conductive layer in the first dielectric layer; forming a second dielectric layer above the first dielectric layer; forming a second conductive layer in the second dielectric layer, the second conductive layer and the first conductive layer being in electrical contact; forming a third dielectric layer above the second dielectric layer, the third dielectric layer having a thermal conductivity of 5 W / mK to 500 W / mK; and forming a resistive device in the third dielectric layer. Simple Explanation of the Diagram

[0007] The various aspects of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are only used for illustrative purposes. In fact, the dimensions of the elements may be arbitrarily enlarged or reduced to clearly show the features of this disclosure. According to some embodiments of this disclosure, Figure 1 is a view of one of the various stages of manufacturing a semiconductor device structure. According to some embodiments of this disclosure, Figures 2A-2B are cross-sectional side views of one of the various stages of manufacturing a semiconductor device structure. According to some embodiments of this disclosure, Figures 3-10 are cross-sectional side views of various exemplary semiconductor structures. According to some embodiments of this disclosure, Figure 11 is a flowchart of a method for manufacturing a semiconductor interconnect structure. According to some embodiments of this disclosure, Figure 12 is a cross-sectional side view of a resistor device at one of the various stages of manufacturing a semiconductor interconnect structure. Implementation

[0008] The following provides many different embodiments or examples to implement different components of the embodiments disclosed herein. Specific examples of components and configurations are described below to simplify the embodiments disclosed herein. Of course, these are merely examples and are not intended to limit the embodiments disclosed herein. For example, the dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or desired characteristics of the apparatus. Furthermore, the following description of forming a first component above or on a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component is formed between the first and second components, such that the first and second components do not need to be in direct contact. Additionally, the embodiments of the present invention may repeat element symbols and / or letters in many examples. These repetitions are for simplification and clarity and do not in themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0009] Spatially relative terms, such as "below," "below," "lower," "above," "above," "on," "top," "higher," etc., may be used here to facilitate the description of the relationship between one or more components or features in the diagram. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0010] According to some embodiments of this disclosure, Figure 1 is a view of one of the various stages of manufacturing a semiconductor device structure 100. As shown in Figure 1, the semiconductor device structure 100 includes a substrate 101 having at least a plurality of devices thereon. Devices such as transistors, diodes, imaging sensors, resistors, capacitors, inductors, memory cells, combinations thereof, and / or other suitable devices can be formed on the substrate 101. In some embodiments, interconnect structures can be formed on or under the devices.

[0011] According to some embodiments disclosed herein, Figures 2A-2B are cross-sectional side views of various stages of manufacturing the semiconductor device structure 100. Figure 2A is a cross-sectional side view of the semiconductor device structure 100 taken along line AA of Figure 1, and Figure 2B is a cross-sectional side view of the semiconductor device structure 100 taken along line BB of Figure 1. Line AA of Figure 1 extends in a direction generally perpendicular to the longitudinal direction of the gate stack 106, and line BB of Figure 1 extends in the longitudinal direction of the gate stack 106. As shown in Figures 2A and 2B, the semiconductor device structure 100 includes a substrate 101 and one or more devices 102 formed on the substrate 101. Interconnect structures may be formed above the devices 102.

[0012] Substrate 101 may be a semiconductor substrate. In some embodiments, substrate 101 includes at least a crystalline semiconductor layer on its surface. Substrate 101 may include crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenide arsenide (GaAsSb), and indium phosphide (InP). In some embodiments, substrate 101 is formed of Si. In some embodiments, substrate 101 is a silicon-on-insulator (SOI) substrate, which includes an insulating layer (not shown) disposed between two silicon layers. In one aspect, the insulating layer is an oxygen-containing material, such as an oxide.

[0013] The substrate 101 may include various regions that have been appropriately doped with impurities (e.g., p-type or n-type impurities). For example, for an n-type fin field-effect transistor (FinFET), the dopant is phosphorus, and for a p-type fin field-effect transistor, the dopant is boron.

[0014] As described above, device 102 can be any suitable device, such as a transistor, diode, imaging sensor, resistor, capacitor, inductor, memory cell, or a combination thereof. In some embodiments, device 102 is a transistor, such as planar field-effect transistors (FETs), fin field-effect transistors, nanostructured transistors, or other suitable transistors. Nanostructured transistors can include nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MCB) transistors, or any transistor having gate electrodes surrounding the channel. Examples of device 102 formed between substrate 101 and interconnect structures (such as interconnect structure 200 shown in Figures 3-10) can be fin field-effect transistors or nanostructures, as shown in Figures 2A and 2B. The exemplary device 102 may include a source / drain (S / D) region 104 and a gate stack 106 disposed between the source / drain region 104 (serving as a source region) and the source / drain region 104 (serving as a drain region). Although only one gate stack 106 is formed on the substrate 101, two or more gate stacks 106 may also be formed on the substrate 101. A channel region 108 is formed between the source / drain region 104 (serving as a source region) and the source / drain region 104 (serving as a drain region).

[0015] The source / drain region 104 may include semiconductor materials such as Si or Ge, III-V compound semiconductors, II-VI compound semiconductors, or other suitable semiconductor materials. Exemplary source / drain regions 104 may include, but are not limited to, Ge, SiGe, GaAs, AlGaAs, GaAsP, SiP, InAs, AlAs, InP, GaN, InGaAs, InAlAs, GaSb, AlP, GaP, etc. The source / drain region 104 may include p-type dopants, such as boron; n-type dopants, such as phosphorus or arsenic; and / or other suitable dopants including combinations thereof. The source / drain region 104 may be formed by epitaxial growth methods using chemical vapor deposition (CVD), atomic layer deposition (ALD), or molecular beam epitaxy (MBE). The channel region 108 may include one or more semiconductor materials, such as Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, or InP. In some embodiments, the channel region 108 includes the same semiconductor material as the substrate 101. In some embodiments, the device 102 is a fin field-effect transistor, and the channel region 108 is a plurality of fins, each having at least three surfaces wrapped around the gate stack 106. In some other embodiments, the device 102 is a nanoplate transistor, and the channel region 108 is surrounded by the gate stack 106.

[0016] Each gate stack 106 includes a gate electrode layer 110 disposed above or partially / completely surrounding the channel region 108. The gate electrode layer 110 may be a metallic material, such as tungsten, cobalt, aluminum, ruthenium, copper, or multiple layers thereof, and may be formed by atomic layer deposition, plasma-enhanced chemical vapor deposition (PECVD), molecular beam deposition (MBD), physical vapor deposition (PVD), or any suitable deposition technique. Each gate stack 106 may include an interface dielectric layer 112, a gate dielectric layer 114 disposed on the interface dielectric layer 112, and one or more conformal layers 116 disposed on the gate dielectric layer 114. The gate electrode layer 110 may be disposed on the conformal layer 116. The interface dielectric layer 112 may include a dielectric material, such as an oxygen-containing or nitrogen-containing material, or multiple layers thereof, and may be formed by any suitable deposition method, such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or atomic layer deposition. The gate dielectric layer 114 may include a dielectric material, such as an oxygen-containing or nitrogen-containing material, a high dielectric constant dielectric material having a dielectric constant greater than that of silicon dioxide, or multiple layers thereof. The gate dielectric layer 114 may be formed by any suitable method, such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or atomic layer deposition. The compliant layer 116 may include one or more barrier layers and / or capping layers, such as nitrogen-containing materials, such as tantalum nitride (TaN), titanium nitride (TiN), etc. The compliant layer 116 may further include one or more work function layers, such as aluminum titanium carbide, aluminum titanium oxide, aluminum titanium nitride, etc. The term "compliant" may be used in this disclosure to describe films having substantially the same thickness in various regions. The compliant layer 116 can be deposited by atomic layer deposition, plasma-assisted chemical vapor deposition, molecular beam deposition or any suitable deposition technique.

[0017] One or more gate spacers 118 may be formed along the sidewalls of the gate stack 106 (e.g., the sidewalls of the gate dielectric layer 114). The gate spacers 118 may include silicon carbide, silicon nitride, silicon oxynitride, silicon carbon nitride, etc., multilayers thereof, or combinations thereof, and may be deposited by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable deposition techniques.

[0018] A portion of the gate stack 106 and the gate spacer 118 may be formed on the isolation region 103. The isolation region 103 is formed on the substrate 101. The isolation region 103 may include an insulating material, such as an oxygen-containing material, a nitrogen-containing material, or a combination thereof. The insulating material may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), or other suitable deposition processes. In one aspect, the isolation region 103 includes silicon oxide formed by a flowable chemical vapor deposition process.

[0019] A contact etch stop layer (CESL) 124 is formed on portions of the source / drain region 104 and the isolation region 103, and an interlayer dielectric (ILD) 126 is formed on the contact etch stop layer 124. The contact etch stop layer 124 can provide a mechanism to stop the etching process when an opening is formed in the interlayer dielectric layer 126. The contact etch stop layer 124 can be compliantly deposited on the surfaces of the source / drain region 104 and the isolation region 103. The contact etch stop layer 124 can include oxygen-containing or nitrogen-containing materials, such as silicon nitride, silicon carbon nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, etc., or combinations thereof, and can be deposited by chemical vapor deposition, plasma-assisted chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any suitable deposition technique. The first dielectric 126 may include an oxide, which is made of tetraethyl orthosilicate (TES), undoped silicate glass, or doped silica, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicate glass (BSG), organosilicate glass (OSG), SiOC, and / or any suitable low dielectric constant dielectric material (e.g., a material with a dielectric constant lower than that of silica), and may be deposited by spin coating, chemical vapor deposition, flow-through chemical vapor deposition, plasma-assisted chemical vapor deposition, physical vapor deposition, or any suitable deposition technique.

[0020] As shown in Figures 2A and 2B, a silicate layer 120 is formed on at least a portion of each source / drain region 104. The silicate layer 120 may comprise one or more materials having the following composition: WSi, CoSi, NiSi, TiSi, MoSi, and TaSi. In some embodiments, the silicate layer 120 comprises a metallic or metal alloy silicate, and the metallic material includes noble metals, refractory metals, rare earth metals, alloys thereof, or combinations thereof. A conductive contact 122 is disposed on each silicate layer 120. The conductive contact 122 may comprise one or more materials having the following composition: Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, or TaN, and the conductive contact 122 may be formed by any suitable method, such as electrochemical plating (ECP) or physical vapor deposition. Forming the silicate layer 120 and the conductive contact 122 may include: firstly, forming openings in the first dielectric 126 and the contact etch stop layer 124 to expose at least a portion of the source / drain region 104, then forming the silicate layer 120 on the exposed portion of the source / drain region 104, and then forming the conductive contact 122 on the silicate layer 120.

[0021] According to some embodiments of this disclosure, Figure 3 is a cross-sectional side view of an exemplary semiconductor structure 300, including an interconnect structure 301. In some embodiments, the interconnect structure 301 may be formed above or below the semiconductor device structure 100. According to some embodiments of this disclosure, Figure 11 is a flowchart of a method 1100 for manufacturing the interconnect structure 301. To better describe this disclosure, the cross-sectional side view of the semiconductor structure 300 in Figure 3 and the method 1100 in Figure 11 will be discussed together. It will be understood that method 1100 does not show all operations, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in a different order than that shown in Figures 3 and 11.

[0022] As shown in Figure 3, a semiconductor substrate 202 is provided. The semiconductor substrate 202 may be similar to the substrate 101 discussed above. A plurality of devices 204 and a middle end of the line (MEOL) structure 206 may be formed on the semiconductor substrate 202. In some embodiments, the plurality of devices 204 may be the device 102 shown in Figures 2A and 2B.

[0023] In the mid-process structure 206, low-level interconnects (contacts), such as conductive contacts 122 shown in Figures 2A and 2B, are formed above the source / drain region 104 and the gate electrode layer 110. The mid-process structure 206 can have a smaller critical dimension and can be more closely spaced compared to the corresponding components formed in the subsequent back-end processes. The purpose of the contact layer in the mid-process structure 206 is to electrically connect the various regions of the transistor, namely the source / drain and the metal gate electrode, to the higher-level interconnects in the back-end processes.

[0024] As shown in operation 302 of Figures 3 and 11, dielectric layer 208 is formed on mid-process structure 206. In some embodiments, dielectric layer 208 may include an interlayer dielectric layer. In some embodiments, dielectric layer 208 may include an interlayer dielectric layer based on silicon carbonitride (SiC xN y), where x and y may be integers or non-integers. For example, dielectric layer 208 may include carbon-doped Si 3N 4. In another example, dielectric layer 208 may be SiBC xN y. In some embodiments, dielectric layer 208 may have a dielectric constant of 3.5 to 5.0. In some embodiments, dielectric layer 208 may be formed at a deposition temperature of 150°C to 425°C by chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, or other suitable processes. In some embodiments, dielectric layer 208 may or may not be formed using additional annealing or ultraviolet (UV) curing processes.

[0025] As shown in operation 304 of Figures 3 and 11, a conductive layer 210 is formed in the dielectric layer 208. In some embodiments, the conductive layer 210 may include Cu, Ni, Co, Ru, Ir, Al, Pt, Pd, Au, Ag, Os, W, Mo, and related alloys. In some embodiments, the conductive layer 210 may be formed at a deposition temperature of 150°C to 425°C by atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroless deposition (ELD), electrochemical plating, or other suitable processes.

[0026] In some embodiments, one or more etch stop layers (ESLs) 212 may be formed over the dielectric layer 208 and the conductive layer 210, as shown in Figure 3. The etch stop layer 212 can be used to control the etch depth in the dielectric layer 214 when the conductive component 218 is subsequently formed in the dielectric layer 214. In some embodiments, the etch stop layer 212 may comprise SiOx, SiOxCyHz, SiCx, SiOxCy, SiNx, SiCxNy, AlNx, AlOx, AOxNy, or doped with Hf, Zr, or Y, or other suitable materials. The etch stop layer 212 and the dielectric layer 208 comprise different materials. In some embodiments, the etch stop layer 212 may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, or other suitable processes at deposition temperatures ranging from 150°C to 425°C.

[0027] As shown in operation 306 of Figures 3 and 11, dielectric layer 214 is formed over etch stop layer 212. In some embodiments, dielectric layer 214 may comprise the same material as dielectric layer 208. In some embodiments, dielectric layer 214 may be formed using a process similar to that used to form dielectric layer 208. As shown in operation 308 of Figures 3 and 11, conductive layer 216 is formed in dielectric layer 214 and is electrically contacted with conductive layer 210 via conductive member 218. In some embodiments, conductive members 216, 218 may be formed in dielectric layer 214 using dual damascene, single damascene, semi-damascene, or other suitable processes.

[0028] Taking a single damascene process as an example, an etch stop layer 212 is formed above the dielectric layer 208 and the conductive layer 210, and a dielectric layer 214 is formed above the etch stop layer 212. An etching process can then be performed to form an opening according to a predetermined pattern. In some embodiments, a barrier layer (not shown) can be deposited in the opening, and a conductive material, such as Cu, can be deposited on the barrier layer. Depositing the conductive material on the barrier layer in the opening can include forming a seed layer on the barrier layer by a physical vapor deposition process, followed by forming the conductive material on the seed layer by an electrodeposition process. The conductive material can form a conductive component 218 in the opening. In some embodiments, a conductive layer 216 can be further formed on the conductive component 218 using a dual damascene process. The top surface of the conductive material is then planarized so that the top surfaces of the conductive layer 216 and the dielectric layer 214 are substantially coplanar.

[0029] It is understood that, in some embodiments, a stack of more than one interconnect layer may be formed on the intermediate process structure 206, such as dielectric layer 208, etch stop layer 212, and dielectric layer 214, including conductive layer 210, conductive layer 216, and conductive component 218 formed therein. For example, as shown in Figure 3, etch stop layer 220 is formed over dielectric layer 214 and conductive layer 216. Dielectric layer 222 is formed over etch stop layer 220, and conductive layer 224 is formed in dielectric layer 222. Etch stop layer 226 is formed over dielectric layer 222 and conductive layer 224, and dielectric layer 228 is formed over etch stop layer 226. Subsequently, conductive layer 230 is formed in dielectric layer 228, electrically contacting conductive layer 224 via conductive component 232. In some embodiments, conductive layer 230 and conductive component 232 may be formed in dielectric layer 228 via dual damascene, single damascene, half damascene, or other suitable processes. The materials and manufacturing processes of dielectric layer 222, conductive layer 224, etch stop layer 226, dielectric layer 228, conductive layer 230 and conductive component 232 can be similar to those of dielectric layer 208, conductive layer 210, etch stop layer 212, dielectric layer 214, conductive layer 216 and conductive component 218, respectively.

[0030] As shown in operation 310 of Figure 11, an etch stop layer 234 is formed over the dielectric layer 228 and the conductive layer 230, and a dielectric layer 236 is formed over the etch stop layer 234. A resistive device 238 is then formed in the dielectric layer 236, as shown in operation 312 of Figure 11. In some embodiments, the resistive device 238 may be a high-resistivity layer covered by the dielectric layer.

[0031] According to some embodiments of this disclosure, Figure 12 is a cross-sectional side view of a resistor device 238 at one of the various stages of manufacturing the semiconductor structure 300. As shown in Figure 12, the resistor device 238 may include a first silicide-blocking layer (SBL) 2381, a first oxide layer 2382, a high-resistivity material layer 2383, a second silicide-blocking layer 2384, and a second oxide layer 2385. In some embodiments, the stack of the first silicide-blocking layer 2381, the first oxide layer 2382, the high-resistivity material layer 2383, the second silicide-blocking layer 2384, and the second oxide layer 2385 may be further covered by a third oxide layer 2386. In some embodiments, a stack of a first silicate barrier layer 2381, a first oxide layer 2382, a high-resistivity material layer 2383, a second silicate barrier layer 2384, and a second oxide layer 2385 may be sequentially deposited on an etch stop layer 234 and then patterned by lithography and etching operations. In some embodiments, the high-resistivity material layer 2383 may include TiN, TaN, or other suitable materials. In some embodiments, the first, second, and third oxide layers 2382, 2385, and 2386 may be silicon oxide layers formed using tetraethyl orthosilicate (TEOS) as a precursor. In some embodiments, the first silicate barrier layer 2381 and the second silicate barrier layer 2384 may each have a thickness of 50 Å to 200 Å. In some embodiments, the first oxide layer 2382 and the second oxide layer 2385 may each have a thickness of 50 Å to 200 Å. In some embodiments, the third oxide layer 2386 may have a thickness of 20 Å to 100 Å. Figure 12 illustrates a resistor device 238 formed on an etch stop layer 234. It is understood that the resistor device 238 may further extend in other directions, such as in the x or y direction, and has a via structure 2387 in contact with a high-resistivity material layer 2383 in the extended portion.

[0032] Dielectric layer 236 may include an interlayer dielectric layer. In some embodiments, dielectric layer 236 may include an interlayer dielectric layer based on SiC xN y. For example, dielectric layer 236 may include carbon-doped Si 3N 4. For another example, dielectric layer 236 may be SiBC xN y. In some embodiments, dielectric layer 236 may have a dielectric constant of 2.0 to 5.0. In some embodiments, dielectric layer 236 may have a dielectric constant of 3.5 to 5.0. In some embodiments, dielectric layer 236 may be formed at a deposition temperature of 150°C to 425°C by chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, or other suitable processes. In some embodiments, dielectric layer 236 may be formed with or without additional annealing or ultraviolet (UV) curing processes. In some embodiments, the materials and fabrication processes of dielectric layer 236 may be similar to those of dielectric layer 222 or dielectric layer 228. In some embodiments, the material and manufacturing process of dielectric layer 236 may differ from the material and manufacturing process of dielectric layer 222 or dielectric layer 228.

[0033] The dielectric layer 236 comprises a material with a thermal conductivity of 5 W / mK to 500 W / mK, thus rapidly dissipating the heat generated by the resistive device 238 and preventing heat accumulation within the semiconductor structure 300. For example, when the dielectric layer 236 comprises carbon-doped Si3N4, the thermal conductivity of carbon-doped Si3N4 can be from 200 W / mK to 400 W / mK, and the dielectric constant can be from 2.0 to 5.0, which not only provides improved thermal conductivity for the semiconductor structure 300 but also has a low dielectric constant. Therefore, localized thermal damage in the semiconductor structure 300 can be prevented.

[0034] It is understood that, in some embodiments, one or more interconnect layers may be further formed on dielectric layer 236. For example, as shown in Figure 3, a conductive layer 240 is formed in dielectric layer 236. An etch stop layer 242 is formed over dielectric layer 236 and conductive layer 240, and a dielectric layer 244 is formed over etch stop layer 242. Subsequently, a conductive layer 246 is formed in dielectric layer 244, electrically contacting conductive layer 240 via conductive component 248. In some embodiments, conductive layer 246 and conductive component 248 may be formed in dielectric layer 244 by dual damascene, single damascene, half damascene, or other suitable processes. The materials and manufacturing processes of etch stop layer 242, dielectric layer 244, conductive layer 246, and conductive component 248 may be similar to those of etch stop layer 212, dielectric layer 214, conductive layer 216, and conductive component 218, respectively. In some embodiments, the resistor 238 may be electrically isolated from the conductive layer 240, and the resistor 238 may be in contact with other conductive layers through a via structure 2387. In some embodiments, the resistor 238 may be electrically connected to the conductive layer 240 through the via structure 2387.

[0035] According to some embodiments disclosed herein, Figure 4 is a cross-sectional side view of another exemplary semiconductor structure 400, including an interconnect structure 401. The structure and materials of the layers of semiconductor structure 400 are similar to those of the layers of semiconductor structure 300. The difference in semiconductor structure 400 lies in the material and manufacturing process of dielectric layer 250, in which resistive devices 238 are formed. In some embodiments, the structure and materials of resistive device 238 in Figure 4 may be the same as or similar to those of resistive device 238 in Figure 12.

[0036] As shown in Figure 4, dielectric layer 250 is formed above etch stop layer 234. Dielectric layer 250 may include an interlayer dielectric layer. In some embodiments, dielectric layer 250 may include an interlayer dielectric layer based on crystalline SiC xO y. In some embodiments, dielectric layer 250 may have a dielectric constant of 1.0 to 5.0. In some embodiments, dielectric layer 250 may have a dielectric constant of 2.0 to 5.0. In some embodiments, dielectric layer 250 may be formed at a deposition temperature of 150°C to 425°C by chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, or other suitable processes. In some embodiments, dielectric layer 250 may or may not be formed using additional annealing or ultraviolet (UV) curing processes.

[0037] The dielectric layer 250 comprises a material with a thermal conductivity of 5 W / mK to 500 W / mK, thus rapidly dissipating the heat generated by the resistive device 238 to the outside of the component and preventing heat accumulation inside the component. For example, when the dielectric layer 250 comprises an interlayer dielectric layer based on crystalline SiC xOy, the thermal conductivity of crystalline SiC xOy can be from 200 W / mK to 400 W / mK, and the dielectric constant can be from 2.0 to 5.0, which not only provides improved thermal conductivity for the semiconductor structure 400 but also has a low dielectric constant. Therefore, the reliability and efficiency of the semiconductor structure 400 are improved.

[0038] According to some embodiments disclosed herein, Figure 5 is a cross-sectional side view of another exemplary semiconductor structure 500, including an interconnect structure 501. The structure and materials of the layers of semiconductor structure 500 are similar to those of the layers of semiconductor structure 300. The difference of semiconductor structure 500 is that semiconductor structure 500 is a structure without etch stop layers, for example, it does not have the etch stop layers 212, 220, 226, 234, 242 shown in Figures 3 and 4. In some embodiments, the structure and materials of resistor device 238 in Figure 5 may be the same as or similar to those of resistor device 238 in Figure 12.

[0039] Following operation 304 in Figure 11, which forms the conductive layer 210 in the dielectric layer 208, a capping layer 280 may be selectively formed over the conductive layer 210, as shown in Figure 5. In some embodiments, the capping layer 280 may comprise graphene. In some embodiments, the capping layer 280 may comprise Si xN y. In some embodiments, the capping layer 280 may be selectively deposited on the conductive layer 210 at a deposition temperature of 150°C to 425°C using atomic layer deposition, chemical vapor deposition, or other suitable processes.

[0040] For example, the surfaces of dielectric layer 208 and conductive layer 210 can be plasma-treated to remove metal oxides formed on the upper surface of conductive layer 210 and promote the deposition of capping layer 280 (e.g., graphene). The plasma treatment can also modify the surface of dielectric layer 208 to suppress graphene growth on its surface. Therefore, graphene can be selectively deposited only on conductive layer 210, for example, Cu. During the plasma treatment, the substrate temperature is maintained between approximately 25°C (room temperature) and approximately 425°C. In some embodiments, the plasma input power is approximately 100W to approximately 1000W.

[0041] Plasma processing may include single-step or multi-step processes, each of which may involve a hydrogen-based gas, an ammonia-based gas, or an argon-based gas. In some embodiments, a self-assembled monolayer (SAM) (not shown) is formed on the surface of dielectric layer 208, which may further suppress the deposition of graphene layers. The self-assembled monolayer may be formed from silane-based materials, phosphate-based materials, amine-based materials, and / or thiol-based materials. In some embodiments, plasma processing may be omitted.

[0042] Following plasma treatment, a capping layer 280, such as graphene, is selectively formed on the surface of the conductive layer 210. In some embodiments, the graphene layer can be formed by thermochemical vapor deposition or plasmachemical vapor deposition using one or more of methane, ethane, propane, or other hydrocarbon gases, as well as hydrogen. The graphene layer can be a single-layer or multi-layer structure. The graphene layer can be selectively formed on the surface of the conductive layer 210, as the underlying metal, such as Cu or Ni, promotes the growth of the graphene layer. During graphene formation, the substrate temperature is maintained between 150°C and 425°C.

[0043] As shown in Figure 5, capping layer 282 can be selectively formed on conductive layer 216, capping layer 284 can be selectively formed on conductive layer 224, capping layer 286 can be formed on selectively conductive layer 230, and capping layer 288 can be selectively formed on conductive layer 240. Capping layers 282, 284, 286, and 288 can include the same material as capping layer 280 and are formed by the same process as capping layer 280. By forming capping layers 280, 282, 284, 286, and 288 on conductive layers 210, 216, 224, 230, and 240 respectively, etch stop layers between dielectric layers, such as etch stop layers 212, 220, 226, 234, and 242 shown in Figures 3 and 4, can be omitted, and capping layers 280, 282, 284, 286, and 288 can serve as etch stop layers.

[0044] According to some embodiments disclosed herein, Figure 6 is a cross-sectional side view of another exemplary semiconductor structure 600, including an interconnect structure 601. The structure and materials of the layers of semiconductor structure 600 are similar to those of the layers of semiconductor structure 500. The difference between semiconductor structure 600 and semiconductor structure 500 lies in the material and manufacturing process of the dielectric layer 250 in which the resistive device 238 is formed, rather than the dielectric layer 236 in which the resistive device 238 is formed. In some embodiments, the structure and materials of the resistive device 238 in Figure 6 may be the same as or similar to those of the resistive device 238 in Figure 12.

[0045] As shown in Figure 6, dielectric layer 250 is formed over dielectric layer 228 and capping layer 286. Dielectric layer 250 may include an interlayer dielectric layer. In some embodiments, dielectric layer 250 may include an interlayer dielectric layer based on crystalline SiC xO y. In some embodiments, dielectric layer 250 may have a dielectric constant of 1.0 to 5.0. In some embodiments, dielectric layer 250 may have a dielectric constant of 2.0 to 5.0. In some embodiments, dielectric layer 250 may be formed at a deposition temperature of 150°C to 425°C by chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, or other suitable processes. In some embodiments, dielectric layer 250 may or may not be formed using additional annealing or ultraviolet (UV) curing processes.

[0046] The dielectric layer 250 comprises a material with a thermal conductivity of 5 W / mK to 500 W / mK, thus rapidly dissipating the heat generated by the resistive device 238 to the outside of the component and preventing heat accumulation inside the component. For example, when the dielectric layer 250 comprises an interlayer dielectric layer based on crystalline SiC xOy, the thermal conductivity of crystalline SiC xOy can be from 200 W / mK to 400 W / mK, and the dielectric constant can be from 2.0 to 5.0, which not only provides improved thermal conductivity for the semiconductor structure 600 but also has a low dielectric constant. Therefore, the reliability and efficiency of the semiconductor structure 600 are improved.

[0047] According to some embodiments of this disclosure, Figure 7 is a cross-sectional side view of another exemplary semiconductor structure 700, including an interconnect structure 701. As shown in Figure 7, a dielectric layer 252 is formed over a mid-process structure 206. In some embodiments, the dielectric layer 252 may include an interlayer dielectric layer. In some embodiments, the dielectric layer 252 may include an interlayer dielectric layer based on crystalline SiC xO y. In some embodiments, the dielectric layer 252 may have a dielectric constant of 1.0 to 5.0. In some embodiments, the dielectric layer 252 may have a dielectric constant of 2.0 to 5.0. In some embodiments, the dielectric layer 252 may be formed at a deposition temperature of 150°C to 425°C by chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, or other suitable processes. In some embodiments, the dielectric layer 252 may or may not be formed using additional annealing or ultraviolet (UV) curing processes. In some embodiments, the dielectric layer 252 comprises the same material as the dielectric layer 250.

[0048] A conductive layer 210 is formed in the dielectric layer 252. In some embodiments, the material and manufacturing process of the conductive layer 210 of the semiconductor structure 700 may be similar to those of the conductive layer 210 of the semiconductor structure 300. One or more etch stop layers 212 may be formed over the dielectric layer 252 and the conductive layer 210. When the conductive component 218 is subsequently formed in the dielectric layer 254, the etch stop layer 212 may be used to control the etch depth in the dielectric layer 254. In some embodiments, the material and manufacturing process of the etch stop layer 212 of the semiconductor structure 700 may be similar to those of the etch stop layer 212 of the semiconductor structure 300.

[0049] A dielectric layer 254 is formed on the etch stop layer 212. In some embodiments, the dielectric layer 254 may comprise the same material as the dielectric layer 252. In some embodiments, the dielectric layer 254 may be formed using a process similar to that used to form the dielectric layer 252. A conductive layer 216 is formed in the dielectric layer 254 and is electrically contacted with the conductive layer 210 via a conductive component 218. In some embodiments, the material and manufacturing process of the conductive layer 216 of the semiconductor structure 700 may be similar to those of the conductive layer 216 of the semiconductor structure 300. In some embodiments, the material and manufacturing process of the conductive component 218 of the semiconductor structure 700 may be similar to those of the conductive component 218 of the semiconductor structure 300.

[0050] It is understood that, in some embodiments, a stack of more than one interconnect layer may be formed on the intermediate process structure 206, such as dielectric layer 252, etch stop layer 212, and dielectric layer 254, including conductive layer 210, conductive layer 216, and conductive component 218 formed therein. For example, as shown in Figure 7, etch stop layer 220 is formed over dielectric layer 254 and conductive layer 216. Dielectric layer 256 is formed over etch stop layer 220, and conductive layer 224 is formed in dielectric layer 256. Etch stop layer 226 is formed over dielectric layer 256 and conductive layer 224, and dielectric layer 258 is formed over etch stop layer 226. Subsequently, conductive layer 230 is formed in dielectric layer 258, electrically contacting conductive layer 224 via conductive component 232. The materials and manufacturing processes of dielectric layer 256, conductive layer 224, etch stop layer 226, dielectric layer 258, conductive layer 230 and conductive component 232 can be similar to those of dielectric layer 252, conductive layer 210, etch stop layer 212, dielectric layer 254, conductive layer 216 and conductive component 218, respectively.

[0051] An etch stop layer 234 is formed over the dielectric layer 258 and the conductive layer 230, and a dielectric layer 250 is formed over the etch stop layer 234. A resistor device 238 is then formed in the dielectric layer 250. In some embodiments, the structure and materials of the resistor device 238 in Figure 7 may be the same as or similar to those of the resistor device 238 in Figure 12.

[0052] The dielectric layer 250 may include an interlayer dielectric layer. In some embodiments, the dielectric layer 250 may include an interlayer dielectric layer based on crystalline SiC xOy. In some embodiments, the dielectric layer 250 may have a dielectric constant of 1.0 to 5.0. In some embodiments, the dielectric layer 250 may have a dielectric constant of 2.0 to 5.0. In some embodiments, the dielectric layer 250 may be formed at a deposition temperature of 150°C to 425°C by chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, or other suitable processes. In some embodiments, the dielectric layer 250 may be formed with or without additional annealing or ultraviolet (UV) curing processes. In some embodiments, Si(CH3)4, (CH3)3SiH, and / or CO2 may be used as precursors for forming the interlayer dielectric layer (dielectric layer 250) based on crystalline SiC xOy.

[0053] The dielectric layer 250 comprises a material with a thermal conductivity of 5 W / mK to 500 W / mK, thus rapidly dissipating the heat generated by the resistive device 238 to the outside of the component and preventing heat accumulation inside the component. For example, when the dielectric layer 250 comprises an interlayer dielectric layer based on crystalline SiC xOy, the thermal conductivity of crystalline SiC xOy can be from 200 W / mK to 400 W / mK, and the dielectric constant can be from 2.0 to 5.0, which not only provides improved thermal conductivity for the semiconductor device but also has a low dielectric constant. Therefore, the reliability and efficiency of the semiconductor structure 700 are improved.

[0054] It is understood that, in some embodiments, one or more stacks of interconnect layers may be further formed on dielectric layer 250. For example, as shown in Figure 7, conductive layer 240 is formed in dielectric layer 250. Etch stop layer 242 is formed on dielectric layer 250 and conductive layer 240, and dielectric layer 260 is formed on etch stop layer 242. Subsequently, conductive layer 246 is formed in dielectric layer 260, electrically contacting conductive layer 240 via conductive component 248. In some embodiments, conductive layer 246 and conductive component 248 may be formed in dielectric layer 260 by dual damascene, single damascene, half damascene, or other suitable processes.

[0055] According to some embodiments of this disclosure, Figure 8 is a cross-sectional side view of another exemplary semiconductor structure 800, including an interconnect structure 801. The structure and materials of the layers of semiconductor structure 800 are similar to those of the layers of semiconductor structure 700. The difference in semiconductor structure 800 lies in the material and manufacturing process of the dielectric layer 236 in which the resistive device 238 is formed, rather than in the dielectric layer 250 in which the resistive device 238 is formed. In some embodiments, the structure and materials of the resistive device 238 in Figure 8 may be the same as or similar to those of the resistive device 238 in Figure 12.

[0056] As shown in Figure 8, dielectric layer 236 is formed above etch stop layer 234. Dielectric layer 236 may include an interlayer dielectric layer. In some embodiments, dielectric layer 236 may include an interlayer dielectric layer based on SiC xN y. For example, dielectric layer 236 may include carbon-doped Si 3N 4. For another example, dielectric layer 236 may be SiBC xN y. In some embodiments, dielectric layer 236 may have a dielectric constant of 2.0 to 5.0. In some embodiments, dielectric layer 236 may have a dielectric constant of 3.5 to 5.0. In some embodiments, dielectric layer 236 may be formed at a deposition temperature of 150°C to 425°C by chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, or other suitable processes. In some embodiments, dielectric layer 236 may or may not be formed using additional annealing or ultraviolet (UV) curing processes. In some embodiments, Si(CH3)4, (CH3)3SiH, NH3 and / or N2 can be used as precursors for forming an interlayer dielectric layer (dielectric layer 236) based on SiCxNy. Different precursors and process conditions can be used when forming dielectric layer 236 compared to dielectric layer 250.

[0057] The dielectric layer 236 comprises a material with a thermal conductivity ranging from 5 W / mK to 500 W / mK, thus rapidly dissipating the heat generated by the resistive device 238 to the outside of the component and preventing heat accumulation inside the component. For example, when the dielectric layer 236 comprises carbon-doped Si3N4, the thermal conductivity of carbon-doped Si3N4 can be from 200 W / mK to 400 W / mK, and the dielectric constant can be from 2.0 to 5.0, which not only provides improved thermal conductivity for the semiconductor device but also has a low dielectric constant. Therefore, the semiconductor structure 800 can significantly improve the reliability and efficiency of the semiconductor device.

[0058] According to some embodiments of this disclosure, Figure 9 is a cross-sectional side view of another exemplary semiconductor structure 900, including an interconnect structure 901. The structure and materials of the layers of semiconductor structure 900 are similar to those of the layers of semiconductor structure 700. The difference of semiconductor structure 900 is that semiconductor structure 900 is a structure without an etch stop layer. As shown in Figure 9, a capping layer 280 may be formed over conductive layer 210. In some embodiments, capping layer 280 may include graphene. In some embodiments, capping layer 280 may include Si xN y. In some embodiments, the materials and manufacturing processes of capping layer 280 in semiconductor structure 900 may be similar to those of capping layer 280 in semiconductor structure 500. In some embodiments, the structure and materials of resistor device 238 in Figure 9 may be the same as or similar to those of resistor device 238 in Figure 12.

[0059] According to some embodiments disclosed herein, Figure 10 is a cross-sectional side view of another exemplary semiconductor structure 1000, including an interconnect structure 1001. The structure and materials of the layers of semiconductor structure 1000 are similar to those of the layers of semiconductor structure 900. The difference between semiconductor structure 1000 and semiconductor structure 900 lies in the material and manufacturing process of the dielectric layer 236 in which the resistive device 238 is formed. In some embodiments, the structure and materials of the resistive device 238 in Figure 10 may be the same as or similar to those of the resistive device 238 in Figure 12.

[0060] As shown in Figure 10, dielectric layer 236 is formed over dielectric layer 258 and capping layer 286. Dielectric layer 236 may include an interlayer dielectric layer. In some embodiments, dielectric layer 236 may include an interlayer dielectric layer based on SiC xN y. For example, dielectric layer 236 may include carbon-doped Si 3N 4. For another example, dielectric layer 236 may be SiBC xN y. In some embodiments, dielectric layer 236 may have a dielectric constant of 2.0 to 5.0. In some embodiments, dielectric layer 236 may have a dielectric constant of 3.5 to 5.0. In some embodiments, dielectric layer 236 may be formed at a deposition temperature of 150°C to 425°C by chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, or other suitable processes. In some embodiments, dielectric layer 236 may or may not be formed using additional annealing or ultraviolet (UV) curing processes.

[0061] The dielectric layer 236 comprises a material with a thermal conductivity of 5 W / mK to 500 W / mK, thus rapidly dissipating the heat generated by the resistive device 238 and preventing heat accumulation within the semiconductor structure 1000. For example, when the dielectric layer 236 comprises carbon-doped Si3N4, the thermal conductivity of carbon-doped Si3N4 can be from 200 W / mK to 400 W / mK, and the dielectric constant can be from 2.0 to 5.0, which not only provides improved thermal conductivity for the semiconductor device but also has a low dielectric constant. Therefore, the reliability and efficiency of the semiconductor structure 1000 are improved.

[0062] According to some of the above embodiments, the interlayer dielectric layer, such as dielectric layer 236 or dielectric layer 250, in which the resistive device 238 is formed can help dissipate heat from the resistive device 238, thereby improving the performance of the semiconductor device. At the same time, by using the materials and processes described in some of the above embodiments to form the interlayer dielectric layer, such as dielectric layer 236 or dielectric layer 250, a low dielectric constant value for the interlayer dielectric layer can also be maintained.

[0063] In one example aspect, this disclosure provides an interconnect structure comprising: a first dielectric layer; a first conductive layer disposed in the first dielectric layer; a second dielectric layer disposed above the first dielectric layer; a second conductive layer disposed in the second dielectric layer and electrically contacting the first conductive layer; a third dielectric layer disposed above the second dielectric layer, wherein the third dielectric layer comprises a silicon carbide (SiCN) based material; and a resistive device disposed in the third dielectric layer.

[0064] In some embodiments, the first dielectric layer and the second dielectric layer comprise silicon carbide-based materials.

[0065] In some embodiments, the materials of the first dielectric layer and the second dielectric layer are different from those of the third dielectric layer.

[0066] In some embodiments, the first dielectric layer and the second dielectric layer comprise a material based on crystalline silicon carbide (SiOC).

[0067] In some embodiments, the method further includes: a first etch stop layer disposed between the second dielectric layer and the first dielectric layer; and a second etch stop layer disposed between the third dielectric layer and the second dielectric layer.

[0068] In some embodiments, the method further includes: a first capping layer disposed on the first conductive layer; and a second capping layer disposed on the second conductive layer, wherein the second dielectric layer directly contacts the first dielectric layer, and the third dielectric layer directly contacts the second dielectric layer.

[0069] In some embodiments, the first capping layer and the second capping layer comprise graphene.

[0070] In some embodiments, the first capping layer and the second capping layer comprise silicon nitride.

[0071] In other embodiments, this disclosure provides an interconnect structure including: a first dielectric layer; a first conductive layer disposed in the first dielectric layer; a second dielectric layer disposed above the first dielectric layer; a second conductive layer disposed in the second dielectric layer and electrically contacting the first conductive layer; a third dielectric layer disposed above the second dielectric layer, wherein the third dielectric layer comprises a material based on crystalline silicon oxide (SiOC); and a resistive device disposed in the third dielectric layer.

[0072] In other embodiments, the thermal conductivity of the third dielectric layer ranges from 5 W / mK to 500 W / mK.

[0073] In other embodiments, the dielectric constant of the third dielectric layer is between 1.0 and 7.0.

[0074] In other embodiments, the first and second dielectric layers comprise silicon carbide-based materials.

[0075] In other embodiments, the first and second dielectric layers comprise silicon carbide-based materials.

[0076] In other embodiments, the second dielectric layer and the first dielectric layer are separated by a first etch stop layer, and the third dielectric layer and the second dielectric layer are separated by a second etch stop layer.

[0077] In other embodiments, it further includes: a first capping layer disposed on the first conductive layer; and a second capping layer disposed on the second conductive layer, wherein the second dielectric layer directly contacts the first dielectric layer, and the third dielectric layer directly contacts the second dielectric layer.

[0078] In other embodiments, the resistive device includes a high-resistance layer covered by at least one dielectric layer.

[0079] In yet another embodiment, this disclosure provides a method for forming an interconnect structure, comprising: forming a first dielectric layer on a semiconductor substrate; forming a first conductive layer in the first dielectric layer; forming a second dielectric layer above the first dielectric layer; forming a second conductive layer in the second dielectric layer, the second conductive layer and the first conductive layer being in electrical contact; forming a third dielectric layer above the second dielectric layer, the third dielectric layer having a thermal conductivity of 5 W / mK to 500 W / mK; and forming a resistive device in the third dielectric layer.

[0080] In some other embodiments, the third dielectric layer comprises a silicon carbide-based material or a crystalline silicon oxide-based material.

[0081] In some other embodiments, it further includes: forming a first capping layer on a first conductive layer; and forming a second capping layer on a second conductive layer, wherein the second dielectric layer directly contacts the first dielectric layer, and the third dielectric layer directly contacts the second dielectric layer.

[0082] In some other embodiments, the method further includes: selectively depositing a first capping layer on a first conductive layer; and selectively depositing a second capping layer on a second conductive layer.

[0083] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the embodiments of the present invention, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of the embodiments of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0084] 100: Semiconductor Device Structure 101:Substrate 102: Device 103: Quarantine Zone 104: Source / Drain Region 106: Gate Stacking 108: Passage Area 110: Electrode layer 112: Dielectric layer 114: Dielectric layer 116: Adaptive Layer 118: Spacer 120: Silicon layer 122: Contact element 124: Contact Etching Stop Layer 126: Interlayer Dielectric 200: Interconnection Structure 202:Substrate 204: Apparatus 206: Mid-range process architecture 208: Dielectric layer 210: Conductive layer 212: Etching Stop Layer 214: Dielectric layer 216: Conductive layer 218: Conductive components 220: Etching Stop Layer 222: Dielectric layer 224: Conductive layer 226: Etching Stop Layer 228: Dielectric layer 230: Conductive layer 232: Conductive components 234: Etching Stop Layer 236: Dielectric layer 238: Resistor device 240: Conductive layer 242: Etching Stop Layer 244: Dielectric layer 246: Conductive layer 248: Conductive components 250: Dielectric layer 252: Dielectric layer 254: Dielectric layer 256: Dielectric layer 258: Dielectric layer 260: Dielectric layer 280: Cap layer 282: Cap layer 284: Cap layer 286: Cap layer 288: Cap layer 300: Semiconductor Structure 301: Interconnection Structure 302: Operation 304: Operation 306: Operation 308: Operation 310: Operation 312: Operation 400: Semiconductor Structure 401: Interconnection Structure 500: Semiconductor Structure 501: Interconnection Structure 600: Semiconductor Structure 601: Interconnection Structure 700: Semiconductor Structure 701: Interconnection Structure 800: Semiconductor Structure 801: Interconnection Structure 900: Semiconductor Structure 901: Interconnection Structure 1000: Semiconductor Structure 1001: Interconnection Structure 1100: Method 2381: Silicon barrier layer 2382: Oxide layer 2383: High-resistivity material layer 2384: Silicon barrier layer 2385: Oxide layer 2386: Oxide layer 2387: Guide Hole Structure AA: Line BB: Line

Claims

1. An interconnection structure, comprising: First dielectric layer; A first conductive layer is disposed in the first dielectric layer; A second dielectric layer is disposed above the first dielectric layer; A second conductive layer is disposed in the second dielectric layer and is electrically in contact with the first conductive layer; a third dielectric layer is disposed above the second dielectric layer, wherein the third dielectric layer comprises a silicon carbide (SiCN) based material, and the materials of the first dielectric layer and the second dielectric layer are different from those of the third dielectric layer; And a resistive device disposed in the third dielectric layer, wherein the resistive device includes: a first silica barrier layer; a first oxide layer on the first silica barrier layer; a high-resistivity material layer on the first oxide layer; a second silica barrier layer on the high-resistivity material layer; and a second oxide layer on the second silica barrier layer.

2. The interconnect structure as described in claim 1, wherein the first dielectric layer and the second dielectric layer comprise silicon carbide-based materials.

3. The interconnect structure as described in claim 1, wherein the first dielectric layer and the second dielectric layer comprise a material based on crystalline silicon oxide (SiOC).

4. The interconnection structure as described in claim 1 further includes: A first etch stop layer is disposed between the second dielectric layer and the first dielectric layer; And a second etch stop layer is disposed between the third dielectric layer and the second dielectric layer.

5. The interconnection structure as described in claim 1, further comprising: A first capping layer is disposed on the first conductive layer; And a second capping layer disposed on the second conductive layer, wherein the second dielectric layer directly contacts the first dielectric layer, and the third dielectric layer directly contacts the second dielectric layer.

6. An interconnection structure, comprising: First dielectric layer; A first conductive layer is disposed in the first dielectric layer; A second dielectric layer is disposed above the first dielectric layer; A second conductive layer is disposed in the second dielectric layer and electrically contacts the first conductive layer; a third dielectric layer is disposed above the second dielectric layer, wherein the third dielectric layer comprises a material based on crystalline silicon oxide (SiOC); and a resistive device is disposed in the third dielectric layer.

7. The interconnect structure as described in claim 6, wherein the thermal conductivity of the third dielectric layer is from 5 W / mK to 500 W / mK.

8. The interconnect structure as described in claim 7, wherein the dielectric constant of the third dielectric layer is from 1.0 to 7.

0.

9. The interconnect structure as claimed in claim 6, wherein the second dielectric layer and the first dielectric layer are separated by a first etch stop layer, and the third dielectric layer and the second dielectric layer are separated by a second etch stop layer.

10. A method for forming an interconnect structure, comprising: A first dielectric layer is formed on a semiconductor substrate; A first conductive layer is formed in the first dielectric layer; A first capping layer is formed on the first conductive layer; a second dielectric layer is formed above the first dielectric layer; a second conductive layer is formed in the second dielectric layer, and the second conductive layer and the first conductive layer are in electrical contact; a second capping layer is formed on the second conductive layer; a third dielectric layer is formed above the second dielectric layer, the third dielectric layer having a thermal conductivity of 5 W / mK to 500 W / mK, wherein the second dielectric layer is in direct contact with the first dielectric layer, and the third dielectric layer is in direct contact with the second dielectric layer; And forming a resistive device in the third dielectric layer, wherein forming the resistive device includes: depositing a first silica barrier layer; depositing a first oxide layer; depositing a high-resistivity material layer; depositing a second silica barrier layer; and depositing a second oxide layer.

11. An interconnection structure, comprising: First dielectric layer; A first conductive layer is disposed in the first dielectric layer; A second dielectric layer is disposed above the first dielectric layer; A second conductive layer is disposed in the second dielectric layer and is in electrical contact with the first conductive layer; a third dielectric layer is disposed above the second dielectric layer, wherein the third dielectric layer has a thermal conductivity of 5 W / mK to 500 W / mK and the third dielectric layer contains a material different from the first dielectric layer and the second dielectric layer. And a resistive device disposed in the third dielectric layer, wherein the resistive device includes: a first silica barrier layer; a first oxide layer on the first silica barrier layer; a high-resistivity material layer on the first oxide layer; a second silica barrier layer on the high-resistivity material layer; and a second oxide layer on the second silica barrier layer.

12. An interconnection structure, comprising: A first dielectric layer, comprising a dielectric material; A first conductive layer is disposed in the first dielectric layer; A second dielectric layer is disposed above the first dielectric layer, wherein the second dielectric layer comprises a material based on crystalline silicon oxide, which is different from the dielectric material; And a resistive device disposed in the second dielectric layer, wherein the resistive device includes: a first silicate barrier layer; a first oxide layer on the first silicate barrier layer; a high-resistivity material layer on the first oxide layer; a second silicate barrier layer on the high-resistivity material layer; and a second oxide layer on the second silicate barrier layer.

13. An interconnection structure, comprising: A first dielectric layer comprising carbon-doped Si3N4 or SiBCxNy; A first conductive layer is disposed in the first dielectric layer; A second dielectric layer is disposed above the first dielectric layer, wherein the second dielectric layer comprises a material based on crystalline silicon oxide; and a resistive device disposed in the second dielectric layer, wherein the resistive device includes: a first oxide layer; a high-resistivity material layer on the first oxide layer; and a second oxide layer on the high-resistivity material layer.

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