Memory device, memory stack, and method of forming memory stack

Abstract

A memory device includes: an alternating stack of silicon oxide layers and word line layers; each word line layer includes a bipolar region adjacent to the silicon oxide layer, the bipolar regions comprising a nitride, carbide, oxide, carbonitride, or a combination thereof of a bipolar metal. The bipolar regions are formed by driving a bipolar film into the gate oxide layer of the word line layer and removing any residual bipolar film.

Description

[Technical Field]

[0001] Embodiments of this invention generally relate to bipolar regions in vertical NAND (V-NAND) or three-dimensional NAND (3D NAND) memory devices. In a particular embodiment, the memory stack of the memory device includes alternating silicon oxide layers and word line layers, and each word line layer includes a bipolar region adjacent to the silicon oxide layer. [Previous Technology]

[0002] Semiconductor technology is developing rapidly, and device sizes are shrinking with technological advancements to provide faster processing and storage per unit space. In NAND devices, scaling involves increasing the number of layers from 48P to greater than 300P (commonly referred to as oxide / nitride stacking). Existing V-NAND memory stacks with alternating oxide and nitride layers require replacement metal gate (RMG) processes to create word lines. The nitride layers in oxide / nitride stacks are replaced by word line metals (or gate metals), typically tungsten (W) or molybdenum (Mo).

[0003] As word line thickness decreases from removing SiN from oxide / nitride die stacks, and as thinner TiN barrier layers or adhesive layers or barrier-free metal-filled designs are required, the critical voltage (Vt) for read / write word lines is affected.

[0004] Therefore, there is a need for systems and methods that can provide a consistent critical voltage (Vt) for the device as the device becomes smaller. [Summary of the Invention]

[0005] One or more embodiments of this invention are directed to a memory device comprising: an alternating stack of silicon oxide layers and word line layers; and each of the word line layers comprises a bipolar region adjacent to the silicon oxide layer, the bipolar regions comprising a nitride, carbide, oxide, carbonitride, or a combination thereof of a bipolar metal.

[0006] An additional embodiment of this invention relates to a memory stack on a substrate, comprising: a plurality of alternating silicon oxide layers and word line layers on the substrate; a plurality of memory vias through at least some of the thickness of the alternating silicon oxide layers and word line layers; and each word line layer comprising: a gate oxide layer including one or more bipolar regions, a gate metal filler layer, and, where appropriate, a barrier layer between the gate oxide layer and the gate metal filler layer, wherein the bipolar regions are adjacent to portions of each silicon oxide layer and memory via, the bipolar regions comprising: a nitride, carbide, oxide, carbonitride, or a combination thereof of bipolar metals and a bipolar metal, wherein the negative charge of the bipolar metal is greater than the negative charge of the metal of the gate metal oxide layer.

[0007] A further embodiment of this invention relates to a method for forming a memory stack, the method comprising: depositing a gate metal oxide layer in alternating openings between silicon oxide layers of the memory stack on a substrate; preparing a bipolar thin film by exposing a substrate surface to a precursor comprising a bipolar metal and, where appropriate, to an auxiliary agent comprising nitrogen, oxygen, and / or carbon; exposing the substrate to a heat treatment, where appropriate, to form a bipolar region; removing any residue of the bipolar thin film; and depositing a metal gate fill layer in the openings. In one or more embodiments, the bipolar film is prepared on a gate oxide layer and the substrate is exposed to a heat treatment to drive the bipolar film into the gate metal oxide layer to form a bipolar region, and the method includes removing any residue of the bipolar film. In one or more embodiments, the bipolar film is prepared on a silicon oxide layer to form a bipolar region, and the gate metal oxide layer is deposited on the bipolar film.

Implementation Method

[0014] Before describing several exemplary embodiments of this invention, it should be understood that this invention is not limited to the details of the construction or process steps set forth in the following description. This invention can have other embodiments and can be practiced or performed in various ways.

[0015] As used in this specification and the accompanying claims, the term "substrate" means a surface on which a process is performed, or a portion thereof. It should also be understood by those skilled in the art that reference to a substrate may also mean only a portion of a substrate, unless the context clearly indicates otherwise. Additionally, reference to deposition on a substrate may mean both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0016] As used herein, “substrate” means any substrate on which a thin film treatment is performed during a manufacturing process or a material surface formed on a substrate. For example, depending on the application, substrate surfaces on which treatments can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes such as polishing, etching, reduction, oxidation, hydroxylation, annealing, ultraviolet (UV) curing, electron beam curing, and / or baking of the substrate surface. In addition to thin film treatments performed directly on the surface of the substrate itself, any of the disclosed thin film treatment steps may also be performed on an underlayer formed on the substrate as disclosed in more detail below, and the term “substrate surface” is intended to include this underlayer as indicated by the context. Therefore, for example, in the case where a thin film / layer or part of a thin film / layer has already been deposited on the substrate surface, the exposed surface of the newly deposited thin film / layer becomes the substrate surface.

[0017] To avoid ambiguity, the identification of materials disclosed herein does not imply stoichiometry. For example, TiN materials contain titanium and nitrogen. These elements may or may not be present in a 1:1 ratio.

[0018] The embodiments of this case relate to volume-free bipolar-based threshold voltage (Vt) tuning in V-NAND metallization. Advantageously, bipolar formation between a silicon oxide layer and a gate metal oxide layer can be used to fabricate memory stacks with appropriate threshold voltage (Vt) as word line thickness decreases. The bipolar region provides enhanced Vt as a barrier layer or binder layer (e.g., TiN), which is thin or completely removed. For some prior art, the thickness of the TiN barrier layer is in the range of 20 Å to 30 Å.

[0019] As the thickness of the TiN barrier layer decreases and approaches zero, the resistivity decreases. Experiments on the resistivity of silicon oxide and word line stacks (without bipolar regions) are shown in Figure 5 and summarized in Table 1. Further improvements in resistivity can be expected with further technological advancements. Table 1 Unobstructed TiN barrier 40 Å α-W 40 Å α-W 31.4 @ 90 Å 39.7 @ 128 Å 20 @ 140 Å 24.8 @ 180 Å 16.0 @ 186 Å 16.2 @ 275 Å

[0020] For extrapolated values ​​of 20 nm stack thickness at 40 Å α-W, the resistivity of the barrier-free stack (15 μΩ·cm) is reduced by 35% compared to the TiN barrier-containing stack (23 μΩ·cm). For barrier-free (15 Å α-W), the resistivity is 16.5 μΩ·cm. Therefore, as the thickness of the TiN barrier layer decreases and approaches zero, the Vt of the stack decreases. In one or more embodiments, the presence of bipolar regions in the memory stack and / or memory device effectively compensates for Vt when the thickness of the barrier layer is reduced to less than 20 Å and even to zero. In one or more embodiments, the Vt benefit is increased without affecting the thickness of the stack because the bipolar film is driven into the gate metal oxide layer. In one or more embodiments, the bipolar regions effectively increase Vt in the range of 100 to 250 mV, and all values ​​and subranges therein or more, without increasing the thickness of the stack.

[0021] One or more embodiments of this invention provide apparatus and methods of forming which are particularly useful in forming vertical NAND (V-NAND) or 3D NAND memory devices, and will be described in this context. Other apparatus and applications are also within the scope of this invention.

[0022] Figure 1 illustrates a perspective cut-out cross-sectional view of the memory device 100. Figure 2 is a cross-sectional view of a stack of memory devices that may exist in a memory device according to one or more embodiments of the present invention. For Figures 1 and 2, the device 100 includes a substrate 101 and alternating silicon oxide layers 132 and word line layers 134, each of which is in contact with a plurality of memory vias 120, which may be multilayered. In some embodiments, the substrate 110 comprises silicon. Typically, each word line layer includes a bipolar region 136 adjacent to the silicon oxide layer 132, the bipolar region 136 comprising a nitride, carbide, oxide, carbonitride, or a combination thereof of a bipolar metal.

[0023] According to one or more embodiments, each of the word line layers 134 includes: a gate metal oxide layer 138, one or more having bipolar regions 136; a barrier layer 140, if applicable; and a metal gate fill layer 142. The bipolar regions 136 are adjacent to the silicon oxide layer 132.

[0024] In some embodiments, the gate metal oxide layer 138 comprises a metal oxide. In some embodiments, the gate metal oxide layer 138 comprises hafnium oxide (e.g., HfO2) or aluminum oxide (e.g., Al2O3). The gate metal oxide layer may be deposited by an atomic layer deposition (ALD) process and may be amorphous and have a thickness between about 20 Å and about 30 Å, and all values ​​and subranges therebetween.

[0025] The bipolar region is adjacent to each silicon layer in the horizontal direction and to a portion of the memory via 120 in the vertical direction, wherein the word line layer intersects with the memory via. The bipolar region 136 comprises: a nitride, carbide, oxide, carbonitride, or combination of the bipolar metal and the bipolar metal. In one or more embodiments, the bipolar metal has a higher electronegativity than the metal of the gate metal oxide layer. In one or more embodiments, the gate oxide layer comprises hafnium oxide, and the bipolar metal comprises: zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), titanium (Ti), zirconium (Zr), niobium (Nb), or a mixture of the above. In one or more embodiments, the gate oxide layer comprises aluminum oxide, and the bipolar region comprises: zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), or a mixture of the above.

[0026] In some embodiments, the barrier layer 140 comprises or is substantially composed of TiN. As used in this regard, "substantially composed of" means that the elements constitute greater than 95%, greater than 98%, greater than 99%, or greater than 99.5% of the material on an atomic basis.

[0027] The barrier layer 140 may have any suitable thickness. In some embodiments, the thickness of the barrier layer 140 is in the range of greater than or equal to 5 Å to less than or equal to 25 Å. In some embodiments, the thickness of the barrier layer is about 10 Å, including 10 Å ± 10%, 10 Å ± 5%, and / or 10 Å ± 1%.

[0028] In some embodiments, there is no barrier layer. In one or more embodiments, the memory device or memory stack does not include a TiN layer.

[0029] The gate metal filler layer 142 comprises any suitable material. The gate metal filler layer 142 may have any suitable thickness. In some embodiments, the thickness of the gate metal filler layer 142 is in the range of greater than or equal to 5 Å to less than or equal to 50 Å. Typically, the gate material filler may be selected based on the desired performance and performance improvement. In one or more embodiments, the gate metal filler layer comprises tungsten (W) or molybdenum (Mo).

[0030] The threshold voltage (Vt) provides the characteristics of the memory stack. Including a bipolar region in the gate metal oxide layer of the memory stack increases Vt. In one or more embodiments, the bipolar region increases Vt by more than or equal to +150 mV relative to a comparison stack without a bipolar region.

[0031] The memory device further includes a plurality of memory vias 120 extending through at least some of the thickness of alternating silicon oxide layers 132 and word line layers 134. Each of the memory vias 120 has a core oxide 112 surrounded by a memory via semiconductor material 114. The memory via semiconductor material 114 is surrounded by memory via dielectrics 116, 118. In some embodiments, the memory via dielectrics 116, 118 include a third layer 117. In some embodiments, the memory via dielectrics include a first memory via oxide layer, a memory via nitride layer, and a second memory via oxide layer.

[0032] In the embodiment shown in Figures 1 and 2, there are two word line layers 134 alternating with the three silicon oxide layers. Those skilled in the art will recognize that this represents only one possible configuration. In some embodiments, there are 48 pairs of word line layers / silicon oxide layers, or 72 pairs, or 96 pairs, or 144 pairs, or even 196 pairs of word line layers / silicon oxide layers.

[0033] Each layer of the memory stack lies within a plane formed by a first direction 101 and a second direction 102. In Figure 2, the first direction 101 is illustrated on the page as a left-to-right direction, the second direction 102 extends in a direction behind the illustrated page, and a third direction 103 extends from the bottom to the top of the page. The first direction 101 and the second direction 102 may also be referred to as the X-axis direction and the Y-axis direction, or similar terms. Those skilled in the art will recognize that the second direction 102 is not limited to a direction extending 90 degrees relative to the first direction 101. The angle between the first direction 101 and the second direction 102 can be any suitable angle. Each of the alternating layers of silicon oxide layer 134 and word line layer 134 has a thickness measured along the third direction 103. The third direction 103 may also be referred to as the Z-axis direction, or similar terms. Those skilled in the art will recognize that the third direction 103 is not limited to a direction extending orthogonally to the plane formed by the first direction 101 and the second direction 102.

[0034] The alternating layers may be formed to any suitable thickness. In some embodiments, the thickness of each silicon oxide layer 132 is approximately equal. In one or more embodiments, each silicon oxide layer 132 has a first material layer thickness. In some embodiments, the thickness of each silicon oxide layer 132 is approximately equal. In some embodiments, the thickness of each word line layer 134 is approximately equal. In one or more embodiments, each word line layer 134 has a second material layer thickness. As used in this aspect, the approximately equal thicknesses are within + / - 5% of each other.

[0035] In one or more embodiments, the thickness of the silicon oxide layer 132 is in the range of about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm. In one or more embodiments, the thickness of the first material layer is in the range of about 0.5 nm to about 40 nm. In one or more embodiments, the thickness of the word line layer 134 is in the range of about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm. In one or more embodiments, the thickness of the second material layer is in the range of about 0.5 nm to about 40 nm.

[0036] Referring to Figure 3, another embodiment of this invention relates to a method 200 for forming a bipolar region. Method 200 deposits a gate metal oxide layer in alternating openings between silicon oxide layers of a memory stack on a substrate at operation 205. The gate metal oxide layer may be formed of a high-dielectric-constant dielectric material, such as hafnium dioxide (HfO2) or aluminum oxide (Al2O3). The deposition process may include an atomic layer deposition (ALD) process, wherein a metal-containing precursor and an oxygen-containing precursor are alternately transferred to an interface layer. In some embodiments, the metal-containing precursor is decontaminated between transfers of the oxygen-containing precursor. The metal may be a transition metal, such as hafnium (Hf), or other metals, such as aluminum (Al). For the oxidant, any oxygen-containing precursor that can react with the metal may be used. For example, the oxygen-containing precursor may be or include water, diatomic oxygen, ozone, hydroxyl-containing precursors or alcohols, nitrogen- and oxygen-containing precursors, plasma-enhanced oxygen including local or distal enhanced oxygen, or any other oxygen-containing material that can be bonded to a metal to produce a metal oxide layer on the interface layer. In one example, the metal-containing precursor is hafnium tetrachloride (HfCl4) and the oxidant is water (H2O) to form a hafnium dioxide (HfO2) layer. The ALD process can be performed at temperatures between 200°C and about 500°C, for example, about 270°C. The gate metal oxide layer deposited by the ALD process may be amorphous and have a thickness between about 20 Å and 30 Å.

[0037] At operation 210, a bipolar film is prepared. In one or more embodiments, the bipolar film is formed on a gate metal oxide layer. In one or more embodiments, the bipolar film is a nitride, carbide, oxide, carbonitride, or a combination thereof of a bipolar metal. In one or more embodiments, the electronegativity of the bipolar metal is greater than that of the metal in the gate metal oxide layer. In one or more embodiments, the bipolar film is formed on a silicon oxide layer before the gate metal oxide layer is deposited, and then the gate metal oxide layer is deposited on the bipolar film.

[0038] In one or more embodiments, the bipolar film is deposited by atomic layer deposition (ALD) at a substrate temperature ranging from 200°C to 500°C. ALD cycles are repeated to obtain a bipolar film of a desired thickness, such as 5 Å to 20 Å, and all values ​​and subranges therebetween. The desired thickness may be based on different materials. In some embodiments, the deposition of the bipolar film is performed by a bipolar film blanket deposition over the entire exposed surface of the gate metal oxide layer, followed by lithography and etching processes to pattern the bipolar film (i.e., forming the bipolar film in certain regions of the semiconductor structure but not in certain other regions). In a subsequent heat treatment (e.g., an annealing process) (at operation 215), dopant species from the bipolar film, such as zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), titanium (Ti), zirconium (Zr), and niobium (Nb), are diffused and bonded to the underlying gate metal oxide layer to form bipolar regions.

[0039] In one or more embodiments, atomic layer deposition is used at a first substrate temperature ranging from 200°C to 500°C, and all values ​​and subranges therein, to prepare a bipolar film on a gate metal oxide layer by exposing the substrate surface to a precursor comprising a bipolar metal, and, where appropriate, to an auxiliary agent comprising nitrogen, oxygen, or carbon. Typically, any suitable metal precursor can be used. In one or more embodiments, the first precursor comprises a metal halide or an organometallic compound. For example, for NbN films, niobium precursors may include, but are not limited to, NbCl5, NbB5, NbBr5, Nb15, NbF5, organoniobium compounds, and combinations thereof.

[0040] In one or more embodiments, the excipient comprises a compound selected from the group consisting of NH3, N2, N2H2, N2H4, nitrogen-containing plasma, and combinations thereof.

[0041] In one or more embodiments, the excipient comprises a compound selected from the group consisting of H2O, H2O2, O3, ethanol, and combinations thereof.

[0042] In one or more embodiments, the excipient comprises a compound selected from the group consisting of CH4, ethanol and H2.

[0043] In one or more embodiments, the excipient comprises a combination of two or more compounds selected from the group consisting of NH3, CH4, ethanol and H2.

[0044] At operation 215, when a bipolar film is formed on the gate metal oxide layer, the substrate is heat-treated to drive the bipolar film into the gate metal oxide layer and form bipolar regions in the gate metal oxide layer. The heat treatment is performed to allow bipolar metal dopant species to diffuse into the underlying gate metal oxide layer. In one or more embodiments, the heat treatment at operation 215 comprises a thermal annealing process performed in an inert environment (such as in a nitrogen (N2) and argon (Ar) environment) in a rapid thermal processing (RTP) chamber, such as a RADOX™ chamber available from Applied Materials, Inc., Santa Clara, California. The heat treatment is optional if the bipolar film is fabricated on alternating silicon layers.

[0045] The heat treatment of operation 215 can be performed at a temperature between about 600°C and about 1000°C (e.g., about 900°C) and at a pressure between about 0.1 Torr and 100 Torr for a time between about 1 second and about 30 seconds.

[0046] At operation 220, according to one or more embodiments, when the bipolar film is formed on the gate metal oxide layer and thermally treated to drive the film into the gate metal oxide layer, any portion of the bipolar film retained on the gate metal oxide layer is removed. The removal process may include a dry plasma etching process. The resulting structure, including the gate metal oxide layer with doped regions, may then be further processed to suit the desired application.

[0047] At operation 225, the gate metal filler is deposited into the opening above or above the gate metal oxide layer.

[0048] Depending on the circumstances, a barrier layer is deposited on the gate metal oxide layer prior to the deposition of the gate metal filler. In one or more embodiments, the barrier layer comprises TiN. In one or more embodiments, the barrier layer thickness is less than 20 Å.

[0049] The present invention includes: a method for forming a bipolar region, the method comprising: depositing a gate metal oxide layer in alternating openings between memory stacked silicon oxide layers on a substrate; preparing a bipolar thin film on the gate oxide layer by exposing a substrate surface to a precursor comprising a bipolar metal and, where appropriate, to an auxiliary agent comprising nitrogen, oxygen, and / or carbon; exposing the substrate to a heat treatment to drive the bipolar film into the gate metal oxide layer and to form a bipolar region; removing any residue of the bipolar film; and depositing a metal gate fill layer in the openings.

[0050] In one or more embodiments, the bipolar film system is prepared using atomic layer deposition at a first substrate temperature ranging from 200°C to 500°C.

[0051] In one or more embodiments, the heat treatment is performed at a second substrate temperature of at least 700°C. In one or more embodiments, the heat treatment is performed at a second substrate temperature in the range of greater than or equal to 700°C to less than or equal to 1050°C.

[0052] In one or more embodiments, before depositing the gate metal oxide layer, the openings between the silicon oxide layers of the memory stack on the substrate are formed by removing the nitride layer of the oxide / nitride mold. In one or more embodiments, memory holes are formed through the thickness of some layers of the oxide / nitride mold before removing the nitride layer of the oxide / nitride mold.

[0053] Most precursors fall within the scope of this invention. Precursors may be plasma, gas, liquid, or solid at ambient temperature and pressure. However, within the ALD chamber, the precursor evaporates. Organometallic compounds or complexes include any chemical containing a metal and at least one organic group, such as alkyl, alkoxy, alkylamido, and anilide. Precursors may consist of organometallic and inorganic / halogenated compounds.

[0054] Typically, any suitable titanium precursor can be used for the optional barrier layer. Therefore, titanium precursors may include, but are not limited to, TiCl4, TiBr4, TiI4, TiF4, and tetramethylamine titanium. Alternatively, any suitable nitrogen source precursor may be used. Examples include, but are not limited to, nitrogen, ammonia, N2H2, or N2H4.

[0055] The method of this invention can be performed in the same chamber or in one or more separate processing chambers. In some embodiments, the substrate is moved from the first chamber to a separate second chamber for further processing. The substrate can be moved directly from the first chamber to the separate processing chamber, or the substrate can be moved from the first chamber to one or more transfer chambers and then to the separate processing chamber. Thus, a suitable processing apparatus may include multiple chambers communicating with a transfer station. Such an apparatus may be referred to as a "clustering tool" or a "clustering system" and the like.

[0056] Typically, clustering tools are modular systems comprising multiple chambers that perform various functions, including substrate centering and orientation, annealing, deposition, and / or etching. According to one or more embodiments, a clustering tool includes at least a first chamber and a central transfer chamber. The central transfer chamber houses a robot capable of moving the substrate back and forth between or among multiple processing chambers and a loading gate chamber. The transfer chamber is typically maintained under vacuum conditions and provides an intermediate platform for moving the substrate back and forth from one chamber to another and / or to the loading gate chamber, located at the front end of the clustering tool. Two well-known clustering tools suitable for use in this application are Centura® and Endura®, both available from Applied Materials, Inc., Santa Clara, California. However, the precise arrangement and combination of chambers may vary for the purpose of performing specific steps of the processes described herein. Other processing chambers that can be used include, but are not limited to, cyclical layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etching, pre-cleaning, chemical cleaning, thermal processing (such as rapid thermal processing (RTP)), plasma nitriding, annealing, orientation, hydroxylation, and other substrate processes. By performing the process in a chamber on a cluster tool, surface contamination of the substrate by atmospheric impurities can be avoided without oxidation before depositing subsequent thin films.

[0057] In some embodiments, the first processing chamber and the second processing chamber are part of the same clustering tool. Therefore, in some embodiments, the method is an in-situ integration method.

[0058] In some embodiments, the first processor chamber and the second processing chamber are different processing tools. Therefore, in some embodiments, the method is an off-site integration method.

[0059] According to one or more embodiments, as the substrate moves from one chamber to the next, the substrate is continuously under vacuum or "loading gate" conditions and is not exposed to ambient air. The transfer chamber is thus "evacuated" under vacuum and vacuum pressure. An inert gas may be present in the processing chamber or the transfer chamber. In some embodiments, the inert gas is used as a purge gas for removing some or all of the reactants. According to one or more embodiments, the purge gas is injected at the outlet of the deposition chamber to prevent reactants from moving from the deposition chamber to the transfer chamber and / or another processing chamber. Thus, the flow of the inert gas forms an air curtain at the outlet of the chamber.

[0060] The substrate can be processed in a single substrate deposition chamber, wherein the single substrate is loaded, processed, and unloaded before processing another substrate. The substrate can also be processed continuously, similar to a transport system, wherein multiple substrates are individually loaded into a first portion of the chamber, move through the chamber, and are unloaded from a second portion of the chamber. The shape of the chamber and the associated transport system can form a straight path or a curved path. Alternatively, the processing chamber can be a rotating rack, wherein multiple substrates move about a central axis and are exposed to deposition, etching, annealing, and / or cleaning processes throughout the rotating rack path.

[0061] The substrate may be stationary or rotating during processing. The rotating substrate may rotate continuously or in stages. For example, the substrate may rotate throughout the entire process, or the substrate may rotate slightly between exposures to different reaction or purge gases. Rotating the substrate (continuously or in stages) during processing can help produce more uniform deposition or etching by minimizing the effects of local variability, such as in the gas flow geometry.

[0062] In an atomic layer deposition type chamber, the substrate may be exposed to a first or second precursor in a process in which the substrate is spatially or temporally separated. A temporary ALD is a first precursor in which the first precursor flows into the chamber to react with the surface. The first precursor is removed from the chamber before the second precursor flows in. In a spatial ALD, the first and second precursors flow into the chamber simultaneously but are spatially separated so that there is a region between the flows to prevent precursor mixing. In a spatial ALD, the substrate moves relative to a gas distribution plate, or vice versa.

[0063] In embodiments where one or more portions of the method occur within a chamber, the process can be a spatial ALD process. Although one or more of the chemical components described above may be incompatible (i.e., producing reactions other than deposition on the substrate surface and / or in the chamber), spatial separation ensures that the reagents are not exposed to each of them in the gas phase. For example, time-based ALD involves purging the deposition chamber. However, in practice, it is sometimes impossible to remove excess reagent from the chamber before additional reagents are introduced. Therefore, any residual reagent in the chamber may react. With spatial separation, there is no need to purify excess reagent, and cross-contamination is limited. Furthermore, a significant amount of time may be used to purify the chamber, and therefore yield can be increased by eliminating the purging step.

[0064] Referring to Figure 4, an additional embodiment of this invention pertains to a processing system 900 for performing the methods described herein. Figure 4 illustrates a system 900 for processing substrates according to one or more embodiments of this invention. The system 900 may be referred to as a swarm tool. The system 900 includes a central transfer station 910 in which a robot 912 is present. The robot 912 is illustrated as a single-blade robot; however, those skilled in the art will recognize that other robot 912 configurations are also within the scope of this invention. The robot 912 is configured to move one or more substrates between chambers connected to the central transfer station 910.

[0065] At least one pre-cleaning / buffer chamber 920 is connected to the central transfer station 910. The pre-cleaning / buffer chamber 920 includes one or more of a heater, a radical source, or a plasma source. The pre-cleaning / buffer chamber 920 can serve as a holding region for various semiconductor substrates or wafer cassettes for processing. The pre-cleaning / buffer chamber 920 can perform a pre-cleaning process or preheat the substrate for processing, or may simply be a grading region for a processing sequence. In some embodiments, two pre-cleaning / buffer chambers 920 are connected to the central transfer station 910.

[0066] In the embodiment shown in Figure 4, the pre-cleaning chamber 920 may serve as a passage chamber between the factory interface 905 and the central transfer station 910. The factory interface 905 may include one or more robots 906 to move substrates from the cassette to the pre-cleaning / buffering chamber 920. Robot 912 may then move the substrates from the pre-cleaning / buffering chamber 920 to other chambers within the system 900.

[0067] The first processing chamber 930 may be connected to the central transfer station 910. The first processing chamber 930 may be configured for ALD to form gate metal oxide layers between silicon oxide layers of memory stacks on the substrate, and may be in fluid communication with one or more reactive gas sources to provide reactive gas flow to the processing chamber 930. The substrate may be moved back and forth in the processing chamber 930 by a robot 912 via an isolation valve 914.

[0068] The processing chamber 940 may also be connected to a central transfer station 910. In some embodiments, the processing chamber 940 includes an atomic layer deposition chamber for depositing a bipolar metal film on a gate metal oxide layer and is in fluid communication with one or more reactive gas sources to provide reactive gas flow to the processing chamber 940. The substrate can be moved back and forth in the processing chamber 940 by a robot 912 via an isolation valve 914.

[0069] In some embodiments, the processing chamber 960 is connected to the central transfer station 910 and configured to heat-treat the substrate.

[0070] In some embodiments, other processing chambers may be configured to perform other parts of the processing method, including removing any remaining bipolar film and depositing a metal gate fill layer. Those skilled in the art will recognize that the number and arrangement of the various processing chambers on the tool may vary, and the embodiment shown in Figure 4 is merely representative of possible configurations. Prior to the operation of depositing gate metal oxide layers in the alternating openings between the silicon oxide layers of the memory stack on the substrate, the memory stack may be processed by removing the nitride layer of the oxide / nitride mold; and in one or more embodiments, memory vias are formed through the thickness of some layers of the oxide / nitride mold before removing the nitride layer of the oxide / nitride mold.

[0071] In some embodiments, the processing system 900 includes one or more metering stations. For example, the metering station may be located within a pre-cleaning / buffer chamber 920, within a central transfer station 910, or within a separate processing chamber. The metering station can be located anywhere within the system 900, allowing for the measurement of groove distances without exposing the substrate to an oxidizing environment.

[0072] At least one controller 950 is coupled to one or more of the central transfer station 910, the pre-cleaning / buffer chamber 920, and the processing chambers 930, 940, or 960. In some embodiments, there are more than one controller 950 connected to the respective chambers or stations, and a main control processor is coupled to each of the individual processing chambers to control the system 900. The controller 950 may be any form of general-purpose computer processor, microcontroller, microprocessor, etc., that can be used in an industrial environment to control the various chambers and subprocessors.

[0073] At least one controller 950 may have a processor 952, a memory 954 coupled to the processor 952, an input / output device 956 coupled to the processor 952, and support circuitry 985 for communication between different electronic components. The memory 954 may include one or more transient memories (e.g., random access memory) and non-transient memories (e.g., storage).

[0074] The processor's memory 954, or computer-readable medium, may be one or more readily accessible memories, such as random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote. Memory 954 may hold an instruction set operable by processor 952 to control the parameters and components of system 900. Support circuitry 958 is coupled to processor 952 to support the processor in a conventional manner. The circuitry may include, for example, cache memory, power supply, clock circuitry, input / output circuitry systems, subsystems, etc.

[0075] The processor may typically store a software routine in memory, which, when executed by the processor, causes the processing chamber to perform the process of this invention. The software routine may also be stored and / or executed by a second processor (illustrated), located at a remote end of hardware controlled by the processor. Some or all of the methods of this invention may also be executed in hardware. Therefore, the process can be implemented in software and executed in hardware (e.g., application-specific integrated circuits or other types of hardware implementation) using a computer system, or as a combination of hardware and software. When executed by the processor, the software routine converts a general-purpose computer into a special-purpose computer (controller), thereby controlling the chamber operation to enable the process to be executed.

[0076] In some embodiments, the controller 950 has one or more configurations to perform various processes or subprocesses to perform the method. The controller 950 may be connected to and configured to operate intermediate elements to perform various functions of the method. For example, the controller 950 may be connected to and configured to control one or more air valves, actuators, motors, slit valves, vacuum controls, etc.

[0077] Some embodiments of the controller 950 have one or more configurations selected from the following: a configuration for moving a substrate on a robot between a plurality of processing chambers and metering stations; a configuration for loading and / or unloading a substrate from a system; a configuration for depositing a gate metal oxide layer in alternating openings between memory stacked silicon oxide layers on the substrate; a configuration for preparing a bipolar film on the gate oxide layer; a configuration for heat-treating the substrate and driving the bipolar film into the gate metal oxide layer; a configuration for removing any remaining bipolar film; and a configuration for depositing a metal gate fill layer.

[0078] Throughout this specification, references to "one embodiment," "some embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of this application. Therefore, the appearance of terms such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in one embodiment" in various places in this specification does not necessarily represent the same embodiment of this application. Furthermore, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0079] Although the disclosure herein has been described with reference to specific embodiments, those skilled in the art will understand that the embodiments described are merely illustrative of the principles and applications of this invention. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatus of this invention without departing from the spirit and scope of this invention. Therefore, this invention may include modifications and variations within the scope of the appended claims and their equivalents. [Simplified Explanation of the Diagram]

[0008] A more specific description of the present invention, briefly summarized above, can be obtained by referring to the embodiments, some of which are illustrated in the accompanying drawings, in a manner that enables a detailed understanding of the above-described features of the present invention. However, it should be noted that the drawings illustrate only typical embodiments of the present invention and are therefore not to be considered as limiting the scope of the present invention, as other equally effective embodiments are permissible.

[0009] Figure 1 is a perspective cut-out cross-sectional view of a memory device according to one or more embodiments of the present invention;

[0010] Figure 2 is a cross-sectional view of a stack of memory devices according to one or more embodiments of this case;

[0011] Figure 3 is a flowchart of a method for forming a bipolar region according to one or more embodiments of this case;

[0012] Figure 4 is a clustering tool according to one or more embodiments of this case; and

[0013] Figure 5 shows the relationship between resistivity (μΩ-cm) and stacking thickness (Å). [Biomaterial Storage]

[0081] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A memory device comprising: a stack of alternating silicon oxide layers and word line layers; and each of the word line layers comprising a bipolar region adjacent to the silicon oxide layer, the bipolar regions comprising a nitride, carbide, oxide, carbonitride, or combination thereof of a bipolar metal, wherein each word line layer comprises: the bipolar regions in a gate metal oxide layer, and a gate metal filler layer, wherein a negative charge of the bipolar metal is greater than a negative charge of a metal in the gate metal oxide layer.

2. The memory device as claimed in claim 1, wherein the bipolar metal comprises: zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), or a mixture thereof.

3. The memory device as claimed in claim 1, wherein the gate metal oxide layer comprises aluminum oxide, and the bipolar metal comprises zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), or a mixture thereof.

4. The memory device as claimed in claim 1, wherein the gate metal oxide layer comprises hafnium oxide, and the bipolar metal comprises: zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), titanium (Ti), zirconium (Zr), niobium (Nb), or a mixture thereof.

5. The memory device as claimed in claim 1, wherein the gate metal filling layer comprises tungsten (W) or molybdenum (Mo).

6. The memory device as claimed in claim 1, wherein each word line layer further includes a barrier layer between the gate metal oxide layer and the gate metal fill layer.

7. The memory device as claimed in claim 6, wherein the barrier layer comprises titanium nitride (TiN).

8. The memory device as claimed in claim 1, further comprising: a plurality of memory holes extending through at least some of the alternating silicon oxide layers and word line layers, each memory hole having a core oxide surrounded by a memory hole semiconductor material.

9. A memory stack on a substrate, comprising: a plurality of alternating silicon oxide layers and word line layers on the substrate; a plurality of memory vias through at least some of the thickness of the alternating silicon oxide layers and word line layers; each word line layer comprising: a gate metal oxide layer including one or more bipolar regions, a gate metal filler layer, and optionally a barrier layer between the gate metal oxide layer and the gate metal filler layer, wherein the bipolar regions are adjacent to portions of each silicon oxide layer and memory vias, the bipolar regions comprising: a nitride, carbide, oxide, carbonitride, or a combination thereof of a bipolar metal, wherein a negative charge of the bipolar metal is greater than a negative charge of a metal of the gate metal oxide layer.

10. The memory stack as claimed in claim 9, wherein the gate metal oxide layer comprises hafnium oxide, and the bipolar metal comprises: zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), titanium (Ti), zirconium (Zr), niobium (Nb), or a mixture thereof.

11. The memory stack as claimed in claim 9, wherein the gate metal oxide layer comprises aluminum oxide, and the bipolar region comprises zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), or a mixture thereof.

12. The memory stack as described in claim 9, wherein each word line layer includes the barrier layer, the barrier layer comprising titanium nitride (TiN).

13. A method of forming a memory stack, the method comprising the steps of: depositing a gate metal oxide layer in alternating openings between silicon oxide layers of a memory stack on a substrate having a surface; preparing a bipolar film by exposing the surface of the substrate to a first precursor comprising a bipolar metal and optionally to an auxiliary comprising nitrogen, oxygen, and / or carbon, wherein the bipolar film is prepared on the gate metal oxide layer; exposing the substrate to a heat treatment to diffuse the bipolar film into the gate metal oxide layer to form a bipolar region; depositing a metal gate fill layer in the openings; and the method further comprising removing any remaining bipolar film on the gate metal oxide layer.

14. The method as described in claim 13, wherein the bipolar film system is prepared by atomic layer deposition at a first substrate temperature ranging from 200°C to 500°C.

15. The method as described in claim 13, wherein the negative charge of the bipolar metal is greater than the negative charge of a metal in the gate metal oxide layer.

16. The method as described in claim 13, wherein the heat treatment is performed at a second substrate temperature of at least 700°C.

17. The method as described in claim 13, wherein the bipolar metal is selected from the group consisting of zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), titanium (Ti), zirconium (Zr), niobium (Nb), and mixtures thereof.

18. The method of claim 13, wherein the first precursor comprises a metal halide or an organometallic compound, and / or the adjuvant comprises a second compound selected from the group consisting of NH3, N2, N2H2, N2H4, nitrogen-containing plasma, H2O, H2O2, O3, ethanol, methane (CH4), H2, and combinations thereof.

19. The method as described in claim 13, wherein after the heat treatment, any portion of the bipolar film remaining on the gate metal oxide layer is removed by a dry plasma etching process.

20. The method as described in claim 14, wherein the bipolar film is blanket-deposited over the entire exposed surface of the gate metal oxide layer, and the method further includes subsequent lithography and etching processes to pattern the bipolar film.

21. The method as described in claim 20, wherein the bipolar film is deposited to a thickness ranging from 5 Å to 20 Å.

22. The method as described in claim 16, wherein the heat treatment is performed in a rapid heat treatment (RTP) chamber.

23. The method as described in claim 22, wherein the heat treatment is performed between about 1 second and about 30 seconds.

24. The method as described in claim 13, wherein the gate metal oxide layer is selected from hafnium dioxide (HfO2) and aluminum oxide (Al2O3).

25. The method as described in claim 24, wherein an atomic layer deposition (ALD) process is used to form the gate metal oxide layer.

26. The method as described in claim 25, wherein a metal-containing precursor and an oxygen-containing precursor are alternately deposited to form the gate metal oxide layer.

27. The method as described in claim 26, wherein the gate metal oxide layer has a thickness between about 20 Å and 30 Å.

28. A method of forming a memory stack, the method comprising the steps of: depositing a gate metal oxide layer in alternating openings between silicon oxide layers of a memory stack on a substrate having a surface; preparing a bipolar film by exposing the surface of the substrate to a first precursor comprising a bipolar metal and optionally to an auxiliary comprising nitrogen, oxygen, and / or carbon; optionally exposing the substrate to a heat treatment to form a bipolar region; and depositing a metal gate fill layer in the openings, wherein the bipolar film blankets the entire exposed surface of the gate metal oxide layer, and patterning the bipolar film using subsequent lithography and etching processes.

29. The method as described in claim 28, wherein the bipolar film is deposited to a thickness ranging from 5 Å to 20 Å.

30. The method as claimed in claim 28, wherein the method further comprises a heat treatment to diffuse the bipolar metal from the bipolar film into the gate metal oxide layer.

31. The method as described in claim 30, wherein the bipolar metal is selected from the group consisting of zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), titanium (Ti), zirconium (Zr), niobium (Nb), and mixtures thereof.

Images