Manufacturing method of semiconductor device and semiconductor device

Abstract

A method for manufacturing a semiconductor device includes: a step of forming a first organic insulating layer having trenches on a substrate; a step of forming a conductive layer having a conductive material on the first organic insulating layer by filling the trenches with a conductive material; a step of removing portions of the conductive layer on the first organic insulating layer to obtain a first wiring structure having a first wiring layer and a first organic insulating layer comprising a first wiring layer comprising conductive material filled in the trenches; a step of providing a second wiring structure having a second organic insulating layer and a second wiring layer; and a step of aligning the first wiring layer and the second wiring layer in corresponding positions and pressing the first wiring structure and the second wiring structure together to form a laminate. In the lamination step, the first wiring layer and the second wiring layer are bonded, and the first organic insulating layer and the second organic insulating layer are bonded.

Description

[Technical Field]

[0001] This disclosure relates to a method for manufacturing a semiconductor device including a wiring layer stacking method, and to a semiconductor device thereof. More specifically, it relates to a method for manufacturing a semiconductor device and a semiconductor device useful for efficiently and cost-effectively manufacturing semiconductor devices with high requirements for miniaturization and high density. [Previous Technology]

[0002] Patent Document 1 discloses a form in which chips with different properties are mixed on a single package for the purpose of increasing the density and performance of semiconductor packages. In this form, the cost is excellent, and the high-density interconnect technology between the chips becomes important.

[0003] As an interconnect technology, in the field of semiconductor mounting, the connection between semiconductor wafers and the flip-chip mounting method, in which semiconductor wafers are connected to semiconductor wafer mounting support members via a plurality of conductive bumps, have attracted attention. In the flip-chip mounting method, due to the stress caused by the difference in the coefficients of thermal expansion of each connecting member, connection abnormalities sometimes occur between the substrate and the semiconductor wafer via the conductive bumps. Therefore, it is known that a method is used to seal the conductive bumps by filling the space between the connecting members with resin (underfill material) to alleviate this stress (for example, see Patent Document 2). Furthermore, the use of negative photosensitive adhesive compositions in the connection between semiconductor wafers and the connection between semiconductor wafers and semiconductor wafer mounting support members has been examined (for example, see Patent Document 3).

[0004] Furthermore, a method for manufacturing a solid-state imaging device by stacking semiconductor wafers with different functions by CuCu bonding has been proposed (for example, see Patent Document 4).

[0005] Furthermore, the case of stacking semiconductor wafers on add-in substrates, wafer-level packaging substrates, fan-out packaging substrates, interposer substrates, etc., has been proposed. Regarding the stacking of semiconductor wafers, a method of expanding the wiring width by multiple rewiring layers, forming bumps or pads on the wiring, and stacking semiconductor wafers by heating and / or pressurizing the molten solder has been examined (for example, see Non-Patent Literature 1).

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2012-529770 [Patent Document 2] Japanese Patent Application Publication No. 10-289969 [Patent Document 3] International Publication No. 2011 / 049011 [Patent Document 4] Japanese Patent Application Publication No. 2019-179782

[0007] [Non-Patent Document 1] Proceedings of 2009 Electronic Components and Technology Conference, 11-13 (2009).

[0008] However, to match the diameter of the bumps or pads formed on the substrate with the diameter of the bumps or pads formed on the semiconductor wafer (semiconductor device), multiple rewiring layers are required, resulting in a corresponding reduction in productivity. Furthermore, by setting up rewiring, miniaturization or high-density in a portion of the wiring layer becomes insufficient. On the other hand, when molten solder is used to connect the substrate and the semiconductor wafer, the solder deforms and comes into contact with adjacent bumps, which sometimes leads to a reduction in the yield of the semiconductor device. Moreover, the shorter distance between solder pieces may also lead to a reduction in insulation reliability. [Summary of the Invention]

[0009] This disclosure was made to solve the above-mentioned problems, and its purpose is to provide a method for manufacturing a semiconductor device and a semiconductor device that can manufacture a semiconductor device with a fine and high-density wiring layer in high yield in the connection of semiconductor wafers to each other, the connection of semiconductor wafers to semiconductor wafers or the connection of a support substrate for mounting semiconductor wafers, or the connection of semiconductor wafers to each other.

[0010] This disclosure relates to a method for manufacturing a semiconductor device. The manufacturing method includes: a step of forming a first organic insulating layer having trenches on a substrate; a step of forming a conductive layer having conductive material on the first organic insulating layer by filling the trenches with conductive material; a step of removing the conductive layer portion on the first organic insulating layer to obtain a first wiring structure having a first wiring layer comprising a first wiring layer and a first organic insulating layer comprising conductive material filled in the trenches; a step of providing a second wiring structure having a second organic insulating layer and a second wiring layer comprising conductive material filled in the trenches disposed on the second organic insulating layer and exposed on the surface; and a step of aligning the first wiring layer and the second wiring layer in a corresponding manner and pressing the first wiring structure and the second wiring structure to form a laminate, wherein in the laminate step, each wiring of the first wiring layer is bonded to each wiring of the second wiring layer, and the first organic insulating layer is bonded to the second organic insulating layer.

[0011] According to the above manufacturing method, a first wiring layer and a second wiring layer formed by filling a trench with a conductive material are bonded together, thereby forming a wiring layer for a semiconductor device. In this case, a semiconductor device having a fine and high-density wiring layer can be manufactured with high yield.

[0012] The method for manufacturing the semiconductor device described above further preferably includes the step of forming a first barrier metal film on at least one side of the bottom and side surfaces of the trench portion of the first organic insulating layer before forming the conductive layer. In this case, in the manufactured semiconductor device, it is possible to prevent conductive materials (such as copper) from diffusing from the wiring layer formed including the first wiring layer into the first organic insulating layer, thereby hindering the insulation of the wiring layer. In this case, the thickness of the first barrier metal film can be 0.001 μm or more and 0.5 μm or less. This can more reliably prevent the diffusion of conductive materials into the organic insulating layer and also sufficiently ensure the cross-sectional area of ​​each wiring in the wiring layer. Furthermore, the thickness of the first barrier metal film can be less than half the width of the trench portion of the first organic insulating layer or half the depth of the trench portion. Even in this case, as described above, it is possible to more reliably prevent the diffusion of conductive materials.

[0013] In the above-described method for manufacturing a semiconductor device, it is preferable that a second barrier metal film is provided on at least one side of the trench portion of the second organic insulating layer, similar to the first organic insulating layer. Furthermore, in the lamination step, it is preferable to align the first wiring layer and the second wiring layer in such a way that the positions of the first barrier metal film on the side of the trench portion of the first organic insulating layer and the second barrier metal film on the side of the trench portion of the second organic insulating layer are offset by less than 50% relative to the thickness of the first barrier metal film in the direction intersecting the side. In this case, the first and second barrier metal films can more reliably prevent the diffusion of conductive materials (e.g., copper) that could diffuse from the inner first and second wiring layers to the outer first and second organic insulating layers, and in particular, can prevent the diffusion of conductive materials from the junction of the first and second barrier metal films.

[0014] In the above-described method for manufacturing a semiconductor device, in the step of obtaining the first wiring structure, the conductive layer portion on the first organic insulating layer can be removed by grinding so that the surface roughness of the first wiring layer of the first wiring structure is 0.05 μm or less. In this case, the bonding between the first wiring layer and the second wiring layer can be performed more reliably, and the wiring layer in the semiconductor device can function more properly.

[0015] In the above-described method for manufacturing a semiconductor device, the surface roughness of the second wiring layer of the second wiring structure can be 0.05 μm or less. In this case, the bonding between the first wiring layer and the second wiring layer can be performed more reliably, and the wiring layer in the semiconductor device can function more appropriately.

[0016] In the above-described method for manufacturing a semiconductor device, the organic material constituting at least one of the first organic insulating layer and the second organic insulating layer has a melt viscosity of 1 kPa·s or more and 1 MPa·s or less at 250°C. In this case, the bonding between the first organic insulating layer and the second organic insulating layer can be performed more reliably. More specifically, if the melt viscosity of the organic insulating material is less than 1 kPa·s, removing the conductive layer portion on the first organic insulating layer may cause contamination of the first wiring layer due to the ductility of the organic insulating layer. However, by having a melt viscosity of 1 kPa·s or more for the organic insulating material, such contamination can be prevented. Furthermore, if the melt viscosity of the organic insulating material is greater than 1 MPa·s, it is necessary to increase the heating temperature when bonding the organic insulating layers together, which may lead to a decrease in productivity. However, by having a melt viscosity of 1 MPa·s or less for the organic insulating material, the temperature when bonding the organic insulating layers together can be reduced, thereby increasing the corresponding productivity. In the above cases, it is preferable that the melt viscosity of at least one of the materials constituting the first organic insulating layer and the second organic insulating layer is 3 kPa·s or more at 250°C, which can further suppress resin flow during bonding. Furthermore, it is preferable that the melt viscosity of the organic insulating material at 250°C is 5 kPa·s or more, which can suppress stress caused by curing shrinkage. On the other hand, it is preferable that the melt viscosity of the organic material constituting at least one of the first organic insulating layer and the second organic insulating layer is 0.8 MPa·s or less at 250°C, which can suppress the formation of voids after bonding. Furthermore, it is preferable that the melt viscosity of the organic material at 250°C is 0.5 MPa·s or less, which allows for low-temperature bonding of the first organic insulating layer and the second organic insulating layer. Therefore, the organic material constituting at least one (preferably both) of the first organic insulating layer and the second organic insulating layer has a melt viscosity of 5 kPa·s or more and 0.5 MPa·s or less at 250°C.

[0017] In the above-described method for manufacturing a semiconductor device, in the step of obtaining the first wiring structure, the conductive layer on the first organic insulating layer can be removed by grinding in a manner where the surface of the first wiring layer is more prominent than the surface of the first organic insulating layer. In this case, the formation of unevenness at the bonding surface when joining the first wiring structure and the second wiring structure is suppressed due to the difference in the coefficients of thermal expansion between the organic resin material constituting the organic insulating layer and the metal material constituting the wiring layer, thereby enabling more reliable deposition of the first wiring structure and the second wiring structure.

[0018] In the above-described method for manufacturing a semiconductor device, the step of forming the first organic insulating layer may include the steps of depositing a photosensitive material on a substrate and exposing and developing the photosensitive material to form the first organic insulating layer. In this case, the first organic insulating layer itself and the trench portion can be easily formed, thereby improving manufacturing efficiency.

[0019] In the above-described method for manufacturing a semiconductor device, the step of forming the first organic insulating layer may include the step of forming trenches on the first organic insulating layer. In this case, when a photosensitive material is disposed on a substrate and the photosensitive material is exposed and developed to form the first organic insulating layer having trenches, finer trenches, i.e., the wirings of the first wiring layer, can be fabricated, and the miniaturization and high density of the wiring layer can be promoted.

[0020] In the above-described method for manufacturing a semiconductor device, the linewidth of each wire in the first wiring layer is 2 μm or less, and the thickness of each wire in the first wiring layer can be 1 μm or less. In this case, a finer and higher density wiring layer can be formed.

[0021] In the above-described method for manufacturing a semiconductor device, a first semiconductor element can be disposed on a substrate on the side opposite to the first organic insulating layer or within the substrate in a first wiring structure; alternatively, a second semiconductor element can be disposed on a second organic insulating layer on the side opposite to the second wiring layer or within the second organic insulating layer in a second wiring structure; or the first semiconductor element and the second semiconductor element can be electrically connected through a wiring layer formed by bonding the first wiring layer and the second wiring layer. In this case, the first semiconductor element and the second semiconductor element can be directly or substantially directly connected through a fine wiring layer. Furthermore, the semiconductor element referred to herein can include at least a semiconductor wafer and a semiconductor chip.

[0022] As another aspect of this disclosure, a semiconductor device is disclosed. The semiconductor device includes: a first wiring structure comprising a substrate, a first organic insulating layer disposed on the substrate and having a first trench, and a first wiring layer made of a conductive material filled within the first trench; and a second wiring structure comprising a second organic insulating layer having a second trench, and a second wiring layer made of a conductive material filled within the second trench. The first wiring structure is deposited on the second wiring structure such that the first wiring layer is bonded to the second wiring layer and the first organic insulating layer is bonded to the second organic insulating layer.

[0023] In the above-mentioned semiconductor device, the wiring layer is formed by the first wiring layer and the second wiring layer. Therefore, similarly as above, a semiconductor device having a fine and high-density wiring layer can be manufactured with high yield.

[0024] The above-described semiconductor device may further include: a first semiconductor element disposed in the first wiring structure on a surface of a substrate opposite to the first organic insulating layer or within the substrate; and a second semiconductor element disposed in the second wiring structure on a surface of a second organic insulating layer opposite to the second wiring layer or within the second organic insulating layer. In this semiconductor device, the first semiconductor element can be electrically connected to the second semiconductor element through a wiring layer formed by bonding the first wiring layer and the second wiring layer. In this case, the first semiconductor element and the second semiconductor element can be directly or substantially directly connected by fine wiring. [Effects of the Invention]

[0025] According to this disclosure, a method for manufacturing a semiconductor device and a semiconductor device are provided that can manufacture a semiconductor device having a fine and high-density wiring layer with high yield.

Implementation Method

[0027] The present embodiment will be described in detail below with reference to the illustrations. In the following description, the same or corresponding parts will be marked with the same symbols, and repeated descriptions will be omitted. Furthermore, regarding positional relationships such as up, down, left, and right, unless otherwise specified, the positional relationships shown in the illustrations will be used. Moreover, the dimensional ratios of the illustrations are not limited to those shown in the illustrations.

[0028] In the description and claims, the use of terms such as "left," "right," "front," "back," "upper," "lower," "above," "below," "first," and "second" is intended to describe, and does not necessarily imply, that this relative position is always present. Furthermore, the term "layer" includes not only the structure of the shape formed across the entire surface when viewed in a top view, but also the structure of the shape formed in a portion of the surface. Also, the term "step" does not only include independent steps; even if it cannot be clearly distinguished from other steps, it is included as long as the desired purpose of the step is achieved. Furthermore, the numerical range indicated by "~" represents the range including the minimum and maximum values ​​recorded before and after "~," respectively. Furthermore, within the numerical ranges described in stages in this specification, the upper or lower limit of the numerical range of a certain stage can be replaced by the upper or lower limit of the numerical range of other stages.

[0029] First, referring to FIG. 1, an example of the configuration of a semiconductor package 1 (semiconductor device) connected by the semiconductor device manufacturing method of this embodiment will be described. Furthermore, the semiconductor device manufacturing method disclosed herein is suitable for configurations requiring miniaturization and high-density (multi-pin) configurations. Also, the manufacturing method disclosed herein can be used in packaging configurations requiring interposers for carrying different types of wafers. However, the manufacturing method disclosed herein is not limited to these configurations and can be used in other configurations.

[0030] FIG1 is a schematic cross-sectional view showing an example of a semiconductor package. As shown in FIG1, the semiconductor package 1 is composed of a substrate 10, semiconductor wafers 20A to 20D (first semiconductor element, second semiconductor element) and wiring members 30. Semiconductor wafers 20A and 20B are mounted on the wiring members 30. Semiconductor wafers 20C and 20D are disposed within the substrate 10. Semiconductor wafers 20A and 20B can be fixed to the wiring members 30 by means of bottom fillers 3A and 3B, or they can be directly fixed to the fourth insulating layer 38 (described later) of the wiring members 30 without using bottom fillers.

[0031] As an example of substrate 10, it is a sealed body formed by sealing semiconductor wafers 20C and 20D with electrodes 11 and 12 using insulating material 13. Semiconductor wafers 20C and 20D within substrate 10 can be connected to external devices via electrodes exposed from insulating material 13. Semiconductor wafers 20C and 20D function, for example, as conductive paths for electrically connecting wiring components 30 to external devices. Insulating material 13 is, for example, a curable resin with insulating properties.

[0032] Semiconductor wafers 20A to 20D may be, for example, volatile memory such as a graphics processing unit (GPU), DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), non-volatile memory such as flash memory, RF chips, silicon photonics chips, MEMS (Micro Electro Mechanical Systems), sensor chips, etc. Semiconductor wafers 20A to 20D may have TSVs, for example, and may be formed by stacking multiple semiconductor elements. In this case, any one of the semiconductor wafers 20A to 20D can use a semiconductor element stacked using TSVs. The thickness of semiconductor wafers 20A and 20B is, for example, 200 μm or less. From the viewpoint of thinning the semiconductor package 1, a thickness of 100 μm or less for semiconductor wafers 20A and 20B is preferable. Furthermore, from an operational point of view, it is better for the thickness of semiconductor wafers 20A and 20B to be 30μm or more.

[0033] Next, the wiring component 30 will be described in detail with reference to FIG. 2. The wiring component 30 is an organic substrate that supports semiconductor wafers, etc., and may be, for example, a build-up substrate in which resin is impregnated in glass cloth or carbon fiber (preform material), a wafer-level packaging substrate, a coreless substrate, a substrate made by thermosetting sealing material, or a substrate for sealing or embedding wafers. The shape of the wiring component 30 may be wafer-shaped (approximately circular in plan view) or panel-shaped (approximately rectangular in plan view) depending on the shape of the substrate 10A described later. Furthermore, from the viewpoint of suppressing warpage, the coefficient of thermal expansion of the wiring component 30 is preferably, for example, 40 ppm / ℃ or less. From the viewpoint of insulation reliability of the wiring component 30, the coefficient of thermal expansion is preferably 20 ppm / ℃ or less.

[0034] As shown in FIG. 2, the wiring component 30 is disposed on the substrate 10A. The substrate 10A is a support for the wiring component 30. The shape of the substrate 10A in top view is, for example, circular or rectangular. When it is circular, the substrate 10 has a diameter of, for example, 200 mm to 450 mm. When it is rectangular, one side of the substrate 10 is, for example, 300 mm to 700 mm.

[0035] The substrate 10A is, for example, a silicon substrate, a glass substrate, or a peelable copper foil. Furthermore, the substrate 10A can be, for example, an add-on substrate, a wafer-level packaging substrate, a coreless substrate, a substrate made by thermosetting sealing material, or a substrate for sealing or embedding wafers. Figure 1 illustrates a configuration (substrate 10) in which semiconductor wafers 20C and 20D are embedded in the substrate 10A, but the substrate 10A can be of other configurations. When a silicon substrate or glass substrate is used as the substrate 10A, a temporary fixing layer (not shown) can be provided to temporarily fix the substrate 10A and the wiring member 30. In this case, by removing the temporary fixing layer, the substrate 10A can be easily peeled off from the wiring member 30. Furthermore, the peelable copper foil is a laminate formed by sequentially overlapping a support, a release layer, and a copper foil. In the peelable copper foil, the support corresponds to the substrate 10A, and the copper foil corresponds to a portion of the material of the copper wiring included in the through wiring 33.

[0036] The wiring component 30 includes: an organic insulating laminate 31 comprising a plurality of organic insulating layers; a plurality of wires 32 arranged within the organic insulating laminate 31; a through wire 33 penetrating the organic insulating laminate 31; and a surface wire 34 formed on and near the surface of the organic insulating laminate 31. The plurality of wires 32 form the wiring layer of the wiring component 30. The wiring layer may include the through wires 33 and the surface wires 34, and the through wires 33 may also be electrically connected to any one of the plurality of wires 32.

[0037] The organic insulating multilayer 31 includes a first insulating layer 35 (first organic insulating layer), a second insulating layer 36 (first organic insulating layer), a third insulating layer 37 (second organic insulating layer), and a fourth insulating layer 38 (second organic insulating layer). The first insulating layer 35 to the fourth insulating layer 38 are sequentially deposited on the substrate 10A. Furthermore, the organic insulating multilayer 31 has an opening H for through wiring 33 and a groove T for each wiring 32. Moreover, the first insulating layer 35 and the second insulating layer 36 have openings Ha for portions 33 of through wiring 33.

[0038] A plurality of slots T are provided in the second insulating layer 36 and the third insulating layer 37, sandwiched between the first insulating layer 35 and the fourth insulating layer 46. Each slot T has a generally rectangular shape in cross-section along a direction orthogonal to the extension direction of the slot T. That is, each slot T has a bottom surface formed by the surface of the first insulating layer 35, a side surface extending from the bottom surface to the fourth insulating layer 38, and a top surface formed by the back surface of the fourth insulating layer 38. The plurality of slots T have a predetermined line width L (horizontal width) and a spacing width S. The line width L and the spacing width S are, for example, 0.5 μm to 10 μm, preferably 0.5 μm to 5 μm, and more preferably 2 μm to 5 μm. From the viewpoint of achieving high-density transmission of the wiring component 30, a line width L of 1 μm to 5 μm is preferred. The line width L and the spacing width S can be set to be the same or different from each other. The linewidth L corresponds to the width of the groove T in a direction orthogonal to the extension direction of the groove T (width L in Figure 2). The spacing width S corresponds to the distance between adjacent grooves T (width S in Figure 2). The depth of the groove T is, for example, equivalent to the combined thickness of the second insulating layer 36 and the third insulating layer 37. Furthermore, the cross-sectional shape of the groove T is not limited to a generally rectangular shape, but can be other shapes (e.g., a generally semi-circular shape).

[0039] It is preferable that the surface roughness of the inner surface of each groove T is 0.01 μm to 0.1 μm. When the surface roughness is 0.01 μm or more, the adhesion and temperature cycling resistance of the objects (conductive materials) in close contact with the first insulating layer 35, the second insulating layer 36, the third insulating layer 37, and the fourth insulating layer 38 within the groove T become better. The temperature cycling resistance referred to here is the resistance to volume change, performance degradation, damage, etc., accompanied by temperature changes. Furthermore, when the surface roughness is 0.1 μm or less, there is a tendency to suppress short circuits in the wiring 32 containing conductive materials and to improve the high-frequency characteristics of the wiring 32. The surface roughness of the inner surface of the groove T can be calculated, for example, by observing the cross-section of the groove T using an electron microscope. Furthermore, the surface roughness mentioned above is the arithmetic mean roughness (Ra) specified in JIS B 0601 2001, and the term "surface roughness" will be referred to as "surface roughness Ra" below.

[0040] The storage modulus of elasticity of the first insulating layer 35, the second insulating layer 36, the third insulating layer 37, and the fourth insulating layer 38 (hereinafter sometimes simply referred to as "each insulating layer 35 to 38") at room temperature is, for example, 500 MPa to 1000 GPa. Here, "room temperature" means approximately 25°C. By having a storage modulus of elasticity of 500 MPa or more, the elongation of each insulating layer 35 to 38 can be suppressed. For example, during the step of grinding the second insulating layer 36 or the third insulating layer 37, it is possible to prevent the second insulating layer 36 or the third insulating layer that elongates during grinding from covering the wiring 32. Furthermore, by having a storage modulus of elasticity of 10 GPa or less, for example, damage to the grinding blade can be prevented, and as a result, the surface of the second insulating layer 36, etc., can be prevented from becoming excessively rough.

[0041] Furthermore, it is preferable that the molten viscosity of the organic material constituting each insulating layer 35 to 38 at 250°C is 1 kPa·s or more and 1 MPa·s or less. In this case, the bonding of the second insulating layer 36 and the third insulating layer 37 can be performed more reliably in the manufacturing method described later. More specifically, if the molten viscosity of the organic insulating material is less than 1 kPa·s, removing the conductive layer portion on the second insulating layer 36 may cause contamination of the wiring 32 (32a) due to the ductility of the organic insulating layer, but this contamination can be prevented by the molten viscosity of the organic insulating material being 1 kPa·s or more. Also, if the molten viscosity of the organic insulating material is greater than 1 MPa·s, the heating temperature required for bonding the insulating layers 36 and 37 to each other needs to be increased, which may lead to a decrease in productivity, but by the molten viscosity of the organic insulating material being less than 1 MPa·s, the temperature required for bonding the insulating layers 36 and 37 to each other can be reduced, thereby increasing the corresponding productivity. In the above-described cases, it is preferable that the melt viscosity of the materials constituting the second insulating layer 36 and the third insulating layer 37 at 250°C is 3 kPa·s or higher, which further suppresses resin flow during bonding. Furthermore, it is preferable that the melt viscosity of the organic insulating material at 250°C is 5 kPa·s or higher, which suppresses stress caused by curing shrinkage. On the other hand, it is preferable that the melt viscosity of the organic materials constituting the second insulating layer 36 and the third insulating layer 37 at 250°C is 0.8 MPa·s or lower, which suppresses the formation of voids after bonding. Furthermore, it is preferable that the melt viscosity of the organic material at 250°C is 0.5 MPa·s or lower, which allows for low-temperature bonding of the second insulating layer 36 and the third insulating layer 37. Therefore, it is even more preferable that the melt viscosity of the organic materials constituting the second insulating layer 36 and the third insulating layer 37 at 250°C is between 5 kPa·s and 0.5 MPa·s.

[0042] The thickness of each insulating layer 35 to 38 is, for example, 0.5 μm to 10 μm. With each insulating layer 35 to 38 having a thickness of 0.5 μm or more, in the organic insulating laminate 31, each insulating layer 35 to 38 helps to alleviate stress and improves the temperature cycling resistance of the organic insulating laminate 31. With each insulating layer 35 to 38 having a thickness of 10 μm or less, warping of the organic insulating laminate 31 is suppressed, and for example, when grinding the second insulating layer 36 or the third insulating layer 37, wiring can be easily exposed. From the viewpoint of forming wiring 32 with a width of 3 μm or less by exposure and development, a thickness of 7 μm or less for the second insulating layer 36 and the third insulating layer 37 is preferable.

[0043] Each insulating layer 35-38 may be composed of a cured form of a photosensitive resin composition. From the viewpoint of the flatness of these layers and manufacturing cost, it is preferable to use a material pre-formed as a film (film-like organic insulating material) when forming these layers. In this case, for example, even if the surface roughness of the substrate 10A is 300 μm or more, a layer with a sufficiently small surface roughness value can be formed. It is preferable that the film-like organic insulating material can be laminated at a temperature of 40°C to 120°C. By setting the lamination temperature to 40°C or higher, the increase of wrinkles (adhesion) of the organic insulating material at room temperature can be suppressed, and good workability can be maintained. By setting the lamination temperature to 120°C or lower, the occurrence of warping in the organic insulating laminate 31 can be suppressed.

[0044] From the viewpoint of suppressing warping of the organic insulating laminate 31, the coefficient of thermal expansion of each insulating layer 35 to 38 after curing is, for example, 80 ppm / ℃ or less. From the viewpoint of the insulation reliability of the wiring component 30, it is preferable that the coefficient of thermal expansion of the insulating layers 35 to 38 after curing is 70 ppm / ℃ or less. Furthermore, from the viewpoint of stress relief and processing accuracy of the organic insulating material, it is even more preferable that the coefficient of thermal expansion of the insulating layers 35 to 38 after curing is 20 ppm / ℃ or more.

[0045] Examples of photosensitive resin compositions used to form the insulating layers 35-38 include compositions that at least contain a photoacid generator and a compound having a tertiary amine group or a nitrogen-containing heterocycle. It is preferable that the composition further contains an alkali-soluble resin. Such photosensitive resin compositions can be prepared in either a negative or positive form.

[0046] As a photoacid generator, there is no particular limitation as long as it is a compound that generates acid by light irradiation. From the viewpoint of effectively generating acid, photoacid generators such as onium salt compounds or sulfonamide compounds are preferred. Examples of onium salt compounds include iodinated salts or strontium salts. Specific examples include diaryl iodides such as diphenyliodotrifluoromethanesulfonate, diphenyliodop-toluenesulfonate, diphenyliodohexafluoroantimonate, diphenyliodohexafluorophosphate, and diphenyliodotetrafluoroborate; triaryl strontium salts such as triphenylstrontium trifluoromethanesulfonate, triphenylstrontium p-toluenesulfonate, and triphenylstrontium hexafluoroantimonate; 4-tributylphenyl-diphenylstrontium p-toluenesulfonate; and 4,7-di-n-butoxynaphthiotetrahydrothiophenonium trifluoromethanesulfonate. Specific examples of sulfonamide compounds include N-(trifluoromethylsulfonyl)succinimide, N-(trifluoromethylsulfonyl)phthalimide, N-(trifluoromethylsulfonyl)diphenylcis-butene diimide, N-(trifluoromethylsulfonyl)bicyclo[2.2.1]hept-5-en-2,3-dicarboxylic sulfonamide, N-(trifluoromethylsulfonyl)naphthophthalimide, N-(p-toluenesulfonyl)-1,8-naphthophthalimide, and N-(10-camphorsulfonyl)-1,8-naphthophthalimide.

[0047] From the viewpoint of resolution, as a photoacid generator, a compound having a trifluoromethanesulfonate group, a hexafluoroantimonate group, a hexafluorophosphate group, or a tetrafluoroborate group can be used.

[0048] As an alkali-soluble resin, there is no particular limitation as long as it has phenolic hydroxyl groups and / or carboxyl groups. However, in addition to polyester resin, polyether resin, polyimide resin, polyamide resin, polyamide-imide resin, polyether-imide resin, polyurethane resin, polyurethane-imide resin, polyurethane-imide-imide resin, silicone polyimide resin, and polyester-imide resin, as well as copolymers of the above and their precursors (polyamide acid, etc.), polybenzoxazole resin, phenoxy resin, polyurethane resin, polyether-urethane resin, polyphenylene sulfide resin, polyester resin, polyether resin, polycarbonate resin, polyetherketone resin, (meth)acrylic acid copolymer, phenolic varnish resin, and phenolic resin, etc., can also be mentioned.

[0049] It is preferable that the photosensitive resin composition is soluble in 2.38% by mass of a tetramethylammonium aqueous solution (TMAH aqueous solution). From the viewpoints of resolution, storage stability, and insulation reliability of the photosensitive resin composition, it is preferable that the photosensitive resin composition contains a compound having phenolic hydroxyl groups. Examples of compounds having phenolic hydroxyl groups include phenol / formaldehyde condensed phenolic varnish resins, cresol / formaldehyde condensed phenolic varnish resins, phenol-naphthol / formaldehyde condensed phenolic varnish resins, polyhydroxystyrene and its polymers, phenol-benzened diethanol condensed resins, cresol-benzened diethanol condensed resins, and phenol-dicyclopentadiene condensed resins.

[0050] It is preferable that the photosensitive resin composition includes a thermosetting resin. Examples of thermosetting resins include acrylate resins, epoxy resins, cyanate ester resins, maleic anhydride resins, allyl anhydride resins, phenolic resins, urea resins, melamine resins, alkyd resins, unsaturated polyester resins, diallyl phthalate resins, polysiloxane resins, resorcinol formaldehyde resins, triallyl cyanate resins, polyisocyanate resins, resins containing tris(2-hydroxyethyl) isocyanurate, resins containing triallyl trimellitate, and thermosetting resins synthesized from cyclopentadiene. From the viewpoint of the photosensitive resin composition's resolution, insulation reliability, and adhesion to metals, it is preferable that the thermosetting resin contains any one of hydroxymethyl, alkoxyalkyl, or glycidyl groups.

[0051] Each insulating layer 35 to 38 may contain filler. It is preferable that the filler content in each layer is less than 1% by mass. From the viewpoint of ease of processing and processing accuracy, the average particle size of the filler is, for example, less than 500 nm. Furthermore, it is even more preferable that each insulating layer 35 to 38 does not contain filler.

[0052] A plurality of wires 32 are arranged in corresponding slots T as described above, and function as conductive paths within the wiring component 30. Therefore, the width of the wires 32 is approximately the same as the line width L of the slot T, and the spacing between adjacent wires 32 is approximately the same as the spacing S of the slot T. From the viewpoint of effectively functioning as conductive paths, it is preferable that the wires 32 contain a highly conductive metallic material. Highly conductive metallic materials include, for example, copper, aluminum, or silver. These metallic materials tend to diffuse into the organic insulating laminate 31 upon heating. From the viewpoint of conductivity and cost, copper is preferable as the metallic material contained in the wires 32.

[0053] It is preferable that the wiring 32 is used to suppress the diffusion of the metallic materials constituting them into the organic insulating laminate 31 and to cover the barrier metal film 39. The barrier metal film 39 is composed of a first barrier metal film 39a and a second barrier metal film 39b. The first barrier metal film 39a is disposed between the wiring 32 (wiring 32a) and the first insulating layer 35 and the second insulating layer 36, and the second barrier metal film 39b is disposed between the wiring 32 (wiring 32b) and the third insulating layer 37 and the fourth insulating layer 38 (see FIG6). The first barrier metal film 39a is disposed in a manner that separates the wiring 32 (wiring 32a) from the first insulating layer 35 and the second insulating layer 36, and seals a portion of the side surface and the bottom surface of the wiring 32. The second barrier metal film 39b is provided to separate the open wiring 32 (wiring 32b) from the third insulating layer 37 and the fourth insulating layer 38, and seals the remaining side and top of the wiring 32.

[0054] The barrier metal film 39, composed of the first barrier metal film 39a and the second barrier metal film 39b, is a metallic material that is difficult to diffuse into the organic insulating layer, such as at least one of titanium, nickel, palladium, chromium, tantalum, tungsten, and gold. From the viewpoint of good adhesion to the inner surface of the tank T, it is preferable that the barrier metal film 39 is a titanium film or an alloy film containing titanium. Furthermore, from the viewpoint of forming the barrier metal film 39 by sputtering, it is preferable that the barrier metal film 39 is a titanium film, tantalum film, tungsten film, chromium film, or an alloy film containing at least one of titanium, tantalum, tungsten, and chromium.

[0055] The thickness of the barrier metal film 39 is less than half the width of the groove T and less than half the depth of the groove T, for example, 0.001 μm to 0.5 μm. From the viewpoint of preventing the diffusion of metal material within the wiring 32, a thickness of 0.01 μm to 0.5 μm for the barrier metal film 39 is preferable. Furthermore, from the viewpoint of improving the flatness of the barrier metal film 39 and the amount of current flowing through the wiring 32, a thickness of 0.001 μm to 0.3 μm for the barrier metal film 39 is preferable. From the above, it can be seen that a thickness of 0.01 μm to 0.3 μm for the barrier metal film 39 is optimal. Moreover, it is preferable that the first barrier metal film 39a and the second barrier metal film 39b are made of the same material, but they can be made of different materials.

[0056] The through-wire 33 is a wiring embedded in the opening H of the organic insulating laminate 31, serving as a connection terminal to an external device. The through-wire 33 is composed of a plurality of mutually stacked metal layers 33a, 33b, and 33c. The through-wire 33 preferably has a through-hole shape, with a through-hole diameter, for example, 1μm to 20μm, more preferably 1μm to 5μm, and even more preferably 2μm to 5μm.

[0057] The surface wiring 34 is used for electrically connecting, for example, semiconductor wafers 20A and 20B mounted on the wiring member 30. Therefore, both ends of the surface wiring 34 protrude from the wiring member 30, and the surface wiring 34 other than these two ends is embedded in the wiring member 30 (more specifically, in the fourth insulating layer 38). Therefore, the fourth insulating layer 38 may be composed of two or more organic insulating layers. Alternatively, the surface wiring 34 may not be formed.

[0058] Hereinafter, the manufacturing method of the wiring component 30 will be described with reference to Figures 3 to 6. The manufacturing method of this embodiment includes: (A) a step of forming a first organic insulating layer having a groove on a substrate; (B) a step of forming a first barrier metal film on the bottom surface and side surface of the groove of the first organic insulating layer; (C) a step of forming a conductive layer having a conductive material on the first organic insulating layer by filling the groove with a conductive material; (D) a step of removing the conductive layer portion on the first organic insulating layer to obtain a first wiring layer and a first wiring structure of the first organic insulating layer, wherein the first wiring layer includes a conductive material filled in the groove. (E) The steps of providing a second wiring structure having a second organic insulating layer and a second wiring layer comprising a conductive material filled in a groove disposed on the second organic insulating layer and exposed on the surface; and (F) The steps of aligning the first wiring layer and the second wiring layer in a corresponding manner and pressing the first wiring structure and the second wiring structure together, wherein in the step of lamination, each wiring of the first wiring layer is joined to each wiring of the second wiring layer, and the first organic insulating layer is joined to the second organic insulating layer.

[0059] First, as shown in FIG3(a), a metal layer 33a is formed on the substrate 10A. The metal layer 33a is formed by patterning a metal film formed on the substrate 10A. In this step, the metal layer 33a is formed, for example, by physical vapor deposition (PVD) methods such as coating, vacuum evaporation or sputtering, printing or spraying using a metal paste, or various electroplating methods. In this embodiment, copper foil can be used as the metal film, for example. The metal layer 33a constitutes a part (lower part) of the through wiring 33.

[0060] In the case of a temporary fixing layer (not shown) between the substrate 10A and the metal layer 33a, the temporary fixing layer may include, for example, a resin containing non-polar components such as polyimide, polybenzoxazole, silicon, and fluorine; a resin containing components that expand or foam upon heating or UV (ultraviolet) exposure; a resin containing components that undergo cross-linking reactions upon heating or UV exposure; or a resin that heats up upon light irradiation. Methods for forming the temporary fixing layer include, for example, spin coating, spray coating, or lamination. From the viewpoint of achieving a high level of balance between operability and carrier peelability, it is preferable that the temporary fixing layer can be easily peeled off by external stimuli such as light or heat. From the viewpoint of being able to peel off in a manner that prevents the temporary fixing layer from remaining in the subsequently manufactured wiring components 30, it is preferable that the temporary fixing layer contains a resin that expands upon heat treatment. In the case of providing a temporary fixing layer between the substrate 10A and the metal layer 33a, the metal layer 33a may be formed from a peelable copper foil. In this case, substrate 10A is equivalent to a support for peelable copper foil, and temporary fixing layer is equivalent to a release layer for peelable copper foil.

[0061] Next, as shown in FIG3(b), a first photosensitive resin layer 35A having a negative photosensitive resin composition is formed on the substrate 10A by covering the metal layer 33a. The photosensitive resin composition used to form the first photosensitive resin layer 35A can be any of the aforementioned materials as the photosensitive resin composition used to form the first insulating layer 35, etc.

[0062] Next, a light mask is disposed on the first photosensitive resin layer 35A, and the first photosensitive resin layer 35A is exposed except for the area that forms the opening H. Thereby, as shown in FIG3(c), an exposed portion 35a and an unexposed portion 35b are formed on the first photosensitive resin layer 35A. As a method for exposing the first photosensitive resin layer 35A, known projection exposure methods, contact exposure methods, or direct tracing exposure methods can be used.

[0063] Next, as shown in FIG3(d), a second photosensitive resin layer 36A is formed on the surface of the first photosensitive resin layer 35A after exposure treatment. The thickness of the second photosensitive resin layer 36A is, for example, 7 μm or less. The photosensitive resin composition used to form the second photosensitive resin layer 36A can be any of the aforementioned materials used as the photosensitive resin composition for forming the second insulating layer 36, etc., and can be the same as or different from the material used to form the first photosensitive resin layer 35A.

[0064] Next, a light mask is disposed on the second photosensitive resin layer 36A, and the second photosensitive resin layer 36A is exposed except for the areas that form the opening H and the groove T. Thereby, as shown in FIG4(a), an exposed portion 36a and an unexposed portion 36b are formed on the second photosensitive resin layer 36A. As a method for exposing the second photosensitive resin layer 36A, known projection exposure methods, contact exposure methods, or direct tracing exposure methods can be used.

[0065] Next, by performing a development process on the first photosensitive resin layer 35A and the second photosensitive resin layer 36A, as shown in FIG4(b), an opening Ha is formed that penetrates the first photosensitive resin layer 35A and the second photosensitive resin layer 36A, and a groove Ta (first groove) is formed in the second photosensitive resin layer 36A with the surface of the first photosensitive resin layer 35A as the bottom surface. In the development process (removal of unexposed portions 35b, 36b), alkaline aqueous solutions such as sodium carbonate or TMAH, organic solvents such as PGMEA, PGME, and cyclopentanone can be used, for example.

[0066] Next, the first photosensitive resin layer 35A and the second photosensitive resin layer 36A are cured by heating. For example, the heating temperature is set to 100 to 200°C and the heating time is set to 30 minutes to 3 hours. Thereby, as shown in FIG4(c), the first photosensitive resin layer 35A and the second photosensitive resin layer 36A become the first insulating layer 35 and the second insulating layer 36.

[0067] Next, as shown in FIG4(d), a first barrier metal film 39a is formed to cover the surface of the second insulating layer 36 and the inner surfaces of the opening Ha and the groove Ta. In this step, the first barrier metal film 39a is formed, for example, by coating, PVD, printing or spraying using a metal paste, or various electroplating methods. In the case of coating, the first barrier metal film 39a is formed by coating a palladium or nickel composite and then heating. In the case of using a metal paste, the first barrier metal film 39a is formed by coating a paste containing metal particles such as nickel or palladium onto the surface of the second insulating layer 36 and the inner surfaces of the opening Ha and the groove Ta, and then sintering.

[0068] Next, as shown in FIG. 5(a), a metal layer 32A is formed on the first barrier metal film 39a by filling the opening Ha and the groove Ta. In this step, the metal layer 32A is formed, for example, by using a metal paste or by electroplating with the first barrier metal film 39a as a seed layer. It is preferable that the thickness of the metal layer 32A is 0.5 to 3 times the combined thickness of the first insulating layer 35 and the second insulating layer 36. When the thickness of the metal layer 32A is 0.5 times or more, there is a tendency to suppress the increase of the surface roughness Ra of the wiring 32 formed in subsequent steps. Furthermore, when the thickness of the metal layer 32A is 3 times or less, there is a tendency to suppress the warping of the metal layer 32A and to achieve good adhesion with respect to the second insulating layer 36.

[0069] Next, as shown in FIG5(b), the second insulating layer 36 is exposed by removing the metal layer 32A and the first barrier metal film 39a on the second insulating layer 36. Herein, wiring 33A is formed by filling the opening Ha with metal. Wiring 32a is also formed by forming a conductive material, metal, within the groove Ta. After removing the metal layer 32A and the first barrier metal film 39a, a surface planarization process for the second insulating layer 36 can be performed. In this case, CMP or rapid machining methods can be used.

[0070] When CMP is used in this step, the slurry can typically be a slurry containing alumina for polishing resin, a slurry containing hydrogen peroxide and silicon oxide for polishing the first barrier metal film 39a, or a slurry containing hydrogen peroxide and ammonium persulfate for polishing the metal layer 32A. Considering the need to reduce costs and control the surface roughness Ra of the second insulating layer 36 and wirings 32a and 33A to 0.01 μm to 1 μm (more preferably 0.05 μm or less), it is preferable to use a slurry containing alumina to polish the second insulating layer 36, the first barrier metal film 39a, and the metal layers 32A (wirings 32a) and 33A. Furthermore, when the second insulating layer 36, the first barrier metal film 39a, and the metal layer 32A (wiring 32a, 33A) are planarized simultaneously, the difference in grinding speed creates dish-shaped depressions on the wiring 32a, 33A. As a result, the flatness of the combined surface of the second insulating layer 36 and the wiring 32a, 33A tends to be significantly impaired. Therefore, from the viewpoint of setting the surface roughness Ra of the above surfaces to 0.03 μm to 0.1 μm, it is better to grind the second insulating layer 36, the first barrier metal film 39a, and the metal layer 32A (wiring 32a, 33A) using a planer's rapid cutting method. Moreover, in this grinding, the surface of the wiring 32a can protrude from the surface of the second insulating layer 36. By using this grinding, the difference in thermal expansion between the second insulating layer 36 and the wiring 32a, etc., can be adjusted.

[0071] Through the above steps, the first wiring structure 30A with a multilayer structure as shown in FIG. 5(b) can be formed on the substrate 10A. Compared with conventional multilayer wiring layers, the first wiring structure 30A shown in FIG. 5(b) can be manufactured with a simpler process.

[0072] Next, as shown in FIG6, a second wiring structure 30B is first formed using the same process as that used to form the first wiring structure 30A described above. The second wiring structure 30B is configured, for example, to have a third insulating layer 37, a fourth insulating layer 38, the remaining portion of wiring 32 (i.e., wiring 32b), the remaining portion of through wiring 33 (i.e., wiring 33B), surface wiring 34, and a second barrier metal film 39b. Wiring 32b and the second barrier metal film 39b (the second barrier metal film) are formed within the groove Tb. The second wiring structure 30B can be manufactured using the same manufacturing process as the first wiring structure 30A described above, or it can be manufactured using other processes. The third insulating layer 37 and the fourth insulating layer 38, as described above, can be made of the same material as the first insulating layer 35 and the second insulating layer 36, and wiring 32b and 33B can also be made of the same material as wiring 32a and wiring 33A. A plurality of wirings 32b form the wiring layer (second wiring layer) in the second wiring structure 30B. This wiring layer may include wirings 33B and surface wirings 34. Furthermore, the second wiring structure 30B may or may not have a substrate equivalent to the substrate 10A, or it may be present during manufacturing and peeled off midway. Also, in the second wiring structure 30B, semiconductor wafers, etc., may be mounted on the side of the fourth insulating layer 38 opposite to the third insulating layer 37 (or within the fourth insulating layer 38).

[0073] Next, as shown in FIG. 6, when the preparation of the second wiring structure 30B is completed, the wirings 32a formed on the surface side of the first wiring structure 30A and the wirings 32b formed on the surface side of the second wiring structure 30B are aligned in a corresponding manner, and the wirings 33A of the first wiring structure 30A and the wirings 33B of the second wiring structure 30B are aligned in position. Then, the second wiring structure 30B is moved relative to the first wiring structure 30A, and lamination is performed while pressure is applied. During this lamination, the first wiring structure 30A and the second wiring structure 30B can be heated while pressure is applied and lamination is performed. The heating temperature in this case is, for example, 25°C to 300°C. Through this layering, each wire 32a of the first wiring structure 30A and each wire 32b of the second wiring structure 30B are joined to form a wiring 32 (wiring body), and each wire 33A of the first wiring structure 30A and each wire 33B of the second wiring structure 30B are joined to form a through wiring 33. At this time, the first barrier metal film 39a located on the outside of each wire 32a and the second barrier metal film 39b located on the outside of each wire 32b are also aligned and joined to form a barrier metal film 39 (joint body). The barrier metal films 39 cover the entire outer side of each wiring 32, preventing the diffusion of the material constituting the wiring 32 into the organic insulating layer. Furthermore, in this lamination step, it is preferable to align the wiring 32a and wiring 32b such that the horizontal deviation of the first barrier metal film 39a and the second barrier metal film 39b when joining them is less than 50% relative to the thickness of the barrier metal film 39. Also, during this joining, the second insulating layer 36 of the first wiring structure 30A and the third insulating layer 37 of the second wiring structure 30B are joined. The joining of the second insulating layer 36 and the third insulating layer 37 thereby forms the wiring member 30 shown in FIG. 2.

[0074] Subsequently, without mounting a semiconductor wafer on the wiring component 30, the required semiconductor wafer is mounted on the back side of the substrate 10 or on the fourth insulating layer 38 to complete the semiconductor package.

[0075] As described above, according to the semiconductor device manufacturing method of this embodiment, the wiring layer of the semiconductor package 1 is formed by bonding the wirings 32a and 32b formed by filling the trenches Ta and Tb with conductive material. In this case, the semiconductor package 1 having a fine and high-density wiring layer can be manufactured with high yield.

[0076] Furthermore, in the manufacturing method of the semiconductor device according to this embodiment, before forming the conductive layer, a first barrier metal film 39a is formed on the bottom and side surfaces of the trench portion Ta of the first insulating layer 35 and the second insulating layer 36. In this case, in the manufactured semiconductor device, conductive materials (such as copper) can be prevented from diffusing from the wiring 32 formed including the wiring 32a into the first insulating layer 35 and the second insulating layer 36, thereby hindering the insulation of the wiring 32. Furthermore, the thickness of the first barrier metal film 39a can be 0.001 μm or more and 0.5 μm or less. In this case, the diffusion of conductive materials into the organic insulating layer can be prevented more reliably, and the cross-sectional area of ​​each wiring 32 can also be sufficiently ensured.

[0077] Furthermore, in the manufacturing method of the semiconductor device of this embodiment, a second barrier metal film 39b is provided on the side and bottom surfaces of the trench portion Tb (second trench portion) of the third insulating layer 37 and the fourth insulating layer 38. Then, in the lamination step, it is preferable to align the wiring 32a and wiring 32b such that the horizontal position deviation of the first barrier metal film 39a and the second barrier metal film 39b is less than 50% relative to the thickness of the first barrier metal film 39a. In this case, the diffusion of conductive material (e.g., copper) that can diffuse from the organic insulating laminate 31 to the outside of the wiring 32 can be more reliably prevented by the first barrier metal film 39a and the second barrier metal film 39b, and in particular, the diffusion of conductive material from the junction of the first barrier metal film 39a and the second barrier metal film 39b can be prevented.

[0078] Furthermore, in the manufacturing method of the semiconductor device according to this embodiment, in the step of obtaining the first wiring structure 30A, the conductive layer portion on the second insulating layer 36 can be removed by grinding so that the surface roughness of the wiring 32a of the first wiring structure 30A is 0.05 μm or less. Similarly, the surface roughness of the wiring 32b of the second wiring structure 30B can also be ground. In this case, the bonding between the wiring 32a and the wiring 32b can be performed more reliably, and the wiring 32 in the semiconductor device can function more appropriately.

[0079] Furthermore, in the manufacturing method of the semiconductor device of this embodiment, the molten viscosity of the organic material constituting each insulating layer 35-38 at 250°C can be 1 kPa·s or more and 1 MPa·s or less. In this case, the bonding between the second insulating layer 36 and the third insulating layer 37 can be performed more reliably. More specifically, if the molten viscosity of the organic insulating material is less than 1 kPa·s, removing the conductive layer portion on the second insulating layer 36 may cause contamination of the wiring 32a due to the ductility of the organic insulating layer, but by having a molten viscosity of 1 kPa·s or more for the organic insulating material, such contamination can be prevented. Also, if the molten viscosity of the organic insulating material is greater than 1 MPa·s, it is necessary to increase the heating temperature when bonding the organic insulating layers together, which may lead to a decrease in productivity, but by having a molten viscosity of 1 MPa·s or less for the organic insulating material, the temperature when bonding the organic insulating layers together can be reduced, thereby increasing the corresponding productivity. In the above-described cases, it is preferable that the melt viscosity of the materials constituting each insulating layer 35-38 at 250°C is 3 kPa·s or higher, which further suppresses resin flow during bonding. Furthermore, it is preferable that the melt viscosity of the organic insulating material at 250°C is 5 kPa·s or higher, which suppresses stress caused by curing shrinkage. On the other hand, it is preferable that the melt viscosity of the organic materials constituting each insulating layer 35-38 at 250°C is 0.8 MPa·s or lower, which suppresses the formation of voids after bonding. Furthermore, it is preferable that the melt viscosity of the organic material at 250°C is 0.5 MPa·s or lower, which allows for low-temperature bonding of the second insulating layer 36 and the third insulating layer 37. Therefore, it is even more preferable that the melt viscosity of the organic materials constituting each insulating layer 35-38 at 250°C is between 5 kPa·s and 0.5 MPa·s.

[0080] Furthermore, in the manufacturing method of the semiconductor device of this embodiment, the conductive layer on the second insulating layer 36 can be removed by grinding in such a way that the surface of the wiring 32a protrudes further than the surface of the second insulating layer 36. Also, the conductive layer on the third insulating layer 37 can be removed by grinding in such a way that the surface of the wiring 32b protrudes further than the surface of the third insulating layer 37. In this case, the formation of unevenness at the bonding surface when joining the first wiring structure 30A and the second wiring structure 30B is suppressed due to the difference in thermal expansion coefficients between the organic resin material constituting the organic insulating layer and the metal material constituting the wiring layer, thereby enabling more reliable deposition of the first wiring structure 30A and the second wiring structure 30B.

[0081] Furthermore, in the manufacturing method of the semiconductor device of this embodiment, a photosensitive material is disposed on a substrate 10A, and the photosensitive material is exposed and developed to form a first insulating layer 35 and a second insulating layer 36. In this case, the insulating layer itself and the trench portion can be easily formed, which can improve manufacturing efficiency. In addition, finer trench portions, i.e., wiring 32a, can be fabricated, which can promote the miniaturization and high density of the wiring layer. Moreover, it is the same as the manufacturing of the second wiring structure 30B.

[0082] Furthermore, in the manufacturing method of the semiconductor device of this embodiment, the linewidth of each wiring 32a and 32b is 2 μm or less, and the thickness of each wiring 32a and 32b can be 1 μm or less. In this case, a finer and higher density wiring layer can be formed.

[0083] The embodiments of this disclosure have been described above, but this disclosure is not limited to the above embodiments and can be appropriately modified without departing from its spirit. For example, in the above embodiments, an example of connecting a semiconductor chip using a wiring member 30 is shown, but the wiring member 30 can be used to connect a semiconductor chip and a semiconductor wafer, or to connect semiconductor wafers to each other. It can be used for other connections. [Simplified Explanation of the Diagram]

[0026] Figure 1 is a schematic cross-sectional view showing an example of a semiconductor package. Figure 2 is a cross-sectional view showing a wiring component in the semiconductor package shown in Figure 1. Figures 3(a) to (d) are schematic cross-sectional views showing the formation process of a wiring component according to an embodiment of the present disclosure. Figures 4(a) to (d) are schematic cross-sectional views showing the formation process of a wiring component according to an embodiment of the present disclosure. Figures 5(a) and (b) are schematic cross-sectional views showing the formation process of a wiring component according to an embodiment of the present disclosure. Figure 6 is a schematic cross-sectional view showing the formation process of a wiring component according to an embodiment of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: The step of forming a first organic insulating layer with grooves on a substrate; The process includes the following steps: forming a conductive layer on the first organic insulating layer by filling the aforementioned groove with conductive material; removing the aforementioned conductive layer portion on the first organic insulating layer to obtain a first wiring structure having a first wiring layer comprising the aforementioned conductive material filled in the aforementioned groove and the aforementioned first organic insulating layer; providing a second wiring structure having a second organic insulating layer and a second wiring layer comprising a conductive material filled in the groove provided on the aforementioned second organic insulating layer and exposed on the surface; and aligning the aforementioned first wiring layer and the aforementioned second wiring layer in a corresponding manner and pressing the aforementioned first wiring structure and the aforementioned second wiring structure to form a laminate, wherein in the laminate step, each wire of the aforementioned first wiring layer is joined with each wire of the aforementioned second wiring layer, and the aforementioned first organic insulating layer is joined with the second organic insulating layer.

2. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the organic material constituting at least one of the aforementioned first organic insulating layer and the aforementioned second organic insulating layer has a melt viscosity of 1 kPa·s or more and 1 MPa·s or less at 250°C.

3. The method for manufacturing a semiconductor device as claimed in claim 2, wherein the organic material constituting at least one of the aforementioned first organic insulating layer and the aforementioned second organic insulating layer has a melt viscosity of 5 kPa·s or more and 0.5 MPa·s or less at 250°C.

4. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the step of forming the first organic insulating layer includes the steps of disposing a photosensitive material on the substrate and exposing and developing the photosensitive material to form the first organic insulating layer.

5. The method for manufacturing a semiconductor device as claimed in claim 4, wherein the aforementioned photosensitive material is a photosensitive resin composition comprising a photoacid generator, a compound having a tertiary amine group or a nitrogen-containing heterocyclic compound, an alkali-soluble resin, and a thermosetting resin.

6. A method for manufacturing a semiconductor device as claimed in claim 1, wherein in the aforementioned stacking step, the first wiring structure and the second wiring structure are heated while being pressurized and stacked, wherein the heating temperature is above 25°C and below 300°C.

7. A method for manufacturing a semiconductor device as described in any one of claims 1 to 6, further comprising the step of forming a first barrier metal film on at least one side of the bottom and side surfaces of the aforementioned trench portion of the aforementioned first organic insulating layer before forming the aforementioned conductive layer.

8. The method for manufacturing a semiconductor device as described in claim 7, wherein the thickness of the aforementioned first barrier metal film is 0.001 μm or more and 0.5 μm or less.

9. A method for manufacturing a semiconductor device as claimed in claim 7, wherein the thickness of the first barrier metal film is less than half the width of the aforementioned trench portion of the first organic insulating layer or less than half the depth of the aforementioned trench portion.

10. A method for manufacturing a semiconductor device as claimed in claim 7, wherein a second barrier metal film is provided on at least one side of the aforementioned trench portion of the aforementioned second organic insulating layer, and in the aforementioned lamination step, the positions of the aforementioned first wiring layer and the aforementioned second wiring layer are aligned such that the positions of the aforementioned first barrier metal film on the aforementioned side of the aforementioned trench portion of the aforementioned first organic insulating layer and the aforementioned second barrier metal film on the aforementioned side of the aforementioned trench portion of the aforementioned second organic insulating layer deviate from the positions of the aforementioned first barrier metal film in the direction intersecting the aforementioned side in such a way that the thickness of the aforementioned first barrier metal film is less than 50%.

11. A method for manufacturing a semiconductor device as claimed in claim 7, wherein the first barrier metal film is formed on the bottom surface and the side surface of the aforementioned trench portion, and a second barrier metal film is disposed on the bottom surface and the side surface of the aforementioned trench portion of the aforementioned second organic insulating layer, and in the aforementioned lamination step, the aforementioned first wiring structure and the aforementioned second wiring structure are laminated in such a manner that the entire wiring body of the aforementioned wiring of the aforementioned first wiring layer and the aforementioned wiring of the aforementioned second wiring layer is covered by the joint of the aforementioned first barrier metal film and the aforementioned second barrier metal film.

12. A method for manufacturing a semiconductor device as described in any one of claims 1 to 6, wherein in the step of obtaining the first wiring structure, the conductive layer portion on the first organic insulating layer is removed by polishing such that the surface roughness of the first wiring layer of the first wiring structure is 0.05 μm or less.

13. A method for manufacturing a semiconductor device as described in any one of claims 1 to 6, wherein the surface roughness of the aforementioned second wiring layer of the aforementioned second wiring structure is 0.05 μm or less.

14. A method for manufacturing a semiconductor device as described in any one of claims 1 to 6, wherein the cured resin composition constituting at least one of the aforementioned first organic insulating layer and the aforementioned second organic insulating layer has a storage elastic modulus of 500 MPa or more and 1000 GPa or less at 25°C.

15. A method for manufacturing a semiconductor device as described in any one of claims 1 to 6, wherein in the step of obtaining the first wiring structure, the conductive layer on the first organic insulating layer is removed by grinding in such a manner that the surface of the first wiring layer is made to protrude more than the surface of the first organic insulating layer.

16. A method for manufacturing a semiconductor device as described in any one of claims 1 to 6, wherein the step of forming the aforementioned first organic insulating layer includes the step of forming the aforementioned trench in the aforementioned first organic insulating layer.

17. A method for manufacturing a semiconductor device as described in any one of claims 1 to 6, wherein the linewidth of each wire in the first wiring layer is 2 μm or less, and the thickness of each wire in the first wiring layer is 1 μm or less.

18. A method for manufacturing a semiconductor device as described in any one of claims 1 to 6, wherein in the first wiring structure, a first semiconductor element is disposed on the substrate on the side opposite to the first organic insulating layer or within the substrate; in the second wiring structure, a second semiconductor element is disposed on the second organic insulating layer on the side opposite to the second wiring layer or within the second organic insulating layer; and the first semiconductor element and the second semiconductor element are electrically connected by a wiring layer formed by bonding the first wiring layer and the second wiring layer.

19. A semiconductor device comprising: a first wiring structure including a substrate, a first organic insulating layer disposed on the substrate and having a first trench, and a first wiring layer made of a conductive material filled in the first trench; and a second wiring structure including a second organic insulating layer having a second trench, and a second wiring layer made of a conductive material filled in the second trench, wherein the first wiring structure is deposited on the second wiring structure such that the first wiring layer is bonded to the second wiring layer and the first organic insulating layer is bonded to the second organic insulating layer.

20. The semiconductor device as claimed in claim 19, further comprising: a first semiconductor element disposed in the first wiring structure on the substrate on a side opposite to the first organic insulating layer or within the substrate; and a second semiconductor element disposed in the second wiring structure on the second organic insulating layer on a side opposite to the second wiring layer or within the second organic insulating layer, wherein the first semiconductor element and the second semiconductor element are electrically connected by a wiring layer formed by bonding the first wiring layer and the second wiring layer.

Images