Semiconductor chip

Abstract

This invention provides a semiconductor wafer. The semiconductor wafer includes: a substrate including a device region and an edge region; a device layer and a wiring layer, sequentially stacked on the substrate; a sub-pad located on the device region; and a residual test pattern located on the edge region, wherein the sidewalls of the residual test pattern are aligned with the sidewalls of the substrate; and an upper dielectric stack covering the sub-pad and the residual test pattern. The upper dielectric stack may expose a portion of the top surface of the residual test pattern. The sidewalls of the upper dielectric stack may have stepped regions.

Description

Technical Field

[0001] [Cross - Reference to Related Applications]

[0002] This U.S. non - provisional application claims priority under 35 U.S.C § 119 to Korean Patent Application No. 10 - 2021 - 0120226, filed on September 9, 2021 with the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

[0003] The present inventive concept relates to semiconductor devices and / or semiconductor packages, and more particularly to semiconductor wafers having stepped sidewalls, semiconductor packages including semiconductor wafers, and / or methods of manufacturing semiconductor wafers. Prior Art

[0004] Generally, a wafer on which semiconductor devices are formed is divided into a chip area on which a plurality of units are formed and a saw street that separates the chips from each other. A plurality of semiconductor devices such as transistors, resistors, and capacitors are formed on the chip area and not on the saw street. The wafer is sawed along the saw street to complete or separate each of the semiconductor devices (or semiconductor wafers). The saw street may provide alignment keys useful for exposing the process and / or test patterns for monitoring the electrical characteristics and defect patterns of the semiconductor devices formed on the chip area to verify whether the process is executed properly. Summary of the Invention

[0005] Some example embodiments of the present inventive concept provide semiconductor wafers with increased reliability.

[0006] Some example embodiments of the present inventive concept provide semiconductor packages with increased reliability.

[0007] Some example embodiments of the present inventive concept provide a method of manufacturing a semiconductor wafer capable of increasing the yield.

[0008] According to some example embodiments of the present invention concept, a semiconductor wafer may include: a substrate including a device region and an edge region; a device layer and a wiring layer stacked on the substrate in sequence; a residual test pattern and a sub-pad located on the wiring layer, the sub-pad being located on the device region, the residual test pattern being located on the edge region, and sidewalls of the residual test pattern being aligned with sidewalls of the substrate; and an upper dielectric stack covering the sub-pad and the residual test pattern. The upper dielectric stack may expose a part of a top surface of the residual test pattern. Sidewalls of the upper dielectric stack may have a stepped region.

[0009] According to some example embodiments of the present invention concept, a semiconductor wafer may include: a substrate including a device region and an edge region; a device layer and a wiring layer stacked on the substrate in sequence; a residual test pattern and a sub-pad located on the wiring layer, the sub-pad being located on the device region, the residual test pattern being located on the edge region, and sidewalls of the residual test pattern being aligned with sidewalls of the substrate; an upper dielectric stack covering the sub-pad and the residual test pattern; a passivation layer located on the upper dielectric stack; a separation dielectric pattern penetrating the wiring layer on the edge region; a bonding pad located in the upper dielectric stack and connected to the sub-pad; a conductive bump penetrating the passivation layer and coupled to the bonding pad; and a solder layer coupled to the conductive bump. The upper dielectric stack may expose a part of a top surface of the residual test pattern. Sidewalls of the upper dielectric stack may have a stepped region. A top surface of the bonding pad may be located at a first depth from a top surface of the passivation layer. A bottom surface of the stepped region may be located at a second depth from the top surface of the passivation layer. The second depth may be about 0.9 times to about 2.0 times the first depth.

[0010] According to some example embodiments of the present invention concept, a semiconductor wafer may include: a substrate including a device region and an edge region; a device layer and a wiring layer stacked on the substrate in sequence; a residual test pattern and a sub-pad located on the wiring layer, the sub-pad being located on the device region, the residual test pattern being located on the edge region, and sidewalls of the residual test pattern being aligned with sidewalls of the substrate; and an upper dielectric stack covering the sub-pad and the residual test pattern. The upper dielectric stack may expose a part of a top surface of the residual test pattern. The device layer may include a device interlayer dielectric layer. The upper dielectric stack may include a plurality of upper dielectric layers stacked in sequence. A surface roughness at sidewalls of the uppermost one of the upper dielectric layers may be less than a surface roughness at sidewalls of the device interlayer dielectric layer.

[0011] According to some example embodiments of the concepts of the present invention, a semiconductor package may include a first semiconductor wafer, a plurality of second semiconductor wafers stacked on the first semiconductor wafer, and a mold layer covering the lateral surfaces of the second semiconductor wafers and the top surface of the first semiconductor wafer. Each of the second semiconductor wafers may include a second substrate and a circuit structure under the second substrate. The second substrate may include a device region and an edge region surrounding the device region. The circuit structure may include: a device layer and a wiring layer stacked in sequence under the second substrate; a sub-pad and a residual test pattern located under the wiring layer, and a dielectric stack covering the bottom surface of the sub-pad and the bottom surface of the residual test pattern. The sidewall of the dielectric stack may have a stepped region. The mold layer may cover the stepped region.

[0012] According to some example embodiments of the concepts of the present invention, a method of manufacturing a semiconductor wafer may include: forming a wiring layer on a substrate including a plurality of device regions and a dicing lane region between the device regions; forming a sub-pad and a test pattern on the wiring layer, the sub-pad being located on a corresponding one of the device regions, and the test pattern being located on the dicing lane region; forming a first upper dielectric layer covering the sub-pad and the test pattern; forming a bonding pad connected to the sub-pad on the first upper dielectric layer; forming a second upper dielectric layer covering the bonding pad and the first upper dielectric layer; etching the second upper dielectric layer on the test pattern to form a preliminary hole exposing the first upper dielectric layer; and etching the first upper dielectric layer under the preliminary hole to form a first hole exposing the test pattern, while etching the second upper dielectric layer on the bonding pad to form a second hole exposing the bonding pad. Brief Description of the Drawings

[0013] FIG. 1 is a plan view showing a semiconductor device according to some embodiments of the concepts of the present invention. FIG. 2A is a cross-sectional view taken along line A-A' of FIG. 1. FIG. 2B is a cross-sectional view taken along line B-B' of FIG. 1. FIG. 3A is an enlarged view showing section P1 of FIG. 2A. FIG. 3B is an enlarged view showing section P2 of FIG. 2A. FIG. 4 is a plan view showing a wafer. FIGS. 5A to 5K are cross-sectional views showing a method of manufacturing a semiconductor wafer having the cross-section of FIG. 2A. FIG. 6 is a cross-sectional view taken along line A-A' of FIG. 1. FIG. 7 is a cross-sectional view showing a method of manufacturing the semiconductor wafer of FIG. 6 according to some example embodiments of the concepts of the present invention. FIG. 8 is a cross-sectional view taken along line A-A' of FIG. 1. FIGS. 9A to 9C are cross-sectional views showing a method of manufacturing the semiconductor wafer of FIG. 8. FIG. 10 is a cross-sectional view showing a semiconductor package according to some example embodiments of the inventive concept. Embodiments

[0014] Some example embodiments of the inventive concept will now be described in detail with reference to the accompanying drawings to help clearly explain the inventive concept.

[0015] Although the terms "same", "equal", or "equivalent" are used in the description of the example embodiments, it should be understood that there may be some inaccuracies. Thus, when an element is referred to as being the same as another element, it should be understood that the element or value is the same as another element within the manufacturing or operable tolerance range (e.g., ±10%) of what is to be manufactured.

[0016] When the terms "about" or "substantially" are used in this specification in connection with a numerical value, the associated numerical value is intended to include the manufacturing or operational tolerance around the stated numerical value (e.g., ±10%). In addition, when the phrases "about" and "substantially" are used in connection with a geometric shape, it is intended that the exactness of the geometric shape is not required, but the tolerance of the shape is within the scope of this disclosure. Further, whether or not a numerical value or shape is modified by "about" or "substantially", it will be understood that such values and shapes are to be considered as including the manufacturing or operational tolerance around the stated numerical value or shape (e.g., ±10%).

[0017] FIG. 1 is a plan view showing a semiconductor device according to some embodiments of the inventive concept. FIG. 2A is a cross-sectional view taken along line A-A' of FIG. 1. FIG. 2B is a cross-sectional view taken along line B-B' of FIG. 1.

[0018] Referring to FIGS. 1, 2A, and 2B, the semiconductor wafer 100 according to the present example embodiment may include a substrate 1 and a circuit structure CS. The substrate 1 may include, for example, a semiconductor material. The substrate 1 may be a single crystal silicon substrate. The substrate 1 may include a device region DR and an edge region ER surrounding the device region DR. The substrate 1 may have a first surface 1a and a second surface 1b opposite to each other. The circuit structure CS may be disposed on the first surface 1a of the substrate 1. The circuit structure CS may include a device layer DL, a wiring layer LI, and an upper dielectric stack UI stacked in sequence.

[0019] On the device region, the transistor TR can be disposed on the first surface 1a of the substrate 1. Although not shown in the figure, on the device region DR, the first surface 1a can be provided with shallow isolation patterns, memory cells, capacitors, and the like. The first surface 1a of the substrate 1 can be covered by the device interlayer dielectric layer 3. The device interlayer dielectric layer 3 can have a single-layer or multi-layer structure, including at least one selected from silicon oxide, silicon nitride, and silicon oxynitride, for example.

[0020] The wafer sidewall 100_S of the semiconductor wafer 100 can include the sidewall of the lower passivation layer 40, the sidewall 1_S of the substrate 1, the sidewall 3_S of the device interlayer dielectric layer 3, the sidewall of the edge lower dielectric stack 7e, the sidewall of the second residual test pattern 14sr, the sidewall UI_S of the upper dielectric stack UI, and the sidewall of the upper passivation layer 29.

[0021] On the device region DR, the device interlayer dielectric layer 3 can be provided with contact plugs 5c connected to the transistor TR therein. On the edge region ER, the device interlayer dielectric layer 3 can be provided with a first protection ring pattern 5g and a first debris dam 5p therein.

[0022] The contact plugs 5c, the first protection ring pattern 5g, and the first debris dam 5p can be made of the same material, such as tungsten. Although not shown, the contact plugs 5c, the first protection ring pattern 5g, and the first debris dam 5p can be covered with a barrier metal provided on their lateral surfaces and bottom surfaces. The barrier metal can include at least one selected from titanium, titanium nitride, tantalum, tantalum nitride, and tungsten nitride, for example. The contact plugs 5c, the first protection ring pattern 5g, and the first debris dam 5p can penetrate the device interlayer dielectric layer 3. The device layer DL can be composed of the transistor TR, the interlayer dielectric layer 3, the contact plugs 5c, the first protection ring pattern 5g, and the first debris dam 5p.

[0023] Similarly, for the fifth protection ring pattern 14g discussed below with reference to FIG. 1, when observed in a plan view, each of the first protection ring patterns 5g can have an annular shape surrounding the device region DR. The first protection ring pattern 5g can be used to protect the device layer DL on the device region DR from moisture and / or physical cracks. Similarly, for the fifth debris dam pattern 14p in FIG. 1, when observed in a plan view, each of the first debris dams 5p can have an annular shape surrounding the first protection ring pattern 5g. The first debris dam 5p can be used to protect the device layer DL on the device region DR from moisture and / or physical cracks.

[0024] The wiring layer LI can be disposed on the device interlayer dielectric layer 3. The wiring layer LI can include a main lower dielectric stack 7m and edge lower dielectric stacks 7e spaced apart from each other. The main lower dielectric stack 7m and the lower dielectric stacks 7e can each include a plurality of lower inter-metal dielectric layers 10. The lower inter-metal dielectric layer 10 can include a low-k dielectric material having a dielectric constant less than that of silicon oxide. For example, the lower inter-metal dielectric layer 10 can be a porous dielectric layer. The lower inter-metal dielectric layer 10 can include SiOCH. Each of the lower inter-metal dielectric layers 10 can have a mechanical strength less than that of the device interlayer dielectric layer 3. Although not shown, an etch stop layer can be inserted between the lower inter-metal dielectric layers 10. The etch stop layer can include, for example, one of silicon nitride, silicon oxynitride, and silicon carbonitride.

[0025] The main lower dielectric stack 7m can cover the device region DR and a part of its adjacent edge region ER. When observed in a plan view, as shown in FIG. 1, the edge lower dielectric stack 7e can have an annular shape, can be disposed on the edge region ER, and can surround the main lower dielectric stack 7m. The edge lower dielectric stack 7e can have an exposed sidewall. The sidewall of the edge lower dielectric stack 7e can be aligned with the sidewall 3_S of the device interlayer dielectric layer 3.

[0026] The wiring layer LI can include a plurality of lower wiring patterns 11 in the main lower dielectric stack 7m disposed on the device region DR, and can also include lower via patterns 9 connecting the lower wiring patterns 11 to each other. The wiring layer LI can further include a lower guard ring structure GS1 and a lower debris dam structure PS1 in the main lower dielectric stack 7m disposed on the edge region ER.

[0027] The lower guard ring structure GS1 can include a second guard ring pattern 11g and a third guard ring pattern 9g connecting the second guard ring patterns 11g to each other. The second guard ring pattern 11g can be located at the same height (horizontal height) as the lower wiring pattern 11, and can include the same material as the lower wiring pattern 11. The third guard ring pattern 9g can be located at the same height (horizontal height) as the lower via pattern 9, and can include the same material as the lower via pattern 9. When observed in a plan view, the second guard ring pattern 11g and the third guard ring pattern 9g can each have an annular shape surrounding the device region DR. The lower guard ring structure GS1 is used to block or protect the wiring layer LI on the device region DR from moisture and / or physical cracks.

[0028] The lower debris dam structure PS1 may include a second debris dam pattern 11p and a third debris dam pattern 9p that connects the second debris dam patterns 11p to each other. The second debris dam pattern 11p may be located at the same height (horizontal height) as the lower wiring pattern 11 and may include the same material as the lower wiring pattern 11. The third debris dam pattern 9p may be located at the same height (horizontal height) as the lower via pattern 9 and may include the same material as the lower via pattern 9. When observed in a plan view, the second debris dam pattern 11p and the third debris dam pattern 9p may each have an annular shape surrounding the lower protection ring structure GS1. The lower protection ring structure GS1 may be used to block or protect the wiring layer LI on the device region DR from moisture and / or physical cracks.

[0029] The wiring layer LI may include a first residual test pattern 11sr disposed in the edge lower dielectric stack 7e and a first test via pattern 9s that connects the first residual test patterns 11sr to each other. The first residual test pattern 11sr may be located at the same height (horizontal height) as the lower wiring pattern 11 and may include the same material as the lower wiring pattern 11. The first test via pattern 9s may be located at the same height (horizontal height) as the lower via pattern 9 and may include the same material as the lower via pattern 9. The first residual test pattern 11sr may be, for example, a part of a test pattern. The first residual test pattern 11sr may have sidewalls aligned with the sidewalls 3_S of the device interlayer dielectric layer 3.

[0030] The wiring layer LI may be composed of a main lower dielectric stack 7m, an edge lower dielectric stack 7e, a lower wiring pattern 11, a lower via pattern 9, a lower protection ring structure GS1, a first residual test pattern 11sr, and a first test via pattern 9s.

[0031] The upper dielectric stack UI can be disposed on the wiring layer LI. The upper dielectric stack UI can include a first upper inter-metal dielectric layer 13, a second upper inter-metal dielectric layer 15, a third upper inter-metal dielectric layer 17, a fourth upper inter-metal dielectric layer 19, a fifth upper inter-metal dielectric layer 23, a sixth upper inter-metal dielectric layer 25, and a seventh upper inter-metal dielectric layer 27 stacked in sequence. The first upper inter-metal dielectric layer 13, the second upper inter-metal dielectric layer 15, the third upper inter-metal dielectric layer 17, the fourth upper inter-metal dielectric layer 19, the fifth upper inter-metal dielectric layer 23, the sixth upper inter-metal dielectric layer 25, and the seventh upper inter-metal dielectric layer 27 can each include a dielectric material having a dielectric constant greater than that of the lower inter-metal dielectric layer 10. The first upper inter-metal dielectric layer 13, the second upper inter-metal dielectric layer 15, the third upper inter-metal dielectric layer 17, the fourth upper inter-metal dielectric layer 19, the fifth upper inter-metal dielectric layer 23, the sixth upper inter-metal dielectric layer 25, and the seventh upper inter-metal dielectric layer 27 can each have a mechanical strength greater than that of the lower inter-metal dielectric layer 10.

[0032] The first upper inter-metal dielectric layer 13 can be provided with a subliner 14, a fifth protection ring pattern 14g, a fifth debris dam pattern 14p, and a second residual test pattern 14sr thereon. The second residual test pattern 14sr can be provided in multiple forms, and multiple second residual test patterns 14sr can be arranged in rows along the edge of the semiconductor wafer 100.

[0033] Although not shown, upper circuitry can be additionally disposed on the first upper inter-metal dielectric layer 13 on the device region DR.

[0034] The device region DR can be provided with a subliner 14 thereon, and the edge region ER can be provided with a fifth protection ring pattern 14g, a fifth debris dam pattern 14p, and a second residual test pattern 14sr thereon. The subliner 14, the fifth protection ring pattern 14g, the fifth debris dam pattern 14p, and the second residual test pattern 14sr can be located at the same horizontal height and can be the same in terms of material and thickness T1.

[0035] The first upper via pattern 12 can penetrate the first upper inter-metal dielectric layer 13 and can connect the sub-pad 14 to one of the lower wiring patterns 11. The fourth protection ring pattern 12g can pass through the first upper inter-metal dielectric layer 13 and can connect the second protection ring pattern 11g to the fifth protection ring pattern 14g. The fourth debris dam pattern 12p can penetrate the first upper inter-metal dielectric layer 13 and can connect the second debris dam pattern 11p to the fifth debris dam pattern 14p. The second test via pattern 12s can penetrate the first upper inter-metal dielectric layer 13 and can connect the first residual test pattern 11sr to the second residual test pattern 14sr. The first upper via pattern 12, the fourth protection ring pattern 12g, the fourth debris dam pattern 12p, and the second test via pattern 12s can be located at the same horizontal height and can be the same in terms of material and thickness.

[0036] The fourth protection ring pattern 12g and the fifth protection ring pattern 14g can form an upper protection ring structure GS2. When observed in a plan view, the upper protection ring structure GS2 can surround the device region DR. The fourth debris dam pattern 12p and the fifth debris dam pattern 14p can form an upper debris dam structure PS2. When observed in a plan view, the upper debris dam structure PS2 can surround the upper protection ring structure GS2. The upper protection ring structure GS2 and the upper debris dam structure PS2 can be used to block or protect the device region DR from moisture and / or physical cracks.

[0037] The second upper inter-metal dielectric layer 15, the third upper inter-metal dielectric layer 17, and the fourth upper inter-metal dielectric layer 19 can be stacked in sequence on the first upper inter-metal dielectric layer 13, the sub-pad 14, the fifth protection ring pattern 14g, the fifth debris dam pattern 14p, and the second residual test pattern 14sr. The first upper inter-metal dielectric layer 13 and the second upper inter-metal dielectric layer 15 can each include, for example, silicon oxide, tetraethyl orthosilicate (TEOS), or high-density plasma (HDP) oxide.

[0038] The third upper inter-metal dielectric layer 17 can include, for example, silicon nitride. In this case, the second upper inter-metal dielectric layer 15 can serve as an etch stop layer. In some exemplary embodiments, the third upper inter-metal dielectric layer 17 can include a material with low hydrogen permeability. In this case, the third upper inter-metal dielectric layer 17 can serve as a hydrogen barrier. For example, the third upper inter-metal dielectric layer 17 can include at least one selected from aluminum oxide (AlOx), tungsten oxide (WOx), and silicon nitride (SiNx).

[0039] The fourth upper metal - dielectric layer 19, the fifth upper metal - dielectric layer 23, the sixth upper metal - dielectric layer 25, and the seventh upper metal - dielectric layer 27 may comprise, for example, one of high - density plasma (HDP) oxide, undoped silicate glass (USG), tetraethyl orthosilicate (TEOS), SiN, SiO₂, SiOC, SiON, and SiCN.

[0040] The first upper metal - dielectric layer 13 may have sidewalls aligned with the sidewalls of the edge lower dielectric stack 7e. The second upper metal - dielectric layer 15, the third upper metal - dielectric layer 17, and the fourth upper metal - dielectric layer 19 may have sidewalls aligned with each other and may partially expose the top surface 14sr_U of the second residual test pattern 14sr.

[0041] The second upper via pattern 22 may be coupled to the sub - pad 14 while penetrating the second upper metal - dielectric layer 15, the third upper metal - dielectric layer 17, and the fourth upper metal - dielectric layer 19. In the device region DR, the bonding pad 21p may be disposed on the fourth upper metal - dielectric layer 19. The fifth upper metal - dielectric layer 23 and the sixth upper metal - dielectric layer 25 may be formed conformally and sequentially on the fourth upper metal - dielectric layer 19. The fifth upper metal - dielectric layer 23 and the sixth upper metal - dielectric layer 25 may conformally cover the sidewalls and the top surface of the bonding pad 21p in sequence.

[0042] A portion of the sixth upper metal - dielectric layer 25 may penetrate the first upper metal - dielectric layer 13, the second upper metal - dielectric layer 15, the third upper metal - dielectric layer 17, the fourth upper metal - dielectric layer 19, and the fifth upper metal - dielectric layer 23 between the upper debris dam structure PS2 and the second residual test pattern 14sr, and may be inserted between the main lower dielectric stack 7m and the edge lower dielectric stack 7e. The groove GR1 may be formed in the first upper metal - dielectric layer 13, the second upper metal - dielectric layer 15, the third upper metal - dielectric layer 17, the fourth upper metal - dielectric layer 19, and the fifth upper metal - dielectric layer 23 and between the main lower dielectric stack 7m and the edge lower dielectric stack 7e, and a portion of the sixth upper metal - dielectric layer 25 may be coupled to the device inter - dielectric layer 3 while covering the sidewalls and the bottom surface of the groove GR1. The sixth upper metal - dielectric layer 25 may act as a cover layer.

[0043] The seventh upper metal - dielectric layer 27 may have a flat top surface. A portion of the seventh upper metal - dielectric layer 27 may be inserted into the groove GR1, thereby filling the groove GR1 and forming the separation dielectric pattern 27b.

[0044] When observed in a plan view, as depicted in FIG. 1, the sidewall 27_S of the seventh upper inter-metal dielectric layer 27 may have a recessed region LRC that is laterally recessed in a first direction X (or towards the device region DR). Multiple lateral recessed regions LRC may be provided, and the multiple recessed regions LRC may correspondingly overlap with the second residual test pattern 14sr. When observed in a plan view, the seventh upper inter-metal dielectric layer 27 may have an irregular structure (e.g., a square wave shape) at its sidewall 27_S. The sidewalls of the second upper inter-metal dielectric layer 15, the third upper inter-metal dielectric layer 17, the fourth upper inter-metal dielectric layer 19, the fifth upper inter-metal dielectric layer 23, and the sixth upper inter-metal dielectric layer 25 may have a planar shape similar to the sidewall 27_S of the seventh upper inter-metal dielectric layer 27.

[0045] Referring to FIGS. 1 and 2A, in the lateral recessed region LRC, the semiconductor wafer 100 may have a stepped region SDR or a stepped profile at its wafer sidewall 100_S. The stepped region SDR may include a first stepped region SDR(1) and a second stepped region SDR(2). The stepped region SDR may be a double-stepped region. For example, the semiconductor wafer 100 may have a stepped wafer sidewall 100_S. The wafer sidewall 100_S of the semiconductor wafer 100 may have a stepped shape.

[0046] The sidewall 27_S of the seventh upper inter-metal dielectric layer 27 may have a first stepped region SDR(1) in the recessed region LRC. The upper dielectric stack UI may have a first stepped region SDR(1) at its sidewall UI_S. For example, the seventh upper inter-metal dielectric layer 27 may have upper sidewalls 27_S(1) and lower sidewalls 27_S(2) that are offset from each other. For the seventh upper inter-metal dielectric layer 27, the upper sidewall 27_S(1) may be connected to the lower sidewall 27_S(2) via an intermediate surface 27_M. The seventh upper inter-metal dielectric layer 27 may have a top surface 27_U that is stepped relative to the intermediate surface 27_M, and the intermediate surface is stepped relative to the top surface 14sr_U of the second residual test pattern 14sr (or relative to the top surface of the first upper inter-metal dielectric layer 13), and the second stepped region SDR(2) may be formed by the intermediate surface 27_M and the top surface 14sr_U that are stepped relative to each other. The intermediate surface 27_M of the seventh upper inter-metal dielectric layer 27 may be located at a second depth DT2 from the top surface of the passivation layer 29. The second depth DT2 may be, for example, about 0.9 times to about 2.0 times the first depth DT1 that will be discussed below.

[0047] Referring to FIGS. 1 and 2B, when observed in a cross-section taken along line B-B' of semiconductor wafer 100, the wafer sidewall 100_S may not be stepped, but may be vertically flat. For example, the first upper inter-metal dielectric layer 13, the second upper inter-metal dielectric layer 15, the third upper inter-metal dielectric layer 17, the fourth upper inter-metal dielectric layer 19, the fifth upper inter-metal dielectric layer 23, the sixth upper inter-metal dielectric layer 25, and the seventh upper inter-metal dielectric layer 27 may have sidewalls that are all aligned with each other. The upper dielectric stack UI may have a sidewall aligned with the device inter-layer dielectric layer 3. When observed in a cross-section taken along line B-B' of semiconductor wafer 100, the wafer sidewall 100_S may coincide with the cut surface CTS.

[0048] Referring to FIGS. 1 and 2A, when observed in a cross-section taken along line A-A' of semiconductor wafer 100, the cut surface CTS may include the sidewall of the lower passivation layer 40, the sidewall 1_S of the substrate 1, the sidewall 3_S of the device inter-layer dielectric layer 3, the sidewall of the edge lower dielectric stack 7e, and the sidewall of the second residual test pattern 14sr.

[0049] The seventh upper inter-metal dielectric layer 27 may serve as a buried dielectric layer. When observed in a plan view, the grooves GR1 and the isolation dielectric pattern 27b may each have an annular shape surrounding the device region DR.

[0050] The isolation dielectric pattern 27b and the sixth upper inter-metal dielectric layer 25 may each include a dielectric material having a dielectric constant and mechanical strength greater than those of the lower inter-metal dielectric layer 10. The density of the sixth upper inter-metal dielectric layer 25 may be greater than the density of the isolation dielectric pattern 27b. For example, the sixth upper inter-metal dielectric layer 25 may include a high density plasma (HDP) oxide, and the isolation dielectric pattern 27b may include tetraethyl orthosilicate (TEOS).

[0051] Since the wiring layer LI includes the lower inter-metal dielectric layer 10 having a low mechanical strength, physical cracks may easily propagate along the lower inter-metal dielectric layer 10 toward the device region DR. In contrast, according to some exemplary embodiments of the present inventive concept, the grooves GR1 and the isolation dielectric pattern 27b and the sixth upper inter-metal dielectric layer 25 located in the grooves GR1 may block or prevent physical cracks from propagating from the edge region ER toward the device region DR.

[0052] When the lower inter-metal dielectric layer 10 includes a porous dielectric material, moisture can be easily introduced into the semiconductor wafer 100. In contrast, according to some exemplary embodiments of the inventive concept, the groove GR1 and the isolation dielectric pattern 27b positioned in the groove GR1 and the sixth upper inter-metal dielectric layer 25 can block or prevent moisture from being introduced into the device region DR from the outermost side (e.g., the cut surface CTS) of the semiconductor wafer 100. Accordingly, the reliability of the semiconductor wafer 100 can be increased.

[0053] The lower sidewall 27_S(2) of the seventh upper inter-metal dielectric layer 27 can be aligned with the sidewalls of the second upper inter-metal dielectric layer 15, the third upper inter-metal dielectric layer 17, the fourth upper inter-metal dielectric layer 19, the fifth upper inter-metal dielectric layer 23, and the sixth upper inter-metal dielectric layer 25. The upper passivation layer 29 can be disposed on the upper dielectric stack UI. The upper passivation layer 29 can have a single-layer or multi-layer structure, which includes at least one selected from silicon oxide, silicon nitride, and SiCN. The upper passivation layer 29 can have sidewalls aligned with the upper sidewall 27_S(1) of the seventh upper inter-metal dielectric layer 27.

[0054] The conductive bump 37 can be coupled to the bonding pad 21p while penetrating the upper passivation layer 29 and the fifth upper inter-metal dielectric layer 23, the sixth upper inter-metal dielectric layer 25, and the seventh upper inter-metal dielectric layer 27. The conductive bump 37 can be disposed in the second hole H2 formed in the fifth upper inter-metal dielectric layer 23, the sixth upper inter-metal dielectric layer 25, and the seventh upper inter-metal dielectric layer 27. The second hole H2 can have a first depth DT1. The first depth DT1 can correspond to the distance between the top surface of the upper passivation layer 29 and the top surface of the bonding pad 21p.

[0055] A portion of the conductive bump 37 can protrude beyond the upper passivation layer 29. The solder layer 39 can be bonded to the conductive bump 37. The bonding pad 21p can include a metal, such as aluminum. The conductive bump 37 can include a metal, such as copper. The solder layer 39 can include at least one selected from, for example, tin, lead, and silver.

[0056] The lower passivation layer 40 can cover the second surface 1b of the substrate 1. The lower passivation layer 40 can have a single-layer or multi-layer structure, which includes at least one selected from, for example, silicon oxide, silicon nitride, and SiCN.

[0057] On the device region DR, the through electrode TSV can penetrate through the device interlayer dielectric layer 3, the substrate 1, and the lower passivation layer 40. The through electrode TSV can be coupled to one of the lower wiring patterns 11. The through dielectric layer TL can be inserted between the through electrode TSV and the substrate 1. The through dielectric layer TL can be, for example, a silicon oxide layer. The lower passivation layer 40 can be provided with a lower bonding pad 46 coupled to the through electrode TSV thereunder. The through electrode TSV can include a metal, such as tungsten or copper. The lower bonding pad 46 can include a metal, such as copper, gold, nickel, or aluminum.

[0058] FIG. 3A is an enlarged view showing the section P1 of FIG. 2A. FIG. 3B is an enlarged view showing the section P2 of FIG. 2A.

[0059] Referring to FIGS. 1, 2A, 3A, and 3B, in the laterally recessed region LRC, the sidewall 27_S of the seventh upper intermetal dielectric layer 27 or the sidewall UI_S of the upper dielectric stack UI can have a relatively smooth surface with relatively small surface roughness. In contrast, the sidewall 3_S of the device interlayer dielectric layer 3 can have a relatively rough surface or relatively large surface roughness. The sidewall 27_S of the seventh upper intermetal dielectric layer 27 or the sidewall UI_S of the upper dielectric stack UI can be formed by an etching process and can thus have relatively small surface roughness, but the sidewall 3_S of the device interlayer dielectric layer 3 can be formed by blade cutting and can thus have relatively large surface roughness.

[0060] The seventh upper intermetal dielectric layer 27 can have a relatively large surface roughness at the sidewall 27_S in a cross-section taken along the line B - B' shown in FIG. 2B, while having a relatively small surface roughness at the sidewall 27_S in a cross-section taken along the line A - A' shown in FIG. 2A.

[0061] For the semiconductor wafer 100 according to some exemplary embodiments of the inventive concept, the metal pattern located at the same horizontal height as the bonding pad 21p may not be exposed on the sidewall UI_S of the upper dielectric stack UI. Therefore, an electrical short circuit caused by metal burrs may not occur when the semiconductor wafer 100 is mounted. Thus, the reliability of the semiconductor package including the semiconductor wafer 100 can be increased.

[0062] FIG. 4 is a plan view showing a wafer. FIGS. 5A to 5K are cross-sectional views showing a method of manufacturing a semiconductor wafer having the cross-section of FIG. 2A. FIGS. 5A to 5K are cross-sectional views taken along the line A - A' of FIG. 4.

[0063] Referring to FIGS. 4 and 5A, a plurality of device regions DR can be configured on a wafer W. Each of the device regions DR can be referred to as a chip region. A saw street region SR can be disposed between the device regions DR. The wafer W can correspond to the substrate 1 of FIG. 5A. A general process can be used to form a device layer DL on the first surface 1a of the substrate 1. The device layer DL and the substrate 1 can be etched to form holes for through electrodes, and through electrodes TSV and through dielectric layers TL can be formed in the holes.

[0064] A general process can be formed to form a wiring layer LI on the device layer DL. The wiring layer LI can include a lower dielectric stack 7, and the lower dielectric stack includes a plurality of lower inter-metal dielectric layers 10 of FIG. 2A. The lower dielectric stack 7 can be provided with a lower wiring pattern 11, a lower via pattern 9, a lower guard ring structure GS1, a lower debris dam structure PS1, a first test pattern 11s, and a first test via pattern 9s therein.

[0065] A first upper inter-metal dielectric layer 13 can be formed on the wiring layer LI. A first upper via pattern 22, a fourth guard ring pattern 12g, a fourth debris dam pattern 12p, and a second test via pattern 12s can be formed to penetrate the first upper inter-metal dielectric layer 13. A sub-pad 14, a fifth guard ring pattern 14g, a fifth debris dam pattern 14p, and a second residual test pattern 14sr can be formed on the first upper inter-metal dielectric layer 13. A plurality of second test patterns 14s can be provided, and the plurality of second test patterns 14s can be arranged in one or more rows on the saw street region SR.

[0066] A second upper inter-metal dielectric layer 15, a third upper inter-metal dielectric layer 17, and a fourth upper inter-metal dielectric layer 19 can be sequentially stacked on the first upper inter-metal dielectric layer 13 to cover the sub-pad 14, the fifth guard ring pattern 14g, the fifth debris dam pattern 14p, and the second residual test pattern 14sr. A second upper via pattern 22 can be formed to penetrate the second upper inter-metal dielectric layer 15, the third upper inter-metal dielectric layer 17, and the fourth upper inter-metal dielectric layer 19. At this stage, a third test via pattern 22s can be formed to penetrate the second upper inter-metal dielectric layer 15, the third upper inter-metal dielectric layer 17, and the fourth upper inter-metal dielectric layer 19. The second upper via pattern 22 can be connected to the sub-pad 14. The third test via pattern 22s can be connected to the second test pattern 14s.

[0067] A metal-containing layer 21 can be formed on the fourth upper inter-metal dielectric layer 19. The metal-containing layer 21 can include, for example, aluminum.

[0068] Referring to FIGS. 5A and 5B, the metal layer 21 containing gold can be etched to form bonding pads 21p on the device region DR and a third test pattern 21s on the edge region ER. The fifth upper inter-metal dielectric layer 23 can be conformally stacked on the fourth upper inter-metal dielectric layer 19 to cover the bonding pads 21p and the third test pattern 21s. A first mask pattern MK1 can be formed on the fifth upper inter-metal dielectric layer 23. The first mask pattern MK1 can be, for example, a photoresist pattern or a spin-on-hardmask (SOH) pattern. The first mask pattern MK1 can have a first opening OP1. The first opening OP1 can overlap the region between the second test pattern 14s and the upper debris dam structure PS2. The first opening OP1 can each have an annular shape surrounding the device region DR.

[0069] Referring to FIGS. 5B and 5C, the first mask pattern MK1 can be used as an etching mask to etch the second upper inter-metal dielectric layer 15, the third upper inter-metal dielectric layer 17, and the fifth upper inter-metal dielectric layer 19, thereby forming a preliminary groove PGR1 that exposes the first upper inter-metal dielectric layer 13. The first mask pattern MK1 can be removed.

[0070] Referring to FIGS. 5C and 5D, the fifth upper inter-metal dielectric layer 23 in which the preliminary groove PGR1 has been formed can be used as an etching mask to etch the lower dielectric stack 7 into a main lower dielectric stack 7m and an edge lower dielectric stack 7e. Therefore, a groove GR1 that exposes the top surface of the device inter-layer dielectric layer 3 can be formed.

[0071] Referring to FIG. 5E, the sixth upper inter-metal dielectric layer 25 can be conformally formed on the fifth upper inter-metal dielectric layer 23 to cover the sidewalls and the bottom surface of the groove GR1. The seventh upper inter-metal dielectric layer 27 can be formed on the sixth upper inter-metal dielectric layer 25 to form a separated dielectric pattern 27b that fills the groove GR1. A planarization process can be performed so that the seventh upper inter-metal dielectric layer 27 has a flat top surface. The upper passivation layer 29 can be formed on the seventh upper inter-metal dielectric layer 27.

[0072] Referring to FIGS. 5E and 5F, a second mask pattern MK2 may be formed on the seventh upper metal interlayer dielectric layer 27. The second mask pattern MK2 may include a second opening OP2 spaced apart from the third test pattern 21s and overlapping with the second test pattern 14s. The second mask pattern MK2 may be used as an etching mask to etch the upper passivation layer 29 and the fourth upper metal interlayer dielectric layer 19, the fifth upper metal interlayer dielectric layer 23, the sixth upper metal interlayer dielectric layer 25, and the seventh upper metal interlayer dielectric layer 27 thereunder to form one or more preliminary holes PH1 exposing the third upper metal interlayer dielectric layer 17. The third upper metal interlayer dielectric layer 17 may act as an etching stop layer.

[0073] Referring to FIGS. 5F and 5G, after removing the second mask pattern MK2, a third mask pattern MK3 may be formed on the seventh upper metal interlayer dielectric layer 27. The third mask pattern MK3 may have a third opening OP3 and a fourth opening OP4. The third opening OP3 may be formed to overlap with the preliminary hole PH1 and each have a width (refer to W2 in FIG. 5I) greater than the width (refer to W1 in FIG. 5I) of the preliminary hole PH1. The third opening OP3 may expose the top surface of the upper passivation layer 29 in the upper portion of the preliminary hole PH1. The fourth opening OP4 may overlap with the bonding pad 21p.

[0074] Referring to FIGS. 5G and 5H, the third mask pattern MK3 may be used as an etching mask to perform an etching process on the upper dielectric stack UI. Accordingly, the second upper metal interlayer dielectric layer 15 and the third upper metal interlayer dielectric layer 17 below the preliminary hole PH1 may be etched to form a first hole H1 exposing the second test pattern 14s. The upper passivation layer 29 and the seventh upper metal interlayer dielectric layer 27 in the upper portion of the preliminary hole PH1 may be etched to form a first trench TR1 overlapping with the preliminary hole PH1 on the first hole H1. The first trench TR1 may be formed to have sidewalls spaced apart from the third test pattern 21s.

[0075] The first hole H1 may have a first width W1 in FIG. 5I. The first trench TR1 may have a second width W2 in FIG. 5I, which is greater than the first width W1. The first trench TR1 and the first hole H1 may form a double-step structure. During the etching process, the upper passivation layer 29 and the fifth upper metal interlayer dielectric layer 23, the sixth upper metal interlayer dielectric layer 25, and the seventh upper metal interlayer dielectric layer 27 on the bonding pad 21p may be etched to form one or more second holes H2 exposing the bonding pad 21p.

[0076] In some exemplary embodiments of the inventive concept, since the preliminary hole PH1 is formed in advance in the 5G step, in the step of FIG. 5H, the etching target thickness of the upper dielectric pattern UI below the preliminary hole PH1 can be the same as or similar to the etching target thickness of the upper dielectric pattern UI on the bonding pad 21p. Accordingly, it is possible to block or prevent over-etching of the second test pattern 14 and / or the upper portion of the bonding pad 21p that is first exposed when forming the first hole H1 and / or the second hole H2.

[0077] When etching the upper passivation layer 29 and the upper dielectric stack UI to form the first hole H1 and the second hole H2 without forming the preliminary hole PH1, the bonding pad 21p may be first exposed because the second hole H2 is relatively deeper than the first hole H1. In this case, the bonding pad 21p may continuously suffer etching damage during the formation of the first hole H1, and thus the etching by-product Al-F compound may be formed by the reaction between the aluminum contained in the bonding pad 21p and the fluorine contained in the etchant used in the etching process. The etching by-products may be difficult to remove in the cleaning process and may induce contamination of the etching chamber to increase the manufacturing cost. In contrast, according to some exemplary embodiments of the inventive concept, such problems can be alleviated or solved by forming the preliminary hole PH1 at positions where relatively large amounts of etching are required.

[0078] Referring to FIGS. 5H and 5I, the third mask pattern MK3 can be removed to expose the top surface of the upper passivation layer 29. A test process or test can be performed through the first hole H1. For example, the probe needles of a probe card can contact the surface of the second test pattern 14s exposed in the first hole H1, and a test signal can be applied to test whether there is an electrical connection between the second test patterns 14s. Although adjacent second test patterns 14s are shown connected to each other via the third test through-hole pattern 22s and the third test pattern 21s, the exemplary embodiments of the inventive concept are not limited thereto and there can be great variations in the connections between the second test patterns 14s. For example, neither the third test through-hole pattern 22s nor the third test pattern 21s can be formed. In this case, some of the first test patterns 11s and some of the first test through-hole patterns 9s can be connected to each other to electrically connect adjacent second test patterns 14s to each other.

[0079] After terminating the test process, a general process can be performed to form the conductive bumps 37 in the second hole H2 and form the solder layer 39 on the conductive bumps 37.

[0080] Referring to FIG. 5J, the second surface 1b of the substrate 1 may be subjected to a back grinding process to expose the bottom surface of the through dielectric layer TL. The second surface 1b of the substrate 1 may be further partially removed to expose the lateral surface of the through dielectric layer TL. The lower passivation layer 40 may be stacked on the second surface 1b of the substrate 1, and then chemical mechanical polishing (CMP) may be performed to expose the bottom surface of the through electrode TSV. The lower bonding pad 46 may be formed to be coupled to the through electrode TSV.

[0081] Referring to FIGS. 5J and 5K, a blade may be used such that a sawing process may be performed to remove the components on the break region BR and separate the individual semiconductor wafers 100 from each other. The sawing process may remove the substrate 1, the device interlayer dielectric layer 3, the edge lower dielectric stack 7e, the first test pattern 11s, the second test pattern 14s, and the third test pattern 21s, the first test via pattern 9s, the second test pattern 12s, and the third test via pattern 22s, the upper dielectric stack UI, and the upper passivation layer 29, all of which are formed on the break region BR. In this step, the first test pattern 11s and the second test pattern 14s may be partially cut to form the first residual test pattern 11sr and the second residual test pattern 14sr. Additionally, the first hole H1 and the first trench TR1 may also be cut to form a stepped region SDR. Thus, the semiconductor wafer 100 as discussed with reference to FIGS. 1 and 2A may be formed. After the sawing process, the dicing street region SR may have a portion other than the break region BR, and the said portion of the dicing street region SR may be the edge region ER of the semiconductor wafer 100.

[0082] In the manufacturing method of some exemplary embodiments of the inventive concept, the third test pattern 21s may not be present on the second test pattern 14s. In addition, as discussed above, the third test pattern 21s may also be omitted. Since the break region BR is not provided or is provided with a small amount of relatively thick third test pattern 21s thereon, it is possible to minimize or prevent the blade teeth from being blocked by the aluminum contained in the third test pattern 21s during the sawing process. When the aluminum is mostly blocked in the blade teeth, sawing defects such as uncut or damaged blades or semiconductor wafers may occur. On the contrary, some exemplary embodiments of the inventive concept can solve such sawing defects.

[0083] The sawing process may cause surface roughness differences as discussed with reference to FIGS. 3A and 3B.

[0084] FIG. 6 is a cross-sectional view taken along line A-A' of FIG. 1.

[0085] Referring to FIG. 6, a semiconductor wafer 101 according to some exemplary embodiments of the present embodiment may have a stepped region SDR at its wafer sidewall 101_S. For example, the top surface 14sr_U of the second residual test pattern 14sr may be stepped relative to the top surface of the upper passivation layer 29, and the sidewall UI_S of the upper dielectric stack UI may be offset from the sidewall 3_S of the device interlayer dielectric layer 3. The sidewalls of the second upper intermetal dielectric layer 15, the third upper intermetal dielectric layer 17, the fourth upper intermetal dielectric layer 19, the fifth upper intermetal dielectric layer 23, the sixth upper intermetal dielectric layer 25, and the seventh upper intermetal dielectric layer 27 may be aligned with each other. Other structural features may be the same as or similar to the structural features discussed above.

[0086] FIG. 7 is a cross-sectional view showing a method of manufacturing the semiconductor wafer of FIG. 6 according to some exemplary embodiments of the present inventive concept.

[0087] Referring to FIG. 7, after forming the preliminary hole PH1 as depicted in FIG. 5F, when removing the second mask pattern MK2 and then forming the third mask pattern MK3 as depicted in FIG. 5G, the third opening OP3 may be formed to completely overlap the preliminary hole PH1. For example, the third opening OP3 may be formed to have the same width as the width of the preliminary hole PH1 and a position that is substantially or completely consistent with the position of the preliminary hole PH1. When the same process as discussed above is subsequently performed, the first trench TR1 of FIG. 5H may not be formed, and a semiconductor wafer 101 having the configuration of FIG. 6 may be formed.

[0088] FIG. 8 is a cross-sectional view taken along line A-A' of FIG. 1.

[0089] Referring to FIG. 8, a semiconductor wafer 102 according to some exemplary embodiments of the present embodiment may have a stepped region SDR at its wafer sidewall 102_S. The stepped region SDR may include a first stepped region SDR(1) and a second stepped region SDR(2). The stepped region SDR may be a double-stepped region.

[0090] The second upper metal interlayer dielectric layer 15 and the third upper metal interlayer dielectric layer 17 may have sidewalls aligned with each other. The fourth upper metal interlayer dielectric layer 19, the fifth upper metal interlayer dielectric layer 23, the sixth upper metal interlayer dielectric layer 25, and the seventh upper metal interlayer dielectric layer 27 may have sidewalls aligned with each other. The second upper metal interlayer dielectric layer 15 may have a sidewall 15_S offset from the sidewall 27_S of the seventh upper metal interlayer dielectric layer 27. Thus, the third upper metal interlayer dielectric layer 17 may have a partially exposed top surface 17_S. The exposed top surface 17_S of the third upper metal interlayer dielectric layer 17 and the top surface of the upper passivation layer 29 may form a step difference to form a first stepped region SDR(1). The exposed top surface 17_S of the third upper metal interlayer dielectric layer 17 may be stepped relative to the top surface 14sr_U of the second residual test pattern 14sr (or relative to the top surface of the first upper metal interlayer dielectric layer 13), and a second stepped region SDR(2) may be formed by the top surface 17_S and the top surface 14sr_U that are stepped relative to each other. The top surface 14sr_U of the second residual test pattern 14sr may be located at a third depth DT3 of the top surface 17_S of the third upper metal interlayer dielectric layer 17. The third depth DT3 may be, for example, about 0.9 times to about 2.0 times the first depth DT1 to be discussed below. Other structural features may be the same as or similar to the structural features discussed above.

[0091] FIGS. 9A to 9C are cross-sectional views showing a method of manufacturing the semiconductor wafer of FIG. 8.

[0092] Referring to FIG. 9A, the second mask pattern MK2 may be removed in the state of FIG. 5F, and a third mask pattern MK3 may be formed. The third mask pattern MK3 may have a third opening OP3 and a fourth opening OP4. The third opening OP3 may have a width smaller than the width of the preliminary hole PH1. A part of the third mask pattern MK3 may be inserted into the preliminary hole PH1 to cover the entire inner sidewall of the preliminary hole PH1 and also cover a part of the bottom surface of the preliminary hole PH1. The third opening OP3 may only expose a part of the bottom surface of the preliminary hole PH1. For example, the area of the top surface 17_S of the third upper metal interlayer dielectric layer 17 exposed to the preliminary hole PH1 may be smaller than the area of the top surface 17_S of the third upper metal interlayer dielectric layer 17 exposed to the third opening OP3.

[0093] Referring to FIG. 9B, the third mask pattern MK3 can be used as an etching mask, such that an etching process can be performed to etch the upper dielectric pattern UI exposed in the third opening OP3 and the fourth opening OP4 and to etch the second upper inter-metal dielectric layer 15 and the third upper inter-metal dielectric layer 17, which can result in the formation of a first hole H1 exposing the second test pattern 14s. During the etching process, the upper passivation layer 29 and the fifth upper inter-metal dielectric layer 23, the sixth upper inter-metal dielectric layer 25, and the seventh upper inter-metal dielectric layer 27 on the bonding pad 21p can be etched to form one or more second holes H2 exposing the bonding pad 21p.

[0094] Referring to FIGS. 9B and 9C, the third mask pattern MK3 can be removed to expose the inner sidewalls of the preliminary hole PH1. In some exemplary embodiments of the present embodiment, the preliminary hole PH1 can be referred to as a first trench TR1. The inner sidewalls of the first trench TR1 and the inner sidewalls of the first hole H1 can form a double-step structure. Other process steps can be the same as or similar to the process steps discussed above.

[0095] FIG. 10 is a cross-sectional view showing a semiconductor package according to some exemplary embodiments of the present inventive concept.

[0096] Referring to FIG. 10, a semiconductor package 1000 according to some exemplary embodiments of the present inventive concept can include a first semiconductor wafer 100a, a second semiconductor wafer 100b, a third semiconductor wafer 100c, a fourth semiconductor wafer 100d, and a fifth semiconductor wafer 100e stacked in sequence. The first semiconductor wafer 100a can have a different type from the second semiconductor wafer 100b to the fifth semiconductor wafer 100e. The first semiconductor wafer 100a can be, for example, a logic circuit wafer. The second semiconductor wafer 100b to the fifth semiconductor wafer 100e can be the same memory wafers. For example, the memory wafers can be DRAM, NAND flash, SRAM, MRAM, or PRAM. This exemplary embodiment discloses a structure in which one logic circuit wafer and four memory wafers are stacked, but the number of logic circuit wafers and the number of memory wafers can be changed differently, but not limited thereto. The first semiconductor wafer 100a can have a width greater than the widths of the second semiconductor wafer 100b to the fifth semiconductor wafer 100e. The semiconductor package 1000 can be a high bandwidth memory (HBM) wafer.

[0097] The first semiconductor wafer 100a can be referred to as or replaced with a package substrate or a redistribution substrate.

[0098] The mold layer MD can cover the top surface of the first semiconductor wafer 100a and the lateral surfaces of the second semiconductor wafer 100b to the fifth semiconductor wafer 100e. The mold layer MD can include a dielectric resin, such as an epoxy molding compound (EMC). The mold layer MD can further include a filler, and the filler can be dispersed in the dielectric resin. The filler can include, for example, silicon dioxide (SiO₂). The mold layer MD can have a top surface coplanar with the second surface 1b of the substrate 1 included in the fifth semiconductor wafer 100e.

[0099] Each of the first semiconductor wafer 100a to the fifth semiconductor wafer 100e can have the same or similar characteristics as one or more of the semiconductor wafers 100 discussed with reference to FIGS. 1 to 3B, the semiconductor wafers 101 discussed with reference to FIG. 6, and the semiconductor wafers 102 discussed with reference to FIG. 8. For example, the semiconductor package 1000 can have a structure in which a plurality of reverse semiconductor wafers 100, semiconductor wafers 101, and / or semiconductor wafers 102 discussed with reference to FIGS. 1 to 3B, FIG. 6, and FIG. 8 are stacked therein. Similar to the semiconductor wafers 100 discussed with reference to FIGS. 1 to 3B, the semiconductor wafers 101 discussed with reference to FIG. 6, and the semiconductor wafers 102 discussed with reference to FIG. 8, each of the first semiconductor wafer 100a to the fifth semiconductor wafer 100e can include a circuit structure CS disposed on the first surface 1a of the substrate 1. For the sake of avoiding repetitive description of the circuit structure CS explained above with reference to FIGS. 1 to 3B, FIG. 6, and FIG. 8, it is omitted. Due to the inversion of the semiconductor wafers 100 discussed with reference to FIGS. 1 to 3B, the semiconductor wafers 101 discussed with reference to FIG. 6, and the semiconductor wafers 102 discussed with reference to FIG. 8, the terms "top / upper" and "bottom / lower" are interchangeable based on the perspective.

[0100] Among the first semiconductor wafer 100a to the fifth semiconductor wafer 100e, the underlying semiconductor wafer can include a lower bonding pad 46 coupled to a solder layer 39 disposed on the overlying semiconductor wafer.

[0101] Each of the first semiconductor wafer 100a to the fifth semiconductor wafer 100e can have a stepped region SDR at its edge region. The stepped regions SDR of the second semiconductor wafer 100b to the fifth semiconductor wafer 100e can be filled with the mold layer MD. The mold layer MD can cover the bottom surface of the second residual test pattern 14sr and the sidewalls of the upper dielectric stack UI.

[0102] The fifth semiconductor wafer 100e at the top position may not include any of the through-hole electrodes TSV and the lower bonding pads 46. Other structural features may be the same as or similar to the structural features discussed above. The redistribution line pattern 35 may be disposed on the top surface of the first semiconductor wafer 100a (or the second surface 1b of the substrate 1) and may be coupled to the solder layer 39 of the second semiconductor wafer 100b.

[0103] Since the semiconductor package 1000 according to some exemplary embodiments of the present invention includes semiconductor wafers 100a to 100e with increased reliability, it is possible to block or prevent electrical short circuits caused by metal burrs and increase the reliability of the semiconductor package 1000.

[0104] According to some exemplary embodiments of the concept of the present invention, the semiconductor wafer and the semiconductor package including the semiconductor wafer may be configured such that the thick metal pattern at the same horizontal height as the bonding pad is not exposed on the sidewall of the upper dielectric stack. Therefore, when the semiconductor wafer is installed, electrical short circuits caused by metal burrs may not occur. Thus, the reliability of the semiconductor wafer and the semiconductor package can be increased.

[0105] In a method of manufacturing a semiconductor wafer according to some exemplary embodiments of the concept of the present invention, since the fracture region is not provided with or is provided with a small number of thick metal patterns at the same horizontal height as the bonding pad, it is possible to block or prevent damage to the blade or the semiconductor wafer and minimize or prevent sawing defects. Additionally, according to a method of manufacturing a semiconductor wafer according to some exemplary embodiments of the concept of the present invention, since the preliminary holes are formed at the positions of layers with different etching target thicknesses, and thus a relatively large amount of etching is required in the regions where the bonding pads can be prevented from being damaged by etching and the etching equipment can be prevented from being contaminated. Therefore, the yield can be increased.

[0106] Although the present invention concept has been described in conjunction with some exemplary embodiments shown in the accompanying drawings, those of ordinary skill in the art should understand that various changes and modifications can be made without departing from the technical spirit and basic features of the present invention concept. It will be obvious to those of ordinary skill in the art that various alternatives, modifications, and changes can be made without departing from the scope and spirit of the present invention concept.

[0107] 1: Substrate 1a: First surface 1b: Second surface 1_S, 3_S, 15_S, 27_S, UI_S: Side Wall 3: Device Interlayer Dielectric 5c: Contact Plug 5g: First Protection Ring Pattern 5p: First Debris Dam 7: Lower Dielectric Stack 7e: Edge Lower Dielectric Stack 7m: Main Lower Dielectric Stack 9: Lower Via Pattern 9g: Third Protection Ring Pattern 9p: Third Debris Dam Pattern 9s: First Test Via Pattern 10: Lower Metal Interconnect Dielectric 11: Lower Wiring Pattern 11g: Second Protection Ring Pattern 11p: Second Debris Dam Pattern 11s: First Test Pattern 11sr: First Residual Test Pattern 12: First Upper Via Pattern 12g: Fourth Protection Ring Pattern 12p: Fourth Debris Dam Pattern 12s: Second Test Via Pattern 13: First Upper Metal Interconnect Dielectric 14: Sub-Pad 14g: Fifth Protection Ring Pattern 14p: Fifth Debris Dam Pattern 14s: Second Test Pattern 14sr: Second Residual Test Pattern 14sr_U, 17_S, 27_U: Top Surface 15: Second Upper Metal Interconnect Dielectric 17: Third Upper Metal Interconnect Dielectric 19: Fourth Upper Metal Interconnect Dielectric 21: Metal-Containing Layer 21p: Bonding Pad 21s: Third Test Pattern 22: Second Upper Via Pattern 22s: Third Test Via Pattern 23: Fifth Upper Metal Interconnect Dielectric 25: Sixth Upper Metal Interconnect Dielectric 27: Seventh Upper Metal Interconnect Dielectric 27b: Separation dielectric pattern 27_M: Intermediate surface 27_S(1): Upper sidewall 27_S(2): Lower sidewall 29: Upper passivation layer 35: Redistribution line pattern 37: Conductive bump 39: Solder layer 40: Lower passivation layer 46: Lower bonding pad 100, 101, 102: Semiconductor wafers 100_S, 101_S, 102_S: Wafer sidewalls 100a: First semiconductor wafer 100b: Second semiconductor wafer 100c: Third semiconductor wafer 100d: Fourth semiconductor wafer 100e: Fifth semiconductor wafer 1000: Semiconductor package A - A', B - B': Lines BR: Fracture zone CS: Circuit structure CTS: Cutting surface DL: Device layer DR: Device area DT1: First depth DT2: Second depth DT3: Third depth ER: Edge area GR1: Groove GS1: Lower protection ring structure GS2: Upper protection ring structure H1: First hole H2: Second hole LI: Wiring layer LRC: Lateral recessed area MD: Mold layer MK1: First mask pattern MK2: Second mask pattern MK3: Third mask pattern OP1: First opening OP2: Second opening OP3: Third opening OP4: Fourth opening P1, P2: Sections PGR1: Preliminary Groove PH1: Preliminary Hole PS1: Lower Debris Dam Structure PS2: Upper Debris Dam Structure SDR: Stepped Area SDR(1): First Stepped Area SDR(2): Second Stepped Area SR: Cutting Track Area T1: Thickness TL: Through-Dielectric Layer TR: Transistor TR1: First Groove TSV: Through-Silicon Via UI: Upper Dielectric Stack W: Wafer W1: First Width W2: Second Width X: First Direction

Claims

1. A semiconductor wafer, comprising: The substrate includes the device area and the edge area; The device layer and wiring layer are stacked sequentially on the substrate; A residual test pattern and sub-pad are located on the wiring layer, the sub-pad is located on the device area, the residual test pattern is located on the edge area, and the sidewalls of the residual test pattern are aligned with the sidewalls of the substrate; an upper dielectric stack covers the sub-pad and the residual test pattern; a bonding pad is located in the upper dielectric stack and connected to the sub-pad; a passivation layer covers the upper dielectric stack; and conductive bumps that penetrate the passivation layer and are coupled to the bonding pad, wherein the upper dielectric stack exposes a portion of the top surface of the residual test pattern, and wherein the sidewalls of the upper dielectric stack have stepped areas.

2. The semiconductor wafer of claim 1, wherein the upper dielectric stack comprises a plurality of upper dielectric layers stacked in sequence, and the uppermost of the upper dielectric layers has the stepped region on its sidewall.

3. The semiconductor wafer of claim 1, wherein the upper dielectric stack comprises a plurality of upper dielectric layers stacked in sequence, and the sidewall of the lowermost of the upper dielectric layers is offset from the sidewall of the uppermost of the upper dielectric layers.

4. The semiconductor wafer of claim 1, wherein the device layer includes an inter-device dielectric layer, the upper dielectric stack includes a plurality of upper dielectric layers stacked in sequence, and the surface roughness at the sidewall of the uppermost of the upper dielectric layers is less than the surface roughness at the sidewall of the inter-device dielectric layer.

5. The semiconductor wafer of claim 1, wherein the wiring layer comprises a lower dielectric stack comprising a plurality of lower dielectric layers, the upper dielectric stack comprising a plurality of upper dielectric layers, each of the lower dielectric layers comprising a dielectric material having a dielectric constant less than that of silicon oxide, and each of the upper dielectric layers comprising a dielectric material having a dielectric constant greater than that of the dielectric material contained in each of the lower dielectric layers.

6. The semiconductor wafer of claim 5, wherein a portion of the upper dielectric layer penetrates the lower dielectric stack over the edge region to divide the lower dielectric stack into a main lower dielectric stack and an edge lower dielectric stack, the main lower dielectric stack covering the device region and a portion of the edge region, and the edge lower dielectric stack covering the remainder of the edge region.

7. The semiconductor wafer as described in claim 6, further comprising: A protective ring structure, located in the main lower dielectric stack, surrounds the device area when viewed in a plan view; A debris dam structure is located in the main lower dielectric stack, and when viewed in the plan view, the debris dam structure surrounds the protective ring structure.

8. The semiconductor wafer as claimed in claim 1, wherein the sub-pad and the residual test pattern are at the same horizontal level and are identical in material and thickness.

9. The semiconductor wafer as described in claim 1, further comprising: A solder layer is coupled to the conductive bump.

10. The semiconductor wafer of claim 1, wherein the upper dielectric stack comprises a plurality of upper dielectric layers stacked in sequence, and the sidewall of the uppermost of the upper dielectric layers has a square wave shape when viewed in a plan view.

11. A semiconductor wafer, comprising: The substrate includes the device area and the edge area; The device layer and wiring layer are stacked sequentially on the substrate; A residual test pattern and sub-pad are located on the wiring layer, the sub-pad is located on the device area, the residual test pattern is located on the edge area, and the sidewalls of the residual test pattern are aligned with the sidewalls of the substrate; an upper dielectric stack covers the sub-pad and the residual test pattern; a passivation layer is located on the upper dielectric stack; a separating dielectric pattern penetrates the wiring layer on the edge area; and a bonding pad is located in the upper dielectric stack and connected to the sub-pad. Conductive bumps penetrate the passivation layer and are coupled to the bonding pad; and a solder layer coupled to the conductive bump, wherein the upper dielectric stack exposes a portion of the top surface of the residual test pattern, wherein the sidewalls of the upper dielectric stack have stepped regions, wherein the top surface of the bonding pad is located at a first depth from the top surface of the passivation layer, wherein the bottom surface of the stepped region is located at a second depth from the top surface of the passivation layer, and wherein the second depth is approximately 0.9 to approximately 2.0 times the first depth.

12. The semiconductor wafer of claim 11, wherein the upper dielectric stack comprises a plurality of upper dielectric layers stacked in sequence, and the uppermost of the upper dielectric layers has the stepped region on its sidewall.

13. The semiconductor wafer of claim 11, wherein the upper dielectric stack comprises a plurality of upper dielectric layers stacked in sequence, and the sidewall of the lowermost of the upper dielectric layers is offset from the sidewall of the uppermost of the upper dielectric layers.

14. The semiconductor wafer of claim 11, wherein the device layer includes an inter-device dielectric layer, the upper dielectric stack includes a plurality of sequentially stacked upper dielectric layers, and the surface roughness at the sidewall of the uppermost of the upper dielectric layers is less than the surface roughness at the sidewall of the inter-device dielectric layer.

15. A semiconductor wafer, comprising: The substrate includes the device area and the edge area; The device layer and wiring layer are stacked sequentially on the substrate; The residual test pattern and sub-pad are located on the wiring layer, the sub-pad is located on the device area, the residual test pattern is located on the edge area, and the sidewall of the residual test pattern is aligned with the sidewall of the substrate; and an upper dielectric stack covering the sub-pad and the residual test pattern, wherein the upper dielectric stack exposes a portion of the top surface of the residual test pattern, wherein the device layer includes an inter-device dielectric layer, wherein the upper dielectric stack includes a plurality of sequentially stacked upper dielectric layers, and wherein the surface roughness at the sidewall of the uppermost of the upper dielectric layers is less than the surface roughness at the sidewall of the inter-device dielectric layer.

16. The semiconductor wafer of claim 15, wherein the sidewall of the residual test pattern is offset from the sidewall of the upper dielectric stack.

17. The semiconductor wafer of claim 15, wherein the sidewalls of the upper dielectric stack have stepped regions.

18. The semiconductor wafer of claim 15, wherein the upper dielectric stack comprises a plurality of upper dielectric layers stacked in sequence, and the sidewall of the uppermost of the upper dielectric layers has a stepped region.

19. The semiconductor wafer of claim 15, wherein the upper dielectric stack comprises a plurality of upper dielectric layers stacked in sequence, and the sidewall of the lowermost of the upper dielectric layers is offset from the sidewall of the uppermost of the upper dielectric layers.

20. The semiconductor wafer of claim 15, wherein the upper dielectric stack comprises a plurality of upper dielectric layers stacked in sequence, and the sidewall of the uppermost of the upper dielectric layers has a square wave shape when viewed in a plan view.

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