Radio frequency impedance matching circuit, method of matching impedance, semiconductor processing tool, and method of fabricating semiconductor

Abstract

In one embodiment, an RF impedance matching circuit is disclosed. The matching circuit includes at least one electronically variable capacitor (EVC). Each EVC includes a plurality of fixed capacitors, each of which has a corresponding switching circuit for switching the fixed capacitor on and off to change the total capacitance of the EVC. Each switching circuit includes a switch operatively coupled to the fixed capacitor to switch the fixed capacitor on and off. The switch includes at least one series of a plurality of PIN or NIP diodes connected in series. For each series, at least one of the diodes in the series has a balancing capacitor connected in parallel with the diode.

Description

[Technical Field]

[0001] This invention relates to a radio frequency impedance matching circuit. [Previous Technology]

[0002] In the manufacture of semiconductor devices (such as microprocessors, memory chips, and other integrated circuits), plasma processes are used at various manufacturing stages. A plasma process involves energizing a gas mixture by introducing RF (radio frequency) energy into the gas molecules. This gas mixture is typically contained within a vacuum chamber (also known as a plasma chamber), and the RF energy is introduced through electrodes or other components within the chamber. In a typical plasma process, an RF generator produces power at the desired RF frequency and power, and this power is transmitted to the plasma chamber via RF cables and networks.

[0003] To provide efficient power transfer from the RF generator to the plasma chamber, an RF matching network is located between the RF generator and the plasma chamber. The purpose of the RF matching network is to convert the plasma impedance to a value suitable for the RF generator. In many cases, especially in semiconductor processes, the RF power is transmitted through a 50 Ohm coaxial cable, and the system impedance (output impedance) of the RF generator is also 50 Ohms. On the other hand, the plasma impedance driven by the RF power varies based on the plasma chemistry and other conditions within the plasma chamber. For maximum power transfer, this impedance must be converted to a reactance-free 50 Ohm (i.e., 50 + j0). The RF matching network performs the function of continuously converting the plasma impedance of the RF generator to 50 Ohms. In most cases, this conversion results in the impedance at the input side of the RF matching network becoming 50 + j0 Ohms, i.e., a purely reactance-free 50 Ohms.

[0004] The RF matching network may include variable capacitors and a microprocessor-based control circuit for controlling these capacitors. The value and size of these variable capacitors are affected by the power handling capability of the plasma chamber, the operating frequency, and the impedance range. The main variable capacitor used in the RF matching network is the vacuum variable capacitor (VVC). The VVC is an electromechanical device consisting of two concentric metal rings that move relative to each other to change capacitance. In complex semiconductor processes where impedance changes are very rapid, rapid and frequent movement can stress the VVC, causing it to fail. VVC-based RF matching networks are one of the final electromechanical components in semiconductor manufacturing processes.

[0005] However, as semiconductor devices shrink and become more complex, feature geometries become extremely small. Consequently, the processing time for manufacturing these features decreases, typically to the range of 5-6 seconds. Current RF matching networks require 1-2 seconds to adjust the process, resulting in significant instability of process parameters for a substantial portion of the process time. Electronic variable capacitor (EVC) technology (see, for example, U.S. Patent No. 7,251,121, which is incorporated herein by reference in its entirety) reduces this semiconductor processing adjustment time from 1-2 seconds to less than 500 microseconds. EVC-based matching networks are a type of solid-state matching network. The reduced adjustment time significantly increases the available stabilization processing time, thereby improving yield and performance.

[0006] Although EVC technology is known, it has not yet been developed into an industry-recognized alternative to VVC. Because EVC is a purely electronic device, it is not a one-to-one replacement for VVC in RF matching networks. Therefore, further advancements are needed to fully utilize EVC as part of RF matching networks. [Summary of the Invention]

[0007] The present invention relates to a radio frequency (RF) impedance matching circuit, the matching circuit comprising an RF input configured to be operatively coupled to an RF source providing an RF signal; an RF output configured to be operatively coupled to a plasma chamber; at least one electronically variable capacitor (EVC), wherein each of the at least one EVC includes a plurality of fixed capacitors, each of the fixed capacitors having a corresponding switching circuit for switching the fixed capacitor on and off to change the total capacitance of the EVC; and a control circuit configured to... The fixed capacitors of each EVC are configured to be switched on and off to enable impedance matching; wherein each switching circuit of each fixed capacitor in each EVC includes a switch operatively coupled to the fixed capacitor to switch the fixed capacitor on and off, the switch including at least one series of multiple diodes connected in series, each of the series-connected diodes being a PIN diode or a NIP diode; wherein for each of the at least one series, at least one of the diodes in the series has a balancing capacitor connected in parallel with the diode.

[0008] In another embodiment, the impedance matching method includes coupling a radio frequency (RF) input of a matching circuit to an RF source providing an RF signal; coupling an RF output of the matching circuit to a plasma chamber, wherein the matching circuit includes at least one electronically variable capacitor (EVC), wherein each of the at least one EVC includes a plurality of fixed capacitors, each of the fixed capacitors having a corresponding switching circuit for switching the fixed capacitor on and off to change a total capacitance of the EVC; and a control circuit configured to switch the fixed capacitors of each EVC on and off to enable impedance matching; wherein Each switching circuit for each fixed capacitor in each EVC includes a switch operatively coupled to the fixed capacitor to turn the fixed capacitor on and off. The switch includes at least one series of multiple diodes connected in series, each of the diodes being a PIN diode or a NIP diode. For each of the at least one series, at least one of the diodes in the series has a balancing capacitor connected in parallel with the diode. The impedance is matched by turning on or off the corresponding fixed capacitor by at least one of the switching circuits of the at least one EVC to change the total capacitance of the EVC.

[0009] In another embodiment, a semiconductor process tool includes a plasma chamber configured to deposit material onto or etch material from a substrate; an impedance matching circuit operatively coupled to the plasma chamber, the matching circuit including an RF input configured operatively coupled to an RF source providing an RF signal; an RF output configured operatively coupled to the plasma chamber; and at least one electronically variable capacitor (EVC), wherein each of the at least one EVC includes a plurality of fixed capacitors, each of the fixed capacitors having a corresponding switching circuit for switching the fixed capacitor on and off. A capacitor is provided to change the total capacitance of the EVC; and a control circuit is configured to switch a fixed capacitor of each EVC on and off to enable impedance matching; wherein each switching circuit of each fixed capacitor in each EVC includes a switch operatively coupled to the fixed capacitor to switch the fixed capacitor on and off, the switch including at least one series of multiple diodes connected in series, each of the series-connected diodes being a PIN diode or a NIP diode; wherein for each of the at least one series, at least one of the diodes in the series has a balancing capacitor connected in parallel with the diode.

[0010] In another embodiment, a method of manufacturing a semiconductor includes placing a substrate in a plasma chamber configured to deposit a material layer on or etch a material layer from the substrate; energizing plasma within the plasma chamber by coupling RF power from an RF source to the plasma chamber to perform deposition or etching; and simultaneously energizing the plasma by performing impedance matching by an impedance matching circuit coupled between the plasma chamber and the RF source, the matching circuit including an RF input configured to be operatively coupled to the RF source; an RF output configured to be operatively coupled to the plasma chamber; and at least one electronically variable capacitor (EVC), wherein each of the at least one EVC includes a plurality of fixed capacitors, the fixed capacitors being... Each capacitor has a corresponding switching circuit for switching the fixed capacitor on and off to change the total capacitance of the EVC; and a control circuit configured to switch the fixed capacitors of each EVC on and off to enable impedance matching; wherein each switching circuit of each fixed capacitor in each EVC includes a switch operably coupled to the fixed capacitor to switch the fixed capacitor on and off, the switch including at least one series of multiple diodes connected in series, each of the series-connected diodes being a PIN diode or a NIP diode; wherein for each of the at least one series, at least one of the diodes in the series has a balancing capacitor connected in parallel with the diode.

[0011] In yet another embodiment, the RF impedance matching circuit includes an RF input configured to be operatively coupled to an RF source providing an RF signal; an RF output configured to be operatively coupled to a plasma chamber; at least one electronically variable capacitor (EVC), wherein each of the at least one EVC includes a plurality of fixed capacitors, each of the fixed capacitors having a corresponding switching circuit for switching the fixed capacitor on and off to change the total capacitance of the EVC; and a control circuit configured to switch the fixed capacitors of each EVC on and off to enable impedance matching; wherein each switching circuit of each fixed capacitor in each EVC includes a switch operatively coupled to the fixed capacitor to switch the fixed capacitor on and off, the switch including at least one series of a plurality of diodes connected in series, each of the series-connected diodes being a PIN diode or a NIP diode; and wherein each of the series-connected diodes is directly located on a non-conductive heat sink.

[0012] In another embodiment, a method for matching impedance includes coupling a radio frequency (RF) input of a matching circuit to an RF source providing an RF signal; coupling the RF output of the matching circuit to a plasma chamber, wherein the matching circuit includes at least one electronically variable capacitor (EVC), wherein each of the at least one EVC includes a plurality of fixed capacitors, each of the fixed capacitors having a corresponding switching circuit for switching the fixed capacitor on and off to change a total capacitance of the EVC; and a control circuit configured to switch the fixed capacitors of each EVC on and off to enable impedance. Matching; wherein each switching circuit of each fixed capacitor in each EVC includes a switch operatively coupled to the fixed capacitor to turn the fixed capacitor on and off, the switch including at least one series of multiple diodes connected in series, each of the series-connected diodes being a PIN diode or a NIP diode; and wherein each of the series-connected diodes is directly positioned on a non-conductive heat sink; and impedance matching is achieved by switching the corresponding fixed capacitor by at least one of the switching circuits in at least one EVC to change the total capacitance of the EVC.

[0013] In another embodiment, a semiconductor process tool includes a plasma chamber configured to deposit material onto or etch material from a substrate; an impedance matching circuit operatively coupled to the plasma chamber, the matching circuit including an RF input configured operatively coupled to an RF source providing an RF signal; an RF output configured operatively coupled to the plasma chamber; and at least one electronically variable capacitor (EVC), wherein each of the at least one EVC includes a plurality of fixed capacitors, each of the fixed capacitors having a corresponding switching circuit for switching on and off. The circuit includes a fixed capacitor disconnected to change the total capacitance of the EVC; and a control circuit configured to switch the fixed capacitors of each EVC on and off to enable impedance matching; wherein each switching circuit of each fixed capacitor in each EVC includes a switch operatively coupled to the fixed capacitor to switch the fixed capacitor on and off, the switch including at least one series of multiple diodes connected in series, each of the series-connected diodes being a PIN diode or a NIP diode; and wherein each of the series-connected diodes is directly mounted on a non-conductive heat sink.

[0014] In another embodiment, a method of manufacturing a semiconductor includes placing a substrate in a plasma chamber configured to deposit a material layer on or etch a material layer from the substrate; energizing plasma within the plasma chamber by coupling radio frequency power from an RF source into the plasma chamber to perform deposition or etching; and simultaneously energizing the plasma by performing impedance matching via an impedance matching circuit coupled between the plasma chamber and the RF source, the matching circuit including at least one electronically variable capacitor (EVC), wherein each of the at least one EVC includes a plurality of fixed capacitors, each of the fixed capacitors having a corresponding open circuit. A switching circuit for switching fixed capacitors to change the total capacitance of the EVC; and a control circuit configured to turn the fixed capacitors of each EVC on and off to enable impedance matching; wherein each switching circuit of each fixed capacitor in each EVC includes a switch operably coupled to the fixed capacitor to turn the fixed capacitor on and off, the switch including at least one series of multiple diodes connected in series, each of the series-connected diodes being a PIN diode or a NIP diode; and wherein each of the series-connected diodes is directly located on a non-conductive heat sink.

Implementation Method

[0016] The following description of preferred embodiments is exemplary in nature and is not intended to limit the invention. The description of the exemplary embodiments is intended to be read in conjunction with the accompanying drawings, which are considered an integral part of the entire written description. In the description of the exemplary embodiments disclosed herein, any reference to direction or orientation is for ease of description only and is not intended to limit the scope of the invention in any way. The discussion herein describes and illustrates some possible non-limiting combinations of features that may exist alone or in other combinations of features. Furthermore, as used herein, the term "or" should be interpreted as a logical operator whose result is true when one or more of its operands are true. Furthermore, as used herein, the phrase "based on" should be interpreted as meaning "at least partially based on," and therefore is not limited to the interpretation of "fully based on."

[0017] The features of this invention can be implemented in software, hardware, firmware, or a combination thereof. The computer program described herein is not limited to any particular embodiment and can be implemented in an operating system, application, foreground or background processing, driver, or any combination thereof. The computer program can execute on a single computer or server processor, or multiple computers or server processors.

[0018] The processor described herein may be any central processing unit (CPU), microprocessor, microcontroller, computing or programmable device or circuit configured to execute computer program instructions (e.g., code). Various processors may be embodied in any suitable type of computer and / or server hardware (e.g., desktop computers, laptops, notebook computers, tablet computers, mobile phones, etc.) and may include all common auxiliary components required to form a functional data processing device, including but not limited to buses, software and data storage (e.g., volatile and non-volatile memory, input / output devices, graphical user interfaces (GUI), removable data storage) and wired and / or wireless communication interface devices including Wi-Fi, Bluetooth, LAN, etc.

[0019] The computer-executable instructions or programs (e.g., software or code) and data described herein are programmable and explicitly embodied in a non-transitory computer-readable medium accessible and recoverable by an individual processor as described herein, and are configured and instructed by executing the instructions encoded in the medium to perform the required functions and processes. A device specifically configured with a programmable processor containing such non-transitory computer-executable instructions or programs may be referred to as a "programmable device" or "device," and multiple programmable devices communicating with each other may be referred to as a "programmable system." It should be noted that the non-transitory "computer-readable medium" described herein may include, but is not limited to, any suitable volatile or non-volatile memory, including random access memory (RAM) and its various types, read-only memory (ROM) and its various types, USB flash memory, or optical data storage devices (e.g., internal / external hard disks, floppy disks, magnetic tape CD-ROMs, DVD-ROMs, optical discs, ZIP™ drives, Blu-ray discs, and others), which can be written to and / or read by a processor operatively connected to the medium.

[0020] In some embodiments, the present invention may be embodied in the form of computer-implemented processes and apparatus, such as processor-based data processing and communication systems or computer systems for performing these processes. The present invention may also be embodied in software or computer code embodied in a non-transitory computer-readable storage medium, wherein, when loaded into and executed by the data processing and communication system or computer system, the computer code segments configure the processor to establish specific logic circuitry configured for performing the processing.

[0021] In the following description of the circuits shown and described, those skilled in the art will understand that, for clarity, not all peripheral circuits or components are shown in the drawings or described in the description. Furthermore, the terms "coupled" and "operably coupled" can refer to direct or indirect coupling between two components in a circuit.

[0022] The following description of preferred embodiments is exemplary in nature and is not intended to limit the invention. The description of the exemplary embodiments is intended to be read in conjunction with the accompanying drawings and is considered an integral part of the entire written description. In the description of the exemplary embodiments disclosed herein, any references to directions or orientations are for convenience of description only and are not intended to limit the scope of the invention in any way. Relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “below,” “over,” “below,” “right,” “left,” “top,” “bottom,” “front,” and “rear,” and their derivatives (e.g., “horizontally,” “downward,” “downward,” etc.) should be interpreted as referring to the directions described subsequently or the directions shown in the figures in the discussion. These relative terms are for convenience of description only and, unless explicitly indicated, do not require the equipment to be constructed or operated in a particular orientation. Unless otherwise explicitly stated, terms such as “attachment,” “addition,” “connection,” “coupling,” “interconnection,” “fixation,” and other similar terms refer to relationships in which structures are directly or indirectly fixed or attached to each other through an intermediary structure, as well as relationships in which they are movable or rigidly attached. The discussion herein describes and illustrates some possible, non-restrictive combinations of features that may exist alone or in other combinations of features. Furthermore, as used herein, the term “or” should be interpreted as a logical operator whose result is true when one or more of its operands are true. Additionally, as used herein, the phrase “based on” should be interpreted as meaning “at least partially based on,” and therefore is not limited to the interpretation of “fully based on.”

[0023] As stated throughout, "range" is used as a shorthand to describe each value within the range. Any numerical value within the range can be chosen as an endpoint value. Furthermore, all references cited herein are incorporated in their entirety. In the event of any conflict between the definitions in this invention and those in the cited references, the definitions in this invention shall prevail. Semiconductor Process System

[0024] Please refer to FIG1, which illustrates a semiconductor device manufacturing system 5 utilizing an RF generator 15. The system 85 includes an RF generator 15 and a semiconductor manufacturing tool 86. The semiconductor manufacturing tool 86 includes a mating network 11 and a plasma chamber 19. In other embodiments, the generator 15 or other power source may be formed as part of the semiconductor manufacturing tool.

[0025] The semiconductor device may be a microprocessor, a memory chip, or other type of integrated circuit or device. A substrate 27 may be placed in the plasma chamber 19, wherein the plasma chamber 19 is configured to deposit a material layer on the substrate 27 or etch a material layer from the substrate 27. Plasma processes involve energizing a gas mixture by introducing RF energy into the gas molecules, thereby energizing the gas mixture. This gas mixture is typically contained in a vacuum chamber (plasma chamber 19), and the RF energy is typically introduced into the plasma chamber 19 via electrodes. Therefore, the plasma can be energized by coupling RF power from an RF source 15 to the plasma chamber 19, thereby performing deposition or etching.

[0026] In a typical plasma process, the RF generator 15 generates power with a radio frequency typically between 3 kHz and 300 GHz, and this power is transmitted to the plasma chamber 19 via RF cables and networks. To provide efficient power conversion from the RF generator 15 to the plasma chamber 19, an intermediate circuit is used to match the fixed impedance of the RF generator 15 with the variable impedance of the plasma chamber 19. Such an intermediate circuit is commonly referred to as an RF impedance matching network, or more simply as an RF matching network. The purpose of the RF matching network 11 is to transform the variable plasma impedance to a value more closely matching the fixed impedance of the RF generator 15. Examples of such matching networks are provided in commonly owned U.S. Patent Publications 2021 / 0183623 and 2021 / 0327684 (the contents of which are incorporated herein by reference in their entirety). Matching Network

[0027] Figure 2 is a block diagram of an embodiment of a semiconductor process system 85 having a process tool 86 including an L-configuration RF impedance matching network 11. As will be discussed in further detail below, this example matching network 11 utilizes an electronically variable capacitor (EVC) for both the shunt variable capacitor 33 and the series variable capacitor 31. It should be noted that the invention is not so limited. For example, one of the EVCs (e.g., the shunt EVC 33) may be a mechanically variable VVC, or may be replaced by a variable inductor.

[0028] This example matching network 11 has an RF input 13 connected to an RF source 15 and an RF output 17 connected to a plasma chamber 19. An RF input sensor 21 may be connected between the RF impedance matching network 11 and the RF source 15. An RF output sensor 49 may be connected between the RF impedance matching network 11 and the plasma chamber 19, thus monitoring the RF output from the impedance matching network and the plasma impedance presented by the plasma chamber 19. Some embodiments may include only one of the input sensor 21 and the output sensor 49. The function of these sensors 21 and 49 is described in more detail below.

[0029] As discussed above, the RF impedance matching network 11 helps to maximize the amount of RF power transferred from the RF source 15 to the plasma chamber 19 by matching the impedance at the RF input 13 with the fixed impedance of the RF source 15. The matching network 11 may consist of a single module in a single housing, and the single housing is designed for electrical connection to the RF source 15 and the plasma chamber 19. In other embodiments, the components of the matching network 11 may be located in different housings, some components may be located outside the housing, and / or some components may share a housing with a component outside the matching network.

[0030] As known in the art, plasma within a plasma chamber 19 typically experiences fluctuations beyond operational control, thus the impedance presented by the plasma chamber 19 is a variable impedance. Since this variable impedance of the plasma chamber 19 cannot be fully controlled, an impedance matching network can be used to establish impedance matching between the plasma chamber 19 and the RF source 15. Additionally, the impedance of the RF source 15 can be fixed at a set value by the design of the specific RF source 15. Although the fixed impedance of an RF source 15 may experience slight fluctuations during use due to factors such as heat or other environmental changes, because these fluctuations do not significantly change the original set impedance value of the fixed impedance, the impedance of the RF source 15 is still considered a fixed impedance for impedance matching purposes. Other types of RF sources 15 can be designed such that the impedance of the RF source 15 can be set during or after use. The impedance of this type of RF source 15 is still considered fixed because it can be controlled by a user (or at least by a programmable controller), and the set value of the impedance can be known at any time during operation, thus making the set value effectively a fixed impedance.

[0031] The RF source 15 may be an RF generator of a type well known in the art, and generate an RF signal with appropriate frequency and power for use in the process performed within the plasma chamber 19. The RF source 15 may be electrically connected to the RF input 13 of the RF impedance matching network 11 via a coaxial cable, which has the same fixed impedance as the RF source 15 for impedance matching purposes.

[0032] The plasma chamber 19 includes a first electrode 23 and a second electrode 25, and in a process well known in the art, the first and second electrodes 23, 25, combined with a suitable control system (not shown) and the plasma in the plasma chamber, enable one or both of depositing material on a substrate 27 and etching material from the substrate 27.

[0033] In an exemplary embodiment, the RF impedance matching network 11 includes a series variable capacitor 31, a shunt variable capacitor 33, and a series inductor 35 to form an "L"-shaped matching network. The shunt variable capacitor 33 is shown connected in parallel to a reference potential between the series variable capacitor 31 and the series inductor 35, which in this case is ground 40, and those skilled in the art will understand that the RF impedance matching network 11 can be configured with the shunt variable capacitor 33 connected in parallel to the reference potential at the RF input 13 or the RF output 17.

[0034] Alternatively, the RF impedance matching network 11 can be configured with other matching network configurations, such as a "T" type configuration or a "π" or "pi" type configuration, as shown in FIG3. In some embodiments, the variable capacitor and switching circuit described below may be included in any configuration suitable for an RF impedance matching network.

[0035] In an exemplary embodiment, each of the series variable capacitor 31 and the shunt variable capacitor 33 may be an electronic variable capacitor (EVC), as described in U.S. Patent No. 7,251,121, which is effectively formed as a capacitor array consisting of a plurality of discrete capacitors. The series variable capacitor 31 is connected in series between the RF input 13 and the RF output 17 (and is also connected in parallel between the RF source 15 and the plasma chamber 19). The shunt variable capacitor 33 is connected in parallel between the RF input 13 and ground 40. In other configurations, the shunt variable capacitor 33 may be connected in parallel between the RF output 19 and ground 40. Other configurations that do not deviate from the RF matching network functionality may also be implemented. In yet another configuration, the shunt variable capacitor 33 may be connected in parallel between a reference potential and one of the RF input 13 and the RF output 19.

[0036] The series variable capacitor 31 is connected to a series RF choke and filter circuit 37 and a series drive circuit 39. Similarly, the shunt variable capacitor 33 is connected to a shunt RF choke and filter circuit 41 and a shunt drive circuit 43. Each of the series and shunt drive circuits 39 and 43 is connected to a control circuit 45, which is configured with a suitable processor and / or signal generation circuit to provide an input signal for controlling the series and shunt drive circuits 39 and 43. A power supply 47 is connected to each of the RF input sensor 21, the series drive circuit 39, the shunt drive circuit 43, and the control circuit 45 to provide operating power with designed current and voltage to each of these components. The voltage level provided by the power supply 47, and therefore the voltage level used by the RF input sensor 21, the series drive circuit 39, the shunt drive circuit 43, and the control circuit 45 to perform their respective specified tasks, is determined by design. In other embodiments, various electronic components may be used to enable the control circuit 45 to send commands to the variable capacitors. Furthermore, while the drive circuit, RF choke, and filter system are shown as separate from the control circuit 45, these components can also be considered as forming part of the control circuit 45.

[0037] In an example embodiment, the control circuit 45 includes a processor. The processor can be any type of properly programmed processing device (or a collection of two or more processing devices working together), such as a computer or microprocessor configured to execute computer program instructions (e.g., code). The processor can be embodied in any suitable type of computer and / or server hardware (e.g., desktop computers, laptops, notebook computers, tablets, mobile phones, etc.) and can include all common auxiliary components required to form a functional data processing device, including but not limited to a bus, software and data storage (such as volatile and non-volatile memory, input / output devices, graphical user interfaces (GUIs), removable data storage), and wired and / or wireless communication interface devices including Wi-Fi, Bluetooth, LAN, etc. The processor in this example embodiment is configured using a specific algorithm to enable the matching network to perform the functions described herein.

[0038] By combining the series variable capacitor 31 and the shunt variable capacitor 33, the combined impedance of the RF impedance matching network 11 and the plasma chamber 19 can be controlled by the control circuit 45, the series drive circuit 39 and the shunt drive circuit 43 to match or at least substantially match the fixed impedance of the RF source 15.

[0039] The control circuit 45 is the central hub of the RF impedance matching network 11, as it receives multiple inputs from sources such as the RF input sensor 21 and series and shunt variable capacitors 31, 33, performs necessary calculations to determine the changes in the series and shunt variable capacitors 31, 33, and transmits commands to the series and shunt variable capacitors 31, 33 to establish impedance matching. This control circuit 45 is a type of control circuit commonly used in semiconductor manufacturing processes and is therefore known to those skilled in the art. Any difference in this control circuit 45 compared to prior art control circuits occurs in the programming differences, enabling the RF impedance matching network 11 to perform the switching and impedance matching of the variable capacitors 31, 33 at a certain speed.

[0040] Each of the series and shunt RF chokes and filter circuits 37, 41 is configured to allow DC signals to pass between the series and shunt drive circuits 39, 43 and the respective series and shunt variable capacitors 31, 33, while simultaneously blocking the RF signal from the RF source 15, thereby preventing the RF signal from leaking to the outputs of the series and shunt drive circuits 39, 43 and the output of the control circuit 45. The series and shunt RF chokes and filter circuits 37, 41 are of a type known to those skilled in the art.

[0041] Figure 3 is a block diagram of an embodiment of a semiconductor process system 85A with a pi configuration matching network 11A, which is the opposite of the L configuration matching network in Figure 2. For ease of understanding, the RF choke and filter, drive circuit and power supply of Figure 2 are omitted in this figure. With the same reference values ​​as in Figure 2 used in Figure 3, it is understood that the relevant components may have features similar to those discussed in Figure 2.

[0042] The most obvious difference between the L and pi configurations is that the L configuration uses a series capacitor 31 and a shunt capacitor 33, while the pi configuration uses two shunt capacitors 31A and 33A. However, the control circuit can change the capacitance of these shunt variable capacitors 31A and 33A to achieve impedance matching. As discussed earlier, each of these shunt variable capacitors 31A and 33A can be an EVC. It can be controlled by a choke, filter, and driver, similar to the method discussed earlier with respect to Figure 2. EVC capacitor array

[0043] Figure 4 is a block diagram of an embodiment of an electronic circuit 150 for providing variable capacitance using an electronic variable capacitor 151. The circuit 150 utilizes an EVC 151 comprising two capacitor arrays 151a and 151b. In this example, the first capacitor array 151a has a first plurality of discrete fixed capacitors, each having a first capacitance value. The second capacitor array 151b has a second plurality of discrete fixed capacitors, each having a second capacitance value. The first capacitance value differs from the second capacitance value, allowing the EVC 151 to provide coarse and fine control over the capacitance generated by the EVC 151. The first and second capacitor arrays are coupled in parallel between a signal input 113 and a signal output 130.

[0044] The first and second capacitance values ​​can be any values ​​sufficient to provide the required total capacitance value for the EVC 151. In one embodiment, the second capacitance value is less than or equal to half (1 / 2) of the first capacitance value. In another embodiment, the second capacitance value is less than or equal to one-third (1 / 3) of the first capacitance value. In yet another embodiment, the second capacitance value is less than or equal to one-quarter (1 / 4) of the first capacitance value.

[0045] The electronic circuit 150 further includes a control circuit 145, which may have features similar to those of the control circuit 45 described above. The control circuit 145 is operatively coupled to the first capacitor array 151a and the second capacitor array 151b via a command input 129, and the command input 129 is operatively coupled to the first capacitor array 151a and the second capacitor array 151b. In an example embodiment, the command input 129 has a direct electrical connection to the capacitor arrays 151a and 151b, but in other embodiments, this connection may be indirect. The coupling of the control circuit 145 to the capacitor arrays 151a and 151b will be discussed in further detail below.

[0046] The control circuit 145 is configured to change the variable capacitance of the EVC 151 by controlling (a) the on and off states of each of the first plurality of discrete fixed capacitors and (b) the second plurality of discrete fixed capacitors. As described above, the control circuit 145 may have features similar to those of the control circuit 45 in the foregoing figures. For example, the control circuit 145 may receive input from the capacitor arrays 151a and 151b, perform calculations to determine changes to the capacitor arrays 151a and 151b, and transmit commands to the capacitor arrays 151a and 151b to change the capacitance of the EVC 151. The EVC 151 of FIG4 may include a plurality of electronic switches. Each electronic switch may be configured to actuate and deactivate one or more discrete capacitors.

[0047] As with the control circuit 45 in the foregoing figures, the control circuit 145 can also be connected to a drive circuit 139 and an RF choke and filter circuit 137. The control circuit 145, the drive circuit 139, and the RF choke and filter circuit 137 can have capabilities similar to those discussed in the foregoing figures. In an example embodiment, the drive circuit 139 is operatively coupled between the control circuit 145 and the first and second capacitor arrays 151a, 151b. The drive circuit 139 is configured to change the variable capacitance based on a control signal received from the control circuit 145. The RF filter 137 is operatively coupled between the drive circuit 139 and the first and second capacitor arrays 151a, 151b. In response to the control signal sent by the control unit 145, the drive circuit 139 and the RF filter 137 are configured to send a command signal to the command input 129. The command signal is configured to change the variable capacitance by instructing at least one of the electronic switches to activate or deactivate (a) at least one of the first plurality of discrete capacitors or (b) at least one of the second plurality of discrete capacitors.

[0048] In an example embodiment, the drive circuit 139 is configured to turn a high-voltage source on and off in less than 15 microseconds, wherein the high-voltage source controls the electronic switches of each of the first and second capacitor arrays to change the variable capacitance. However, the EVC 151 can be switched using any of the components or speeds discussed in this application.

[0049] The control circuit 145 is configured to calculate coarse and fine adjustment capacitance values ​​provided by the respective capacitor arrays 151a and 151b. In an example embodiment, the control circuit 145 is configured to calculate a coarse adjustment capacitance value to be provided by controlling the on and off states of the first capacitor array 151a. Furthermore, the control circuit is configured to calculate a fine adjustment capacitance value to be provided by controlling the on and off states of the second capacitor array 151b. In other embodiments, the capacitor arrays 151a and 151b may provide capacitance at alternative levels. In other embodiments, the EVC may utilize additional capacitor arrays.

[0050] The EVC 151 in Figure 4 can be used in various systems requiring a variable capacitance. For example, the EVC 151 can be used as a series EVC and / or a shunt EVC in an L-matching network or as one or both of a shunt EVC in a pi-matching network. It is generally desirable that the difference between these capacitance values ​​allows for a sufficiently fine resolution of the total capacitance of the circuit and a wide range of capacitance values ​​to achieve better impedance matching at the input of an RF matching network, and the EVC 151 allows for this. Switching discrete capacitors on and off changes the EVC capacitance.

[0051] As discussed above, an EVC is a type of variable capacitor that can use multiple switches, each switch for establishing an open or short circuit, and each has an individual series capacitor to change the capacitance of the variable capacitor. These switches can be mechanical (such as relays) or solid-state (such as PIN diodes, transistors, or other switching devices). The following is a discussion of methods for configuring an EVC or other variable capacitor to provide varying capacitance.

[0052] In a “cumulative setting” sometimes referred to as an EVC or other variable capacitor, the capacitor value is linearly increased from a minimum starting point (all switches are on) by gradually increasing the number of trimmer capacitors connected to the circuit. Once the maximum number of trimmer capacitors is connected to the circuit, a coarse-adjustment capacitor is turned on, and the trimmer capacitors are turned off. This procedure begins by increasing the number of trimmer capacitors connected to the circuit until all trimmer and coarse-adjustment capacitors are turned on, at which point another coarse-adjustment capacitor is turned on and the trimmer capacitors are turned off. This procedure can continue until all coarse-adjustment and trimmer capacitors are turned on.

[0053] In this embodiment, all fine-tuning capacitors have the same or substantially similar values, and all coarse-tuning capacitors have the same or substantially similar values. Furthermore, the capacitance value of a coarse-tuning capacitor is approximately equal to the combined capacitance value of all fine-tuning capacitors plus one additional fine-tuning capacitor connected to the circuit, thus achieving a linear increase in capacitance. However, these embodiments are not so limited. The fine-tuning capacitors (and coarse-tuning capacitors) do not need to have the same or substantially similar values. Furthermore, the capacitance value of a coarse-tuning capacitor does not need to be equal to the combined capacitance value of all fine-tuning capacitors plus one additional fine-tuning capacitor. In one embodiment, the coarse-tuning capacitance value and the fine-tuning capacitance value have a ratio substantially similar to 10:1. In another embodiment, the second capacitance value is less than or equal to half (1 / 2) of the first capacitance value. In another embodiment, the second capacitance value is less than or equal to one-third (1 / 3) of the first capacitance value. In yet another embodiment, the second capacitance value is less than or equal to one-quarter (1 / 4) of the first capacitance value.

[0054] An example of the aforementioned embodiment in an ideal setting is that the fine-tuning capacitors are equal to 1 pF and the coarse-tuning capacitors are equal to 10 pF. In this ideal setting, when all switches are off, the capacitance is 0 pF. When the first switch is off, there is 1 pF in the circuit. When the second switch is off, there is 2 pF in the circuit, and so on, until all nine fine-tuning switches are off, providing 9 pF. Then, the first 10 pF capacitor is connected to the circuit and the nine fine-tuning switches are turned on to provide a total capacitance of 10 pF. The fine-tuning capacitors are then connected to the circuit to provide capacitances from 11 pF to 19 pF. Then, another coarse-tuning capacitor is connected to the circuit, and all fine-tuning capacitors can be disconnected from the circuit to provide 20 pF. This procedure can be repeated until the desired capacitance is achieved.

[0055] This can be taken further. Using the previous example with nine 1 pF capacitors and nine 10 pF capacitors, the variable capacitor circuit can have even larger values, such as 100 pF, to turn the circuit on and off. This would allow the previous capacitor array to go up to 99 pF, and then the 100 pF capacitor could be used for the next increment. This can be repeated further with larger increments and can also be used in conjunction with any counting system. According to this accumulation setting, increasing the total capacitance of a variable capacitor can be achieved by turning on more coarse adjustment capacitors or more fine adjustment capacitors than already turned on, without turning off the already turned-on coarse adjustment capacitors. Furthermore, when the total variable capacitance increases and the control circuit does not turn on more coarse adjustment capacitors than already turned on, the control circuit turns on more fine adjustment capacitors than already turned on. U.S. Patent Nos. 10,431,428 and 11,195,698 concerning accumulation settings are incorporated herein by reference in their entirety. It should be noted that the claimed invention is not limited to the use of this accumulation setting. For example, U.S. Patent Nos. 10,679,824 and 10,692,699, which are incorporated herein by reference in their entirety, are for the purpose of discussing alternative settings, such as "partial binary".

[0056] Figure 5 is a schematic diagram of a variable capacitor system 155 for switching on and off an electronic variable capacitor with a fixed capacitor. While using reference element numbers similar to those in Figure 4 in this figure, it should be understood that the relevant components may have features similar to those discussed in Figure 4. The variable capacitor system 155 includes a variable capacitor 151 for providing varying capacitance. The variable capacitor 151 has an input 113 and an output 130. The variable capacitor 151 includes a plurality of discrete fixed capacitors 153 operably coupled in parallel. The plurality of capacitors 153 includes a first (fine-tuning) capacitor 151a and a second (coarse-tuning) capacitor 151B. Furthermore, the variable capacitor 151 includes a plurality of switches 161. In the switches 161, an on / off relationship is operably coupled in series to each of the plurality of capacitors to switch on and off each capacitor, thereby allowing the variable capacitor 151 to provide varying total capacitance. The variable capacitor 151 has a variable total capacitance that increases when the discrete capacitor 153 is turned on and decreases when the discrete capacitor 153 is turned off.

[0057] The switches 161 may be coupled to a switch drive circuit 139 for driving the switches to turn on and off. The variable capacitor system 155 may further include a control unit 145 operatively coupled to the variable capacitor 151. Specifically, the control unit 145 is operatively coupled to the drive circuit 139 for instructing the drive circuit 139 to turn on one or more of the switches 161, thereby turning on or off one or more of the capacitors 153. In one embodiment, the control unit 145 may form part of a control unit for controlling the variable capacitor, such as a control unit that instructs the variable capacitors of a matching network to change capacitance to achieve impedance matching. The drive circuit 139 and the control unit 145 may have similar features to those discussed above with reference to FIG. 4, and therefore may also utilize an RF choke and filter as discussed above. Switching circuit for electronic variable capacitor

[0058] Figure 6 shows an embodiment of a switching circuit 140A for a matching network according to one embodiment. In the example embodiment, the EVC 151 is the EVC 151 of Figure 5, but the EVC of the present invention is not so limited, as it may have any alternative features discussed herein, including different numbers of discrete fixed capacitors 153, and discrete fixed capacitors with different values ​​than those discussed in Figure 5. Furthermore, the EVC may form part of any type of matching network, including the various types of matching networks discussed herein. An example matching network is coupled between an RF source and a plasma chamber, for example, as shown in the foregoing figures.

[0059] The example EVC includes a plurality of discrete fixed capacitors 153A, 153B coupled to a first terminal 113. Each discrete capacitor 153A, 153B has a corresponding switch 161A, 161B configured to turn the discrete capacitor on and off to change the total capacitance of the EVC 151. In the example embodiment, the switch 161A is connected in series with the discrete capacitor 153A, but the invention is not so limited. Furthermore, in the example embodiment, the switch 161A is a PIN diode, but the invention is not so limited and may be another type of switch such as a NIP diode. In yet another embodiment, the switch may be a MOSFET, a JFET, or other type of switch. Furthermore, in the example embodiment, the PIN diodes have a common anode configuration such that the anodes of each PIN diode 161A, 161B are coupled to a ground 40, which can be any common node. However, the invention is not so limited, as in other embodiments, the EVC can use a common cathode configuration such that the cathodes of each PIN diode are coupled to the ground 40 (and the components of the drive circuit are changed accordingly). Furthermore, it should be noted that two or more switches can be used in series to increase the voltage rating and / or two or more switches can be used in parallel to increase the current rating of the channel.

[0060] Each PIN diode switch 161A, 161B has its own switching circuit 140A, 140B, which is connected to a control circuit 145. The switching circuit 140B is shown as including switch 161B, filter 141B (which may be similar to the filter circuits 37, 41 described above), and drive circuit 139B. Filter 141B may be, for example, an LC circuit, similar to filter circuit 9 of U.S. Patent No. 10,340,879 or the filter circuit next to output 207 of FIG. 6A of U.S. Patent No. 9,844,127. Each of these patents is incorporated herein by reference in its entirety.

[0061] Example switch circuit 140A has the same components as switch circuit 140B, but the drive circuit 139A is shown in more detail. The drive circuit 139A can be integrated with the PIN diode 161A (or other type of switch), or with the discrete fixed capacitors of the EVC in the matching network. Those skilled in the art will also appreciate that some components of the drive circuit 139A can be replaced with other components that perform the same necessary functions, while also allowing for greater variability in other circuit parameters (e.g., voltage range, current range, and the like).

[0062] This example drive circuit 139A has two inputs 105A-1 and 105A-2 for receiving control signals from the control circuit to control the voltage on the common output 107A connected to and driving the PIN diode 161A. The voltage on the common output 107A causes the PIN diode 161A to switch between an on state and an off state, thus also turning on / off and off / off the discrete capacitor 153A connected to the PIN diode 161A. In this exemplary embodiment, the state of the discrete capacitor follows the state of the corresponding PIN diode, such that when the PIN diode is on, the discrete capacitor is also on / off, and similarly, when the PIN diode 161A is off, the discrete capacitor is also off / off. Therefore, the description of the state of the PIN diode 161A herein essentially describes the accompanying state of the corresponding discrete capacitor 153A of the EVC 151.

[0063] In a preferred embodiment, each of the first power switch 111A and the second power switch 113A is a MOSFET with a body diode; however, in other embodiments, either of these power switches may be another type of switch, including any other type of semiconductor switch. The present invention can utilize various switching circuit configurations. For example, the present invention can utilize any of the switching circuits disclosed in U.S. Patent Application No. 9,844,127, such as those shown in Figures 3, 6A, and 6B; and any of the switching circuits disclosed in U.S. Patent Application No. 10,340,879, such as the switching circuit shown in Figure 18. As stated above, these patents are incorporated herein by reference in their entirety.

[0064] In an example embodiment, a high-voltage power supply 115A is connected to the first power switch 111A to provide a high-voltage input, and this high-voltage input is switchable to the common output 107A. A low-voltage power supply 117A is connected to the second power switch 113A to provide a low-voltage input, and this low-voltage input is also switchable to the common output 107A. In the configuration of the illustrated drive circuit 139A, the low-voltage power supply 117A can supply a low-voltage input of approximately -3.3V. This negative low voltage is sufficient to provide a forward bias for switching the PIN diode 161A. For other configurations of the drive circuit 139A, a higher or lower voltage input can be used, and the low-voltage input can have a positive polarity, depending on the configuration and type of the controlled electronic switch.

[0065] In this example switching circuit 140A, the first power switch 111A and the second power switch 113A are configured to connect the high-voltage power supply 115A and the low-voltage power supply 117A asynchronously to the common output 107A to switch the PIN diode 161A between an on and off state, thereby turning on and off the corresponding discrete capacitor 153A. The high-voltage power supply 115A provides a reverse-biased DC voltage to the PIN diode switch 161A. This may be referred to as the "cutoff voltage" because it reverse-biases the PIN diode 161A and thus prevents current flow, thereby turning off its corresponding discrete capacitor 153A. As used herein, the term "cutoff voltage" will refer to any voltage used to turn a switch off or on its corresponding discrete capacitor. It should be further noted that the switching circuit is not limited to the switching circuit shown in FIG6, but may be any circuit for switching on and off discrete capacitors, including that disclosed in U.S. Patent No. 9,844,127, which is incorporated herein by reference in its entirety.

[0066] In an example embodiment, the control circuit provides separate control signals to separate the inputs 105A-1 and 105A-2 of the drive circuit 139A. In this embodiment, the separate inputs 105A-1 and 105A-2 are coupled to the first and second power switches 111A and 113A, respectively. The control signals supplied to the separate inputs may be of opposite polarities. In a preferred embodiment, the first and second power switches 161A and 113A are MOSFETs, and the separate control signals are directed to separate drivers to power the MOSFETs. In an alternative embodiment, the control circuit 145 provides a common input signal. The common input signal can asynchronously control the ON and OFF states of the first power switch 111A and the second power switch 113A, such that when the first power switch 111A is in the ON state, the second power switch 113A is in the OFF state, and similarly, when the first power switch is in the OFF state, the second power switch 113A is in the ON state. Thus, the common input signal controls the first power switch 111A and the second power switch 113A, and asynchronously connects the high-voltage input and the low-voltage input to the common output for switching the PIN diode 161A between the ON and OFF states. However, the present invention is not limited to this asynchronous control.

[0067] The inputs 105A-1 and 105A-2 can be configured to receive any type of suitable control signal for the selected switch type of the first power switch 111A and the second power switch 113A, which may be, for example, a +15V control signal. In a preferred embodiment, the drive circuit has a separate driver for driving each of the first power switch 111A and the second power switch 112A. In another embodiment, the first and second power switches 111A and 113A are selected such that they can receive a common input signal.

[0068] In one exemplary embodiment, a power supply 118 is coupled to the input of a low-voltage power supply 117A. In a preferred embodiment, the power supply 118 provides 24VDC. However, the invention is not so limited and other power supplies may be used.

[0069] In an example embodiment, when the second power switch 113A is on, a current 163A flows between the PIN diode 161A and the low-voltage power supply 117A. Simultaneously, current flows from the power supply 118 to the input of the low-voltage power supply 117A and to the ground 40. A sensor may be located at a node of the switching circuit 140A to measure a parameter associated with the current 163A flowing between the low-voltage power supply 117A and the PIN diode switch 161A. In an example embodiment, a sensor 164A is located at an input of the low-voltage power supply 117A and measures the current 167A flowing into that input from the power supply 118 (which is associated with the current 163A). In other embodiments, the sensor may be located at other locations within the switching circuit 140A, such as at node 165A (the output of the low-voltage power supply) or node 166A (the anode of PIN diode 161A), or in the path of the filter 141A between the drive circuit and the switch (e.g., the driver output 107A or the output of the filter 141A). In an exemplary embodiment, the parameter is the current value flowing at the node, but in other embodiments, the measured parameter may be any parameter (including voltage) associated with the current flowing through the switch or such switches. In yet another embodiment, the parameter may be any parameter associated with the drive circuit.

[0070] It should be noted that the matching network discussed herein can be combined with a bias circuit, such as the bias circuit discussed in patent application PCT / US22 / 23395 filed on April 5, 2022, which is incorporated herein by reference in its entirety. For example, the bias inductor of the bias circuit can be used to switch the fixed discrete capacitor of the EVC in series, which is not grounded. The capacitance value is determined to achieve matching.

[0071] Figure 7 is a flowchart illustrating a procedure 500A for impedance matching according to one embodiment. The matching network may include elements similar to those described above. In one embodiment, the matching network of Figure 3 is utilized. In the first step of the example procedure 500A of Figure 7, the input impedance at RF input 13 is determined (step 501A). The input impedance is based on the RF input parameters detected at RF input 13 by RF input sensor 21. The RF input sensor 21 may be any sensor configured to detect one of the RF input parameters at RF input 13. The input parameter may be any parameter measurable at RF input 13, including a voltage, a current, or a phase at RF input 13. In the example embodiment, the RF input sensor 21 detects voltage, current, and phase at the RF input 13 of the matching network 11. Based on the RF input parameters detected by the RF input sensor 21, the control circuit 45 determines the input impedance.

[0072] Next, the control circuit 45 determines the plasma impedance presented by the plasma chamber 19 (step 502A). In one embodiment, the plasma impedance determination is based on the input impedance (determined in step 501A), the capacitance of the series EVC 31, and the capacitance of the shunt EVC 33. In other embodiments, the plasma impedance determination can be made using an output sensor 49 operatively coupled to the RF output, wherein the RF output sensor 49 is configured to detect an RF output parameter. The RF output parameter can be any parameter measurable at the RF output 17, including a voltage, a current, or a phase at the RF output 17. The RF output sensor 49 can detect the output parameter at the RF output 17 of the matching network 11. Based on the RF output parameter detected by the RF output sensor 21, the control circuit 45 can determine the plasma impedance. In yet another embodiment, the plasma impedance determination can be based on both the RF output parameter and the RF input parameter.

[0073] Once the variable impedance of the plasma chamber 19 is known, the control circuit 45 can determine the modification of the variable capacitance of one or both of the series and shunt EVCs 31, 33 to achieve impedance matching. Specifically, the control circuit 45 determines a first capacitance value for the series variable capacitor and a second capacitance value for the shunt variable capacitor (step 503A). These values ​​represent new capacitance values ​​for the series EVC 31 and the shunt EVC 33 to achieve impedance matching or at least a substantial impedance matching. In an example embodiment, the determination of these first and second capacitance values ​​is based on the variable plasma impedance (determined in step 502A) and the fixed RF source impedance.

[0074] Once the first and second capacitor values ​​are determined, the control circuit 45 generates a control signal to change at least one of the series variable capacitor and the shunt variable capacitor to the first capacitor value and the second capacitor value, respectively (step 504A). This process takes approximately t = -5 microseconds. The control signal instructs the switching circuit to change the variable capacitor of one or both of the series and shunt EVCs 31 and 33.

[0075] In the example embodiment, the EVCs change while the RF source continues to provide the RF signal to the RF input of the matching network. There is no need to stop providing the RF signal before changing the EVCs. The determination of the new capacitance value and the change of the EVCs can be performed continuously (and repeatedly), while the RF signal is continuously provided to the matching network.

[0076] Compared to approximately 1-2 seconds for an RF matching network using VVCs, the changes to these EVCs 31 and 33 require a total of approximately 9-11 microseconds (µsec). Once the switch to different variable capacitors is complete, there is a delay period because the additional discrete capacitors constituting these EVCs are added to the circuit and charged. This part of the matching adjustment process takes approximately 55 milliseconds. Finally, the RF power distribution 403 shows a reduction from approximately 380 mV peak-to-peak to approximately 100 mV peak-to-peak exactly before t=56 milliseconds. This reduction in the RF power distribution 403 represents a reduction in the reflected power 407, and it occurs within approximately 10 milliseconds, at which point the matching adjustment process is considered complete.

[0077] Changing the series variable capacitor and the shunt variable capacitor may involve transmitting a control signal to the series drive circuit 39 and the shunt drive circuit 43 to control the series variable capacitor and the shunt variable capacitor, respectively. The series drive circuit 39 is operatively coupled to the series EVC 31, and the shunt drive circuit 43 is operatively coupled to the shunt EVC 43. When the EVCs 31 and 33 switch to the desired capacitance value, the input impedance can be matched with the fixed RF source impedance (e.g., 50 ohms), thus resulting in impedance matching. If sufficient impedance matching is not achieved due to fluctuations in the plasma impedance, the 500A procedure can be repeated one or more times to achieve impedance matching or at least a substantial impedance matching.

[0078] Using an RF matching network 11 such as that shown in Figure 3, the input impedance can be expressed as follows:

[0079] Wherein Zin is the input impedance, ZP is the plasma impedance, ZL is the series inductor impedance, Zseries is the series EVC impedance, and Zshunt is the shunt EVC impedance. In the example embodiment, the input impedance (Zin) is determined using the RF input sensor 21. The control circuit knows the EVC impedances (Zseries and Zshunt) at any given time because the control circuit is used to command the various discrete fixed capacitors of each of the series and shunt EVCs to turn on or off. Furthermore, the series inductor impedance (ZL) is a fixed value. Therefore, the system can use these values ​​to solve for the plasma impedance (ZP).

[0080] Based on the determined plasma impedance (ZP) and the known required input impedance (typically 50 Ohm) and the known series inductor impedance (ZL), the system can determine a new series EVC impedance () and a shunt EVC impedance ().

[0081] Based on the newly calculated series EVC variable impedance () and shunt EVC variable impedance (), the system can then determine a new capacitance value (first capacitance value) for the series variable capacitor and a new capacitance value (second capacitance value) for the shunt variable capacitor. When these new capacitance values ​​are used with the series EVC 31 and the shunt EVC 33 respectively, impedance matching can be achieved.

[0082] The example method, which calculates the required first and second capacitance values ​​in one step and reaches those values, is significantly faster than gradually moving the two EVCs to zero or minimizing the reflected power / reflection coefficient. In semiconductor plasma processes requiring faster adjustment schemes, this approach provides a significant improvement in the speed of matching network adjustment. It should be noted that the method used to determine the new EVC capacitance values ​​discussed herein is merely an example. In other embodiments, other parameters and / or methods may be used to determine new EVC capacitance values. For example, the parameters based on a new capacitance value could be any parameter relating to the plasma chamber. Using a parameter matrix to determine capacitance values.

[0083] Figure 8 provides an alternative procedure 500 for matching impedance using a parameter matrix. In the example procedure, the control circuit 45 (see the matching network component in Figure 3) is configured and / or programmed to perform each of these steps. As one of the two initial steps, the RF parameters are measured at the RF input 13 by the RF input sensor 21, and the input impedance at the RF input 13 is calculated using the measured RF parameters (step 501). In this example procedure 500, the forward voltage and forward current are measured at the RF input 13. In some other embodiments, the RF parameters may be measured at the RF output 17 by the RF output sensor 49, but in such embodiments, different calculations than those described below may be required. In yet another embodiment, the RF parameters may be measured at both the RF input 13 and the RF output 17.

[0084] The impedance matching circuit coupled between the RF source 15 and the plasma chamber 19 may be characterized by one of several parameter matrix types known to those skilled in the art, including two-port parameter matrices. An S-parameter matrix and a Z-parameter matrix are two examples of such parameter matrices. Other examples include (but are not limited to) a Y-parameter matrix, a G-parameter matrix, an H-parameter matrix, a T-parameter matrix, and an ABCD-parameter matrix. Those skilled in the art will also understand that these various parameter matrices can be mathematically transformed from one to another for a circuit (such as a matching network). The second initial step of the example procedure 500 is to look up the parameter matrix for the existing configuration of the impedance matching circuit in a parameter lookup table (step 502). The existing configuration of the impedance matching circuit is defined by the existing operating parameters of the impedance matching circuit, in particular the existing array configuration of both the series EVC 31 and the shunt EVC 33. In order to achieve an impedance matching, the existing configuration of the impedance matching circuit is changed to a new configuration of the impedance matching circuit as part of the example program 500.

[0085] The parameter lookup table includes a plurality of parameter matrices, each of which relates to a specific configuration of the cascaded EVC 31 and the shunt EVC 33. The parameter lookup table may include one or more of the aforementioned parameter matrix types. In this example program 500, the parameter lookup table includes at least a plurality of S-parameter matrices. In some embodiments, the parameter lookup table may include at least a plurality of Z-parameter matrices. In embodiments where the parameter lookup table includes multiple types of parameter matrices, different types of parameter matrices are associated in the parameter lookup table in such a way that the need for mathematical transformations between different types of parameter matrices is eliminated. For example, the T-parameter matrix may be included as part of the parameter lookup table, wherein each T-parameter matrix is ​​associated with an associated S-parameter matrix derived from a transformation between the two matrices.

[0086] The input impedance calculation (step 501) and the parameter matrix lookup (step 502) can be performed in any order. After completing the calculation of the input impedance (step 501) and confirming the parameter matrix of the existing configuration of the impedance matching circuit in the parameter lookup table (step 502), the plasma or load impedance can then be calculated using the calculated input impedance and the parameter matrix of the existing configuration (step 503). Next, based on the calculated plasma impedance, a matching configuration of the series EVC 31 and the shunt EVC 33 that can achieve one impedance match or at least one substantial impedance match between the RF source 15 and the plasma chamber 19 is found in an array configuration lookup table (step 504). These matching configurations from the array configuration lookup table are array configurations that will generate new capacitance values ​​for the series EVC 31 and the shunt EVC 33, and an impedance match is achieved by the new array configuration and the associated new capacitance values. The array configuration lookup table is an array configuration table for the series EVC 31 and the shunt EVC 33, and it includes every possible array configuration when the series EVC 31 and the shunt EVC 33 are used in combination. Alternatively, the actual capacitance values ​​of the EVCs 31 and 33 can be calculated during the program; however, such on-the-fly calculation of these capacitance values ​​is inherently slower than finding the matching configuration in the array configuration lookup table. After confirming the matching configurations of the series EVC 31 and the shunt EVC 33 in the array configuration lookup table, one or both of the series array configuration and the shunt array configuration are then changed (step 505) to the separately confirmed matching configurations of the series EVC 31 and the shunt EVC 33.

[0087] The change of the series array configuration and the shunt array configuration (step 505) may include the control circuit 45 transmitting a control signal to the series drive circuit 39 and the shunt drive circuit 43 to control the series array configuration and the shunt array configuration respectively, wherein the series drive circuit 39 is operatively coupled to the series EVC 31, and the shunt drive circuit 43 is operatively coupled to the shunt EVC 43. When the EVCs 31, 33 have been switched to the matching configuration, the input impedance can be matched with the fixed RF source impedance (e.g., 50 Ohms), thus resulting in impedance matching. If sufficient impedance matching cannot be obtained due to fluctuations in the plasma impedance, the procedure 500 may be repeated one or more times to obtain impedance matching or at least a substantial impedance matching.

[0088] The lookup tables used in the procedure described above were compiled before the RF matching network was used in conjunction with the plasma chamber 19. When these lookup tables were created, the RF matching network 11 was tested before being used with a plasma chamber to determine at least one parameter matrix and load impedance associated with each array configuration of the series EVC 31 and the shunt EVC 33. The parameter matrices obtained from the tests were compiled into the parameter lookup table such that at least one parameter matrix of each type was associated with a separate array configuration of the EVCs 31, 33. Similarly, the load impedances were compiled into the array configuration lookup table such that each parameter matrix was associated with a separate array configuration of the EVCs 31, 33. These pre-compiled lookup tables take into account the fixed RF source impedance (e.g., 50 Ohm), the power output of the RF source, and the operating frequency of the RF source, as well as other factors related to the operation of the RF matching network. Therefore, each lookup table may have tens of thousands or more entries to cover all possible configurations of the EVCs 31 and 33. The number of possible configurations is primarily determined by the number of discrete fixed capacitors constituting each of the EVCs 31 and 33. When compiling these lookup tables, possible safety limitations, such as the maximum permissible voltage and current at critical locations within the matching network, may be considered, and this may be used to exclude entries in one or more of the lookup tables related to certain configurations of the EVCs 31 and 33.

[0089] As is known in the art, the S-parameter matrix consists of components called scattering parameters or simply S-parameters. An S-parameter matrix for the impedance matching circuit has four S-parameters, namely S11, S12, S21, and S22, each representing a voltage ratio at the RF input 13 and the RF output 17. All four S-parameters of the impedance matching circuit are predetermined and / or calculated so that the complete S-parameter matrix is ​​known. Parameters of other types of parameter matrices can also be predetermined and / or calculated and incorporated into the parameter matrix. For example, a Z-parameter matrix of the impedance matching circuit has four Z-parameters, namely Z11, Z12, Z21, and Z22.

[0090] By compiling the parameter lookup table in this manner, the entire time cost of a specific calculation occurs during the testing phase of the RF matching network, rather than during the actual use of the RF matching network 11 and a plasma chamber 19. Furthermore, because finding a value in a lookup table takes less time than calculating the same value in real time, using the lookup table can help reduce the overall time required to achieve an impedance match. In a plasma deposition or etching process, which may involve hundreds or thousands of impedance matching adjustments throughout the process, this time saving can contribute to direct cost savings in the overall process.

[0091] From the start of the matching adjustment procedure, which begins when the control circuit determines the variable impedance of the plasma chamber and the series and shunt matching configurations, to the end of the matching adjustment procedure, the entire matching adjustment procedure of the RF impedance matching network using EVC has an experience time of approximately 110 microseconds or approximately 150 microseconds or less when the RF power reflected back to the RF source decreases. This short experience time of a single iteration of the matching adjustment procedure represents a significant increase for the VVC matching network. Furthermore, due to this short experience time of a single iteration of the matching adjustment procedure, the RF impedance matching network using EVC can repeatedly execute the matching adjustment procedure, repeating the two determination steps and generating another control signal to further change the array configuration of one or both of the electronic variable capacitors. By iteratively repeating the matching adjustment procedure, it is expected that a better impedance match can be established in approximately 2-4 iterations of the matching adjustment procedure. Furthermore, depending on the duration of each repetition of the matching adjustment procedure, it is expected to be repeated 3-4 times within 500 microseconds or less. Assuming that a single iteration of the matching adjustment procedure using a VVC-based RF impedance matching network takes 1-2 seconds, this ability to perform multiple iterations in a very short time is a significant advantage for RF impedance matching networks using EVC.

[0092] Those skilled in the art will understand that for an RF impedance matching network using EVC, several factors may contribute to the sub-millisecond duration of the impedance matching process. These factors may include the power of the RF signal, the configuration and design of the EVC, the type of matching network used, and the type and configuration of the drive circuit used. Other unlisted factors may also contribute to the overall duration of the impedance matching process. Therefore, it is anticipated that the entire matching adjustment process for an RF impedance matching network with EVC, from the start of the process (i.e., the adjustment required to establish the impedance matching through the measurement and calculation of the control circuit) to the end of the process (the point in time when the efficiency of the RF power coupled to the plasma chamber increases due to an impedance match and the reduction of the reflected power), should not exceed approximately 500 microseconds. Even within the same 500-microsecond range of matching adjustment processes, this processing time still represents a significant improvement compared to RF impedance matching networks using VVC.

[0093] Table 1 presents data comparing the operating parameters of an EVC instance and a VVC instance. As can be seen, in addition to enabling fast switching of an RF impedance matching network, the EVC has several advantages: Table 1 parameter EVC Typical 1000pF vacuum capacitor capacitance 20 pF ~ 1400 pF 15 pF ~ 1000 pF reliability high Low reaction time ~ 500 microseconds 1 s ~ 2 s ESR ~ 13 mW ~ 20 mW Voltage 7 kV 5kV Current handling capability 216 A rms 80 A rms volume 4.5 in 3 75 in 3

[0094] As can be seen, in addition to the rapid switching capabilities that EVCs can achieve, EVCs also introduce advantages in reliability, current handling, and size. Additional advantages of using the RF impedance matching network of an EVC and / or the switching circuitry itself used in such EVCs include: Ÿ The disclosed RF impedance matching network does not contain any moving parts, thus reducing the likelihood of mechanical failure to the likelihood of other entire circuits that can be used as part of the semiconductor process. For example, a typical EVC can be formed from a durable ceramic substrate with copper metallization to form discrete capacitors. The elimination of moving parts also increases resistance to damage caused by thermal fluctuations during use. Ÿ Compared to a VVC, the EVC has a small size, thus reducing volume and weight and saving valuable space in manufacturing facilities. Ÿ The design of the EVC introduces the ability to customize the RF matching network to meet the specific design requirements of specific applications. The EVC can be configured with custom capacitance ranges, one example being a non-linear capacitance range. Such custom capacitance ranges can provide better impedance matching for a wider range of processes. For another example, a custom capacitance range can provide greater resolution in certain areas of impedance matching. A custom capacitance range also enables the generation of higher trigger voltages, thus simplifying plasma collisions. This brief matching adjustment procedure (~500 microseconds or less) allows the RF impedance matching network to better keep up with plasma variations in the process, thereby increasing plasma stability and resulting in more controlled power in the process. The use of digitally controlled, non-mechanical EVCs in an RF impedance matching network provides greater opportunities for fine-tuning the control algorithm through programming. Compared to VVCs, EVCs exhibit superior low-frequency (kHz) performance. Balanced RF voltage across series-connected PIN diodes.

[0095] As discussed above, PIN diodes can be used as solid-state switches in RF matching networks, such as the matching networks shown in Figures 1-3. (PIN diodes will be discussed below, but those skilled in the art will understand that this discussion also applies to NIP diodes.) As discussed above, an EVC may include fixed capacitors, each having a switching circuit for turning a fixed capacitor on and off. For example, an EVC may utilize the switching circuit 140A of Figure 6. In this switching circuit 140A, the switch is a single-PIN diode 161A.

[0096] PIN diodes are effective RF switches because they have very low leakage current and capacitance in the off state. These characteristics allow a PIN diode to appear open when off. Some commercially available PIN diodes have a maximum cutoff voltage of several kilovolts. This maximum cutoff voltage is often referred to as the reverse breakdown voltage. If this voltage is exceeded, the device will exhibit a breakdown fault. This breakdown voltage limits the usable power range of the PIN diode. PIN diodes also have a maximum current rating in the on state. This finite current rating also limits the maximum effective power range of the diode. To build a high-power RF switch using PIN diodes, multiple diodes can be connected in series and parallel. Figure 9 provides an example of such a PIN diode array. Adding PIN diodes in series increases the maximum cutoff voltage of the diode-based switch 261A, while connecting PIN diodes in parallel increases the overall current carrying capacity of the switch 261A. While adding PIN diodes in this way will increase the overall voltage and current carrying capacity of the switch, it is preferable that diodes D1-D9 share the RF potential equally, thereby effectively preventing any device from failing.

[0097] The exemplary PIN diode switch is turned on using a forward bias current. In high-power applications, this current can be approximately 0.5A. This forward bias current keeps the PIN diode in a low-resistance conduction state. In the off or cut-off state, the exemplary PIN diode receives a reverse voltage from cathode to anode that is greater than the peak RF potential of the circuit. This ensures that the PIN diode remains in a reverse bias state and does not conduct in the forward direction. When multiple PIN diodes are connected in series, it is desirable to have an equal shared reverse cut-off voltage across each PIN diode. If the RF potential of one of these diodes exceeds the DC cut-off voltage across that diode, conduction mode is entered.

[0098] Balancing resistors can be used to balance the voltage across each PIN diode, see, for example, the balancing resistor 169A (R1-R3) in Figure 9. In an exemplary embodiment, the resistance is significantly lower than the leakage resistance across the PIN diode, but its resistance is not so low as to consume excessive power. In some specific examples, the balancing resistors are of the same value (e.g., 10MΩ), although the invention is not so limited.

[0099] In high-power applications, PIN diodes typically require cooling and are cooled using heat sinks. Figure 10 shows one potential configuration for heat dissipation. Specifically, Figure 10 shows a PIN diode 251 mounted on (and possibly fabricated on) a substrate 252 that conducts heat but not electricity. The substrate may have copper wiring to enable electrical connections. The substrate may be ceramic but is not so limited. Preferably, the substrate is an electrical insulator and an excellent thermal conductor. This allows the PIN diode to be electrically isolated from the package or heat sink while still having low thermal resistance from the junction to the housing. The substrate 252 is positioned on a heat sink 253. The substrate may be clamped to the heat sink, and thermal paste may be placed therebetween. While the invention is not so limited, heat sinks are typically grounded and made of a metallic conductive material. As will be discussed in more detail below, a parasitic capacitance 254 is generated between the PIN diode 251 and the conductive heat sink 253.

[0100] The balancing resistor 169A in Figure 9 balances the DC cutoff voltage, but may not properly balance the RF voltage. At higher frequencies, the capacitive response of the PIN diode junction capacitance may be equal to or less than the value of the DC balancing resistor. In this case, the junction capacitance can become the main factor in balancing the RF voltage across the series-connected PIN diodes. Furthermore, when multiple PIN diodes are connected in series, the junction capacitance from the die to ground and the capacitance form a voltage divider. This voltage divider affects the voltage distribution across the PIN diodes. Therefore, this unequal voltage distribution limits the practical range of series-connected PIN diodes. Figure 9 shows these parasitic capacitances 171. Cp1-4 is the capacitance from the die to the heat sink, while Cj1-3 is the capacitance from the cathode to the anode when the diode is off.

[0101] In an ideal environment, the cutoff voltage is evenly distributed across each of the PIN diodes. For example, if three diodes are used and the DC cutoff voltage is 3kV, the cutoff voltage will be evenly distributed, such that there is 1kV across each diode. The RF potential will also be evenly distributed.

[0102] Figure 11 is a diagram of the voltage across the diode based on the diode switch in Figure 9, based on an analog simulation. This model is used for a 3kV, 17A PIN diode. This diode has a junction capacitance of 2.2pF and a leakage current of 10uA at 3kV. The amplitude of the 13MHz frequency source is 2500V. A 3kV DC cutoff voltage is used.

[0103] Figure 11 shows waveforms 201-203, illustrating how the voltage across each PIN diode switch is affected by parasitic capacitance from the die to ground. Waveform 201 shows the voltage across the first diode D1. This diode D1 has the largest RF voltage across it. Waveform 202 shows the voltage across the second diode D2. This diode D2 has the second largest potential. Waveform 203 shows the voltage across the third diode D3. This diode D3 has the smallest RF voltage across it. The voltage across D1 exceeds the 1kV cutoff voltage. Therefore, D1 conducts forward during a portion of the sine wave. Floating heatsink

[0104] One method to eliminate parasitic capacitance to ground is to remove the grounding by using a floating heatsink. In this example, the heatsink acts as the ground. In this case, the additional parasitic capacitance Cp5 will lie between the floating heatsink and the circuit ground. This option is shown as the parasitic capacitance Cp5 in Figure 9.

[0105] Figure 12 is a diagram of the trans-diode voltage based on a diode switch in Figure 9 using a floating heatsink. In this simulation, a very small 0.1pF capacitor is used to simulate the capacitance from the heatsink to ground, and an extremely high 1000MΩ resistor is used to simulate the resistance from the heatsink to ground.

[0106] Figure 12 shows unequal voltages across the PIN diodes. Waveform 204 is the voltage across D1, waveform 205 is the voltage across D2, and waveform 206 is the voltage across D3. The voltages are unequal because the heatsink acts as a floating ground plane. Parasitic capacitances from the PIN diodes to the floating ground are coupled to each other. The capacitances across each diode are unequal, therefore the voltages are unbalanced. One possible solution to this problem is to use a single floating heatsink for each PIN diode die. This would eliminate the common coupling path between parasitic capacitances. However, this approach may not be practical from a mechanical implementation standpoint because the heatsinks could be very large. Unevenly balanced resistors

[0107] As shown in Figure 11, the voltages across the PIN diodes are uneven, and the diode system with the largest voltage potential conducts in the forward direction. This is because the DC cutoff voltage is not greater than the RF potential across this diode. One solution to this problem is to use unequal values ​​for the balancing resistors. In one embodiment, referring back to Figure 9, R1 is 15MΩ, R2 is 10MΩ, and R3 is 5MΩ. Figure 13 shows the simulation results. Waveform 207 is the voltage across diode D1, waveform 208 is the voltage across diode D2, and waveform 209 is the voltage across diode D3. Figure 13 shows the simulation results. The DC cutoff voltage across each diode is proportional to the uneven RF potential. The RF waveform is centered on the DC displacement. All three diodes are currently kept in the off state and do not conduct in the forward direction. However, if the RF potential across one of these diodes is greater than the reverse voltage rating of that diode, the diode will still break down and damage the device. This method does not obtain the full voltage rating potential of series-connected diodes because it does not distribute the voltage equally across each diode. Balancing capacitors

[0108] Since unequal voltage distribution is the result of a series of equal voltage dividers formed by parasitic capacitance, one solution is to use lumped elements or integrated printed balancing capacitors to restore voltage balance across each diode. In one embodiment, the printed capacitors are formed on a substrate with copper wiring and utilize the dielectric constant of the substrate material; however, the invention is not so limited.

[0109] Figure 14 shows a diode-based switch 162B according to one embodiment using balancing capacitors 170B (Cb1, Cb2). As shown, balancing capacitors Cb1, Cb2 are added across each of the first diodes 173 and second diodes 174 in each string 168B to change the voltage across them in the off state. Although not shown, balancing capacitors may also be added across the last diode 175 in each string 168B. In an exemplary embodiment, parasitic cathode-to-anode capacitance is used for the last diode 175 (D3, D6, D9) instead of capacitors. Furthermore, in this embodiment, balancing resistors 169B are of equal value because balancing capacitors 170B make the RF potential across each diode equal, although the invention is not so limited. In other embodiments, balancing resistors may be omitted.

[0110] In Figure 14, switch 162B shows a string 168B with diodes connected in series. Three strings 168B are shown, but in other embodiments, there may be any number of strings. Each of these series-connected diodes is a PIN diode, but the diodes may be replaced with NIP diodes. For each string 168B, at least one of these diodes has a balancing capacitor 170B connected in parallel with one of the diodes. In this example, the first diode 173 in each string is connected in parallel with a balancing capacitor Cb1, and the second capacitor 174 in each string is connected in parallel with a balancing capacitor Cb2. The third diode 175 does indeed have a parallel balancing capacitor, but in other specific examples, these diodes 175 may have a single balancing capacitor.

[0111] In an exemplary embodiment, the diodes of string 168B are configured in an array such that the first diode D1 of the first string 176 is connected in parallel to the first diodes D4 and D7 of each of the other strings 177 and 178, and the second diode D2 of the first string 176 is connected in parallel to the second diodes D5 and D6 of each of the other strings. Furthermore, the first diodes 173 of each of the strings 168B share a common first balancing capacitor Cb1, and the second diodes 174 of each string 168B share a second balancing capacitor Cb2. Additionally, in this embodiment, the first diodes 173 of each of the strings 168B share a common first balancing resistor R1 connected in parallel with the first diodes 173, and the second diodes 174 of each string 168B share a common second balancing resistor R2 connected in parallel with the second diodes 174.

[0112] The values ​​of the balancing capacitors can be different or the same. These values ​​can be selected by various methods and can be determined by the specific switches used, the values ​​of the diodes, the expected values ​​of parasitic capacitance, the values ​​of the resistors, etc. Although multiple methods can be used to calculate the capacitance value, they can be used alternately by trial and error to determine the most effective capacitance value so that the voltage across each diode is equal (or nearly evenly distributed).

[0113] Figure 15 shows an alternative configuration using a balancing capacitor in a diode-based switch 162C. This configuration is the same as in Figure 14, except that the diodes in a particular column of the array (e.g., the first diodes 173C (D1, D4, D7)) are not coupled in parallel to each other. In this case, instead of having a balancing capacitor (e.g., Cb1) parallel to each column (e.g., the first diode 173C), there is a separate balancing capacitor for each diode in parallel with the first and second diode columns 173C, 174C. In this embodiment, the last column of diodes 175C has no balancing capacitor. In other embodiments, the diodes in the last column may also have their own balancing capacitors. In other words, diode D1 has a balancing capacitor Cb11, diode D2 has a balancing capacitor Cb21, diode D4 has a balancing capacitor Cb12, diode D5 has a balancing capacitor Cb22, diode D7 has a balancing capacitor Cb1n, and diode D2 has a balancing capacitor Cb2n. The balancing resistor is omitted in this figure, but may be included similarly to that in Figure 14.

[0114] Figure 16 below is a simulation schematic of a diode-based switch 162D, which uses a balancing capacitor and resistor array similar to that in Figure 14. For diodes D1, D2, and D3, the simulation uses 3kV, 17A PIN diodes with a junction capacitance of 2.2 and a leakage current of 10uA at 3kV. A 13MHz frequency source V1 with an amplitude of 2500V (coupled to ground 40) is used. A 3kV DC cutoff voltage is used. Note that the simulation schematic of Figure 16 has been simplified. The voltage source V1 may also include a DC offset voltage (e.g., 3kV). The DC offset voltage can be used to simulate the cutoff voltage, which is typically fed to the cathode of the PIN diode through a choke coil. When the switch is on, the choke coil can also be used to alternately feed a forward bias voltage (e.g., -5V).

[0115] A single first string of 168D PIN diodes D1, D2, D3 is used, each with corresponding balancing resistors 169D (Rb1, Rb2, Rb3) to evenly distribute the 3kV cutoff voltage. In this simulation, the resistance of each of these balancing resistors 169D is 10 MΩ. The first two diodes D1, D2 have corresponding balancing capacitors 170D. Balancing capacitor Cb1 has a capacitance of 3 pF and balancing capacitor Cb2 has a capacitance of 1 pF. Parasitic capacitances 171 are also denoted as Cp1, Cp2, and Cp3, respectively. A bias inductor Lbias (1m) is used as an RF choke. It has high impedance at the operating frequency and provides a DC return path for both the DC cutoff voltage and the forward bias voltage. In addition, a DC blocking capacitor C1 is used to allow RF to pass through but block the DC blocking voltage. Resistor R1 (10MΩ) is the RF load.

[0116] Figure 17 is a diagram of the trans-diode voltage based on a diode switch in Figure 15 according to an embodiment using a balancing capacitor. As can be observed, the RF potential is balanced, and the voltage across each diode is represented by waveform 210.

[0117] As discussed above, the diode-based EVC discussed herein can be incorporated into RF matching networks. This matching network for impedance matching can be used in semiconductor manufacturing tools. Such matching networks can also be used in impedance matching methods and / or in methods for manufacturing semiconductors that include impedance matching. Non-conductive heat sink

[0118] As discussed above regarding Figure 10, the use of a conductive metallic heat sink can lead to a parasitic capacitance 254 that causes an imbalance in the RF potential across the diode based on the diode switch. The above solution uses a balancing capacitor to address this problem and balance the RF potential.

[0119] Another method for maintaining the RF potential balance across the diode is to use a non-conductive heat sink, as shown in Figure 18. According to this method, the heat sink 255 is made of a thermally conductive but electrically insulating material. The diode 251 based on the diode switch is positioned directly on the non-conductive heat sink, rather than on a non-conductive substrate positioned on a conductive heat sink. In some embodiments, the heat sink comprises or is made of ceramic materials, such as beryllium oxide (BeO), aluminum nitride (AlN), or alumina ceramic (Al2O3). Such materials are effective thermal conductors and also effective electrical insulators. Various other composite materials can also be used instead of ceramics. The heat sink can be air-cooled or water-cooled.

[0120] Once the conductivity of the heat sink is removed, the circuit schematic is similar to that in Figure 9, but without the parasitic capacitance 171. Therefore, the RF potential is equal and balanced across the diodes 251 and 168A.

[0121] As discussed above with respect to Figure 10, when a PIN diode array is fabricated on a non-conductive substrate, the substrate can have copper wiring for electrical connections. These components can be soldered to the substrate. If the substrate is attached to a conductive heat sink, the substrate can be clamped to the heat sink, and thermal paste can be applied therebetween. However, the thermal paste increases the additional thermal resistance of the components and raises the temperature of the components mounted thereon. By eliminating the conductive heat sink, the substrate clamping element and thermal paste can be eliminated, making the non-conductive heat sink and the circuit ceramic substrate a homogeneous component. According to this embodiment, the circuit can be fabricated directly above the ceramic heat sink.

[0122] It should be noted that, in addition to eliminating (or reducing) the trans-diode voltage imbalance of the switch, the non-conductive heatsink of Figure 18 offers another advantage. In L-type matching (as shown in Figure 2), parasitic capacitance from the series output capacitor (see, for example, series capacitor 31 in Figure 2) to ground can be a problem because this capacitance can limit the range of the matching network. As discussed herein, parasitic capacitance can be generated when the switching circuit is placed on a ceramic substrate, which in turn clamps to the grounded conductive heatsink. This is particularly noticeable at higher frequencies where the reactance of the parasitic capacitance becomes lower. By mounting the capacitor array on a ceramic heatsink, parasitic capacitance can be eliminated, thus increasing the tuning range. Alternatively, the conductive heatsink can be floating.

[0123] Although the embodiments of the matching network discussed herein use L or pi configurations, it should be noted that the claimed matching network can be configured as other matching network configurations, such as "T" configurations. Unless otherwise stated, the variable capacitors, switching circuits and methods discussed herein can be used with any configuration suitable for an RF impedance matching network.

[0124] Although the embodiments discussed herein use one or more variable capacitors in a matching network to achieve impedance matching, it should be noted that any variable reactance element can be used. A variable reactance element may include one or more discrete reactance elements, wherein one reactance element is a capacitor or inductor or a similar reactance device.

[0125] The entire contents of this application are incorporated herein by reference into jointly owned U.S. Patent No. 10,460,912, U.S. Publication No. US2021 / 0327684, U.S. Publication No. US2021 / 0327684 and U.S. Patent No. 10,984,985.

[0126] Although the invention has been described with respect to specific embodiments, including preferred embodiments of the present invention, those skilled in the art will understand that the system technology described above is subject to various variations and arrangements. It should be understood that other embodiments may be used, and the structure and function may be modified without departing from the scope of the invention. Therefore, the spirit and scope of the invention should be broadly defined as set forth in the claims below. [Simplified Explanation of the Diagram]

[0015] This invention will be more fully understood by way of embodiments and accompanying drawings, in which: Figure 1 is a block diagram of an embodiment of a semiconductor process system. Figure 2 is a block diagram of an embodiment of a semiconductor process system having an L-configuration matching network. Figure 3 is a block diagram of an embodiment of a semiconductor process system having a pi configuration matching network. Figure 4 is a block diagram of an embodiment of a circuit using an electronic variable capacitor to provide variable capacitance. Figure 5 is a schematic diagram of a variable capacitor system for switching discrete capacitors of an electronic variable capacitor. Figure 6 is a block diagram of an embodiment of a switching circuit for EVC. Figure 7 is a flowchart of an exemplary process for matching impedance by changing variable capacitance. Figure 8 is a flowchart of an exemplary process for changing variable capacitance by matching impedance using a parameter matrix. Figure 9 is a diode-based switch using a balancing resistor according to an embodiment. Figure 10 is a block diagram of a diode-based switch located on a ceramic substrate on a metal heat sink according to an embodiment. Figure 11 is a diagram of the transdiode voltage of the diode-based switch of Figure 9. Figure 12 is a diagram of the trans-diode voltage of the diode-based switch in Figure 9 using a floating heatsink. Figure 13 is a diagram of the trans-diode voltage of the diode-based switch in Figure 9 using unequal balancing resistors. Figure 14 is a diagram of a diode-based switch using a balancing capacitor according to one embodiment. Figure 15 is a diagram of a diode-based switch using a balancing capacitor according to another embodiment. Figure 16 is a schematic diagram of a diode-based switch using a balancing capacitor according to one embodiment. Figure 17 is a diagram of the trans-diode voltage of the diode-based switch in Figure 15 using a balancing capacitor according to one embodiment. Figure 18 is a block diagram of a diode-based switch located on a ceramic heatsink according to another embodiment.

Claims

1. A radio frequency (RF) impedance matching circuit comprising: an RF input configured to be operatively coupled to an RF source providing an RF signal; an RF output configured to be operatively coupled to a plasma chamber; and at least one electronically variable capacitor (EVC), wherein, Each of the at least one EVC includes a plurality of fixed capacitors, each of the fixed capacitors having a corresponding switching circuit for switching the fixed capacitor on and off to change the total capacitance of the at least one EVC; and a control circuit configured to switch the fixed capacitors of each EVC on and off to enable impedance matching; wherein each of the switching circuits of each fixed capacitor in each EVC includes: a switch operably coupled to the fixed capacitor to switch the fixed capacitor on and off, the switch including at least one series of a plurality of diodes connected in series, each of the series-connected diodes being a PIN diode or a NIP diode; wherein for each of the at least one series, at least one of the diodes in the series has a balancing capacitor connected in parallel with the diode.

2. The RF impedance matching circuit as described in claim 1, wherein, The value of each of these balancing capacitors is based on an expected value of one or more parasitic capacitances in the switching circuit when such balancing capacitors are not present.

3. The RF impedance matching circuit as described in claim 1, wherein, The series-connected diodes comprise at least two series-connected complex diodes coupled in parallel to each other.

4. The RF impedance matching circuit as described in claim 3: Wherein, The at least two strings of diode systems are configured in an array such that a first diode of a first string is connected in parallel with a plurality of first diodes of each of the other strings, and a second diode of the first string is coupled in parallel with a plurality of second diodes of each of the other strings; wherein the first diodes of each of the at least two strings share a common first balancing capacitor, and the second diodes of each of the at least two strings share a common second balancing capacitor.

5. The RF impedance matching circuit as described in claim 4, wherein, The first diodes of each of the at least two strings share a common first balancing resistor coupled in parallel with the first diodes, and the second diodes of each of the at least two strings share a common second balancing resistor coupled in parallel with the second diodes.

6. The RF impedance matching circuit as described in claim 5, wherein, The common first balancing resistor and the common second balancing resistor have equal resistance values.

7. The RF impedance matching circuit as described in claim 4, wherein, The common first balancing capacitor has a different capacitance value than the common second balancing capacitor.

8. The RF impedance matching circuit as described in any of the preceding claims, wherein, Each of the diodes connected in series is located on a thermally conductive but non-conductive substrate, which is located on a conductive heat sink.

9. The RF impedance matching circuit as described in claim 8, wherein, The substrate contains a ceramic material.

10. A method for impedance matching, comprising: coupling a radio frequency (RF) input of a matching circuit to an RF source providing an RF signal; and coupling an RF output of the matching circuit to a plasma chamber, wherein, The matching circuit includes: at least one electronically variable capacitor (EVC), wherein each of the at least one EVC includes a plurality of fixed capacitors, each of the fixed capacitors having a corresponding switching circuit for switching the fixed capacitor on and off to change a total capacitance of the at least one EVC; and a control circuit configured to switch the fixed capacitors of each EVC on and off to enable impedance matching; wherein each of the switching circuits of each fixed capacitor in each EVC includes: a switch operably coupled to the fixed capacitor to switch the fixed capacitor on and off, the switch including at least one series of a plurality of diodes connected in series, each of the series-connected diodes being a PIN diode or a NIP diode; In this context, for each of the at least one series, at least one of the diodes in the series has a balancing capacitor connected in parallel with the diode; and impedance matching is achieved by switching at least one of the switching circuits of the at least one EVC on and off its corresponding fixed capacitor to change the total capacitance of the at least one EVC.

11. The method for matching impedance as described in claim 10, wherein, The value of each of these balancing capacitors is based on an expected value of one or more parasitic capacitances in the switching circuit when such balancing capacitors are not present.

12. The method for matching impedance as described in claim 10, wherein, The at least one series-connected diodes comprise at least two complex series-connected diodes coupled in parallel to each other.

13. The method for matching impedance as described in claim 12: wherein, The at least two strings of diode systems are configured in an array such that a first diode of a first string is connected in parallel with a plurality of first diodes of each of the other strings, and a second diode of the first string is connected in parallel with the second diode of each of the other strings; wherein the first diodes of each of the at least two strings share a common first balancing capacitor, and the second diodes of each of the at least two strings share a common second balancing capacitor.

14. The method for matching impedance as described in claim 13, wherein, The first diodes of each of the at least two strings share a common first balancing resistor coupled in parallel with the first diodes, and the second diodes of each of the at least two strings share a common second balancing resistor coupled in parallel with the second diodes.

15. The method for matching impedance as described in claim 14, wherein, The common first balancing resistor and the common second balancing resistor have equal resistance values.

16. The method for matching impedance as described in claim 13, wherein, The common first balancing capacitor has a different capacitance value than the common second balancing capacitor.

17. A method for matching impedance as described in any one of claims 10 to 15, wherein, Each of the diodes connected in series is located on a thermally conductive but non-conductive substrate, which is positioned on a conductive heat sink.

18. The method for matching impedance as described in claim 17, wherein, The substrate contains a ceramic material.

19. A semiconductor manufacturing tool comprising: a plasma chamber configured to deposit a material onto or etch a material from the substrate; and an impedance matching circuit operatively coupled to the plasma chamber, the matching circuit comprising: an RF input configured operatively coupled to an RF source providing an RF signal; an RF output configured operatively coupled to the plasma chamber; and at least one electronically variable capacitor (EVC), wherein... Each of the at least one EVC includes a plurality of fixed capacitors, each of which has a corresponding switching circuit for switching the fixed capacitor on and off to change the total capacitance of the at least one EVC; and a control circuit configured to switch the fixed capacitors of each EVC on and off to enable impedance matching; wherein each of the switching circuits of each fixed capacitor in each EVC includes: a switch operably coupled to the fixed capacitor to switch the fixed capacitor on and off, the switch including at least one series of a plurality of diodes connected in series, each of the series-connected diodes being a PIN diode or a NIP diode; wherein for each of the at least one series, at least one of the diodes in the series has a balancing capacitor connected in parallel with the diode.

20. A method of manufacturing a semiconductor, the method comprising: placing a substrate in a plasma chamber, the plasma chamber being configured to deposit a material layer on the substrate or etch a material layer from the substrate; energizing plasma within the plasma chamber by coupling RF power from an RF source to the plasma chamber to perform deposition or etching; and simultaneously energizing the plasma by performing impedance matching via an impedance matching circuit coupled between the plasma chamber and the RF source, the matching circuit comprising: an RF input configured to be operatively coupled to the RF source; an RF output configured to be operatively coupled to the plasma chamber; and at least one electronically variable capacitor (EVC), wherein... Each of the at least one EVC includes a plurality of fixed capacitors, each of which has a corresponding switching circuit for switching the fixed capacitor on and off to change the total capacitance of the at least one EVC; and a control circuit configured to switch the fixed capacitors of each EVC on and off to enable impedance matching; wherein each of the switching circuits of each fixed capacitor in each EVC includes: a switch operably coupled to the fixed capacitor to switch the fixed capacitor on and off, the switch including at least one series of a plurality of diodes connected in series, each of the series-connected diodes being a PIN diode or a NIP diode; wherein for each of the at least one series, at least one of the diodes in the series has a balancing capacitor connected in parallel with the diode.

21. A radio frequency (RF) impedance matching circuit comprising: an RF input configured to be operatively coupled to an RF source providing an RF signal; an RF output configured to be operatively coupled to a plasma chamber; and at least one electronically variable capacitor (EVC), wherein, Each of the at least one EVC includes a plurality of fixed capacitors, each of which has a corresponding switching circuit for switching the fixed capacitor on and off to change the total capacitance of the at least one EVC; and a control circuit configured to switch the fixed capacitors of each EVC on and off to enable impedance matching; wherein each of the switching circuits of each fixed capacitor in each EVC includes a switch operably coupled to the fixed capacitor to switch the fixed capacitor on and off, the switch including at least one series of a plurality of diodes connected in series, each of the series-connected diodes being a PIN diode or a NIP diode; and wherein each of the series-connected diodes is directly positioned on a non-conductive heat sink.

22. The RF impedance matching circuit as described in claim 21, wherein, The radiator contains a ceramic material.

23. The RF impedance matching circuit as described in claim 22, wherein, The ceramic material is one of beryllium oxide (BeO), aluminum nitride (AlN), or alumina ceramic (Al2O3).

24. The RF impedance matching circuit as described in any one of claims 21 to 23, wherein, The series-connected diodes comprise at least two series-connected complex diodes coupled in parallel to each other.

25. The RF impedance matching circuit as described in claim 24, wherein, The at least two strings of diode systems are configured into an array such that a first diode of a first string is coupled in parallel to a plurality of first diodes of each of the other strings, and a second diode system of the first string is coupled in parallel to a plurality of second diodes of each of the other strings.

26. A method for impedance matching, comprising: coupling a radio frequency (RF) input of a matching circuit to an RF source providing an RF signal; and coupling an RF output of the matching circuit to a plasma chamber, wherein, The matching circuit includes: at least one electronically variable capacitor (EVC), wherein each of the at least one EVC includes a plurality of fixed capacitors, each of the fixed capacitors having a corresponding switching circuit for switching the fixed capacitor on and off to change the total capacitance of the at least one EVC; and a control circuit configured to switch the fixed capacitors of each EVC on and off to enable impedance matching; wherein each of the switching circuits of each fixed capacitor in each EVC includes a switch operatively coupled to the fixed capacitor to switch the fixed capacitor on and off, the switch including at least one series of a plurality of diodes connected in series, each of the series-connected diodes being a PIN diode or a NIP diode; and wherein each of the series-connected diodes is directly positioned on a non-conductive heat sink; and impedance matching is achieved by switching at least one of the switching circuits of the at least one EVC on and off its corresponding fixed capacitor to change the total capacitance of the at least one EVC.

27. The method for matching impedance as described in claim 26, wherein, The radiator contains a ceramic material.

28. The method for matching impedance as described in claim 27, wherein, The ceramic material is one of beryllium oxide (BeO), aluminum nitride (AlN), or alumina ceramic (Al2O3).

29. A method for matching impedance as described in any one of claims 26 to 28, wherein, The series-connected diodes comprise at least two series-connected complex diodes coupled in parallel to each other.

30. The method for matching impedance as described in claim 29, wherein, The at least two strings of such diode systems are configured into an array such that a first diode of a first string is connected in parallel to a plurality of first diodes of each of the other strings, and a second diode of the first string is coupled in parallel to a second diode of each of the other strings.

31. A semiconductor manufacturing tool comprising: a plasma chamber configured to deposit a material onto or etch a material from the substrate; and an impedance matching circuit operatively coupled to the plasma chamber, the matching circuit comprising: an RF input configured operatively coupled to an RF source providing an RF signal; an RF output configured operatively coupled to the plasma chamber; and at least one electronically variable capacitor (EVC), wherein... Each of the at least one EVC includes a plurality of fixed capacitors, each of which has a corresponding switching circuit for switching the fixed capacitor on and off to change the total capacitance of the at least one EVC; and a control circuit configured to switch the fixed capacitors of each EVC on and off to enable impedance matching; wherein each of the switching circuits of each fixed capacitor in each EVC includes a switch operably coupled to the fixed capacitor to switch the fixed capacitor on and off, the switch including at least one series of a plurality of diodes connected in series, each of the series-connected diodes being a PIN diode or a NIP diode; and wherein each of the series-connected diodes is directly positioned on a non-conductive heat sink.

32. A method of manufacturing a semiconductor, the method comprising: placing a substrate in a plasma chamber, the plasma chamber being configured to deposit a material layer on the substrate or etch a material layer from the substrate; energizing plasma within the plasma chamber by coupling RF power from an RF source to the plasma chamber to perform deposition or etching; and simultaneously energizing the plasma by performing impedance matching via an impedance matching circuit coupled between the plasma chamber and the RF source, the matching circuit comprising: at least one electronically variable capacitor (EVC), wherein, Each of the at least one EVC includes a plurality of fixed capacitors, each of which has a corresponding switching circuit for switching the fixed capacitor on and off to change the total capacitance of the at least one EVC; and a control circuit configured to switch the fixed capacitors of each EVC on and off to enable impedance matching; wherein each of the switching circuits of each fixed capacitor in each EVC includes a switch operably coupled to the fixed capacitor to switch the fixed capacitor on and off, the switch including at least one series of a plurality of diodes connected in series, each of the series-connected diodes being a PIN diode or a NIP diode; and wherein each of the series-connected diodes is directly positioned on a non-conductive heat sink.

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