Three-dimensional integration of processing chiplet and static random-access memory (SRAM) chiplets

Abstract

An electronic device comprising: (i) a processing chip configured to process data and having a first side and a second side; (ii) one or more first static random access memory (SRAM) chips disposed on the first side of the processing chip and configured to store a first portion of the data; (iii) one or more second SRAM chips disposed on the second side of the processing chip and configured to store a second portion of the data; (iv) one or more first electrical terminals disposed on the first side of the processing chip and configured to electrically connect the first side of the processing chip to the first SRAM chips; and (v) one or more second electrical terminals disposed on the second side of the processing chip and configured to electrically connect the second side of the processing chip to the second SRAM chips.

Description

[Technical Field]

[0001] This invention generally relates to electronic devices, and more particularly to a method and system for improving the performance of electronic devices by stacking processing chips and static random access memory (SRAM) chips together. [Previous Technology]

[0002] Various techniques are known in this art for integrating processing and static random access memory (SRAM) capabilities in an electronic device.

[0003] The above description is presented as a general overview of the relevant art in this field and should not be construed as an admission that any information contained herein constitutes prior art against this patent application. [Summary of the Invention]

[0004] One embodiment described herein provides an electronic device comprising: (i) a processing chip configured to process data and having a first side and a second side; (ii) one or more first static random access memory (SRAM) chips disposed on the first side of the processing chip and configured to store a first portion of the data; (iii) one or more second SRAM chips disposed on the second side of the processing chip and configured to store a second portion of the data; (iv) one or more first electrical terminals disposed on the first side of the processing chip and configured to electrically connect the first side of the processing chip to the one or more first SRAM chips; and (v) one or more second electrical terminals disposed on the second side of the processing chip and configured to electrically connect the second side of the processing chip to the one or more second SRAM chips.

[0005] In some embodiments, the electronic device includes one or more through-silicon vias (TSVs) formed through at least a portion of the processing wafer and configured to conduct electrical signals between the processing wafer and at least one of the first and second electrical terminals. In other embodiments, the one or more first SRAM wafers include at least first and second given SRAM wafers, and the first given SRAM wafer includes: (i) a first given side facing the first side of the processing wafer and connected to the one or more first electrical terminals, and (ii) a second given side facing the second given SRAM wafer stacked on the first given SRAM wafer. In yet another embodiment, the first given side of the first given SRAM wafer is disposed on the one or more first electrical terminals configured to exchange data between the processing wafer and the first given SRAM wafer.

[0006] In some embodiments, the electronic device includes one or more third electrical terminals disposed on the second side of the first given SRAM wafer and configured to electrically connect the second side of the first given SRAM wafer to the second given SRAM wafer. In other embodiments, the electronic device includes one or more given TSVs formed through at least a portion of the first given SRAM wafer and configured to conduct electrical signals between the processing wafer and at least one of the first and second given SRAM wafers. In still other embodiments, at least one of the TSVs and at least one of the given TSVs are different from each other.

[0007] In some embodiments, at least one of the TSVs: (i) has a first length passing through at least a portion of the processing wafer, (ii) has a first width along a first side of the processing wafer, and (iii) contains a first metal layer having a first volume within the processing wafer, and at least one of the given TSVs: (a) has a second length passing through at least a portion of the first given SRAM wafer, (b) has a second width along a third side of the first given SRAM wafer, and (c) contains a second metal layer having a second volume within the first given SRAM wafer, and at least one of the first and second items is different from each other: (1) length, (2) width, (3) metal layer, and (4) volume. In other embodiments, the processing wafer is formed on a first substrate and includes a first metal interconnect, and at least the first and second given SRAM wafers are formed on a second substrate and include a second metal interconnect. In yet another embodiment, the first side includes a first surface of one of the first substrates and the second side includes the first metal interconnects, and the third side includes: (i) a second surface of one of the second substrates, or (ii) the second metal interconnects.

[0008] In some embodiments, the first and second SRAM chips comprise a first and a second number of SRAM chips, and the first and second numbers are different from each other. In other embodiments, the first and second SRAM chips comprise a first and a second number of SRAM chips, and the first and second numbers are equal to each other.

[0009] In some embodiments, the electronic device includes at least one of the following: (i) a first circuit board (CB) substrate facing a first external SRAM chip of one of the first SRAM chips, (ii) a second CB substrate facing a second external SRAM chip of one of the second SRAM chips, and (iii) one or more third CB substrates, which or the others face one or more edges of the electronic device, at least one of the edges being orthogonal to at least one of the first, second, and third sides. In other embodiments, the electronic device includes third electrical terminals disposed on at least one of the first, second, and third CB substrates and configured to conduct signals between: (i) at least one of the first, second, and third CB substrates, and (ii) at least one of the following: (a) a processing chip, (b) one or more of the first SRAM chips, and (c) one or more of the second SRAM chips.

[0010] According to one embodiment of the present invention, a method for manufacturing an electronic device is further provided, the method comprising: disposing one or more first static random access memory (SRAM) chips on the first side of a processing chip having a first side and a second side; disposing one or more second SRAM chips on the second side of the processing chip; disposing one or more first electrical terminals on the first side of the processing chip for electrical connection between the first side of the processing chip and the one or more first SRAM chips; and disposing one or more second electrical terminals on the second side of the processing chip for electrical connection between the second side of the processing chip and the one or more second SRAM chips.

[0011] In some embodiments, placing the one or more first SRAM chips includes placing at least first and second given SRAM chips, the first given SRAM chip comprising: (i) a first given side disposed facing the first side of the processing chip and connected to the one or more first electrical terminals, and (ii) a second given side disposed facing the second given SRAM chip stacked on the first given SRAM chip. In other embodiments, the method includes testing at least one of: (i) a processing chip, (ii) one or more of the first SRAM chips, (iii) one or more of the second SRAM chips, (iv) a stack of processing chips comprising being electrically connected to at least one of the first and second SRAM chips, and (v) a circuit board (CB) substrate electrically connected to the stack.

[0012] The invention will be more fully understood from the following detailed description of embodiments thereof, taken in conjunction with the drawings, wherein:

Implementation Method

[0015] Cross-reference to related applications

[0016] This application claims the right to U.S. Provisional Patent Application No. 63 / 194,812, filed May 28, 2021, the disclosure of which is incorporated herein by reference.

[0017] Electronic devices (such as central processing units (CPUs), application-specific integrated circuits (ASICs) and system-on-a-chip (SoC) devices) typically integrate (i) logic functions for processing data and (ii) static random access memory (SRAM) functions for performing high-speed storage operations on data processed by the logic functions.

[0018] Improvements in manufacturing technology (such as through size reduction and the introduction of FinFETs) reduce the cost of transistors in logic functions. However, the scaling rate of SRAM functionality is substantially slower and therefore limits the reduction in electronic performance and / or cost of integrated electronic devices. In other words, a SoC including a CPU and SRAM may have insufficient processing and / or memory resources, or may require an increased size and cost for the SoC to incorporate the required processing and / or memory resources.

[0019] One possible temporary solution is to replace at least some of the SRAM functions with other memory functions, such as Dynamic Random Access Memory (DRAM). However, this configuration can limit the performance of the integrated electronic device because the data rate of communication between logic and DRAM is about ten times (10X) slower than the data rate of communication between logic and a corresponding SRAM. Another possible temporary solution is to use a multi-chip module (MCM) configuration to integrate different logic and SRAM chips side by side. However, the area occupied by the MCM configuration device is usually substantially larger than the area occupied by the SoC, and the number of channels used to route signals between two or more chips is insufficient to obtain the required performance of the MCM.

[0020] Embodiments of the invention described herein provide techniques for improving the cost and / or electronic performance of electronic devices by stacking a plurality of SRAM chips on at least two sides of a logic chip (also referred to herein as a processing chip configured to process data). In the background of this invention and within the scope of the claims, the term "chip" refers to an integrated circuit (IC) containing a well-defined subset of functionality. In one embodiment, each chip is configured to be vertically integrated with other chips on an interposer in a single package.

[0021] In some embodiments, an electronic device includes a set of integrated chips implemented in one or more logic chips and one or more SRAM chips. In this example, an electronic device includes: (i) a processing chip configured to process data and having a first side and a second side, (ii) one or more first SRAM chips, which are disposed on the first side of the processing chip and configured to store a first portion of data, and (iii) one or more second SRAM chips, which are disposed on the second side of the processing chip and configured to store a second portion of the data processed in the processing chip.

[0022] In some embodiments, each wafer includes: (i) a substrate having an active side (having active elements as described herein) and a passive side (not having active elements), (ii) active elements, such as transistors, formed in the active side of the substrate, and (iii) metal connections formed above the transistors and configured to interconnect between the transistors and between the wafer and electrical terminals (such as bumps or microbumps) disposed between adjacent stacked wafers. A first side of the wafer includes the surface of the passive side of the substrate, and is also referred to herein as a back side or back face of the wafer, and a second side of the wafer (also referred to herein as a front side or front face of the wafer) includes metal connections configured to interconnect elements of the wafer in a desired manner (e.g., between doped regions in one or more transistors). In these embodiments, pairs of wafers can be configured in various ways (e.g., face-to-face, back-to-back, or face-to-back).

[0023] The substrate of the wafer typically comprises a single-crystal semiconductor substrate having low conductivity. In some embodiments, one or more through-silicon vias (TSVs) are formed through at least one of the wafers, and typically each of the substrates. The TSVs are configured to conduct electrical signals between metal connections of a pair of wafers stacked in a back-to-back or face-to-face configuration.

[0024] In some embodiments, a designated electronic device includes a designated processing chip, and first and second designated SRAM chips face first and second sides of the designated processing chip, respectively. In these embodiments, the designated electronic device includes: (i) a first set of bumps disposed between the first side of the designated processing chip and the first designated SRAM chip, and (ii) a second set of bumps disposed between the second side of the designated processing chip and the second designated SRAM chip. It should be noted that in this configuration, the designated processing chips are stacked as follows: (i) back-to-back or back-to-back with the first designated SRAM chip, and (ii) face-to-face or face-to-back with the second designated SRAM chip (depending on the side configuration of the first and second designated SRAM chips).

[0025] In some embodiments, in a face-to-face configuration: (i) one or more bumps are formed between the metal connection (pad) of the designated processing wafer and the second designated SRAM wafer, (ii) one or more pads may be formed between a TSV and the metal connection, and (iii) one or more bumps may be formed between the two TSVs of each of the two stacked wafers (e.g., the designated processing wafer and the second designated SRAM wafer). In a face-to-back configuration, one or more bumps are formed between the TSVs, and one or more bumps may be formed between a TSV and the metal connection. In a back-to-back configuration, all bumps are formed between the two TSVs of each of the two stacked wafers, as described above. Embodiments relating to various configurations of wafers, TSVs and bumps are described in detail below in Figures 1, 2 and 3.

[0026] In some embodiments, stacking any suitable number of SRAM chips on both sides of a processing chip provides the electronic device with sufficient SRAM resources relative to the processing capability of the processing chip. The number of stacked SRAM chips may be equal on both sides of the processing chip, or different numbers of SRAM chips may be stacked on different sides of the processing chip. Furthermore, the electronic device may include one or more additional processing chips disposed between the stacks of SRAM chips.

[0027] In some embodiments, the electronic device includes, for example, circuit board (CB) substrates electrically connected to one or more chips via balls. In a first exemplary configuration, a surface of a first CB substrate faces a surface of an external SRAM chip stacked on top of an SRAM chip and is electrically connected to the external SRAM chip using balls. In a second exemplary configuration, a surface of a second CB substrate is disposed orthogonally to the front and back sides of the processing and SRAM chips and is electrically connected (for example, via balls) to metal connections of some or all of the processing and SRAM chips. In a third exemplary configuration, the electronic device may include, for example, up to six CB substrates electrically connected (for example, via balls) to six facets of the stack of processing and SRAM chips, respectively. Depending on the specifications of processing and memory capabilities and the respective number of processing and SRAM chips stacked together in the electronic device, these exemplary configurations improve the bandwidth and customization of the electronic device. These embodiments are illustrated and described in detail below in Figures 1 through 3.

[0028] In some embodiments, at least one processing chiplet has redundancy of one of its CPU cores, such that given data intended to be processed in a first CPU core that becomes inactive can be transferred to a second CPU core for processing. In a chiplet stack having one or more processing chipslets, this redundancy of CPU cores can improve (i) yield in manufacturing and (ii) reliability during operation of the chiplet stack. For example, one embodiment of CPU core redundancy is described in U.S. Patent Application 17 / 071,910 (filed by Chang et al., October 15, 2020), the disclosure of which is incorporated herein by reference. Similarly, SRAM chipsets typically have redundancy of memory blocks, such that in response to the identification that a first memory block is inactive, data intended to be stored in the first memory block can be stored in a second, different memory block.

[0029] In some embodiments, redundancy in the CPU core and memory blocks, along with testing of individual chiplets, CB substrates, and two or more stacked chiplets, improves yield and reduces costs associated with the manufacture of such electronic devices. The manufacturing and testing procedures are described in further detail below in Figure 4.

[0030] The foregoing description is presented as a general overview of embodiments of the invention described in detail herein.

[0031] FIG1 is a schematic cross-sectional view of an electronic device 11 according to one embodiment described herein.

[0032] In some embodiments, the electronic device 11 includes a processing chiplet (PC) 22 and a plurality of static random access memory (SRAM) chiplets (SC) 33a, 33b, 33c, and 33d. The PC 22 includes a substrate 14 having an active side (also referred to herein as front-end process (FEOL) 16) and a passive side. In this example, the substrate 14 includes a semiconductor wafer, such as a wafer made of single-crystal silicon.

[0033] In some embodiments, active elements (such as transistors) are formed in the active side of substrate 14. For example, wells and source / drain (S / D) of the transistor are formed on the active side using ion implantation, and gates (such as finFET gates) are formed on the surface of the substrate (e.g., using diffusion and deposition processes), such that FEOL 16 includes wells, S / D and gates of the transistor of FEOL 16 (and, where applicable, other active elements (e.g., diodes)) and / or passive elements (e.g., resistors and capacitors).

[0034] In some embodiments, the electronic device 11 includes a metal connection formed above the transistors of FEOL 16 and configured to interconnect the transistors of FEOL 16 to perform processing functions in PC 22, also referred to herein as back-end process (BEOL) 18. The terms FEOL and BEOL relate to the manufacturing process of a chiplet in which the transistors are formed in the front end of the production line and the interconnects are formed in the back end of the production line. It should be noted that even if a portion of FEOL 16 is formed within substrate 14, the term "substrate 14" still refers to the passive side of the substrate, and the term FEOL 16 refers to the active side of the substrate and the transistors formed therein.

[0035] In some embodiments, each SC 33 includes (i) a substrate 14, which is generally similar to the substrate 14 of PC 22 and has its passive side, (ii) FEOL 15, which includes the active side of the substrate having transistors and other active and passive elements formed therein, and (iii) BEOL 17, which has metal connections for interconnection between the transistors of FEOL 15. It should be noted that FEOL 15 and 16 both have transistors configured in different configurations. For example, the transistors of FEOL 15 are configured with repeating memory cells (e.g., about four or six transistors typically configured in a flip-flop circuit), while the transistors of FEOL 16 are configured with several types of logic libraries that do not typically form a repeating pattern.

[0036] In some embodiments, at current state-of-the-art process nodes, FEOL 16 may include between approximately 10 billion and 80 billion transistors (depending on the wafer size), and therefore BEOL 18 typically includes between approximately eight and twenty metal layers for interconnection between the FEOL transistors. However, SRAM wafers typically include millions of cells, and therefore BEOL 17 requires a much smaller number of metal layers, for example, between approximately two and six metal layers. Due to the different configurations of the FEOL and BEOL of the SRAM wafer, the FEOL and BEOL of PC 22 and SC 33 have different numbers, while the passive side of the substrate is similar, and therefore, the same number 14 is obtained.

[0037] In some embodiments, the electronic device 11 includes one or more (typically hundreds or thousands) through-silicon vias (TSVs) 44 formed along at least a portion of the thickness of PC 22 and SC 33 along a Y-axis. The TSVs 44 are configured to conduct electrical signals between wafers, and more specifically, between PC 22 and SC 33. In the example of FIG1, the TSVs 44 are formed through the entire thickness of the entire wafer, except where the TSVs 44 are not formed in SC 33b of the substrate 14. In other embodiments, the TSVs 44 may be formed only through the substrate 14 and FEOLs 15 and 16, such that the metal layer of the BEOL is used to conduct electrical signals together with the TSVs 44.

[0038] In the background of this invention and within the scope of the invention claims, the passive side surface of the substrate 14 of the chiplet is also referred to herein as the back surface of the chiplet, and the outer surfaces of BEOL 17 and 18 are also referred to herein as the front surface of the chiplet. In these embodiments, the pairs of chipslets of the electronic device 11 can be configured in various configurations (such as face-to-face, back-to-back, or face-to-back). In the example of FIG1, SC 33a and 33b are flipped such that PC 22 and SC 33a are configured in a face-to-face configuration (i.e., FEOL 17 and 18 face each other), and all other pairs of chipslets are configured in a face-to-back configuration (i.e., BEOL 17 and substrate 14 face each other).

[0039] Referring now to illustrations 7, 8, 9, 10 and 13, they show the interface between the small chips of electrical device 11.

[0040] In some embodiments, the electronic device 11 includes a plurality of electrical terminals configured to electrically connect respective pairs of wafers. In this example, such electrical terminals include bumps or microbumps made of copper and having a width (e.g., along the X-axis) between about 10 µm and 30 µm and a height (along the Y-axis) between about 5 µm and 20 µm, referred to herein as bump 19. It should be noted that the TSV 44 is configured to conduct electrical signals between, for example, the processing wafer 22 and at least one of the bumps 19 described in detail below.

[0041] In the examples of Figures 7 and 10, bump 19a is configured to electrically connect between (i) TSV 44a of PC 22 and (ii) TSV 44b of SC 33a and 33c located on both sides of PC 22. In the example of Figure 9, bump 19a is configured to electrically connect between BEOLs 18 and 17 of PC 22 and SC 33a, respectively. However, in the section shown in Figure 8, the back-to-back configuration does not have a TSV, so no electrical signal is conducted, and therefore, this section does not require a bump. It should be noted that when the BEOLs of two small chips face each other, the bump is used to conduct electrical signals between the metal connectors of the BEOLs and, where appropriate, conductive pads (not shown), even if there is no TSV in each section.

[0042] Referring back to illustration 8, in other embodiments, bump 19 may be formed as an interface between the mechanically supporting substrate 14 and BEOL 17. Such bumps may be referred to as dummy bumps, which do not conduct electrical signals. Referring back to illustration 13, a bump 19b is formed between (i) TSV 44d formed through BEOL 17 via SC 33b, and (ii) TSV 44c formed through SC 33a.

[0043] In some embodiments, TSVs 44a, 44b, 44c, and 44d are all similar. In other embodiments, each TSV 44 needs to conduct signals with different properties (such as voltage and current), and therefore, two or more of TSVs 44a, 44b, 44c, and 44d may be different from each other. Each TSV 44 has a predefined length along the Y-axis, a width (e.g., diameter) along the X-axis, and other structural properties (such as sidewall angles). Furthermore, each TSV 44 is filled with a metal (e.g., a copper alloy) of a suitable type with a suitable texture, volume, and sublayer. For example, BEOL 17 is thinner than (along the Y-axis) BEOL 18 (due to having fewer metal layers, as described above), and therefore, TSV 44b is shorter than TSV 44a. Similarly, TSV 44d is shorter than (along the Y-axis) TSV 44c and may include: (i) a different copper alloy and / or (ii) a different width for conducting signals with higher currents and / or voltages between PC 22 and SC 33b.

[0044] Similarly, in some embodiments, bumps 19a and 19b are all similar. In other embodiments, at least two bumps 19a and 19b differ from each other (e.g.) in length and / or width along the Y and X axes, respectively, and / or in the type of one or more of their layers. As described with respect to TSV, the characteristics and structure of each bump 19 are determined based on the nature of the electrical signals conducted through it.

[0045] In some embodiments, differences in certain features of the TSV and bumps (e.g., different materials) require different respective procedural operations, which increase the manufacturing cost of the electronic device 11. Other differences, such as the width (along the X-axis) of different bumps and / or TSVs, can be incorporated into the same procedural operation suitable for the design using one of their respective lithography masks.

[0046] In some embodiments, the electronic device 11 includes a suitable substrate, such as an interposer or any other suitable type of packaging substrate. In this example, the substrate includes a printed circuit board (CB) substrate configured to conduct signals between the electronic device 11 and an external electronic device (not shown) of an electronic system, referred to herein as a CB 12. The electronic device 11 includes a plurality of balls 55 configured to conduct electrical signals between the TSV 44 and the CB 12. In this example, the CB 12 faces an external wafer (e.g., SC 33d), and the balls 55 are disposed between the CB 12 and the SC 33d.

[0047] In some embodiments, the ball 55 is made of any suitable (typically solderable) material, has a typical diameter between about 50 µm and 100 µm, and is formed using any suitable ball grid array (BGA) soldering procedure or any other suitable procedure. In other embodiments, instead of the ball 55, the electronic device 11 may include a land grid array (LGA), a pin grid array (PGA), or any other suitable type of electrical terminal formed between the CB 12 and one or more external wafers of the electronic device 11.

[0048] It should be noted that, depending on the processing and memory capabilities of a particular electronic device, the bandwidth and customization of the electronic device 11 can be improved by vertical three-dimensional (3D) integration of the processing chip 22 and one of the plurality of SRAM chips 33. In this example, the electronic device 11 includes one processing chip and four SRAM chips 33, but in other embodiments, another electronic device may include at least one of the following: (i) a plurality of processing chips, and (ii) different numbers of SRAM chips disposed on both sides and / or different sides of the processing chip. For example, the electronic device may include three SRAM chips 33 stacked on a first side of one of the PC 22 and two SRAM chips 33 stacked on a second side of the electronic device. Furthermore, two or more SRAM chips may be different from each other, and the orientation (front and back sides) of the SRAM chips may be changed to obtain the desired electrical properties of the respective electronic device.

[0049] The configuration of electronic device 11 is provided by way of example to illustrate certain problems solved by embodiments of the present invention and to demonstrate the application of such embodiments in enhancing the performance of such electronic device. However, embodiments of the present invention are by no means limited to this particular type of exemplary electronic device, and the principles described herein can be similarly applied to, for example, other types of electronic devices shown below in Figures 2 and 3.

[0050] FIG2 is a schematic cross-sectional view of an electronic device 21 according to another embodiment described herein.

[0051] In some embodiments, electronic device 21 includes CBs 12a and 12b facing SCs 33b and 33d, respectively. The plurality of CBs 12 reduces the distance required to conduct at least some electrical signals, and thus improves the bandwidth and data rate for processing data within electronic device 21 and / or for transmitting data between electronic device 21 and external devices of the electronic system mentioned above in FIG. 1. Furthermore, electronic device 21 includes balls 55a and 55b for conducting electrical signals between (i) TSV 44 and (ii) CBs 12a and 12b.

[0052] In some embodiments, the PC 22 of electronic device 21 is flipped (inverted) compared to the orientation of PC 22 in electronic device 11 of FIG. 1 above. Furthermore, the orientations of SC 33a, 33b, and 33d are also flipped. In this configuration, PC 22 and SC 33c are configured face-to-face, SC 33a and 33b are configured back-to-back, PC 22 and SC 33a are configured back-to-back, and SC 33c and 33d are also configured back-to-back. It should be noted that in the configuration of electronic device 21, the BEOL 17 of the external SRAM chips (e.g., SC 33b and 33d) faces CB 12a and 12d respectively, which may alter (e.g., improve) the data rate of at least some of the signals transmitted between the stacked chips and CB.

[0053] As described above in Figure 1, the electronic device 21 may include any suitable number of SRAM chips 33 stacked on each side of the PC 22.

[0054] FIG3 is a schematic cross-sectional view of an electronic device 31 according to another embodiment described herein.

[0055] In some embodiments, the orientation of the chiplets of electronic device 31 (i.e., PC 22 and SC 33a to 33d) is similar to that of the chiplets of electronic device 21, but in other embodiments, the number of chiplets and / or the orientation of at least one chiplet may be changed, as described above in Figures 1 and 2.

[0056] In some embodiments, the electronic device 31 includes six CBs 12a, 12b, 12c, 12d, 12e and 12f (CBs 12e and 12f are depicted in a hypothetical plan view) and six sets of balls 55a, 55b, 55c, 55d, 55e and 55f (balls 55f are depicted in a hypothetical plan view) for electrically connecting the CBs to the stacked wafers.

[0057] In some embodiments, each CB 12 faces one of the facets of the stacked wafers. CB 12a and 12b face SC 33b and 33d respectively, as described above in FIG2, and the surfaces of CB 12a and 12b are generally parallel to the outer surfaces of SC 33b and 33d, and are also generally parallel to the outer surfaces of the other wafers of the electronic device 31.

[0058] In some embodiments, the outer surfaces of CB 12c and 12d are generally orthogonal to the front and back sides of PC 22 and SC 33a to 33d, and are electrically connected to the processing of electronic device 31 and some or all of the BEOLs of SRAM chips via balls 55c and 55d, respectively. For example, (i) CB 12c is electrically connected to PC 22 and the BEOLs of SC 33b and 33d via ball 55c, and (ii) CB 12d is electrically connected to the BEOL of PC 22 and the BEOLs of all SRAM chips (e.g., SC 33a to 33d) via ball 55d.

[0059] In some embodiments, the outer surfaces of CB 12e and 12f are generally orthogonal to the front and back sides of PC 22 and SC 33a to 33d, and are electrically connected to the entire BEOL of the electronic device 31 via balls 55e and 55f, respectively. It should be noted that CB 12e and 12f are shown with dashed boxes because they are positioned along the Z-axis of the XYZ coordinate system, such that they are positioned outside the XY plane of the cross-sectional view of FIG3. For example, CB 12e is closer to and CB 12f is further away from the viewer of the cross-sectional view of FIG3 compared to the stacked wafers.

[0060] In some embodiments, balls 55c to 55f are disposed on and typically directly connected to the respective stacked wafer BEOLs of the electronic device 31. In the context of this invention, the term "direct" refers to a connection between a wafer and a respective ball that does not use a TSV. It should be noted that in a so-called direct connection, the electronic device 31 may include one or more layers (e.g., conductive pads) disposed between: (i) CB 12 and the respective ball 55, and (ii) the ball 55 and the respective wafer BEOL.

[0061] In some embodiments, the configuration of electronic device 31 can improve bandwidth and data rate compared to the configuration of one or both of electronic devices 11 and 21. The integration of multiple (e.g., six) CB 12 shortens the distance used for signal transmission, and therefore can also improve the signal integrity and / or power integrity of such electronic devices. Furthermore, the configuration of CB 12 and ball 55 can be changed depending on the specifications of processing and memory capabilities and the number of processing and SRAM chips stacked together in electronic device 31, as described in detail above in Figures 1 and 2.

[0062] The configuration of the electronic device 31 is provided by way of example to illustrate certain problems solved by embodiments of the present invention and to demonstrate the application of such embodiments in enhancing the performance of the electronic device.

[0063] However, embodiments of the present invention are by no means limited to this particular type of exemplary electronic device, and the principles described herein can be similarly applied to, for example, other types of electronic devices shown above in Figures 1 and 2, or to any other suitable configuration in other suitable types of electronic devices.

[0064] Figure 4 is a schematic flowchart illustrating a method for manufacturing an electronic device 31 according to one embodiment described herein. The method begins with an SRAM die-forming operation 100 to produce SC 33 (e.g., SC 33a to 33d) and to form TSV 44 and bumps 19. It should be noted that operation 100 is performed at the wafer scale (i.e., wafer level), such that a plurality (e.g., tens or hundreds) of SRAM dies (including TSV 44) are formed on the wafer (e.g., substrate 14) described above in Figure 1, and subsequently, bumps 19 are formed on the surface of substrate 14 and on the BEOL 17 of the SRAM dies. In the background of this invention and within the scope of the claims, the term "SRAM die" refers to an SRAM die after the formation of TSV 44 and bumps 19 and before dicing the wafer and forming SC 33.

[0065] In an SRAM testing and sorting operation 102, a testing and sorting procedure is performed on all SRAM dies of the wafer to select fully functional (also referred to herein as "good") SRAM dies and to remove non-functional or partially functional (also referred to herein as "bad") SRAM dies. In some embodiments, SRAM dies typically have memory block redundancy, such that in response to the identification of a first memory block as non-functional, data intended to be stored in the first memory block can be stored in a second, different memory block. Alternatively or additionally, various techniques (such as error correction codes (ECC)) are applied to SRAM dies. Memory block redundancy and EEC are used to improve the yield of SRAM dies (i.e., the number of good SRAM dies per wafer).

[0066] In some embodiments, after testing and sorting, the wafer is diced and the SRAM dies are processed to produce SRAM chips 33 that are held for use in the production of electronic devices 31.

[0067] In a logic chiplet formation operation 104, a logic die for manufacturing a processing chiplet 22 is produced at the wafer level, including forming a TSV 44 and bumps 19, as described for an SRAM die in operation 100 above.

[0068] In a logic test and classification operation 106, a test and classification procedure is performed on all logic chips of the wafer to select logic chips that are fully functional (also referred to herein as "good") and to select and discard logic chips that are not functional or partially functional (also referred to herein as "bad").

[0069] In some embodiments, at least one and generally all logic dies have redundancy in one of their CPU cores, such that given data intended to be processed in a non-functional first CPU core can be transferred to a second CPU core in the same logic die for processing. This CPU core redundancy feature can be used to improve the yield of logic dies on a wafer, as described above for SRAM dies in operation 102.

[0070] In some embodiments, after testing and sorting, the wafer is diced and the well-processed logic dies are used to produce a processed chiplet 22 that is held for use in the production of electronic device 31.

[0071] In a 3D integration operation 108, the tested PC 22 and the tested SC 33a to 33d are stacked together, as shown in the cross-sectional view of the electronic device 31 (excluding CB 12) shown and described in detail above in Figure 3.

[0072] In a stack test operation 110, a testing and classification process is performed on the stacked wafers formed in operation 108. In some embodiments, redundancy in memory and CPU cores, as well as ECC technology, are used to improve the yield of the tested stacked wafers. Operation 110 ends with one or more cells of PC 22 and SC 33a to 33d that have been tested and are in good condition, as shown above in Figure 3.

[0073] In a substrate integration operation 112, balls 55 are generated on the tested stack of PC 22 and SC 33a to 33d and / or on CB 12a to 12f, and the tested stack of PC 22 and SC 33a to 33d is integrated with CB 12a to 12f to produce an electronic device 31 whose structure and functionality are described in Figure 3 above.

[0074] After completing one of the final test operations 114 of the method, the electronic device 31 is tested and, after successfully passing the test, the electronic device 31 is ready for use in any suitable electronic system.

[0075] In other embodiments, at least one of the testing and sorting operations (e.g., operations 102, 106, 110 and 114) may be partially performed (e.g., some tests are performed on all or some of the dies and / or wafers and / or electronic devices intended to be tested) or may be skipped in order to reduce the production cost of electronic device 31.

[0076] It should be noted that the embodiments described above are by way of example, and the present invention is not limited to the content specifically shown and described above. In fact, the scope of the present invention includes both combinations and sub-combinations of the various features described above, as well as variations and modifications of the invention that would occur to those skilled in the art after reading the foregoing description and which were not disclosed in the prior art. Documents incorporated herein by reference shall be considered an integral part of the application, except that any terminology defined in these incorporated documents in a manner that conflicts with the definitions expressly or implicitly made in this specification shall be considered solely in accordance with the definitions in this specification. [Simplified Explanation of the Diagram]

[0013] Figures 1, 2 and 3 are schematic cross-sectional views of respective electronic devices according to embodiments described herein; and

[0014] Figure 4 is a schematic flowchart illustrating a method for producing the electronic device of Figure 3 according to one embodiment described herein.

Claims

1. An electronic device comprising: A processing chiplet configured to process data and having a first side and a second side; one or more first static random access memory (SRAM) chipslets, or the like, disposed on the first side of the processing chiplet and configured to store a first portion of the data; one or more second SRAM chipslets, or the like, disposed on the second side of the processing chiplet and configured to store a second portion of the data; one or more first electrical terminals, or the like, disposed on the first side of the processing chiplet and configured to electrically connect the first side of the processing chiplet to the one or more first SRAM chipslets; One or more second electrical terminals, or the like, disposed on the second side of the processing chip and configured to electrically connect the second side of the processing chip to the one or more second SRAM chips; and one or more through-silicon vias (TSVs) formed through at least a portion of the processing chip and configured to conduct electrical signals between the processing chip and at least one of the first and second electrical terminals.

2. The electronic device of claim 1, wherein the one or more first SRAM chips include at least first and second given SRAM chips, and wherein the first given SRAM chip includes: (i) a first given side facing the first side of the processing chip and connected to the one or more first electrical terminals, and (ii) a second given side facing the second given SRAM chip stacked on the first given SRAM chip.

3. The electronic device of claim 2, wherein the first given side of the first given SRAM chip is disposed on one or more first electrical terminals of at least a portion of the first portion configured to exchange data between the processing chip and the first given SRAM chip.

4. The electronic device of claim 2, further comprising one or more third electrical terminals disposed on a second side of one of the first given SRAM chips and configured to electrically connect the second side of the first given SRAM chip to the second given SRAM chip.

5. The electronic device of claim 2, further comprising one or more given TSVs formed through at least a portion of the first given SRAM chip and configured to conduct electrical signals between the processing chip and at least one of the first and second given SRAM chips.

6. The electronic device of claim 5, wherein at least one of the TSVs and at least one of the given TSVs are different from each other.

7. The electronic device of claim 6, wherein at least one of the TSVs: (i) has a first length passing through at least a portion of the processing wafer, (ii) has a first width along the first side of the processing wafer, and (iii) contains a first metal layer having a first volume within the processing wafer, and the at least one of the given TSVs: (a) has a second length passing through at least a portion of the first given SRAM wafer, (b) has a second width along the second side of the first given SRAM wafer, and (c) contains a second metal layer having a second volume within the first given SRAM wafer, and wherein at least one of the first and second items is different from each other: (1) length, (2) width, (3) metal layer and (4) volume.

8. The electronic device of claim 2, wherein the processing chip is formed on a first substrate and includes a first metal interconnect, and at least the first and second given SRAM chips are formed on a second substrate and include a second metal interconnect.

9. The electronic device of claim 8, wherein the first side includes a first surface of one of the first substrates and the second side includes the first metal interconnects, and wherein the second side includes: (i) a second surface of one of the second substrates, or (ii) the second metal interconnects.

10. The electronic device of claim 1, wherein the first and second SRAM chips comprise a first and a second number of SRAM chips, wherein the first and second numbers are different from each other.

11. The electronic device of claim 1, wherein the first and second SRAM chips comprise a first and a second number of SRAM chips, wherein the first and second numbers are equal to each other.

12. The electronic device of claim 1, further comprising at least one of the following: (i) a first circuit board (CB) substrate facing a first external SRAM chip of one of the first SRAM chips, (ii) a second CB substrate facing a second external SRAM chip of one of the second SRAM chips, and (iii) one or more third CB substrates, which or the others face one or more edges of the electronic device, wherein at least one of the edges is orthogonal to at least one of the first side, the second side and a third side.

13. The electronic device of claim 12, further comprising a third electrical terminal disposed on at least one of the first, second and third CB substrates and configured to conduct signals between: (i) at least one of the first, second and third CB substrates, and (ii) at least one of: (a) a processing chip, (b) one or more of the first SRAM chips, and (c) one or more of the second SRAM chips.

14. A method for producing an electronic device, the method comprising: One or more first static random access memory (SRAM) chips are disposed on the first side of a processing chip having a first side and a second side; one or more second SRAM chips are disposed on the second side of the processing chip; one or more first electrical terminals are disposed on the first side of the processing chip for electrical connection between the first side of the processing chip and the one or more first SRAM chips; one or more second electrical terminals are disposed on the second side of the processing chip for electrical connection between the second side of the processing chip and the one or more second SRAM chips; and one or more through-silicon vias (TSVs) are formed through at least a portion of the processing chip for conducting electrical signals between the processing chip and at least one of the first and second electrical terminals.

15. The method of claim 14, wherein placing the one or more first SRAM chips includes placing at least first and second given SRAM chips, wherein the first given SRAM chip comprises: (i) a first given side, which is positioned to face the first side of the processing chip and connected to the one or more first electrical terminals, and (ii) a second given side, which is positioned to face the second given SRAM chip stacked on the first given SRAM chip.

16. The method of claim 14 further includes placing at least one of the following: (i) a first circuit board (CB) substrate facing a first external SRAM chip of one of the first SRAM chips, (ii) a second CB substrate facing a second external SRAM chip of one of the second SRAM chips, and (iii) one or more third CB substrates, which or the others face one or more edges of the electronic device, wherein at least one of the edges is orthogonal to at least one of the first side, the second side and a third side.

17. The method of claim 16 further includes placing a third electrical terminal on at least one of the first, second and third CB substrates for conducting signals between: (i) at least one of the first, second and third CB substrates, and (ii) at least one of: (a) a processing chiplet, (b) one or more of the first SRAM chipslet, and (c) one or more of the second SRAM chipslet.

18. The method of claim 14 further includes testing at least one of the following: (i) processing a chiplet, (ii) one or more of the first SRAM chipslets, (iii) one or more of the second SRAM chipslets, (iv) a stack of the processing chipslet including being electrically connected to at least one of the first and second SRAM chipslets, and (v) being electrically connected to one or more circuit board (CB) substrates of the stack.

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