Semiconductor device and method of manufacturing the same

Abstract

A source region, a drain region, a buried insulating film, a gate insulating film, and a gate electrode of a semiconductor device are formed in a main surface of a semiconductor substrate. The buried insulating film is buried in a first trench formed between the source region and the drain region. The first trench has a first side surface and a first bottom surface. The first side surface faces the source region in a first direction extending from one of the source and drain regions to the other. The first bottom surface is connected to the first side surface and runs along the main surface of the semiconductor substrate. A crystal plane system (111) plane is formed on the first surface of the semiconductor substrate, which is the first side surface of the first trench. A crystal plane system (100) plane is formed on the second surface of the semiconductor substrate, which is the bottom surface of the first trench.

Description

[Previous Technology]

[0001] This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device comprising a lateral double-diffused MOS (LDMOS) and a method for manufacturing the same.

[0002] A semiconductor device comprising a laterally diffused MOS (LDMOS) is known (see, for example, Non-Patent Document 1). The semiconductor device described in Non-Patent Document 1 has a source region and a drain region formed in a main surface of a semiconductor substrate, and a buried insulating film formed in a trench formed between the source region and the drain region. The trench has a first side surface facing the source region, a second side surface facing the drain region, and a bottom surface connecting the first side surface and the second side surface to each other. Non-Patent Document 1 discloses that the on-resistance can decrease as an interior angle of the trench formed by the first side surface and the bottom surface increases.

[0003] The disclosed technologies are listed below. [Non-Patent Document 1] S. Haynie et al., "Power LDMOS with Novel STI Profile for Improved Rsp, BVdss, and Reliability" (Proceedings of the 22nd International Symposium on Power Semiconductor Devices and ICs, Hiroshima) [Summary of the Invention]

[0004] The trenches in the conventional semiconductor device described above are formed by, for example, a dry etching method. Therefore, the aforementioned interior angles of the trenches formed from the first side surface and the bottom surface vary depending on conditions such as trench size and pattern density. Consequently, the characteristics of the semiconductor device also change. That is, from the viewpoint of improving the characteristics of the semiconductor device, there is room for improvement in conventional semiconductor devices.

[0005] One objective of this embodiment is to improve the characteristics of a semiconductor device. Other objectives and novel features will be understood from the description in this specification and the drawings.

[0006] A semiconductor device according to one embodiment includes: a source region formed in a main surface of a semiconductor substrate; a drain region separated from the source region and formed in the main surface of the semiconductor substrate; a buried insulating film embedded in a first trench formed in the main surface of the semiconductor substrate between the source region and the drain region in a plan view; a gate insulating film formed on a portion of the main surface of the semiconductor substrate positioned between the source region and the drain region; and a gate electrode formed on the gate insulating film such that one end portion is positioned on the buried insulating film. The first trench has a first side surface facing the source region in a first direction extending from one of the source region and the drain region to the other, and a first bottom surface connected to the first side surface and along the main surface of the semiconductor substrate. A crystal plane of the first surface of the semiconductor substrate, which is the first side surface of the first trench, is a (111) plane. A crystal plane (100) is a second surface of the semiconductor substrate, which is the bottom surface of the first trench.

[0007] A method of manufacturing a semiconductor device according to an embodiment includes: forming a first trench in a main surface of a semiconductor substrate by a wet etching method; forming a buried insulating film in the main surface of the semiconductor substrate by filling the first trench with an insulating film; forming a gate electrode on the main surface of the semiconductor substrate via a gate insulating film such that one end portion of the gate electrode is positioned on the buried insulating film; and forming a source region and a drain region separated from each other in the main surface of the semiconductor substrate by an ion implantation method. The first trench has a first side surface facing the source region in a first direction extending from one of the source region and the drain region to the other, and a first bottom surface connected to the first side surface and along the main surface of the semiconductor substrate. A crystal plane of the first surface of the semiconductor substrate, which is the first side surface of the first trench, is a (111) plane. A crystal plane (100) is a second surface of the semiconductor substrate, which is the bottom surface of the first trench.

[0008] According to one embodiment, the characteristics of the semiconductor device can be improved.

Implementation Method

[0010] In the following, a semiconductor device according to an embodiment will be described in detail with reference to the accompanying drawings. It should be noted that in the specification and drawings, the same components or corresponding components are represented by the same element symbols or shaded lines, and redundant descriptions of such components are omitted. Furthermore, in the drawings, configurations may be omitted or simplified in some cases for ease of description. In some cases, shaded lines are even added to a plan view. In some cases, a cross-sectional view may be shown as an end view. At least some of the embodiments and modifications may be combined as appropriate.

[0011] [First Embodiment] FIG1 is a plan view showing an example of a configuration of a main portion of a semiconductor device SD1 according to a first embodiment. FIG2 is a cross-sectional view showing an example of a configuration of the main portion of the semiconductor device SD1 according to the first embodiment. FIG2 is a cross-sectional view along line AA in FIG1.

[0012] In Figures 1 and 2, an X direction (first direction) and a Y direction (second direction) are each along a main surface of a semiconductor substrate SUB. The X direction extends from one of a source region SR and a drain region DR to the other. In a planar view, the Y direction is orthogonal to the X direction. A Z direction (third direction) is the thickness direction of the semiconductor substrate SUB. The X, Y, and Z directions are orthogonal to each other.

[0013] The semiconductor device SD1 includes a semiconductor substrate SUB, a buried insulating film BIF1, a component isolation film EIF, a gate insulating film GIF, a gate electrode GE, an insulating layer IL, a first contact plug CP1, a second contact plug CP2 and a wiring WR.

[0014] The semiconductor substrate SUB is, for example, a silicon substrate of p-conductivity or n-conductivity. The semiconductor substrate SUB has a main surface MSF and a back surface BSF opposite to the main surface MSF. The main surface MSF of the semiconductor substrate SUB is a device forming surface on which a semiconductor device is formed. The crystal plane of the main surface MSF of the semiconductor substrate SUB is a (100) plane. In this specification, a predetermined crystal plane includes a crystal plane equivalent to that crystal plane. For example, the (100) plane and the (010) plane are equivalent to each other. It should be noted that "crystal plane" means a lattice plane represented by the Miller index.

[0015] A source region SR, a back gate region BGR, a drain region DR, a host region BR and a drift region DFTR are formed in a semiconductor substrate SUB.

[0016] The source region SR is formed in the main surface MSF of the semiconductor substrate SUB. In a first embodiment, the source region SR is formed to surround the back gate region BGR in a planar view. The source region SR has a first conductivity type. The first conductivity type is p-type or n-type. The impurity concentration of the source region SR is, for example, 1×10¹⁷ cm⁻³ or greater and 1×10²¹ cm⁻³ or less.

[0017] The back gate region (BGR) is formed in the main surface (MSF) of the semiconductor substrate (SUB). The back gate region (BGR) is formed to be surrounded by the source region (SR) in the X direction. The back gate region (BGR) has a second conductivity type different from the first conductivity type. The second conductivity type is p-type or n-type. The impurity concentration of the back gate region (BGR) is, for example, 1 × 10¹⁷ cm⁻³ or greater and 1 × 10²¹ cm⁻³ or less.

[0018] The drain region DR is formed in the main surface MSF of the semiconductor substrate SUB. The drain region DR is separated from the source region SR. The drain region DR has the first conductivity type described above. The impurity concentration of the drain region DR is, for example, 1×10¹⁷ cm⁻³ or greater and 1×10²¹ cm⁻³ or less.

[0019] The host region BR is formed in the main surface MSF of the semiconductor substrate SUB to surround the source region SR and the back gate region BGR. The host region BR is in direct contact with the source region SR and the back gate region BGR. The host region BR has the aforementioned first conductivity type. The impurity concentration of the host region BR is, for example, 1×10¹⁴ cm⁻³ or greater and 1×10¹⁸ cm⁻³ or less.

[0020] A drift region DFTR is formed in the main surface MSF of the semiconductor substrate SUB to at least surround the drain region DR. The drift region DFTR surrounds the drain region DR and the buried insulating film BIF1. The drift region DFTR is separated from the main body region BR. The drift region DFTR is in direct contact with the drain region DR and the buried insulating film BIF1. The drift region DFTR has the aforementioned second conductivity type. The impurity concentration of the drift region DFTR is, for example, 1×10¹⁴ cm⁻³ or greater and 1×10¹⁸ cm⁻³ or less.

[0021] A first trench TR11 and a second trench TR2 are formed in the main surface MSF of the semiconductor substrate SUB.

[0022] A first trench TR11 is formed in a planar view between the source region SR and the drain region DR in the main surface MSF of the semiconductor substrate SUB. In a first embodiment, the entire first trench TR11 is formed in a planar view between the source region SR and the drain region DR. The first trench TR11 is formed to surround the source region SR and the back gate region BGR in a planar view. The first trench TR11 is separated from each of the source region SR, the drain region DR, and the back gate region BGR. The first trench TR11 has a first side surface SSF1, a second side surface SSF2, and a first bottom surface BSF1. The first trench TR11 has a substantially annular shape in a planar view. Alternatively, the first trench TR11 may have a linear shape along the Y direction in a planar view.

[0023] The first side surface SSF1 faces the source region SR in the X direction. The first side surface SSF1 faces the source region SR via a portion of the semiconductor substrate SUB. The crystal plane system (111) plane of the first surface SF1 of the semiconductor substrate SUB, which is the first side surface SSF1 of the first trench TR11. The crystal plane system (111) plane of the entire first surface SF1.

[0024] The first bottom surface BSF1 is connected to both the first side surface SSF1 and the second side surface SSF2. The first bottom surface BSF1 is along the main surface MSF of the semiconductor substrate SUB. The entire first bottom surface BSF1 is along the main surface MSF of the semiconductor substrate SUB. The first bottom surface BSF1, which is the first trench TR11, is a crystal plane system (100) plane of the second surface SF2 of the semiconductor substrate SUB. The entire second surface SF2 of the semiconductor substrate SUB is a crystal plane system (100) plane. The crystal plane of the second surface SF2 of the semiconductor substrate SUB is the same as the crystal plane of the main surface MSF of the semiconductor substrate SUB.

[0025] The second side surface SSF2 faces the drain region DR in the X direction. The second side surface SSF2 is in direct contact with the drain region DR. The second side surface SSF2 is positioned on the opposite side of the first side surface SSF1 in the X direction. The crystal plane system (111) plane of the third surface SF3, which is one of the semiconductor substrate SUBs of the second side surface SSF2 of the first trench TR11. The entire crystal plane system (111) plane of the third surface SF3.

[0026] A second trench TR2 is formed to surround a first trench TR11 in the main surface MSF of a semiconductor substrate SUB. The second trench TR2 is separate from the first trench TR11. The second trench TR2 surrounds the source region SR, the drain region DR, and the gate electrode GE in a planar view. The second trench TR2 has a third side surface SSF3 and a second bottom surface BSF2.

[0027] The third side surface SSF3 faces the source region SR or the drain region DR in the X direction. In the first embodiment, the third side surface SSF3 faces the drain region DR in the X direction. The third side surface SSF3 is in direct contact with the drain region DR. The crystal plane of the fourth surface SF4, which is one of the semiconductor substrate SUBs of the third side surface SSF3 of the second trench TR2, is not specifically limited. The fourth surface SF4 may or may not have a specific crystal plane. The fourth surface SF4 may have a crystal plane such as (111) plane.

[0028] The crystal plane of the fourth plane SF4 may be the same as or different from the crystal plane of the first surface SF1 and the crystal plane of the third surface SF3. In the first embodiment, the fourth surface SF4 does not have a specific crystal plane.

[0029] The second bottom surface BSF2 is connected to the third side surface SSF3. The second bottom surface BSF2 runs along the main surface MSF of the semiconductor substrate SUB. The entire second bottom surface BSF2 runs along the main surface MSF of the semiconductor substrate SUB.

[0030] The first interior angle θ1 of one of the first trenches TR11 formed by the first bottom surface BSF1 and the first side surface SSF1 is greater than the second interior angle θ2 of the second trench TR2 formed by the second bottom surface BSF2 and the third side surface SSF3 (θ1 > θ2). From the viewpoint that the device isolation characteristics are improved by the device isolation film EIF while reducing the on-resistance between the source region SR and the drain region DR, this is better.

[0031] The buried insulating film BIF1 is buried in the first trench TR11. The buried insulating film BIF1 is formed in the main surface MSF of the semiconductor substrate SUB. The thickness of the buried insulating film BIF1 is not specifically limited, as long as the required withstand voltage and on-resistance can be achieved simultaneously. The material of the buried insulating film BIF1 is, for example, silicon oxide.

[0032] The device isolation film EIF is buried in the second trench TR2. The device isolation film EIF is formed in the main surface MSF of the semiconductor substrate SUB. The thickness of the device isolation film EIF is not specifically limited, as long as the desired device isolation characteristics are achieved. The thickness of the device isolation film EIF is preferably greater than the thickness of the buried insulating film BIF1. Therefore, the device isolation characteristics can be improved, while achieving the desired withstand voltage and on-resistance. The material of the device isolation film EIF is, for example, silicon oxide.

[0033] A gate insulating film GIF is formed on a portion of the main surface MSF of a semiconductor substrate SUB located between the source region SR and the drain region DR, which are separated from each other. The gate insulating film GIF is adjacent to the buried insulating film BIF1. The thickness of the gate insulating film GIF is, for example, 2 nm or greater and 100 nm or less. The material of the gate insulating film GIF is, for example, silicon oxide.

[0034] The gate electrode GE is formed on the gate insulating film GIF. The gate electrode GE is formed on the main surface MSF of the semiconductor substrate SUB via the gate insulating film GIF. As shown in Figure 2, one end of the gate electrode GE is positioned on the buried insulating film BIF1. The material of the gate electrode GE is, for example, conductive polycrystalline silicon.

[0035] An insulating layer IL is formed on the main surface MSF of the semiconductor substrate SUB to cover the gate electrode GE. The thickness of the insulating layer IL is, for example, 50 nm or more and 1 µm or less. The material of the insulating layer IL is, for example, silicon oxide.

[0036] A first contact plug CP1 is formed in the insulating layer IL to reach the drain region DR. The first contact plug CP1 can employ one of the known configurations used in semiconductor technology as a contact plug (via). The first contact plug CP1 has, for example, a barrier film and a conductive film formed on the barrier film. Examples of materials for the barrier film include titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). The conductive film is made of, for example, tungsten (W), aluminum (Al), or copper (Cu).

[0037] A second contact plug CP2 is formed in the insulating layer IL to reach both the source region SR and the back gate region BGR. One part of the second contact plug CP2 reaches the source region SR. Another part of the second contact plug CP2 reaches the back gate region BGR. The configuration example of the second contact plug CP2 is the same as the configuration example of the first contact plug CP1.

[0038] Wiring WR is formed on insulating layer IL. Wiring WR contacts first contact plug CP1 or second contact plug CP2. As wiring WR, a known configuration used as a wiring in semiconductor technology can be adopted. Wiring WR is, for example, a stacked film in which a barrier metal, a conductive film, and a barrier metal are stacked in this order. Examples of materials constituting the barrier metal include titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). Examples of materials constituting the conductive film include aluminum, copper, and tungsten.

[0039] (Method for Manufacturing a Semiconductor Device) Next, an example of a method for manufacturing a semiconductor device SD1 according to the first embodiment will be described. Figures 3 to 9 are cross-sectional views showing an example of the steps included in the method for manufacturing the semiconductor device SD1.

[0040] A method for manufacturing a semiconductor device SD1 includes, for example, (1) a step of preparing a semiconductor substrate SUB; (2) a step of forming a second trench TR2; (3) a step of forming a first trench TR11; (4) a step of forming a buried insulating film BIF1 and a device isolation film EIF; (5) a step of forming a gate insulating film GIF and a gate electrode GE; (6) a step of forming a source region SR, a drain region DR and a back gate region BGR; and (7) a step of forming an insulating layer IL, a first contact plug CP1, a second contact plug CP2 and wiring WR.

[0041] (1) Fabrication of Semiconductor Substrate SUB First, as shown in FIG3A, a semiconductor substrate SUB is fabricated. The semiconductor substrate SUB can be purchased or manufactured as a commercially available product. In a first embodiment, a host region BR and a drift region DFTR are formed in the semiconductor substrate SUB. An insulating film IF is formed in the main surface MSF of the semiconductor substrate SUB. The insulating film IF is, for example, a stacked film of a silicon oxide film and a silicon nitride film formed on the silicon oxide film. The method for forming the host region BR and the drift region DFTR is, for example, an ion implantation method. The method for forming the insulating film IF is, for example, a thermal oxidation method or a CVD method.

[0042] (2) Formation of the Second Trench TR2 Next, as shown in FIG4, a second trench TR2 is formed in the main surface MSF of the semiconductor substrate SUB. At this time, the insulating film IF can be used as an etching mask. The second trench TR2 is formed to surround the region in which the source region SR, drain region DR and gate electrode GE are formed in a planar view. The method for forming the second trench TR2 is, for example, a dry etching method or a wet etching method. The method for forming the second trench TR2 is preferably a dry etching method. Therefore, the second interior angle θ2 of the second trench TR2 (see FIG2) can be made smaller than the first interior angle θ1 of the first trench TR11. When the second trench TR2 is formed by a wet etching method, one example of the etching solution is the same as the etching solution used to form the first trench TR11.

[0043] (3) Formation of the first trench TR11 Next, as shown in FIG5, a first trench TR11 is formed in the first surface SF1 of the semiconductor substrate SUB. At this time, the insulating film IF can be used as an etching mask. The method for forming the first trench TR11 is a wet etching method. The etching rate varies depending on the crystal orientation of the semiconductor substrate SUB. Therefore, the surface of the semiconductor substrate SUB forming the inner surface of the first trench TR11 is composed of crystal planes with the lowest etching rate. In the first embodiment, the crystal plane system (111) plane of the first surface SF1 of the semiconductor substrate SUB corresponding to the first side surface SSF1 of the first trench TR11. The crystal plane system (111) plane of the third surface SF3 of the semiconductor substrate SUB corresponding to the second side surface SSF2 of the first trench TR11. The crystal plane system (100) plane of the second surface SF2 of the semiconductor substrate SUB corresponding to the first bottom surface BSF1 of the first trench TR11. In this case, the first interior angle θ1 of the first trench TR11 is 125 degrees or greater and 130 degrees or less. Therefore, it can be inferred that the first trench TR11 is formed by a wet etching method.

[0044] The etching solution used to form the first trench TR11 is, for example, an aqueous solution of potassium hydroxide (KOH), an aqueous solution of tetramethylammonium hydroxide (TMAH), an aqueous solution of ethylenediamine-catechol (EDP), an aqueous solution of hydrazine (N2H4), an aqueous solution of sodium hydroxide, or an aqueous solution of cesium hydroxide (CsOH).

[0045] (4) Formation of the buried insulating film BIF1 and the component isolation film EIF Next, as shown in FIG6, the buried insulating film BIF and the component isolation film EIF are formed. Specifically, an insulating film is buried in the first trench TR11 and the second trench TR2. The method for forming the insulating film is, for example, a CVD method. An excess portion of the insulating film formed outside the first trench TR11 and the second trench TR2 and the insulating film EIF are removed by, for example, a CMP method.

[0046] (5) Formation of Gate Insulating Film GIF and Gate Electrode GE Next, as shown in FIG7, a gate insulating film GIF and a gate electrode GE are formed on the main surface MSF of the semiconductor substrate SUB. The gate electrode GE is formed on the gate insulating film GIF. The gate electrode GE is formed such that one end portion of the gate electrode GE is positioned on the buried insulating film BIF1. The gate electrode GE is formed on the main surface MSF of the semiconductor substrate SUB via the gate insulating film GIF. Specifically, a stacked film is formed on the main surface MSF of the semiconductor substrate SUB, consisting of an insulating film for the gate insulating film GIF and a conductive film for the gate electrode GE. Next, the stacked film is patterned into a desired shape. The method for forming the insulating film is, for example, thermal oxidation or CVD. The method for forming the conductive film is, for example, CVD. The method for patterning the stacked film is, for example, photolithography and dry etching.

[0047] (6) Formation of source region SR, drain region DR and back gate region BGR Next, as shown in FIG8, source region SR, drain region DR and back gate region BGR are formed in the main surface MSF of semiconductor substrate SUB. Source region SR is formed adjacent to gate electrode GE in a planar view. Drain region DR is formed adjacent to buried insulating film BIF1 in a planar view. The method for forming source region SR, drain region DR and back gate region BGR is, for example, an ion implantation method.

[0048] (7) Formation of insulating layer IL, first contact plug CP1, second contact plug CP2 and wiring WR Next, as shown in FIG9, a wiring layer comprising insulating layer IL, first contact plug CP1, second contact plug CP2 and wiring WR is formed on semiconductor substrate SUB. As a method for forming the wiring layer, a known method as one of the methods for forming multilayer wiring layers in semiconductor technology can be used.

[0049] The method for forming the insulating layer IL is, for example, a CVD method. A first contact plug CP1 and a second contact plug CP2 are formed by forming a through hole in the insulating layer IL and then filling the through hole with a conductive material. A conductive film is formed on the insulating layer IL by sputtering and then patterning the conductive film into a desired shape to form a wiring WR.

[0050] The semiconductor device SD1 according to the first embodiment can be manufactured by the above manufacturing method.

[0051] (Effect) In the semiconductor device SD1 according to the first embodiment, the first surface SF1 of the semiconductor substrate SUB, which serves as the first side surface SSF1 of the first trench TR11, is a crystal plane system (111). The second surface SF2 of the semiconductor substrate SUB, which serves as the first bottom surface BSF1 of the first trench TR11, is a crystal plane system (100). The first trench TR11 is formed by a wet etching method. Since the etching rate varies depending on the lattice plane, the first trench TR11 is composed of the surface of the semiconductor substrate SUB having a predetermined lattice plane. Since the shape of the first trench TR11 is defined by the lattice plane of the semiconductor substrate SUB, compared to the case where the first trench TR11 is formed by a dry etching method, the shape of the first trench TR11 is less likely to fluctuate depending on the size and pattern density of the trench TR11. Furthermore, compared to the case where the first trench TR11 is formed by dry etching, the first side surface SSF1 facing the source region SR in the X direction becomes a more gently sloping surface. Therefore, shock ionization occurring at the corner portion of the first trench TR11 located near the intersection of the first surface SF1 and the second surface SF2 can be reduced. Therefore, the on-resistance between the source region SR and the drain region DR can be reduced. Therefore, the characteristics of the semiconductor device SD1 can be improved.

[0052] [Second Embodiment] The semiconductor device SD2 according to the second embodiment differs from the semiconductor device SD1 according to the first embodiment mainly in the shape of a first trench TR12, the shape of a buried insulating film BIF2, and the position of the components. Therefore, in the following text, components that are the same as those in the semiconductor device SD1 according to the first embodiment are represented by the same element symbols, and their descriptions are omitted.

[0053] FIG10 is a plan view showing an example of a configuration of the main portion of the semiconductor device SD2 according to the second embodiment. FIG11 is a cross-sectional view showing an example of a configuration of the main portion of the semiconductor device SD2. FIG11 is a cross-sectional view along line AA in FIG10.

[0054] The semiconductor device SD2 includes a semiconductor substrate SUB, a buried insulating film BIF2, a component isolation film EIF, a gate insulating film GIF, a gate electrode GE, a sidewall insulating film SW, an insulating layer IL, a first contact plug CP1, a second contact plug CP2, and wiring WR.

[0055] The source region SR, back gate region BGR, drain region DR, body region BR, and drift region DFTR are formed in the semiconductor substrate SUB. In the second embodiment, the positions of each region are different from those in the first embodiment.

[0056] The source region SR is formed in the main surface MSF of the semiconductor substrate SUB. The source region SR is in contact with the device isolation film EIF via the back gate region BGR. In the second embodiment, the source region SR is formed to be surrounded by the back gate region BGR in a planar view.

[0057] The back gate region BGR is formed in the main surface MSF of the semiconductor substrate SUB. The back gate region BGR is formed to be sandwiched between the source region SR and the device isolation film EIF in the X direction.

[0058] The drain region DR is formed in the main surface MSF of the semiconductor substrate SUB. The drain region DR is separated from the source region SR. The drain region DR is formed such that the upper surface of the drain region DR is exposed from the buried insulating film BIF2 in a planar view.

[0059] The main body region BR is formed in the main surface MSF of the semiconductor substrate SUB to surround the source region SR and the back gate region BGR. The main body region BR is in direct contact with the source region SR, the back gate region BGR and the device isolation film EIF.

[0060] The drift region DFTR is formed in the main surface MSF of the semiconductor substrate SUB to at least surround the drain region DR. The drift region DFTR surrounds the drain region DR and the buried insulating film BIF2. The drift region DFTR is separated from the main region BR. The drift region DFTR is in direct contact with the drain region DR.

[0061] The first trench TR12 and the trench TR2 are formed in the main surface of the semiconductor substrate SUB.

[0062] A first trench TR12 is formed in a planar view between a source region SR and a drain region DR in the main surface MSF of a semiconductor substrate SUB. A portion of the first trench TR12 is formed in a planar view between the source region SR and the drain region DR. Another portion of the first trench TR12 overlaps with the drain region DR. The first trench TR12 is formed to be surrounded by the source region SR in a planar view. The first trench TR12 is separated from the source region SR. The first trench TR12 has a first side surface SSF1 and a first bottom surface BSF1. In a second embodiment, the first trench TR12 does not have a second side surface SSF2. The first trench TR12 has a substantially rectangular shape in a planar view. A portion of the first bottom surface BSF1 is the upper surface of the drain region DR.

[0063] The third side surface SSF3 of the second groove TR2 is directed toward the source region SR or drawer region DR in the X direction. In a second embodiment, the third side surface SSF3 faces the source region SR via the back gate region BGR in the X direction. The third side surface SSF3 is in indirect contact with the source region SR via the back-gated pole region BGR.

[0064] The buried insulating film BIF2 is embedded in the first groove TR12. In a second embodiment, the buried insulation film BIF2 is embedded in a portion of the first groove TR12 such that the drawer region DR is exposed from the buried insulation film BIF2 in a plan view. Buried insulating film BIF2 formed in the main surface MSF of the semiconductor substrate SUB. The thickness of the buried insulation film BIF2 is not subject to specific restrictions, as long as the desired voltage resistance and on-resistance can be achieved simultaneously. The material in which the insulating film BIF2 is buried is, for example, silicon oxide.

[0065] One of the penetrating portions of the DR reaching the drain zone is formed in the buried insulating film BIF2. One of the inner surfaces of the penetrating part of the PP is formed continuously with one of the side surfaces of the sidewall insulating film SW. Therefore, the use of sidewall insulating film SW as an etching mask can be employed to form the penetrating portion of PP. Therefore, the fabrication procedure of the semiconductor device SD2 can be simplified.

[0066] The sidewall insulation film SW is formed on the main surface MSF of the semiconductor substrate SUB to make direct contact with the side surface of the gate electrode GE. The material of the sidewall insulating film SW is, for example, silicon oxide.

[0067] The insulating layer IL is formed on the main surface MSF of the semiconductor substrate SUB to cover the gate electrode GE. A portion of the insulating layer IL is embedded in the penetrating portion PP.

[0068] A portion (lower portion) of the first contact plug CP1 is formed in the penetrating portion PP. The above portion of the first contact plug CP1 is in direct or indirect contact with the inner surface of the buried insulating film BIF2. In a second embodiment, the above-mentioned portion of the first contact plug CP1 is in contact with the inner surface of the buried insulating film BIF2 through the above-mentioned portion of the insulating layer IL. In the penetrating portion PP, the above portion of the insulating layer IL is formed between the first contact plug CP1 and the buried insulating film BIF2. When the material of the insulating layer IL is a low dielectric constant film, the fact that the above part of the first contact plug CP1 is in contact with the inner surface of the embedded insulating film BIF2 through the above part of the insulating layer IL is better from the point of view that the parasitic capacitance between the draw zone DR and the gate electrode GE can be further reduced.

[0069] (Method for Manufacturing a Semiconductor Device) Next, an example of a method for manufacturing a semiconductor device SD2 according to the second embodiment will be described. Figures 12 to 19 are cross-sectional views showing an example of the steps included in the method for manufacturing the semiconductor device SD2.

[0070] A method for manufacturing a semiconductor device SD2 includes, for example, (1) a step of preparing a semiconductor substrate SUB; (2) a step of forming a second trench TR2; (3) a step of forming a first trench TR12; (4) a step of forming a buried insulating film BIF2 and a device isolation film EIF; (5) a step of forming a gate insulating film GIF, a gate electrode GE and a sidewall insulating film SW; (6) a step of forming a through portion PP; (7) a step of forming a source region SR, a drain region DR and a back gate region BGR; and (8) a step of forming an insulating layer IL, a first contact plug CP1, a second contact plug CP2 and wiring WR.

[0071] (1) Preparation of semiconductor substrate SUB First, as shown in FIG12, a semiconductor substrate SUB is prepared. The method for preparing the semiconductor substrate SUB is the same as one step of preparing the semiconductor substrate SUB in (1) of the first embodiment.

[0072] (2) Formation of the second trench TR2 Next, as shown in FIG13, a second trench TR2 is formed in the main surface MSF of the semiconductor substrate SUB. The method for forming the second trench TR2 is the same as one of the steps in (2) of the first embodiment for forming the second trench TR2.

[0073] (3) Formation of the first trench TR12 Next, as shown in FIG14, a first trench TR12 is formed in the main surface MSF of the semiconductor substrate SUB. The method for forming the first trench TR12 is the same as the step of forming the first trench TR12 in (3) of the first embodiment, except that the position and shape of the first trench TR12 are different.

[0074] (4) Formation of the buried insulating film BIF2 and the component isolation film EIF Next, as shown in FIG15, the buried insulating film BIF2 and the component isolation film EIF are formed. Specifically, an insulating film is buried in the first trench TR12 and the second trench TR2. The method for forming the insulating film is, for example, a CVD method. For example, an excess portion of the insulating film formed outside the first trench TR12 and the second trench TR2 and the insulating film EIF are removed by a CMP method.

[0075] (5) Formation of gate insulating film GIF, gate electrode GE and sidewall insulating film SW Next, as shown in FIG16, gate insulating film GIF, gate electrode GE and sidewall insulating film SW are formed on the main surface MSF of substrate SUB. The method for forming gate insulating film GIF and gate electrode GE is the same as one step of forming gate insulating film GIF and gate electrode GE in (5) of the first embodiment. An insulating film is formed on semiconductor substrate SUB by, for example, CVD method to cover the structure composed of gate insulating film GIF and gate electrode GE, and then the insulating film is patterned by over-etching to form sidewall insulating film SW.

[0076] (6) Formation of the Penetrating Portion PP Next, as shown in FIG17, a penetrating portion PP is formed in a portion of the buried insulating film BIF2 exposed from the gate electrode GE and the sidewall insulating film SW. The sidewall insulating film SW can be used as an etching mask. The method for forming the penetrating portion PP is, for example, a dry etching method. The penetrating portion PP can be formed simultaneously with the over-etching used to form the sidewall insulating film SW.

[0077] (7) Formation of the source region SR, drain region DR, and back gate region BGR Next, as shown in FIG18, the source region SR, drain region DR, and back gate region BGR are formed in the main surface MSF of the semiconductor substrate SUB. The source region SR is formed adjacent to the gate electrode GE in a planar view. The drain region DR is formed adjacent to the buried insulating film BIF2 in a planar view. The method for forming the source region SR, drain region DR, and back gate region BGR is, for example, an ion implantation method.

[0078] (8) Formation of insulating layer IL, first contact plug CP1, second contact plug CP2 and wiring WR Next, as shown in FIG19, a wiring layer including insulating layer IL, first contact plug CP1, second contact plug CP2 and wiring WR is formed on semiconductor substrate SUB. Insulating film IL is formed on the main surface MSF of semiconductor substrate SUB to fill the penetrating portion PP. The method of forming insulating film IL, first contact plug CP1, second contact plug CP2 and wiring WR is the same as the step of forming insulating layer IL, first contact plug CP1, second contact plug CP2 and wiring WR in (7) of the first embodiment, except that a portion of insulating layer IL and a portion of first contact plug CP1 (lower portion) are formed to be positioned in penetrating portion PP.

[0079] The semiconductor device SD2 according to the second embodiment can be manufactured by the above manufacturing method.

[0080] (Effect) The second embodiment achieves the same effect as the first embodiment. Furthermore, in the semiconductor device SD2 according to the second embodiment, a portion of the first bottom surface BSF1 of the first trench TR12 is the upper surface of the drain region DR. That is, the first trench TR12 does not have a second side surface facing the drain region DR in the X direction. Therefore, compared to the semiconductor device SD1 according to the first embodiment, the length of the current path between the source region SR and the drain region DR can be shortened. Therefore, the characteristics of the semiconductor device SD2 can be improved.

[0081] The present invention is not limited to the above embodiments, and various modifications can be made without departing from its spirit. For example, the semiconductor device SD1 according to the first embodiment may have the sidewall insulating film SW according to the second embodiment. Furthermore, the steps of forming the first trench TR11 and TR12 and the step of forming the second trench TR2 can be performed in the same sequence. Therefore, the manufacturing process can be reduced. In this case, the crystal plane system (111) of the fourth surface SF4 of the semiconductor substrate SUB, which is the third side surface SSF3 of the second trench TR2, is planar. The crystal plane system (100) of the fifth surface SF5 of the semiconductor substrate SUB, which is the second bottom surface BSF2 of the second trench TR2, is planar. The thicknesses of the first trench TR11 and TR12 and the thickness of the second trench TR2 are the same.

[0082] Furthermore, even when presenting a specific numerical instance, values ​​exceeding or falling below one of the numerical instances are applicable, except where the value is theoretically clearly limited to that numerical instance. Furthermore, as for the description of the material, it means "B mainly composed of A" or similar, and it is not intended to exclude materials containing other components.

[0083] In addition, at least a portion of each embodiment and at least a portion of each modification may be combined with each other as appropriate. [Simplified Explanation of the Diagram]

[0009] Figure 1 is a plan view showing one example of an configuration of a main portion of a semiconductor device according to a first embodiment. Figure 2 is a cross-sectional view showing one example of a configuration of the main portion of the semiconductor device according to a first embodiment. Figure 3 is a cross-sectional view showing one example of a step included in a method of manufacturing a semiconductor device according to a first embodiment. Figure 4 is a cross-sectional view showing one example of a step included in a method of manufacturing a semiconductor device according to a first embodiment. Figure 5 is a cross-sectional view showing one example of a step included in a method of manufacturing a semiconductor device according to a first embodiment. Figure 6 is a cross-sectional view showing one example of a step included in a method of manufacturing a semiconductor device according to a first embodiment. Figure 7 is a cross-sectional view showing one example of a step included in a method of manufacturing a semiconductor device according to a first embodiment. Figure 8 is a cross-sectional view showing one example of a step included in a method of manufacturing a semiconductor device according to a first embodiment. Figure 9 is a cross-sectional view showing one example of a step included in a method of manufacturing a semiconductor device according to a first embodiment. Figure 10 is a plan view showing one example of an configuration of a main portion of a semiconductor device according to a second embodiment. Figure 11 is a cross-sectional view showing one example of the configuration of the main part of the semiconductor device according to the second embodiment. Figure 12 is a cross-sectional view showing one example of a step included in a method of manufacturing a semiconductor device according to the second embodiment. Figure 13 is a cross-sectional view showing one example of a step included in a method of manufacturing a semiconductor device according to the second embodiment. Figure 14 is a cross-sectional view showing one example of a step included in a method of manufacturing a semiconductor device according to the second embodiment. Figure 15 is a cross-sectional view showing one example of a step included in a method of manufacturing a semiconductor device according to the second embodiment. Figure 16 is a cross-sectional view showing one example of a step included in a method of manufacturing a semiconductor device according to the second embodiment. Figure 17 is a cross-sectional view showing one example of a step included in a method of manufacturing a semiconductor device according to the second embodiment. Figure 18 is a cross-sectional view showing one example of a step included in a method of manufacturing a semiconductor device according to the second embodiment. Figure 19 is a cross-sectional view showing one example of a step included in a method of manufacturing a semiconductor device according to the second embodiment.

Claims

1. A semiconductor device comprising: A source region formed in a main surface of a semiconductor substrate; a drain region separated from the source region and formed in the main surface of the semiconductor substrate; a buried insulating film buried in a first trench formed in a planar view between the source region and the drain region in the main surface of the semiconductor substrate; a gate insulating film formed on a portion of the main surface of the semiconductor substrate positioned between the source region and the drain region; a gate electrode formed on the gate insulating film such that one end portion is positioned on the buried insulating film; a sidewall insulating film formed on a side surface of the gate electrode and on the buried insulating film; an insulating layer formed on the main surface of the semiconductor substrate to cover the gate electrode; and a contact plug formed in the insulating layer to reach the drain region; wherein the first trench has: A first side surface facing the source region in a first direction extending from one of the source region and the drain region to the other; and a first bottom surface connected to the first side surface and along the main surface of the semiconductor substrate, wherein a crystal plane of the first surface of the semiconductor substrate, which is the first side surface of the first trench, is a (111) plane, wherein a crystal plane of the second surface of the semiconductor substrate, which is the bottom surface of the first trench, is a (100) plane, wherein a penetration portion reaching the drain region is formed in the buried insulating film, wherein a side surface of the penetration portion is continuously formed with a side surface of the sidewall insulating film, wherein the drain region is formed adjacent to the buried insulating film in a plan view on the main surface of the semiconductor substrate exposed from the buried insulating film in the penetration portion, wherein a portion of the first bottom surface of the first trench is an upper surface of the drain region. The buried insulating film is buried in the first trench, and the first trench is formed in a plan view in the area between the source region and the drain region on the main surface of the semiconductor substrate, and in the area overlapping with the drain region, and a portion of the contact plug is formed in the through portion.

2. The semiconductor device of claim 1, further comprising: An element isolation film is embedded in a second trench formed in the main surface of the semiconductor substrate to surround the source region, the drain region and the gate electrode in a plan view. The second trench has: a third side surface facing the source region or the drain region in a first direction; and a second bottom surface connected to the third side surface and along the main surface of the semiconductor substrate. A first interior angle of the first trench formed by the first bottom surface and the first side surface is greater than a second interior angle of the second trench formed by the second bottom surface and the third side surface.

3. The semiconductor device of claim 2, wherein the thickness of one of the element isolation films is greater than the thickness of one of the buried insulating films.

4. The semiconductor device of claim 1, wherein a portion of the insulating layer is embedded in the penetrating portion.

5. A method for manufacturing a semiconductor device, comprising: The process includes the following steps: forming a first trench in a main surface of a semiconductor substrate using a wet etching method; forming a buried insulating film in the main surface of the semiconductor substrate by filling the first trench with an insulating film; forming a gate electrode on the main surface of the semiconductor substrate via a gate insulating film, such that one end portion of the gate electrode is positioned on the buried insulating film; forming a sidewall insulating film on a side surface of the gate electrode and on the buried insulating film; etching the buried insulating film using the sidewall insulating film as an etching mask, thereby forming a penetrating portion in a portion of the buried insulating film exposed from the gate electrode and the sidewall insulating film; and forming a source region and a drain region separated from each other in the main surface of the semiconductor substrate using an ion implantation method. A step of forming an insulating layer on the main surface of the semiconductor substrate to fill the penetration portion; and a step of forming a contact plug in the insulating layer such that a portion of the contact plug is positioned in the penetration portion and the contact plug reaches the drain region, wherein the first trench has: a first side surface facing the source region in a first direction extending from one of the source region and the drain region to the other; and a first bottom surface connected to the first side surface and along the main surface of the semiconductor substrate, wherein a crystal plane of a first surface of the semiconductor substrate that serves as the first side surface of the first trench is a (111) plane, wherein a crystal plane of a second surface of the semiconductor substrate that serves as the bottom surface of the first trench is a (100) plane, wherein the drain region is self-aligned formed in the main surface of the semiconductor substrate exposed from the buried insulating film in the penetration portion by the ion implantation method, and wherein a portion of the first bottom surface of the first trench is an upper surface of the drain region.

6. The method of manufacturing the semiconductor device as described in claim 5, further comprising: A step of forming a second trench in the main surface of the semiconductor substrate to surround, in a plan view, a region in which the source region, the drain region and the gate electrode are formed, wherein in the step of forming the buried insulating film, a device isolation film is formed on the main surface of the semiconductor substrate by filling the second trench with the insulating film.

7. The method of manufacturing the semiconductor device as claimed in claim 6, wherein one of the methods for forming the second trench is a dry etching method.

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