Cyclic plasma processing

Abstract

A method for processing a substrate includes performing a cyclic plasma process comprising multiple cycles, each cycle comprising purging a plasma processing chamber containing the substrate with a first deposition gas containing carbon. The substrate comprises a first layer containing silicon and a second layer containing a metal oxide. The method further comprises exposing the substrate to a first plasma generated by the first deposition gas to selectively deposit a first polymer film on the first layer relative to a second layer; purging the plasma processing chamber with an etching gas containing fluorine; and exposing the substrate to a second plasma generated by the etching gas to etch the second layer.

Description

[Technical Field]

[0001] [Cross-reference to related applications] This application claims priority to U.S. nonprovisional patent application No. 17 / 339,495, filed on June 4, 2021, the entire contents of which are incorporated herein by reference.

[0002] The present invention generally relates to systems and methods for processing semiconductor devices, and in particular embodiments, to systems and methods for cyclic plasma processing. [Previous Technology]

[0003] Generally speaking, semiconductor devices, such as integrated circuits (ICs), are formed by sequentially depositing and patterning dielectric layers, conductive layers, and semiconductor material layers on a substrate to create a network of electronic components and interconnecting elements (such as transistors, resistors, capacitors, metal lines, contacts, and vias) integrated into a monolithic structure. The processes used to form the constituent structures of semiconductor devices involve the deposition and removal of various materials. For these purposes, various plasma processes are frequently used in semiconductor device manufacturing.

[0004] Plasma etching is a plasma process, a common technique for etching materials by exposing them to a plasma containing a gas of charged substances, neutral substances, or a combination thereof. In plasma etching, etching selectivity and directionality (anisotropy or isotropy) are crucial characteristics determining processing performance. With the continuous innovation in the semiconductor industry introducing new materials and device architectures, further development of plasma etching processes, particularly improvements in selectivity and directionality, is expected to meet the increasing demands of semiconductor device manufacturing. [Summary of the Invention]

[0005] According to a preferred embodiment of the present invention, a method for processing a substrate includes performing a cyclic plasma process comprising multiple cycles, each of the multiple cycles comprising cleaning a plasma processing chamber containing a substrate with a first deposition gas containing carbon, the substrate comprising a first layer containing silicon and a second layer containing a metal oxide; exposing the substrate to a first plasma generated by the first deposition gas to selectively deposit a first polymer film on the first layer relative to the second layer; cleaning the plasma processing chamber with an etching gas containing fluorine; and exposing the substrate to a second plasma generated by the etching gas to etch the second layer.

[0006] According to a preferred embodiment of the present invention, a method of processing a substrate includes performing a cyclic plasma process comprising multiple cycles, one of the multiple cycles comprising: during a first time interval, applying a first power supply to a power electrode of a plasma processing chamber and a first bias power to a bias electrode of the plasma processing chamber, and allowing a carbon-containing deposition gas to flow into the plasma processing chamber to selectively deposit a polymer film on a silicon-containing layer relative to a metal oxide layer; during a second time interval, cleaning the plasma processing chamber with an etch gas containing fluorine; and during a third time interval, applying a second power supply to the power electrode and a second bias power to the bias electrode, and allowing an etch gas to flow into the plasma processing chamber to etch the metal oxide layer, wherein during the third time interval, the silicon-containing layer is covered under the polymer film.

[0007] According to a preferred embodiment of the present invention, a method for processing a substrate includes performing a cyclic plasma process comprising multiple cycles, each of the multiple cycles comprising: cleaning a plasma processing chamber containing a substrate with a deposition gas containing carbon, the substrate including a hard mask and an interlevel dielectric (ILD) layer patterned on a metal oxide etch stop layer (ESL), the metal oxide etch stop layer covering a metal line, the hard mask, the interlevel dielectric layer and the metal oxide etch stop layer including an external exposed surface; performing a region-selective plasma deposition process by exposing the substrate to a first plasma generated by the deposition gas to preferentially deposit a polymer film on the hard mask and the interlevel dielectric layer relative to the metal oxide etch stop layer; cleaning the plasma processing chamber with an etching gas containing fluorine; and performing an etching process by exposing the substrate to a second plasma generated by the etching gas to preferentially etch the metal oxide etch stop layer relative to the hard mask and the interlevel dielectric layer.

Implementation Method

[0016] This disclosure describes embodiments of a circulating plasma processing method for selectively removing metal oxide materials relative to silicon- or other materials using a fluorine-containing etching gas without causing metal corrosion as seen in corrosive etching gases. As further described below, circulating plasma processing can be used to selectively remove etch stop layers (ESLs) containing metal oxides (e.g., alumina) as part of back-to-the-end (BEOL) processes in semiconductor device manufacturing. The embodiments described herein offer the advantages of effectively removing metal oxide materials while reducing the loss of other materials such as silicon-containing hard masking materials and interlayer dielectric (ILD) materials and avoiding metal corrosion. This innovative method achieves this advantage by combining zone-selective plasma deposition to form a protective layer on silicon-containing materials, followed by etching with a fluorine-containing non-corrosive gas to selectively remove target metal oxide materials with little or no protective layer, as further described below. Although described in this disclosure in the context of a copper double damascene process, cyclic plasma processing can be applied to other processes in other structures, as is known to those skilled in the art.

[0017] Generally, the dual damascene back-to-end (BEOL) process is an important step in the fabrication of integrated circuits to form copper (Cu) interconnects. In the dual damascene BEOL process, a first recess, such as a via or trench, is formed and filled with a temporary filler material. Next, a second recess is formed, and the entire recess is filled with copper metal, followed by planarization. The processes for forming vias and trenches may involve removing etch stop layers (ESLs). ESLs can be located between two barrier layers to isolate different metal layers. Although these multilayer stacks can be collectively referred to as etch stop layers, in this disclosure they are referred to as top barrier layer, etch stop layer (ESL), and bottom barrier layer, respectively. Although silicon carbide and silicon nitride have been used as conventional ESL materials, alumina (Al2O3) may be more suitable for ESLs due to its lower dielectric constant (k-value of approximately 4 to 6 as a thin film) and high density. However, the removal of alumina ESLs has been challenging, and conventional methods for etching alumina ESLs are not satisfactory. For example, wet etching processes are often isotropic, which can increase the critical dimensions at the bottom, leading to the risk of via-via or via-trench short circuits. Dry plasma etching using chlorine (Cl) or bromine (Br) gases (e.g., BCl3, HBr, and Cl2) can cause metal line corrosion. On the other hand, non-corrosive gases (e.g., fluorocarbons) can be used for plasma etching, but ESL etching may have lower selectivity for hard mask (HM) and interlayer dielectric (ILD) materials. In various embodiments of this disclosure, the method is based on a cyclic plasma process comprising a region-selective plasma deposition process and a plasma etching process using one or more fluorinated etching gases, and this method advantageously provides better etching selectivity for ESL materials. This advantage can lead to improved fine control over the critical dimensions of semiconductor devices during manufacturing.

[0018] In various embodiments, performing a cyclic plasma process for selectively removing the metal oxide layer is part of a dual damascene back-end (BEOL) process in semiconductor manufacturing. While the cyclic plasma process of this disclosure may be described as a step in a dual damascene BEOL process, the cyclic plasma process may be applied to a single damascene BEOL process or other processes.

[0019] Figures 1A-1M first illustrate a dual-dotted BEOL processing flow (trench priority) according to various embodiments, which undergoes a cyclic plasma process for ESL removal. Figures 2A-2E illustrate an alternative embodiment of a dual-dotted BEOL processing flow (via priority). Furthermore, according to other alternative embodiments, Figures 3A-3C illustrate a cyclic plasma process with two region-selective plasma deposition processing steps. Referring to Figures 4A-4D, several processing flows of the cyclic plasma process are further described for different embodiments. The steps of the cyclic plasma process can be isolated in time or space. To illustrate time / space isolation, a timing diagram of one cycle of a time-multiplexed implementation of the cyclic plasma process is illustrated in Figure 5A, and a corresponding processing flow diagram is illustrated in Figure 5B. Figure 6 illustrates an example plasma processing system. Figures 7A and 7B show an alternative plasma processing system and a corresponding spatial isolation method.

[0020] FIG1A illustrates a cross-sectional view of an incoming substrate 90. In various embodiments, substrate 90 may be part of a semiconductor device and may undergo multiple processing steps, for example, after conventional processing. Therefore, substrate 90 may contain semiconductor layers that function in various microelectronics. For example, a semiconductor structure may be contained in substrate 90 in which various device regions are formed.

[0021] In one or more embodiments, the substrate 90 may be a silicon wafer or a silicon-on-insulator (SOI) wafer. In some embodiments, the substrate 90 may include a silicon-germanium wafer, a silicon carbide wafer, a gallium arsenide wafer, a gallium nitride wafer, and other compound semiconductors. In other embodiments, the substrate 90 includes a heterolayer, such as silicon-germanium on silicon, gallium nitride on silicon, silicon-carbon on silicon, and a silicon layer on a silicon or SOI substrate. In various embodiments, the substrate 90 is patterned or embedded in other components of a semiconductor device.

[0022] As shown in FIG1A, the substrate 90 may further include a metal layer 100 on the substrate. In some embodiments, there may be one or more layers, such as dielectric layers, between the substrate 90 and the metal layer 100. In various embodiments, the metal layer 100 may be formed as part of a patterned metal interconnect on the substrate 90. In embodiments, the metal layer 100 may include copper (Cu), aluminum (Al), doped polycrystalline silicon, tungsten, titanium nitride, tantalum nitride, ruthenium, and other metals. The metal layer 100 may be formed by deposition using, for example, physical vapor deposition (PVD).

[0023] A dielectric layer may be deposited on the metal layer 100 as a bottom barrier layer 115. In some embodiments, the bottom barrier layer 115 may comprise a silicon-based dielectric material, such as silicon nitride and silicon carbon nitride (SiCN). The bottom barrier layer 115 may be deposited using deposition techniques, such as vapor deposition including chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), as well as other plasma treatments such as plasma-enhanced CVD (PECVD), sputtering, and other processes.

[0024] Another dielectric layer may be further deposited as an etch stop layer (ESL) 120 above the bottom barrier layer 115. In various embodiments, the etch stop layer 120 may comprise aluminum oxide, aluminum nitride, or zirconium oxide. The etch stop layer 120 may be deposited using deposition techniques, such as vapor deposition including chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), as well as other plasma treatments such as plasma-enhanced CVD (PECVD), sputtering, and other processes. In some embodiments, the thickness of the etch stop layer 120 may be between 2 nm and 5 nm.

[0025] Referring again to FIG1A, a top barrier layer 125 may be formed on the etch stop layer 120. In some embodiments, the top barrier layer 125 may comprise a silicon-based dielectric material, such as silicon nitride and silicon carbon nitride (SiCN). The top barrier layer 125 may typically be the same material as the bottom barrier layer 115. The top barrier layer 125 may be deposited using deposition techniques, such as vapor deposition including chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), as well as other plasma treatments such as plasma-enhanced CVD (PECVD), sputtering, and other processes.

[0026] Another dielectric layer may be formed on the top barrier layer 125 as an interlayer dielectric (ILD) layer 130. The interlayer dielectric layer 130 may comprise a silicon-based dielectric material having a low dielectric constant (i.e., a low k-value), such as organosilicate glass (SiCOH), dense SiCOH, porous SiCOH, and other porous dielectric materials. The interlayer dielectric layer 130 may be deposited using deposition techniques, such as vapor deposition including chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), as well as other plasma treatments such as plasma-enhanced CVD (PECVD), sputtering, and other processes.

[0027] As further shown in FIG1A, a first hard mask 140 may be formed on an interlayer dielectric (ILD) layer 130. In some embodiments, the first hard mask 140 may comprise silicon nitride. In alternative embodiments, the first hard mask 140 may comprise silicon dioxide (SiO2) or titanium nitride. Furthermore, the first hard mask 140 may be a stacked hard mask, for example, comprising two or more layers using two different materials. The first layer of the first hard mask 140 may comprise a metal substrate, such as titanium nitride, titanium, tantalum nitride, tantalum, tungsten-based compounds, ruthenium-based compounds, or aluminum-based compounds, and the second layer of the first hard mask 140 may comprise a dielectric layer, such as silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, amorphous silicon, or polycrystalline silicon. The first hard mask 140 can be deposited using deposition techniques, such as vapor deposition including chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), as well as other plasma processing such as plasma-enhanced CVD (PECVD), sputtering, and other processes.

[0028] The first photoresist 150 may be deposited on the first hard mask 140, for example, using a coating process or a spin coating process. In various embodiments, the first photoresist 150 may comprise a photosensitive organic material and may be applied to the first hard mask 140 from a solution by, for example, a conventional spin coating technique. As shown in FIG1A, the first photoresist 150 may be patterned using conventional lithography techniques. In various embodiments, the pattern of the first photoresist 150 may be used to form a first groove. In some embodiments, as shown in FIG1B, the first pattern may be used to form a trench.

[0029] FIG1B illustrates the substrate 90 after trench etching to form trench features. The first photoresist 150 in FIG1A serves as a masking layer, and the pattern of the first photoresist 150 is transferred. Trench etching anisotropically removes the first hard mask 140 and portions of the interlayer dielectric (ILD) layer 130 not masked by the first photoresist 150. As shown in FIG1B, trench etching can be stopped before the top barrier layer 125 is exposed to allow space for via formation in subsequent steps. An etch stop layer can be used to stop trench etching, but in some embodiments, timed etch can also be used. In some embodiments, trench etching includes one or more wet etching processes, plasma etching processes, reactive ion etching (RIE) processes, or combinations of these or other etching processes. Any residual first photoresist 150 after trench etching can be removed from the substrate 90 by, for example, conventional plasma ashing techniques.

[0030] Figure 1C illustrates the substrate 90 after trench refilling and the deposition of the second hard mask 142 and the second photoresist 152. At the trench refilling site, after removing any residual first hard mask 140, a filler material 160, referred to as gap filler material, or an organic bottom antireflective coating (BARC), fills the trench features formed in the previous step. The filler material 160 may be spin-coated from a solution of an organic solvent. In some embodiments, the filler material 160 may be deposited using other deposition techniques including vapor deposition. The surface of the filler material 160 may be planarized using a planarization process such as chemical mechanical planarization to make it coplanar with the main surface of the interlayer dielectric layer 130.

[0031] Furthermore, continuing with reference to FIG1C, a second hard mask 142 and a second photoresist 152 are applied for patterning in the next step. The second hard mask 142 may be similar to the first hard mask 140 described above, although in some embodiments it may have a different composition. The second hard mask 142 may be deposited using deposition techniques, such as vapor deposition including chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), and other plasma treatments such as plasma-enhanced CVD (PECVD), sputtering, and other processes. The second photoresist 152 may be similar to the first photoresist 150 described above, although in some embodiments it may have a different composition. The second photoresist 152 is applied to the second hard mask 142 from a solution using, for example, a conventional spin coating technique.

[0032] FIG. 1D illustrates a substrate 90 after the pattern of the second photoresist 152 has been defined by one or more photolithography processes. In various embodiments, the pattern of the second photoresist 152 may be used for the formation of a second groove. In some embodiments, as shown in FIG. 1E, the pattern of the second photoresist 152 may be used for the formation of a via.

[0033] FIG1E illustrates the substrate 90 after via etching followed by removal of the filler material 160. The second photoresist 152 in FIG1D serves as a mask layer, and the pattern of the second photoresist 152 is transferred. The via etching anisotropically removes the second hard mask 142, the filler material 160, and portions of the interlayer dielectric (ILD) layer 130 not masked by the second photoresist 152. The remaining second photoresist 152 and filler material 160 can be removed by, for example, conventional plasma ashing techniques. In this removal step, portions of the second hard mask 142 isolated above the filler material 160 can also be removed. In some embodiments, the via etching process includes one or more wet etching processes, plasma etching processes, reactive ion etching (RIE) processes, or combinations of these or other etching processes.

[0034] FIG1F illustrates the substrate 90 after the removal of the top barrier layer 125 at the bottom of the formed via. In various embodiments, the removal of the top barrier layer may be performed by an etching process, exposing a portion of the etch stop layer (ESL) 120 before a subsequent cyclic plasma process (e.g., FIG1G-1I). In some embodiments, the etching of the top barrier layer 125 includes one or more wet etching processes, plasma etching processes, reactive ion etching (RIE) processes, or combinations of these or other etching processes. In some embodiments, via etching and the etching of the top barrier layer 125 can be performed in a single etching step. In some embodiments, the cyclic plasma process described below can be performed in a manner that achieves at least a portion of the purpose of via etching or the etching of the top barrier layer 125.

[0035] In some embodiments, an optional pretreatment may be performed prior to the cyclic plasma treatment to chemically or physically modify the composition of surface-terminal functional groups of layers present on the substrate 90 (e.g., the second hard mask 142 and the interlayer dielectric (ILD) layer 130 in FIG. 1F) to improve the selectivity of subsequent cyclic plasma treatment. For example, the optional pretreatment may be a plasma treatment using a hydrogen-containing reducing agent. In one embodiment, a plasma treatment using molecular hydrogen (H2) may be performed.

[0036] Figure 1G illustrates the substrate 90 after a region-selective plasma deposition process to form the polymer film 165. In various embodiments, the formation of the polymer film 165 is the first plasma step of a cyclic plasma process. In various embodiments, the polymer film 165 can be selectively formed over the second hard mask 142 and the interlayer dielectric (ILD) layer 130 relative to the etch stop layer 120 by exposing the substrate 90 to a plasma of a deposition gas. In various embodiments, the deposition rate on the second hard mask 142 or the interlayer dielectric (ILD) layer 130 relative to the etch stop layer 120 can be from 5:1 to 1000:1, such that little or no polymer film can be formed on the etch stop layer 120. Therefore, the polymer film 165 is much thicker on the second hard mask 142 or the interlayer dielectric (ILD) layer 130 than on the etch stop layer 120.

[0037] In various embodiments, the deposition gas comprises a mixture of polymer membrane precursors, which includes carbon and a diluent. For example, in various embodiments, the polymer membrane precursor is an alkane. In some embodiments, the deposition gas is a mixture of methane (CH4) and argon (Ar) in any proportion. In some embodiments, the deposition gas may further comprise hydrogen (H2) or nitrogen (N2). In some embodiments, the deposition gas may further comprise ethane, ethylene, and other hydrocarbons.

[0038] In one embodiment, the zone-selective plasma deposition process can be performed using a gas mixture of CH4 and Ar at a processing temperature between 20°C and 120°C, wherein a polymer film 165 is preferentially formed on a second hard mask 142 and an interlayer dielectric (ILD) layer 130, comprising silicon-containing materials such as silicon nitride, silicon oxide, and organosilicon glass (SiCOH), relative to an etch stop layer (ESL) 120 containing alumina. Silicon oxide can be prepared by, for example, plasma-enhanced CVD or flowable CVD using tetraethyl orthosilicate (TEOS) as a precursor. In other embodiments, the polymer film 165 may preferentially be formed on a second hard mask 142 containing titanium nitride, relative to an etch stop layer 120 containing alumina.

[0039] Figure 1H illustrates the substrate 90 after etching the etch stop layer 120 using a fluorine-containing gas in the second plasma step of the cyclic plasma process. When the exposed portion of the etch stop layer 120 is anisotropically etched, the polymer film 165 formed by the first plasma step (region-selective plasma deposition process) described in Figure 1G serves as a protective layer to protect the second hard mask 142 and the interlayer dielectric layer 130. The thicker polymer film 165 formed on the second hard mask 142 or the interlayer dielectric (ILD) layer 130 protects the underlying material from etching, thus allowing for the use of even non-selective or less etchant. If any polymer film 165 present on the etch stop layer 120 is thinner, it will be etched first, followed by the exposed etch stop layer 120.

[0040] In various embodiments, the fluorinated etching gas may contain a gas that is not corrosive to metals containing copper. In various embodiments, the fluorinated gas does not contain chlorine or bromine and will not cause metal corrosion of the metal wire over a long period of time. This differs from chlorine or bromine gases, which may cause copper corrosion during the product's lifespan, leading to product failure.

[0041] In various embodiments, the fluorinated etching gas comprises tetrafluoromethane (CF4), nitrogen trifluoride (NF3), fluoroform (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), and combinations thereof. The fluorinated etching gas may optionally not contain sulfur, which can cause metal corrosion of the metal wire, similar to chlorine or bromine as described above. In some embodiments, the etching gas further comprises any proportion of oxygen (O2). In one or more embodiments, the etching gas further comprises 0.1% to 10% oxygen by volume. The etching gas may further comprise a diluent, such as any proportion of argon (Ar) and nitrogen (N2). In various embodiments, zone-selective plasma deposition (first plasma step) and subsequent etching plasma treatment (second plasma step) may be repeated to achieve a target amount of selective removal of the etch stop layer. Various embodiments of cyclic plasma treatment will be further illustrated with reference to Figures 4A-4D.

[0042] In some embodiments, relative to the polymer film-protected second hard mask 142 and the interlayer dielectric (ILD) layer 130, which comprises silicon-containing materials such as silicon nitride, silicon oxide, and organosilicon glass (SiCOH), an etching plasma treatment (second plasma step) is performed at a processing temperature between 60°C and 120°C using a tetrafluoromethane (CF4) plasma to preferentially remove the etch stop layer 120 containing alumina. In other embodiments, relative to the polymer film-protected second hard mask 142 containing titanium nitride, the etch stop layer 120 containing alumina may be preferentially etched.

[0043] FIG1I illustrates the substrate 90 after the completion of the cyclic plasma treatment. According to various embodiments, the portion of the etch stop layer 120 corresponding to the pattern of the second photoresist 152 defined in FIG1D is removed, and the via extends to the bottom barrier layer 115. In the embodiment shown in FIG1I, the processing parameters of the cyclic plasma treatment can be optimized to completely remove not only the etch stop layer 120 from the second hard mask 142 and the interlayer dielectric layer 130, but also to completely remove the polymer film 165.

[0044] In various embodiments, after the cyclic plasma process, a further step of the dual damascene after-offset (BEOL) process may be performed to form metal interconnects. FIG1J illustrates a substrate 90 after etching to remove a portion of the bottom barrier layer 115 and exposing a portion of the metal layer 100 according to the pattern of the formed vias. In some embodiments, the etching of the bottom barrier layer 115 includes one or more wet etching processes, plasma etching processes, reactive ion etching (RIE) processes, or combinations of these or other etching processes. In some embodiments, at least a portion of the etching of the bottom barrier layer 115 or any other subsequent step of the dual damascene after-offset process may be integrated into one part of the aforementioned cyclic plasma process.

[0045] Figure 1K illustrates the substrate 90 after the diffusion barrier layer 170 has been deposited. In some embodiments, the diffusion barrier layer 170 may comprise tantalum, tantalum nitride, titanium, or titanium nitride. The diffusion barrier layer is designed to prevent metal in the metal layer 100 from diffusing into other components during manufacturing. The diffusion barrier layer 170 may be deposited using deposition techniques such as sputtering, vapor deposition including chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), as well as other plasma treatments such as plasma-enhanced CVD (PECVD) and other processes.

[0046] Figure 1L illustrates the substrate 90 after metal deposition. Metal deposition can be performed by depositing a seed layer of metal (e.g., copper) using sputtering or physical vapor deposition (PVD) techniques, followed by electroplating. In this metal deposition step, vias and trenches are filled with metal. As shown in Figure 1L, in various embodiments, the same metal as the metal layer 100 is typically used for metal deposition.

[0047] Finally, Figure 1M illustrates the substrate 90 after planarization, in which excess metal has been removed by, for example, chemical mechanical planarization (CMP) method.

[0048] In the example embodiments shown in Figures 1A-1M, trench etching (Figure 1B) is performed before via etching (Figure 1E). This order is referred to as trench priority. However, in other embodiments, via etching may be performed before trench etching (via priority), as shown in Figures 2A-2E below.

[0049] In FIG. 2A, the incoming substrate 90 has a structure similar to the aforementioned previous (trench-preferred) embodiment, wherein the layer stack includes a metal layer 100, a bottom barrier layer 115, an etch stop layer (ESL) 120, a top barrier layer 125, and an interlayer dielectric (ILD) layer 130. A first hard mask 240 is formed above the interlayer dielectric layer 130. A first photoresist 250 may be formed on the first hard mask 240, which has a pattern for via etching, similar to the pattern in FIG. 1D. The first hard mask 240 and the first photoresist 250 may be similar to the first hard mask 140 and the first photoresist 150 in FIG. 1A, respectively, although in some embodiments they may have different compositions.

[0050] FIG2B illustrates the substrate 90 after via etching. The first photoresist 250 in FIG2A serves as a mask layer, and the pattern of the first photoresist 250 is transferred. As described in the previous embodiment, via etching can be performed using appropriate etching processes to anisotropically remove portions of the first hard mask 240 and the interlayer dielectric (ILD) layer 130 that are not masked by the first photoresist 250, and expose the top barrier layer 125 located at the bottom of the formed via.

[0051] Figure 2C illustrates the substrate 90 after via refilling and deposition of the second hard mask 242 and the second photoresist 252. At the via refilling site, after removing any residual first hard mask 240, a filler material 260 fills the via feature formed in the previous step. The filler material 260 may be similar to filler material 160, although in some embodiments it may have a different composition. The filler material 260 may be spin-coated from a solution of an organic solvent. In some embodiments, the filler material 260 may be deposited using other deposition techniques including vapor deposition. A planarization process, such as chemical mechanical planarization, may be used to planarize the surface of the filler material 260 to be coplanar with the main surface of the interlayer dielectric layer 130.

[0052] Furthermore, in FIG. 2C, similar to FIG. 1C, a second hard mask 242 and a second photoresist 252 are formed over the interlayer dielectric layer 130 and the filler material 260. The second hard mask 242 and the second photoresist 252 may be similar to the first hard mask 240 and the first photoresist 250, respectively, although they may have different compositions. Similar to the second hard mask 142 in FIG. 1C, the second hard mask 242 may be deposited using a suitable deposition technique. The second photoresist 252 may be applied to the second hard mask 242 from a solution by, for example, a conventional spin-coating technique.

[0053] Figure 2D illustrates the substrate 90 after the pattern of the second photoresist 252 is defined by one or more photolithography processes. The pattern of the second photoresist 252 can be used for trench formation.

[0054] FIG. 2E illustrates the substrate 90 after trench etching. The patterned second photoresist 252 in FIG. 2D serves as a mask layer, and the pattern of the second photoresist 252 is transferred. As in the previous embodiments described above, trench etching can be performed using a suitable etching process to anisotropically remove portions of the second hard mask 242, filler material 260, and interlayer dielectric (ILD) layer 130 that are not masked by the second photoresist 252. As shown in FIG. 2E, trench etching can be performed to completely remove the filler material 260 to expose the top barrier layer located at the bottom of the via, but stopping before the portions of the interlayer dielectric layer 130 not masked by the second photoresist 252 are completely removed. An etch stop layer can be used to stop trench etching, but in some embodiments, timed etching can also be used. Any remaining second photoresist 252 can be removed by, for example, conventional plasma ashing techniques. At this stage, the substrate 90 has a structure with trench and via features, similar to the structure formed by the trench preferred embodiment shown in FIG1E.

[0055] Subsequently, the removal of the top barrier layer 125, the circulating plasma treatment, and the subsequent treatment can be performed in a manner similar to the previous embodiments (e.g., FIG1F, FIG1G-1I, and FIG1J-1M, respectively).

[0056] Although the previous embodiments were described as part of a dual damascene back-to-office (BEOL) process, the cyclic plasma process disclosed herein is not limited to a dual damascene back-to-office process and can be applied to other processes to selectively remove a material (e.g., alumina) having one or more protective layers selectively formed on other materials (e.g., silicon-containing materials). In one embodiment, the cyclic plasma process can be applied to a single damascene back-to-office process. In one cycle of a single damascene back-to-office process, only one recess, such as a trench or via, can be formed, instead of the two recesses formed in a dual damascene back-to-office process. For example, cyclic plasma etching can be performed after via formation (e.g., FIG. 2B).

[0057] In various embodiments, the cyclic plasma treatment may include two isolated region-selective plasma deposition steps. Using the methods of these embodiments, selective etching of the target material from a surface containing two or more materials can be improved. The formation of trenches and vias prior to the cyclic plasma treatment can be performed using a trench-first approach (e.g., Figures 1A-1E) or a via-first approach (e.g., Figures 2A-2E) to obtain the same structure as shown in Figure 1F. Subsequent steps of the cyclic plasma treatment according to these embodiments are illustrated in Figures 3A-3C.

[0058] FIG. 3A illustrates a substrate 90 after a first region-selective plasma deposition process (first plasma step) using a first deposition gas. The first deposition gas may be similar to the deposition gas previously described with reference to FIG. 1G. As shown, a first polymer film 360 may be preferentially formed on the second hard mask 142 relative to the interlayer dielectric (ILD) layer 130 and the etch stop layer (ESL) 120. The composition of the first polymer film 360 may be similar to that of the aforementioned polymer film 165, and formed in a similar manner. At this stage, for example, the composition of the first deposition gas and other processing parameters may be selected to achieve a high deposition rate and / or selectivity for the second hard mask 142.

[0059] Next, in FIG. 3B, the substrate 90 after the second region-selective plasma deposition process (second plasma step) using a second deposition gas is illustrated. A second polymer film 362, with a composition different from the first polymer film 360, may be preferentially formed on the interlayer dielectric layer 130 relative to the second hard mask 142 and the etch stop layer 120. The first polymer film 360, the second polymer film 362, or both may be compositionally similar to the polymer film 165. In one embodiment, the first and second polymer films 360 and 362 may be compositionally identical, but formed at different rates by selecting different processing parameters for the first and second plasma steps. The second deposition gas may be similar to the deposition gas previously described with reference to FIG. 1G. For example, the second deposition gas comprises a mixture of a second polymer film precursor containing carbon and a diluent. In some embodiments, the second polymer film precursor is an alkane. In some embodiments, the deposition gas is a mixture of methane (CH4) and argon (Ar) in any proportion. In some embodiments, the deposition gas may further comprise hydrogen (H2) or nitrogen (N2). The second deposition gas may be the same as or different from the first deposition gas used for the first region-selective plasma deposition process. The composition of the second deposition gas and other processing parameters may be selected to achieve a high deposition rate and / or selectivity for the interlayer dielectric (ILD) layer 130.

[0060] In one embodiment, the processing parameters of the first plasma step may be optimized for the first polymer film 360 formed on a silicon-containing hard mask, and the processing parameters of the second plasma step may be optimized for the second polymer film 362 formed on an interlayer dielectric layer 130 containing a low-k dielectric (e.g., SiCOH). Both conditions remain selective relative to the etch stop layer (ESL) 120 containing aluminum oxide.

[0061] FIG3C illustrates the substrate 90 after etching the etch stop layer 120 using a fluorine-containing gas in the third plasma step of the cyclic plasma process. As previously described in FIG1H, the exposed portion of the etch stop layer 120 is anisotropically etched. The first and second polymer films 360 and 362 formed by the above-described first and second region-selective plasma deposition processes (first and second plasma steps) serve as protective layers to protect the second hard mask 142 and the interlayer dielectric layer 130, respectively.

[0062] Although the above embodiments (e.g., Figures 3A-3C) include two region-selective plasma deposition processing steps, in alternative embodiments, the cyclic plasma process may include any number of region-selective plasma deposition processing steps and one or more etching processes.

[0063] In the following, Figures 4A-4D illustrate the process flow diagram of the circulating plasma treatment corresponding to the foregoing embodiments, wherein Figure 4A corresponds to Figures 1G-1I, Figure 4B corresponds to Figures 1A-1M, Figure 4C corresponds to Figures 2A-2E and 1F-1M, and Figure 4D corresponds to Figures 3A-3C.

[0064] In various embodiments, all steps of the circulating plasma treatment, for example corresponding to FIG1G-1I, can be performed within the plasma treatment apparatus.

[0065] In FIG. 4A, the process flow of a circulating plasma process is illustrated according to various embodiments. The circulating plasma process (block 450A) comprises four main steps: cleaning the plasma processing chamber of the plasma processing tool with a deposition gas containing carbon (block 451), exposing the substrate to plasma generated by the deposition gas (block 452) (e.g., FIG. 1G), cleaning the plasma processing chamber with an etching gas containing fluorine (block 455), and exposing the substrate to plasma with an etching gas (block 456) (e.g., FIG. 1H). Each step of the circulating plasma process can be isolated in time or space. In some embodiments, the circulating plasma process can be performed in a single part of the plasma processing chamber by time multiplexing, as detailed in FIG. 5 and FIG. 6. In other embodiments, the circulating plasma process can be performed in separate parts of the plasma processing chamber, and the substrate can be transferred from one part to another to transition to the next step, as shown in FIG. 7A and 7B.

[0066] As the first step in the circulating plasma process, in block 451, the plasma processing chamber is cleaned with a carbon-containing deposition gas such as methane (CH4), and the substrate temperature is brought to equilibrium at the processing temperature. In various embodiments, the substrate temperature can be increased by, for example, a heater, and cooled by water cooling or liquid helium cooling controlled by a temperature controller.

[0067] Next, in block 452, the first plasma step (region-selective plasma deposition) of the cyclic plasma process is performed by a plasma deposition tool such as a plasma-enhanced chemical vapor deposition (PECVD) tool (e.g., FIG. 1G). By providing plasma source energy from one or more plasma power sources, a plasma of deposition gas is generated in the plasma processing chamber, and the substrate is exposed to the plasma of deposition gas. Precursors for the polymer film 165 can be plasma-excited to form free radicals. These free radicals can adsorb onto the surface and react randomly with each other during the plasma polymerization process to form the polymer film 165 (e.g., FIG. 1G). Differences in adsorption between different materials lead to different plasma polymerization rates, resulting in different film growth rates. Therefore, processing parameters such as power supply, bias power, gas flow rate, processing pressure, processing temperature, processing time, and gas composition can be optimized to achieve region-selective formation of the polymer film.

[0068] Next, in block 455, after terminating the first plasma step by shutting off the plasma power supply, the plasma processing chamber is cleaned with an etching gas containing fluorine. In various embodiments, the substrate temperature may be maintained at the same level as in the first plasma step, or it may be balanced at another processing temperature. In various embodiments, the substrate temperature may be increased by, for example, a heater, and cooled by water cooling or liquid helium cooling controlled by a temperature controller.

[0069] In block 456, a second plasma step is performed to etch the metal oxide (e.g., the etch stop layer 120 in FIG. 1H). As shown in FIG. 1H, the polymer film 165 may also be partially or completely removed during this step. The plasma of the etching gas is generated in the plasma processing chamber, and the substrate is exposed to the plasma of the etching gas. In some embodiments, the polymer film 165 and the etch stop layer 120 containing alumina are anisotropically etched while other materials (e.g., the second hard mask 142 and the interlayer dielectric (ILD) layer 130 in FIG. 1H) are retained.

[0070] In some conventional methods, plasma etching using non-corrosive gases tends to result in non-selective etching. Typical conditions for removing metal oxide materials such as alumina often damage other materials, such as silicon-containing materials used as hard masks and interlayer dielectric (ILD) layers. However, using the methods of the embodiments in this disclosure, such damage can be advantageously minimized or completely eliminated due to the presence of a polymer film formed on such materials during the region-selective deposition in the first plasma step. Processing parameters such as power supply, bias power, gas flow rate, processing pressure, processing temperature, processing time, and gas composition can be optimized to effectively etch the target metal oxide material while simultaneously removing the polymer film.

[0071] In some embodiments, the plasma treatment chamber may be evacuated to a vacuum prior to any cleaning step (e.g., blocks 451 and 455). Furthermore, in some embodiments, one or more additional processing steps may be inserted between the steps. The additional processing may be heat treatment under vacuum, wet treatment, plasma treatment similar to the pretreatment (block 445), or other treatments.

[0072] In various embodiments, these four steps (blocks 451, 452, 455, and 456) can be repeated in a loop to achieve the desired processing performance. A loop can begin from any of the four steps.

[0073] In FIG4B, according to certain embodiments, cyclic plasma processing can be used to selectively remove the etch stop layer (ESL) from the substrate as part of a dual back-to-center (BEOL) process employing a trench-first approach (e.g., FIG1A-1M).

[0074] The substrate may have undergone various manufacturing steps and has a layer stack including a first hard mask 140 and a first photoresist 150 (block 400) (e.g., FIG. 1A). First, trench etching is performed (block 410) (e.g., FIG. 1B) to form the trench features as described above. Next, trench refilling, deposition of a second hard mask 142 and a second photoresist 152, and patterning of the second photoresist 152 are performed (block 420) (e.g., FIG. 1C and 1D). Subsequently, via etching is performed (block 430) (e.g., FIG. 1E). Next, the top barrier layer 125 can be selectively removed (block 440) (e.g., FIG. 1F). In some embodiments, this step of removing the top barrier layer 125 can be integrated into a subsequent cyclic plasma process (block 450B) (e.g., FIG. 1G-1I). Furthermore, optional pretreatment (block 445) can be performed to chemically or physically modify the composition of surface-terminal functional groups of layers present on substrate 90 (e.g., the second hard mask 142 and interlayer dielectric (ILD) layer 130 in FIG. 1F) to improve the selectivity of subsequent cyclic plasma processing. Cyclic plasma processing (block 450B) as previously described with reference to block 450A in FIG. 4A (e.g., FIG. 1G-1I) is then performed.

[0075] Continuing with reference to FIG4B, after the completion of the cyclic plasma process (block 450B), the bottom barrier layer 115 (block 460) can be selectively removed (e.g., FIG1J). In some embodiments, this step of removing the bottom barrier layer 115 can be integrated into the previous cyclic plasma process (block 450B) (e.g., FIG1G-1I). Subsequently, the diffusion barrier layer 170 is deposited, metal is deposited, and planarization is performed to complete the cycle of forming metal interconnects (block 470) (e.g., FIG1K-1M).

[0076] Figure 4C illustrates an example processing flowchart of dual damascene back-end (BEOL) processing using the via-first method according to alternative embodiments (e.g., Figures 2A-2E and 1F-1M).

[0077] Similar to the previously described embodiments employing the trench-first method, the substrate may have undergone various manufacturing steps and has a layer stack (block 402) including a first hard mask 240 and a first photoresist 250 (e.g., FIG. 2A). First, via etching (block 412) (e.g., FIG. 2B) is performed to form the via features as described above. Next, via refilling, deposition of a second hard mask 242 and a second photoresist 252, and patterning of the second photoresist 252 are performed (block 422) (e.g., FIG. 2C and 2D). Then, trench etching (block 432) is performed (e.g., FIG. 2E). Subsequent processing can be similar to the processing flow of the previously described trench-first embodiments (e.g., FIG. 1F-1M and FIG. 4B). The top barrier layer 125 can be selectively removed (block 442) (e.g., FIG. 1F), although in some embodiments, this step of removing the top barrier layer 125 can be integrated into a subsequent cyclic plasma treatment (block 450C) (e.g., FIG. 1G-1I). Furthermore, optional pretreatment (block 447) can be performed to chemically or physically modify the composition of surface-terminal functional groups of layers present on the substrate 90 (e.g., the second hard mask 142 and interlayer dielectric (ILD) layer 130 in FIG. 1F) to improve the selectivity of subsequent cyclic plasma treatments. The cyclic plasma treatment (block 450C) and subsequent treatments can be similar to the aforementioned previous embodiments (e.g., blocks 450B, 460, and 470 in FIG. 4B). After completing the circulating plasma treatment (block 450C), the bottom barrier layer 115 (block 462) can be selectively removed (e.g., FIG. 1J), although in some embodiments this step of removing the bottom barrier layer 115 can be integrated into the previous circulating plasma treatment (block 450C) (e.g., FIG. 1G-1I). Finally, the diffusion barrier layer 170 is deposited, metal is deposited, and planarization is performed (block 472) (e.g., FIG. 1K-1M).

[0078] Figure 4D illustrates an example process flow diagram of a cyclic plasma process comprising two region-selective plasma deposition steps and one etching step, according to different embodiments (e.g., Figures 3A-3C). As previously mentioned, in some embodiments, the cyclic plasma process comprising two region-selective plasma deposition steps can be used to achieve two optimized conditions for plasma deposition of two polymer films on two different materials relative to the target etching material.

[0079] In these embodiments, the cyclic plasma process may include six steps. In addition to the four steps described above (e.g., blocks 451, 452, 455 and 456 in Figures 4A-4C), after the first region-selective plasma deposition step (block 452), a rinsing step using a second deposition gas (block 453) and a region-selective plasma deposition step using a second deposition gas (block 454) are inserted.

[0080] Details of the cyclic plasma process and alternative embodiments are described in this disclosure, focusing on the four main steps: two cleaning steps and a region-selective plasma deposition pre-etch (e.g., block 450A in FIG. 4A). However, it is contemplated that such details can be applied to cyclic plasma processes that include any number of plasma deposition and etching processes (e.g., for block 450D of an example having two deposition steps and one etching step).

[0081] Figure 5A illustrates a timing diagram of the four steps in one cycle of a time-multiplexed implementation of a cyclic plasma process, such as the flowchart shown in Figure 4A. The six horizontal axes in Figure 5A represent the progress of time. The four time intervals T1, T2, T3, and T4 for the four steps of one cycle of the cyclic plasma etching process 230 are schematically shown by four double arrows adjacent to a time axis. Referring to Figure 4A, T1, T2, T3, and T4 correspond to cleaning with deposition gas (block 451), area-selective plasma deposition (block 452), cleaning with etching gas (block 455), and plasma etching (block 456), respectively. Four vertical dashed lines intersecting the time axis define the non-overlapping time intervals T1, T2, T3, and T4. In some embodiments, T1 may be approximately 5 to approximately 60 seconds, T2 may be approximately 1 to approximately 5 seconds, T3 may be approximately 5 to approximately 60 seconds, and T4 may be approximately 1 to 5 seconds. Depending on the respective processing recipe, the durations of time intervals T1, T2, T3, and T4 may be unequal. The six time axes are used to schematically display a line graph of six processing parameters versus time for one of the multiple cycles of the exemplary cyclic plasma etching process 450A shown in Figure 4A. The six processing parameters plotted in Figure 5A are power supply, bias power, processing pressure, deposition gas flow rate, etching gas flow rate, and dilution gas flow rate.

[0082] Although not specifically depicted in Figure 5A, any other processing parameters, such as temperature, can be independently controlled in each step of the cyclic plasma treatment according to the corresponding processing formulation. In some embodiments, time intervals T1 and T3 can be adjusted to stabilize the processing temperatures of T2 and T4, respectively.

[0083] In various embodiments, the substrate is maintained at a temperature between 5°C and 120°C. In some embodiments, the temperature may be varied at each step of the cyclic plasma process, and a cleaning step is used to stabilize the system before plasma generation. In alternative embodiments, the temperature may be programmed to rise or cool during the plasma steps, i.e., time intervals T2 and T4.

[0084] During the time interval T1 shown in Figure 5A, deposition gas is introduced to purge the plasma processing chamber while the power supply and bias power are turned off. In some embodiments, dilution gas may also be used selectively. In various embodiments, the total gas flow rate may be between 20 and 1000 sccm. The processing pressure may be between 5 and 100 mTorr. In some embodiments, the CH4 / Ar gas flow rate is 30 / 150 sccm, and the processing pressure is 10 mTorr.

[0085] Switching from time interval T1 to the next time interval T2 is performed by turning on the power supply and bias power to perform zone-selective plasma deposition. In this step, the formation of the polymer film requires radical-rich conditions. To achieve a radical-rich environment, a sufficiently high power supply can be applied. In various embodiments, the power supply can be between 50W and 1000W, and the bias power can be between 0W and 200W. The total gas flow rate can be between 20 and 1000 sccm. The processing pressure can be between 5 and 100 mTorr. In some embodiments, the power supply is 500W, and the bias power is 100W. The CH4 / Ar gas flow rate is 30 / 150 sccm. The processing pressure is 10 mTorr. In some embodiments, the dilution gas flow rate can be varied between T1 and T2.

[0086] Next, time interval T3 is initiated by shutting down the power supply and bias power. Simultaneously, the gas flow is switched from deposition gas to etching gas to clean the plasma processing chamber. The gas flow rate is independently selected from the conditions in T1 and T2. In various embodiments, the total gas flow rate can be between 20 and 1000 sccm. The processing pressure can be between 5 and 100 mTorr. In some embodiments, the gas flow rate of CF4 / CHF3 / Ar is 60 / 60 / 520 sccm, and the processing pressure is 10 mTorr.

[0087] After cleaning the plasma processing chamber with etching gas, time interval T4 is initiated by turning on the power supply and bias power to release the etching gas and generate plasma. During the etching step, it is important to achieve anisotropic etching conditions so that the material at the bottom of the via is sufficiently etched while causing little or no damage to the sidewalls. For anisotropic etching conditions, a relatively high bias power is required compared to the deposition step. In various embodiments, the power supply can be between 10 and 1000 W, and the bias power can be between 50 and 500 W. The total gas flow rate can be between 20 and 1000 sccm. The processing pressure can be between 5 and 100 mTorr. In some embodiments, the power supply is 50 W and the bias power is 600 W. The gas flow rate of CF4 / CHF3 / Ar is 60 / 60 / 520 sccm, and the processing pressure is 10 mTorr.

[0088] After time interval T4, a next cycle can be performed four time intervals later. This cycle can be repeated any number of times to achieve the desired processing performance. Although Figure 5A illustrates a set of conditions for one cycle of cyclic plasma processing, in various embodiments, each cycle may have conditions with different processing parameters than the first cycle, including any time interval (T1, T2, T3, and T4), gas flow rate, gas composition, processing pressure, processing temperature, power supply, and bias power.

[0089] Furthermore, it should be noted that the line graph in Figure 5A is for illustrative purposes only. For example, the figure shows that the processing parameters change in the form of a step function, but it is understood that instantaneous changes in the processing parameters are not achievable, and a finite response time must be considered before the physical parameters stabilize. In addition, as mentioned above, one or more additional processing steps, such as degassing, heat treatment under vacuum, wet treatment, plasma treatment, etc., can be inserted after any time interval (T1, T2, T3, and T4).

[0090] Figure 5B illustrates a flowchart of the circulating plasma processing according to the embodiment in Figure 5A. At a first time interval (T1) (block 510), if the power supply and bias power are on, they are turned off. A deposition gas containing carbon and a dilution gas are introduced into the plasma processing chamber containing the substrate at a first gas flow rate to clean the plasma processing chamber. At a second time interval (T2) (block 520), power supply is applied at a first level to form a plasma of the deposition gas, and the substrate is exposed to the plasma of the deposition gas. At a third time interval (T3) (block 530), power supply, the first bias power, and the deposition gas are turned off. An etching gas containing tetrafluoromethane (CF4), nitrogen trifluoride (NF3), fluoroform (CHF3), difluoromethane (CH2F2), or fluoromethane (CH3F) and a dilution gas are introduced into the plasma processing chamber at a second gas flow rate to clean the plasma processing chamber. Finally, at the fourth time interval (T4) (block 540), power is applied at the second level to form a plasma of etching gas, and the substrate is exposed to the plasma of etching gas.

[0091] Figure 6 illustrates a plasma system 600 for performing time-multiplexed cyclic plasma etching, as shown in the flowcharts of Figures 4A-4C. The plasma system 600 has a plasma processing chamber 650 configured to directly maintain plasma above a substrate 602 mounted on a substrate support 610. Processing gas can be introduced into the plasma processing chamber 650 via a gas inlet 622 and pumped out of the plasma processing chamber 650 via a gas outlet 624. The gas inlet 622 and the gas outlet 624 may each include a plurality of gas inlets and outlets. The gas flow rate and chamber pressure can be controlled by a gas flow control system 620 coupled to the gas inlet 622 and the gas outlet 624. The gas flow control system 620 may include various components such as a high-pressure gas tank, valves (e.g., throttle valves), pressure sensors, gas flow sensors, vacuum pumps, piping, and an electronically programmable controller. Radio frequency (RF) bias power supply 634 and RF source power supply 630 can be coupled to corresponding electrodes in the plasma processing chamber 650. The substrate support 610 can also be an electrode coupled to the RF bias power supply 634. The RF source power supply 630 is shown coupled to a spiral electrode 632, which coils around the dielectric sidewall 616. In FIG. 6, gas inlet 622 is an opening in the top plate 612, and gas outlet 624 is an opening in the bottom plate 614. The top plate 612 and bottom plate 614 can be conductive and electrically connected to the system ground (reference potential).

[0092] The plasma system 600 is only an example. In various alternative embodiments, the plasma system 600 may be configured to maintain inductively coupled plasma (ICP) or capacitively coupled plasma (CCP) in the plasma processing chamber 650, wherein the inductively coupled plasma has an RF source power supply coupled to a planar coil on a top dielectric cover, and the capacitively coupled plasma is maintained using a disk-shaped top electrode. Gas inlets and outlets may be coupled to the sidewalls of the plasma processing chamber, and in some embodiments, pulsed RF power and pulsed direct current (DC) power may also be used.

[0093] Figures 7A and 7B illustrate a plasma system 700 for performing a cyclic plasma process to implement spatial isolation, wherein Figure 7A is a top view and Figure 7B is a cross-sectional view. In the plasma system 700, the four components of each cycle can be performed in the four spatial isolation sections of the spatial plasma processing chamber 740. The four components of each cycle of the cyclic plasma etching process can be performed by moving the substrate using, for example, the four spatial isolation sections of the spatial plasma processing chamber 740 via a rotatable stage 710.

[0094] In the top view shown in FIG. 7A, the rotatable stage 710 is divided into four parts: a first cleaning section 745, a first plasma section 750, a second cleaning section 755, and a second plasma section 760. These four parts can be separated by, for example, an inert gas curtain 730. Each part may include one or more gas inlets and outlets. In FIG. 7A, the first plasma section 750 has a gas inlet 722 and a gas outlet 724, the second plasma section 760 has a gas inlet 723 and a gas outlet 725, and the two cleaning sections 745 and 755 have a gas inlet 720 and a gas outlet 726. Cleaning with deposition gas (block 451 in Figures 4A-4D) can be performed in the first cleaning section 745, area-selective plasma deposition (block 452 in Figures 4A-4D) is performed in the first plasma section 750, purging with etching gas (block 455 in Figures 4A-4D) is performed in the second cleaning section 755, and plasma etching (block 456 in Figures 4A-4D) is performed in the second plasma section 760.

[0095] For example, as shown in FIG7A, multiple substrates can be mounted on a rotatable stage 710. A first substrate 702, as shown, mounted on the rotatable stage 710 in a first plasma section 750, can undergo a deposition step in one cycle of a cyclic plasma etching process, and then move to a second cleaning section 755 for the next plasma etching step. Simultaneously, another substrate 704, after the plasma etching step, moves back to the first cleaning section 745 for the next plasma deposition step in the cycle. Therefore, multiple substrates can simultaneously undergo different steps of the cyclic plasma process. One revolution of the rotatable stage 710 is equivalent to one cycle of the cyclic plasma etching process.

[0096] In the cross-sectional view shown in FIG7B, plasma portions 750 and 760 are visible. In the exemplary spatial plasma processing chamber 740, plasma portions 750 and 760 are configured to maintain capacitively coupled plasma (CCP) using a top electrode 712 coupled to an RF power supply 714. In the example embodiment shown in FIG7B, a rotatable stage 710 is electrically coupled to ground. The grounded rotatable stage 710 may serve as a bottom electrode. Gas outlets 724, 725, and 726 may be connected to a vacuum pump of a gas flow system and are controlled to maintain the required pressure and gas flow rate for the corresponding portions. One of the inert gas curtains 730 is schematically indicated by a dashed line. The inert gas curtain 730 may be a flow of inert gas (e.g., argon or helium) introduced via one of the gas inlets 720.

[0097] Exemplary embodiments of the present invention are summarized herein. Other embodiments may also be understood from the overall specification and claims.

[0098] Example 1: A method for processing a substrate, the method comprising: performing a cyclic plasma process comprising multiple cycles, each of the multiple cycles comprising cleaning a plasma processing chamber containing a substrate with a first deposition gas containing carbon, the substrate comprising a first layer and a second layer, the first layer comprising silicon and the second layer comprising a metal oxide; exposing the substrate to a first plasma generated by the first deposition gas to selectively deposit a first polymer film on the first layer relative to the second layer; cleaning the plasma processing chamber with an etching gas containing fluorine; and exposing the substrate to a second plasma generated by the etching gas to etch the second layer.

[0099] Example 2: The method of Example 1, wherein the substrate includes a third layer comprising silicon and oxygen, the third layer being a different material from the first layer, and wherein during exposure of the substrate to a first plasma, the first polymer film is selectively deposited on the third layer relative to the second layer.

[0100] Example 3: The method of one of Example 1 or 2 further includes exposing the substrate to a third plasma generated by a second deposition gas containing carbon, so as to selectively deposit a second polymer film on the third layer relative to the second layer.

[0101] Example 4: The method of one of Examples 1 to 3 further includes a pretreatment step prior to cyclic plasma treatment to modify the composition of the surface end functional groups of the first or second layer.

[0102] Example 5: One of the methods of Examples 1 to 4, wherein exposing the substrate to plasma of deposition gas and exposing the substrate to plasma of etching gas are time-isolated by time multiplexing in a fixed area of ​​the plasma processing chamber.

[0103] Example 6: The method of one of Examples 1 to 5, wherein exposing the substrate to plasma of deposition gas and exposing the substrate to plasma of etching gas are spatially isolated in an isolated portion of a plasma processing chamber.

[0104] Example 7: One of Examples 1 to 6, wherein the first layer comprises silicon nitride or silicon dioxide, and wherein the second layer comprises aluminum oxide.

[0105] Example 8: The method of one of Examples 1 to 7 further includes: maintaining the substrate at a first temperature during exposure to a first plasma; and maintaining the substrate at a second temperature, which is different from the first temperature, during exposure to a second plasma.

[0106] Example 9: The method of one of Examples 1 to 8, wherein the first deposition gas contains methane (CH4) and wherein the etching gas contains tetrafluoromethane (CF4), nitrogen trifluoride (NF3), fluoroform (CHF3), difluoromethane (CH2F2) or fluoromethane (CH3F).

[0107] Example 10: The method of one of Examples 1 to 9, wherein the first deposited gas further comprises a mixture containing hydrogen (H2), argon (Ar) or nitrogen (N2).

[0108] Example 11: A method of processing a substrate, the method comprising: performing a cyclic plasma process comprising multiple cycles, one of the multiple cycles comprising: during a first time interval, applying a first power supply to a power electrode of a plasma processing chamber and a first bias power to a bias electrode of the plasma processing chamber, and allowing a carbon-containing deposition gas to flow into the plasma processing chamber to selectively deposit a polymer film on a silicon-containing layer relative to a metal oxide layer; during a second time interval, cleaning the plasma processing chamber with an etching gas containing fluorine; and during a third time interval, applying a second power supply to the power electrode and a second bias power to the bias electrode, and allowing an etching gas to flow into the plasma processing chamber to etch the metal oxide layer, during the third time interval, the silicon-containing layer being covered under the polymer film.

[0109] Example 12: The method of Example 11, wherein a loop in a plurality of loops further includes: during a fourth time interval, cleaning the plasma processing chamber with deposited gas.

[0110] Example 13: The method of one of Examples 11 or 12, wherein the first power supply power is higher than the second power supply power, and the second bias power is higher than the first bias power.

[0111] Example 14: The method of one of Examples 11 to 13, wherein a cycle in a plurality of cycles further comprises: causing a dilution gas to flow through a plasma processing chamber during a first, second, and third time interval, wherein the flow rate of the dilution gas during the second time interval is higher than that during the first time interval.

[0112] Example 15: The method of one of Examples 11 to 14, wherein the deposition gas contains hydrocarbons, the dilution gas contains argon, and the etching gas contains tetrafluoromethane (CF4), nitrogen trifluoride (NF3), fluoroform (CHF3), difluoromethane (CH2F2), or fluoromethane (CH3F).

[0113] Example 16: One of the methods of Examples 11 to 15, wherein the metal oxide layer comprises aluminum oxide.

[0114] Example 17: One of the methods of Examples 11 to 16, wherein a third time interval is selected to completely remove the polymer film.

[0115] Example 18: A method for processing a substrate, the method comprising: performing a cyclic plasma process comprising multiple cycles, each of the multiple cycles comprising: cleaning a plasma processing chamber containing a substrate with a carbon-containing deposition gas, the substrate comprising a hard mask and an interlayer dielectric (ILD) layer patterned on a metal oxide etch stop layer (ESL), the metal oxide etch stop layer (ESL) covering metal lines, the hard mask, the interlayer dielectric layer and the metal oxide etch stop layer comprising external exposed surfaces; performing a region-selective plasma deposition process by exposing the substrate to a first plasma generated by the deposition gas to preferentially deposit a polymer film on the hard mask and the interlayer dielectric layer relative to the metal oxide etch stop layer; cleaning the plasma processing chamber with an etch gas containing fluorine; and performing an etching process by exposing the substrate to a second plasma generated by an etching gas to preferentially etch the metal oxide etch stop layer relative to the hard mask and the interlayer dielectric layer.

[0116] Example 19: The method of Example 18, wherein the metal oxide etch stop layer comprises aluminum oxide, and wherein the deposition gas comprises methane, and wherein the etching gas comprises tetrafluoromethane (CF4), nitrogen trifluoride (NF3), fluoroform (CHF3), difluoromethane (CH2F2) or fluoromethane (CH3F).

[0117] Example 20: The method of one of Example 18 or 19, wherein the cyclic plasma treatment is part of the dual mosaic treatment.

[0118] Although the invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Various modifications and combinations of the illustrative embodiments and other embodiments of the invention will be apparent to those skilled in the art from the description. Therefore, the appended claims are intended to cover any such modifications or embodiments. [Simplified Explanation of the Diagram]

[0008] To more fully understand the present invention and its advantages, please now refer to the following description relating to the accompanying drawings, wherein:

[0009] Figures 1A-1M illustrate cross-sectional views of substrates undergoing various intermediate manufacturing stages of cyclic plasma processing (Figures 1G-1I) in the back-end-of-line (BEOL) process according to various embodiments, wherein Figure 1A illustrates the incoming substrate, Figure 1B illustrates after trench etching, Figure 1C illustrates after trench refilling, Figure 1D illustrates after photoresist patterning, Figure 1E illustrates after via etching, Figure 1F illustrates after removal of the top barrier layer, Figure 1G illustrates after area selective plasma deposition, Figure 1H illustrates after etch stop layer (ESL) etching, Figure 1I illustrates after cyclic plasma processing is completed, Figure 1J illustrates after removal of the bottom barrier layer, Figure 1K illustrates after diffusion barrier layer deposition, Figure 1L illustrates after metallization, and Figure 1M illustrates after planarization;

[0010] Figures 2A-2E illustrate cross-sectional views of substrates undergoing various intermediate manufacturing stages of cyclic plasma processing in the Double Embedded Back-to-Order (BEOL) process according to alternative embodiments, wherein Figure 2A illustrates the incoming substrate, Figure 2B illustrates after via etching, Figure 2C illustrates after via refilling, Figure 2D illustrates after photoresist patterning, and Figure 2E illustrates after trench etching;

[0011] Figures 3A-3C illustrate cross-sectional views of a substrate undergoing cyclic plasma treatment according to different embodiments, wherein Figure 3A illustrates the substrate after selective plasma deposition treatment in a first region, Figure 3B illustrates the substrate after selective plasma deposition treatment in a second region, and Figure 3C illustrates the substrate after etch stop layer (ESL) etching.

[0012] Figures 4A-4D illustrate flowcharts of circulating plasma processing according to various embodiments, wherein Figure 4A illustrates circulating plasma processing according to the embodiments described in Figures 1G-1I, Figure 4B shows a dual-mount BEOL processing (trench priority) including circulating plasma processing according to an example embodiment described in Figures 1A-1M, Figure 4C shows another dual-mount BEOL processing (via priority) including circulating plasma processing according to alternative embodiments described in Figures 2A-2E and 1F-1M, and Figure 4D illustrates circulating plasma processing according to other alternative embodiments described in Figures 3A-3C;

[0013] Figures 5A and 5B illustrate an embodiment of a circulating plasma treatment method in a plasma treatment tool, wherein Figure 5A illustrates a timing diagram of one cycle of a time-multiplexed implementation of the circulating plasma treatment, and Figure 5B illustrates a flowchart of the circulating plasma treatment according to the embodiment in Figure 5A.

[0014] Figure 6 illustrates a cross-sectional view of a plasma system for performing a time-multiplexed cyclic plasma etching process, as shown in the flowcharts in Figures 4A-4D and 5A-5B; and

[0015] Figures 7A and 7B illustrate a plasma system for performing a spatially isolated implementation of cyclic plasma processing, as shown in the flowcharts in Figures 4A-4D and 5A-5B, wherein Figure 7A illustrates a top view and Figure 7B illustrates a cross-sectional view.

Claims

1. A method for processing a substrate, the method comprising: performing a cyclic plasma process comprising a plurality of cycles, each of the plurality of cycles comprising cleaning a plasma processing chamber comprising a substrate comprising a silicon-containing hard mask layer and a metal oxide layer, the silicon-containing hard mask layer comprising a first outer surface and the metal oxide layer comprising a second outer surface; exposing the first outer surface and the second outer surface to a first plasma generated by the first deposition gas to selectively deposit a first polymer film on the silicon-containing hard mask layer relative to the metal oxide layer; stopping the exposure to the first plasma and cleaning the plasma processing chamber with an etching gas comprising fluorine; and exposing the substrate to a second plasma generated by the etching gas to etch the metal oxide layer, the first polymer film protecting the silicon-containing hard mask layer from etching by the second plasma.

2. The method as described in claim 1, wherein the substrate includes a third layer comprising silicon and oxygen, the third layer comprising a third outer surface exposed to the first plasma, the third layer being a different material from the silicon-containing hard mask layer, and wherein, During the exposure of the substrate to the first plasma, the first polymer film is selectively deposited on the third layer relative to the metal oxide layer.

3. The method as described in claim 2 further comprises: exposing the substrate to a third plasma generated by a second deposition gas containing carbon, to selectively deposit a second polymer film on the third layer relative to the metal oxide layer.

4. The method as described in claim 1 further comprises: performing a pretreatment step prior to the cyclic plasma treatment to modify one of the surface-terminal functional groups of the silicon-containing hard mask layer or the metal oxide layer.

5. The method as claimed in claim 1, wherein the exposure of the substrate to the first plasma of the first deposition gas and the exposure of the substrate to the second plasma of the etching gas are performed in a time-isolated region of a fixed area of ​​the plasma processing chamber.

6. The method as claimed in claim 1, wherein the first plasma exposing the substrate to the first deposition gas and the second plasma exposing the substrate to the etching gas are spatially isolated in an isolation portion of the plasma processing chamber.

7. The method as claimed in claim 1, wherein the silicon-containing hard masking layer comprises silicon nitride or silicon dioxide, and wherein the metal oxide layer comprises aluminum oxide.

8. The method as claimed in claim 1 further comprises: maintaining the substrate at a first temperature during exposure to the first plasma; and maintaining the substrate at a second temperature, different from the first temperature, during exposure to the second plasma.

9. The method as claimed in claim 1, wherein the first deposition gas comprises methane (CH4), and wherein the etching gas comprises tetrafluoromethane (CF4), nitrogen trifluoride (NF3), fluoroform (CHF3), difluoromethane (CH2F2), or fluoromethane (CH3F).

10. The method as claimed in claim 1, wherein the first deposition gas further comprises a mixture containing hydrogen (H2), argon (Ar) or nitrogen (N2).

11. The method as described in claim 1, wherein the first outer surface and the second outer surface are parallel to each other.

12. A method of processing a substrate, the method comprising: performing a cyclic plasma process to selectively etch a metal oxide layer of the substrate, the substrate including a silicon-containing layer, the cyclic plasma process comprising a plurality of cycles, one of the plurality of cycles comprising: during a first time interval, applying a first power supply to a power electrode of a plasma processing chamber and a first bias power to a bias electrode of the plasma processing chamber, and allowing a deposition gas comprising methane, ethane or ethylene to flow into the plasma processing chamber to selectively deposit a polymer film on the silicon-containing layer relative to the metal oxide layer; During a second time interval, the inflow of the deposition gas and the application of the first power supply and the first bias power are stopped, and the plasma processing chamber is cleaned with an etching gas containing fluorine; and during a third time interval, a second power supply and a second bias power are applied to the power electrode and the bias electrode, and the etching gas is allowed to flow into the plasma processing chamber to etch the metal oxide layer, during which the silicon-containing layer is covered under the polymer film.

13. The method as described in claim 12, wherein one of the plurality of cycles further comprises: during a fourth time interval, purging the plasma processing chamber with the deposited gas.

14. The method as described in claim 12, wherein the first power supply power is higher than the second power supply power, and the second bias power is higher than the first bias power.

15. The method of claim 12, wherein one of the plurality of cycles further comprises: flowing a dilution gas through the plasma processing chamber during the first, second, and third time intervals, wherein the flow rate of the dilution gas is higher during the second time interval than during the first time interval.

16. The method as described in claim 12, wherein the deposition gas comprises argon and the etching gas comprises tetrafluoromethane (CF4), nitrogen trifluoride (NF3), fluoroform (CHF3), difluoromethane (CH2F2) or fluoromethane (CH3F).

17. The method as described in claim 12, wherein the metal oxide layer comprises aluminum oxide.

18. The method as described in claim 12, wherein the third time interval is selected to completely remove the polymer film.

19. A method for processing a substrate, the method comprising: performing one of a plurality of cycles of cyclic plasma processing, each of the plurality of cycles comprising: cleaning a plasma processing chamber containing a substrate with a deposition gas containing a non-fluorinated hydrocarbon, the substrate including a hard mask and an interlayer dielectric (ILD) layer patterned on a metal oxide etch stop layer (ESL), the metal oxide etch stop layer covering a metal line, the hard mask, the interlayer dielectric layer and the metal oxide etch stop layer including an external exposed surface; performing a region-selective plasma deposition process by exposing the substrate to a first plasma generated by the deposition gas to preferentially deposit a polymer film on the hard mask and the interlayer dielectric layer relative to the metal oxide etch stop layer; After performing the selective plasma deposition process in the region, the plasma processing chamber is cleaned with an etching gas containing fluorine; and after cleaning the plasma processing chamber, an etching process is performed by exposing the substrate to a second plasma generated by the etching gas, so as to preferentially etch the metal oxide etch stop layer relative to the hard mask and the interlayer dielectric layer.

20. The method of claim 19, wherein the metal oxide etch stop layer comprises aluminum oxide, and wherein the deposition gas comprises methane, and wherein the etching gas comprises tetrafluoromethane (CF4), nitrogen trifluoride (NF3), fluoroform (CHF3), difluoromethane (CH2F2), or fluoromethane (CH3F).

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