Application processor for variable frame rate

Abstract

This invention provides an application processor, including a main processor and a display controller controlled by the main processor. The display controller controls a display device located outside the application processor and operating based on a variable frame rate scheme, receives event signals associated with frame updates of the display device, adjusts the frame rate of the display device based on the event signals, records timing information associated with frame updates of the display device based on the event signals, and provides the timing information to the main processor.

Description

Technical Field

[0001] Example embodiments are generally related to semiconductor integrated circuits, and more particularly, to an application processor for variable frame rate and a display system including the application processor. [Cross - Reference to Related Applications]

[0002] This application claims the priority of Korean Patent Application No. 10 - 2021 - 0146488, filed on October 29, 2021, with the Korean Intellectual Property Office (KIPO), the content of which is incorporated herein by reference in its entirety. Prior Art

[0003] With the development of information technology, display devices have become crucial for providing information to users. Various display devices such as liquid crystal displays (LCDs), plasma displays, and electroluminescent displays have been popularized. Among them, electroluminescent displays using light - emitting diodes (LEDs) or organic light - emitting diodes (OLEDs) that emit light by recombining electrons and holes have fast response speeds and reduced power consumption. Recently, with the development of display technology, display devices with variable frame rate have been studied, where: (1) support multiple frame rates rather than just a single / fixed frame rate and (2) change the frame rate in real - time, and various methods for driving and / or controlling display devices with variable frame rate have been studied. Summary of the Invention

[0004] At least one example embodiment of the present disclosure provides an application processor that can effectively implement variable frame rate by recording and providing display monitor information.

[0005] At least one example embodiment of the present disclosure provides a display system including an application processor.

[0006] According to an example embodiment, an application processor includes a main processor and a display controller controlled by the main processor. The display controller controls a display device located outside the application processor and operating based on a variable frame rate scheme, receives an event signal associated with a frame update of the display device, adjusts the frame rate of the display device based on the event signal, records timing information associated with the frame update of the display device based on the event signal, and provides the timing information to the main processor.

[0007] According to an example embodiment, a display system includes a display device and an application processor. The display device operates based on a variable frame rate scheme. The application processor communicates with the display device. The application processor includes a main processor and a display controller controlled by the main processor. The display controller controls the display device, receives an event signal associated with a frame update of the display device, adjusts the frame rate of the display device based on the event signal, records timing information associated with the frame update of the display device based on the event signal, and provides the timing information to the main processor.

[0008] According to an example embodiment, an application processor includes a main processor, a graphics processor, and a display controller. The main processor generates image data. The graphics processor generates rendering data by rendering the image data and generates rendering information associated with the rendering operation. The display controller is controlled by the main processor. The display controller controls a display device located outside the application processor and operating based on a variable frame rate scheme, generates frame data based on the rendering data, transmits the frame data to the display device, receives an event signal associated with a frame update of the display device from the display device, generates a frame rate control signal for adjusting the frame rate of the display device based on the event signal, transmits the frame rate control signal to the display device, records timing information associated with the frame update of the display device based on the event signal, and provides the timing information to the main processor. The main processor generates a performance / power control signal for performing at least one of performance control and power control by comparing the timing information with the rendering information. In response to the rendering rate of the graphics processor being slower than the frame rate of the display device, the main processor performs performance control to increase the rendering rate of the graphics processor. In response to the rendering rate of the graphics processor being faster than the frame rate of the display device, the main processor performs power control to reduce the power consumption of the application processor.

[0009] In an application processor and display system according to an example embodiment, a display controller may provide timing information representing a current displayed hardware state and / or condition to a main processor and / or an operating system (e.g., software) executed by the main processor. Using the timing information, the main processor may change the frame rate of a display device and may also perform performance optimization (e.g., rendering performance of a graphics processor) and / or power optimization. Accordingly, optimization of a variable frame rate scheme for a display device may be supported, and a fine-grained frame rate change may be implemented. Brief Description of the Drawings

[0010] The following detailed description, taken in conjunction with the accompanying drawings, will more clearly understand illustrative, non-limiting example embodiments. FIG. 1 is a block diagram showing an application processor according to an example embodiment. FIG. 2 is a block diagram showing an application processor and a display system including the application processor according to an example embodiment. FIG. 3 is a diagram for describing an operation of a display device included in a display system according to an example embodiment. FIG. 4 is a block diagram showing an example of a display controller included in an application processor according to an example embodiment. FIG. 5 is a diagram for describing an operation of a display controller included in an application processor according to an example embodiment. FIG. 6 is a block diagram showing an application processor according to an example embodiment. FIGS. 7, 8, and 9 are diagrams for describing an operation of an application processor according to an example embodiment. FIGS. 10 and 11 are block diagrams showing an application processor and a display system including the application processor according to an example embodiment. FIG. 12 is a block diagram showing an example of a display device included in a display system according to an example embodiment. FIG. 13 is a circuit diagram showing an example of a pixel included in a display panel, the display panel being included in the display device of FIG. 12. FIG. 14 is a flowchart showing a method of operating an application processor according to an example embodiment. FIG. 15 is a flowchart showing an example of recording timing information in FIG. 14. FIG. 16 is a flowchart showing a method of operating an application processor according to an example embodiment. FIGS. 17 and 18 are flowcharts showing an example of performing at least one of performance control and power control in FIG. 16. FIG. 19 is a block diagram showing an electronic system including a display system according to an example embodiment. Embodiment

[0011] Various exemplary embodiments will be described more fully with reference to the accompanying drawings, in which embodiments are illustrated. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Throughout this application, like reference numerals refer to like elements.

[0012] FIG. 1 is a block diagram showing an application processor according to an exemplary embodiment.

[0013] Referring to FIG. 1, an application processor (AP) 100 includes a main processor 110 and a display controller 120.

[0014] The application processor 100 controls all operations of a system including the application processor 100. For example, as will be described with reference to FIG. 2, the application processor 100 may be included in a display system (e.g., the display system 200 of FIG. 2) and may control all operations of the display system. The application processor 100 may be referred to as a host processor.

[0015] In some exemplary embodiments, the application processor 100 may be implemented in the form of a system-on-chip (SoC).

[0016] The main processor 110 controls all operations of the application processor 100. For example, the main processor 110 may execute an operating system (OS). For example, the operating system may include a file system for file management and device drivers for controlling peripheral devices, such as a display device (e.g., the display device 300 in FIG. 2) or the like at the operating system level. For example, the main processor 110 may include at least one of various processing units, such as a central processing unit (CPU) or the like.

[0017] The display controller 120 is controlled by the main processor 110 and controls the operation of the display device included in the display system. For example, the main processor 110 may generate a display control signal DCONT for controlling the display controller 120 and image data IDAT for generating frame data FDAT. For example, the image data IDAT may be directly provided to the display controller 120 as is, or the image data IDAT may be rendered by a graphics processor (e.g., the graphics processor 140 in FIG. 6) and provided to the display controller 120 as rendered data RDAT. For example, the display controller 120 may generate a control signal ICONT and frame data FDAT based on the display control signal DCONT and based on the image data IDAT or the rendered data RDAT. The control signal ICONT and the frame data FDAT may be provided to the display device. The display controller 120 may be referred to as a display processing unit (DPU).

[0018] As will be described with reference to FIG. 3, the display device may be operated and / or driven based on a variable frame rate scheme, where the frame rate (or refresh rate) is not fixed and is changeable or variable. The frame rate may represent or correspond to the number of frame images displayed on the display device during a unit time interval. The variable frame rate scheme may be referred to as a variable refresh rate (VRR) scheme, an adaptive refresh rate (ARR) scheme, or the like.

[0019] To implement the above variable frame rate scheme, the display controller 120 receives an event signal TE associated with or related to the frame update of the display device, and adjusts or controls the frame rate of the display device based on the event signal TE. For example, the control signal ICONT provided from the display controller 120 to the display device may include a frame rate control signal FCS for adjusting the frame rate of the display device.

[0020] In some example embodiments, the event signal TE associated with the frame update of the display device may be received from the display device. In other example embodiments, when the display device does not transmit the event signal TE associated with the frame update of the display device to the application processor 100, the display device may generate a timing signal corresponding to the frame update of the display device within the application processor 100 and provide the timing signal as the event signal TE. In other words, the event signal TE may be generated and / or provided externally (e.g., from the display device) or internally to the application processor 100.

[0021] In addition, to effectively implement the above variable frame rate scheme, the display controller 120 records and provides display monitoring information and / or display hardware information for the variable frame rate scheme. For example, the display controller 120 records timing information TINF associated with or related to the frame update of the display device based on the event signal TE, and provides the timing information TINF to the main processor 110. The configuration and operation of recording and providing the timing information TINF will be described in detail with reference to FIGS. 4 and 5.

[0022] In some example embodiments, the main processor 110 may perform at least one of performance control and power control based on the timing information TINF. For example, the main processor 110 may generate a performance / power control signal PCONT for performing at least one of performance control and power control based on the timing information TINF. Examples of performance control and power control will be described in detail with reference to FIGS. 6 to 9.

[0023] FIG. 2 is a block diagram showing an application processor and a display system including the application processor according to an example embodiment.

[0024] Referring to FIG. 2, the display system 200 includes an application processor 100 and a display device 300.

[0025] The application processor 100 may be an application processor according to an example embodiment and may be substantially the same as the application processor 100 in FIG. 1. The application processor 100 includes a main processor (MP) 110 and a display controller (DC) 120. The application processor 100 transmits a control signal ICONT and frame data FDAT to the display device 300 and receives an event signal TE. For example, the event signal TE may be received from the display device 300. The display controller 120 generates timing information TINF based on the event signal TE and transmits the timing information TINF to the main processor 110.

[0026] The display device 300 includes a display driver integrated (DDI) circuit 310 and a display panel 360.

[0027] The display driver integrated circuit 310 controls the operation of the display device 300. For example, the display driver integrated circuit 310 may receive a control signal ICONT and frame data FDAT from the application processor 100, and may control the display panel 360 based on the control signal ICONT such that a frame image corresponding to the frame data FDAT is displayed on the display panel 360. Additionally, the display driver integrated circuit 310 may transmit an event signal TE to the application processor 100. For example, the event signal TE may include a tearing effect signal.

[0028] The display panel 360 may perform an image display operation (e.g., may display a frame image) based on or under the control of the display driver integrated circuit 310.

[0029] Examples of the display device 300, the display driver integrated circuit 310, and the display panel 360 will be described in detail with reference to FIGS. 12 and 13.

[0030] Although FIG. 2 shows that the event signal TE is generated and / or provided outside the application processor 100 (e.g., from the display device 300), example embodiments are not limited thereto. For example, the event signal TE may be generated and / or provided inside the application processor 100.

[0031] FIG. 3 is a diagram for describing the operation of a display device included in a display system according to an example embodiment.

[0032] Referring to FIG. 3, an example of a frame image FIMG displayed on the display device 300 over time is shown.

[0033] As described with reference to FIG. 1, the display device 300 may be operated and / or driven by a variable frame rate scheme, where the frame rate is variable or changeable under the control of the display controller 120 (e.g., based on a frame rate control signal FCS).

[0034] For example, during the first operation stage DUR_FR1, the display device 300 may display the frame image FIMG based on the first frame rate (or the first driving frequency). During the second operation stage DUR_FR2 after the first operation stage DUR_FR1, the display device 300 may display the frame image FIMG based on the second frame rate (or the second driving frequency). During the third operation stage DUR_FR3 after the second operation stage DUR_FR2, the display device 300 may display the frame image FIMG based on the third frame rate (or the third driving frequency). In the first operation stage DUR_FR1, the reciprocal of the first time interval T1 between the frame images FIMG may correspond to the first frame rate. In the second operation stage DUR_FR2, the reciprocal of the second time interval T2 between the frame images FIMG may correspond to the second frame rate. In the third operation stage DUR_FR3, the reciprocal of the third time interval T3 between the frame images FIMG may correspond to the third frame rate. For example, FIG. 3 shows that the first time interval T1 is longer than the second time interval T2 and shorter than the third time interval T3, and thus the first frame rate is slower or lower than the second frame rate and faster or higher than the third frame rate. However, the example embodiments are not limited thereto.

[0035] In addition, FIG. 3 shows that all the frame images FIMG may have the same resolution (e.g., the first resolution). For ease of illustration, the resolution of one frame image is shown by the number of small squares included in one frame image.

[0036] FIG. 4 is a block diagram showing an example of a display controller included in an application processor according to an example embodiment.

[0037] Referring to FIG. 4, the display controller 120 may include trigger control logic 122, display timer logic 124, and frame rate control logic 126. The display controller 120 may further include image processing logic 128.

[0038] The trigger control logic 122 may detect an event source. For example, the event source may include an event signal TE received from the display device 300, and the trigger control logic 122 may detect the event signal TE. For another example, the event source may include a timing signal generated inside the application processor 100, and the trigger control logic 122 may detect the timing signal as the event signal TE. The trigger control logic 122 may control the frame rate control logic 126 such that an operation of recording the timing information TINF is triggered based on the event signal TE.

[0039] The display timer logic 124 may record timing information TINF based on the event signal TE. The display timer logic 124 may be referred to as event-driven timer logic.

[0040] The display timer logic 124 may include multiple timers 124a, 124b, and 124c. For example, the multiple timers 124a, 124b, and 124c may include a first timer to an Nth timer, where N is a natural number greater than or equal to two.

[0041] Each of the multiple timers 124a, 124b, and 124c may measure a respective one of the multiple time data included in the timing information TINF. For example, a frame interval during which the display device 300 displays a frame image may be divided into multiple sub-intervals, each of the multiple sub-intervals may correspond to a time interval from a start time point to an end time point, and the multiple timers 124a, 124b, and 124c may be operable to measure the lengths of different sub-intervals among the multiple sub-intervals associated with the frame interval. For example, each of the multiple timers 124a, 124b, and 124c may include a counter that operates based on a clock signal.

[0042] The frame rate control logic 126 may adjust the frame rate of the display device 300 based on the event signal TE. For example, the frame rate control logic 126 may generate a control signal ICONT for controlling the display device 300 based on the event signal TE and the display control signal DCONT provided by the host processor 110, and the control signal ICONT may include a frame rate control signal FCS.

[0043] The frame rate control logic 126 may control the start timing and end timing of the multiple timers 124a, 124b, and 124c based on the event signal TE for recording the timing information TINF. Additionally, the frame rate control logic 126 may assign each of the multiple timers 124a, 124b, and 124c to at least one of the multiple sub-intervals such that the multiple timers 124a, 124b, and 124c measure the lengths of different sub-intervals.

[0044] The frame rate control logic 126 can output timing information TINF. For example, the timing information TINF may include vertical synchronization time information (e.g., Tvsync), skew time information (e.g., Tskew), scan output time information (e.g., Tscanout), or the like. As described with reference to FIG. 1, the timing information TINF can be provided to the main processor 110, and the main processor 110 can generate a performance / power control signal PCONT based on the timing information TINF.

[0045] In some example embodiments, although not shown in detail, the timing information TINF can be stored in a register included in the display controller 120, and software such as an operating system executed by the main processor 110 can obtain the timing information TINF by reading the value of the register. In other example embodiments, the timing information TINF can be implemented as a separate signal transmitted via a physical interface.

[0046] The image processing logic 128 can generate frame data FDAT based on the display control signal DCONT and based on the image data IDAT or the rendering data RDAT.

[0047] In some example embodiments, although not shown in detail, the image processing logic 128 can include a blender and a display quality enhancer. The blender can generate image data by blending multiple layer data corresponding to multiple images to be displayed on one screen of the display device 300. The display quality enhancer can perform at least one display quality enhancement algorithm on the image data.

[0048] Blending refers to the operation of calculating the pixel values actually displayed among several layers (e.g., images) constituting a screen. When blending is performed, the pixel values actually displayed on each pixel can be obtained. For example, when only one layer is placed, configured, or positioned on a pixel, the pixel value included in one layer can be obtained as it is. When two or more than two layers are placed on a pixel, the pixel value included in one of the two or more than two layers can be obtained, or a new pixel value can be obtained based on the pixel values included in the two or more than two layers. Blending can be referred to as mixing and / or composition.

[0049] In some example embodiments, at least one display quality enhancement algorithm may include detail enhancement (DE), scaling (or scaler), adaptive tone map control (ATC), hue saturation control (HSC), gamma and de-gamma, Android open source project (AOSP), color gamut control (CGC), dithering technique (or dithering), round corner display (RCD), sub-pixel rendering (SPR), or the like. DE may represent an algorithm for sharpening the contours of an image. Scaling may represent an algorithm for changing the size of an image. ATC may represent an algorithm for improving outdoor visibility. HSC may represent an algorithm for improving the hue and saturation of colors. Gamma may represent an algorithm for gamma correction or compensation. AOSP may represent an algorithm for processing an image conversion matrix defined by the Android OS (e.g., a mode for colorblind or night mode). CGC may represent an algorithm for matching the color coordinates of a display panel. The dithering technique may represent an algorithm for using a limited number of colors to represent the effect of high-bit colors. RCD may represent an algorithm for processing the round corners of a display panel. SPR may represent an algorithm for increasing the resolution. However, example embodiments are not limited thereto, and at least one display quality enhancement algorithm may further include various other algorithms.

[0050] In some example embodiments, at least some components of the display controller 120 may be implemented as hardware. For example, at least some components of the display controller 120 may be included in a computer-based electronic system. In other example embodiments, at least some components of the display controller 120 may be implemented as an instruction code or a program routine (e.g., a software program). For example, the instruction code or the program routine may be executed by a computer-based electronic system and may be stored in any storage device located inside or outside the computer-based electronic system.

[0051] FIG. 5 is a diagram for describing the operation of a display controller included in an application processor according to an example embodiment.

[0052] Referring to FIG. 5, an example of an event signal TE received by the display controller 120 is shown, and examples of operations of timer TMR1, timer TMR2, and timer TMR3 included in the display controller 120 based on the event signal TE are shown.

[0053] The event signal TE may be activated at time point t1 and deactivated at time point t4. When the event signal TE is activated, the display device 300 may allow the frame image to start. For example, during the activation period of the event signal TE, for example, during the time interval between time point t1 and time point t4, during which the event signal TE has a logic high level, the display device 300 may start displaying the frame image. Additionally, the event signal TE may be activated again at time point t6, and the time interval between time point t1 and time point t6 may represent a cycle (or period) of the event signal TE.

[0054] In some exemplary embodiments, a variable frame rate scheme may be implemented by differently setting the start time point of each frame image within the activation period of the event signal TE (e.g., the time interval between time point t1 and time point t4), while fixing the length of the activation period of the event signal TE and the cycle of the event signal TE (e.g., the time interval between time point t1 and time point t6). However, the exemplary embodiments are not limited thereto, and a variable frame rate scheme may be implemented by changing the length of the activation period of the event signal TE for each frame image or by changing the cycle of the event signal TE for each frame image.

[0055] For example, the display device 300 may start the frame image at time point t2 within the time interval between time point t1 and time point t4. The first time interval TSC between time point t2 and time point t3 may represent a scan output period corresponding to the waiting time during the operation of the display device 300. The second time interval TPT between time point t3 and time point t5 may represent a pixel transfer period, during which data signals are transmitted to a plurality of pixels (e.g., the plurality of pixels PX in FIG. 12) included in the display panel 360 of the display device 300. The display device 300 may end the frame image at time t5. The third time interval TID between time point t5 and time point t6 may represent an idle period after the signal transmission is completed and before the event signal TE is activated again.

[0056] The event signal TE can be activated again at time point t6. The fourth time interval TTA between time point t6 and time point t7 can represent a trigger permission period. Although not shown in detail, the time interval between time point t1 and time point t2 can also include a trigger permission period such as the fourth interval TTA.

[0057] The time interval between time point t1 and time point t6 corresponding to one cycle of the event signal TE or the time interval between time point t2 and time point t7 including the first time interval TSC, the second time interval TPT, the third time interval TID, and the fourth time interval TTA can represent a frame period, during which the display device 300 displays a frame image. The display device 300 can display multiple frame images by repeating multiple frame periods, and the variable frame rate scheme can be implemented by setting the lengths of the frame periods differently according to the various methods described above.

[0058] In some exemplary embodiments, for recording and providing timing information TINF, the frame rate control logic 126 can allocate timer TMR1, timer TMR2, and timer TMR3 to different time intervals, can use timer TMR1, timer TMR2, and timer TMR3 to perform time measurements, can read and output the timing information TINF recorded in timer TMR1, timer TMR2, and timer TMR3 as the results of the time measurements, and can reset (or start or clear) timer TMR1, timer TMR2, and timer TMR3.

[0059] For example, under the control of the frame rate control logic 126, timer TMR1 can be allocated to measure the lengths of the first time interval TSC, the second time interval TPT, the third time interval TID, and the fourth time interval TTA, timer TMR2 can be allocated to measure the length of the first time interval TSC, and timer TMR3 can be allocated to measure the lengths of the third time interval TID and the fourth time interval TTA. In some exemplary embodiments, the allocation of timer TMR1, timer TMR2, and timer TMR3 can be determined in advance at the initial operation time (e.g., when manufacturing the display system 200). In other exemplary embodiments, during the operation of the display system 200, the allocation of timer TMR1, timer TMR2, and timer TMR3 can be changed in real time (or during the runtime).

[0060] In addition, under the control of the frame rate control logic 126, the time measurement using timer TMR1 can start at time point t2, and the time measurement using timer TMR1 can be completed at time point t7. Similarly, the time measurement using timer TMR2 can start at time point t2, and the time measurement using timer TMR2 can be completed at time point t3. The time measurement using timer TMR3 can start at time point t5, and the time measurement using timer TMR3 can be completed at time point t7.

[0061] The frame rate control logic 126 can read first timing information corresponding to the lengths of the first time interval TSC, the second time interval TPT, the third time interval TID, and the fourth time interval TTA from timer TMR1, can read second timing information corresponding to the length of the first time interval TSC from timer TMR2, can read third timing information corresponding to the lengths of the third time interval TID and the fourth time interval TTA from timer TMR3, can output timing information TINF including the first timing information, the second timing information, and the third timing information, and can transmit the timing information TINF to the main processor 110. Thereafter, the frame rate control logic 126 can reset timer TMR1, timer TMR2, and timer TMR3 for subsequent time measurements.

[0062] In the application processor 100 and the display system 200 according to an example embodiment, the event-driven timer of the display controller 120 can be implemented by a plurality of display timers, and the event sources of the display timers can be assigned to hardware logic events. In addition, the event sources of the display timers can be set to software, the display timers can be driven by software, and the values of the display timers can be read and reset by software.

[0063] FIG. 6 is a block diagram showing an application processor according to an example embodiment. Descriptions repeated with FIG. 1 will be omitted.

[0064] Referring to FIG. 6, the application processor 102 includes a main processor 110 and a display controller 120. The application processor 102 may further include a display interface 130, a graphics processor 140, and a power management unit and clock management unit (PMU / CMU) 150.

[0065] The main processor 110 may be described with reference to FIG. 1. The main processor 110 may generate a display control signal DCONT and image data IDAT, and may generate a performance / power control signal PCONT for performing performance control and / or power control based on timing information TINF and rendering information RINF.

[0066] The display controller 120 may be described with reference to FIG. 1. The display controller 120 may generate a control signal ICONT and frame data FDAT based on the display control signal DCONT and rendering data RDAT, and may generate timing information TINF based on an event signal TE. For example, as will be described with reference to FIGS. 10 and 11, when the event signal TE is generated and provided outside the application processor 102 (e.g., from the display device 300), the event signal TE may be received from the display device 300 (e.g., from the display driver integrated circuit 310) via a separate pin and / or channel other than the display interface 130. However, the exemplary embodiments are not limited thereto, and the event signal TE may be generated and provided inside the application processor 102.

[0067] The display interface 130 may be used to communicate with the display device 300. The display interface 130 may transmit the control signal ICONT and the frame data FDAT to the display device 300 (e.g., to the display driver integrated circuit 310).

[0068] In some exemplary embodiments, the display interface 130 may be implemented based on one of various display interface standards, such as one of a mobile industry processor interface (MIPI), a high definition multimedia interface (HDMI), a display port (DP), a low power display port (LPDP), and an advanced low power display port (ALPDP).

[0069] The graphics processor 140 can display the frame images shown on the display device 300. For example, the graphics processor 140 can generate the display data RDAT by displaying the image data IDAT, and can generate the display information RINF associated with the display operation. For example, the display information RINF can include the display rate of the graphics processor 140. For example, the graphics processor 140 can include a graphic processing unit (GPU) or the like.

[0070] The power management unit and the clock management unit 150 can control, manage, and adjust the power and / or the clock signals SCLK and GCLK supplied to the application processor 102. For example, the clock signals SCLK and GCLK can include the system drive clock signal SCLK commonly used in the application processor 102, the graphic drive clock signal GCLK used in the graphics processor 140, or the like. Although not shown in detail, the power can include multiple drive voltages used in the application processor 102.

[0071] In some example embodiments, the main processor 110 can perform at least one of performance control and power control by comparing the timing information TINF with the display information RINF. For example, the main processor 110 can perform at least one of performance control and power control by controlling the operations of the graphics processor 140 and the power management unit and the clock management unit 150 based on the performance / power control signal PCONT. The performance control and the power control will be described with reference to FIGS. 7 to 9.

[0072] Although not shown in FIG. 6, the application processor 102 can further include a system bus, a memory, and multiple functional modules. The system bus can correspond to the signal transmission path between the components in the application processor 102. The memory can store the instructions and data for the operation of the application processor 102. The multiple functional modules can perform various functions of the host processor.

[0073] In some example embodiments, the memory may include volatile memory such as dynamic random access memory (DRAM), static random access memory (SRAM), or the like. In some example embodiments, the memory may include non-volatile memory such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, phase change random access memory (PRAM), resistance random access memory (RRAM), nano floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), or the like. In some example embodiments, the memory may further include a solid state drive (SSD), universal flash storage (UFS), multi-media card (MMC), embedded multi-media card (eMMC), secure digital (SD) card, micro SD card, memory stick, chip card, universal serial bus (USB) card, smart card, compact flash (CF) card, or the like.

[0074] In some example embodiments, the multiple functional modules may include a communication module that performs communication functions (e.g., a code division multiple access (CDMA) module, a long term evolution (LTE) module, a radio frequency (RF) module, an ultra-wideband (UWB) module, a wireless local area network (WLAN) module, a worldwide interoperability for microwave access (WIMAX) module, or the like), a camera module that performs camera functions, an input-output (I / O) module that performs user interface functions (e.g., a touch panel module that performs touch sensing functions), and an audio module that performs I / O of audio signals, including a microphone (MIC) module, a speaker module, or the like. In some example embodiments, the multiple functional modules may further include a global positioning system (GPS) module, a gyroscope module, or the like.

[0075] FIGS. 7, 8, and 9 are diagrams for describing the operation of an application processor according to an example embodiment.

[0076] Referring to FIGS. 7, 8, and 9, examples for describing the performance control and power control of the main processor 110 included in the application processor 102 are shown.

[0077] In FIGS. 7, 8, and 9, "RIMG" represents a display image corresponding to the display data RDAT and used to describe the display rate of the graphics processor 140. "FIMG" represents a frame image corresponding to the frame data FDAT and used to describe the frame rate of the display device 300. "GCLK" and "SCLK" respectively represent the graphics drive clock signal GCLK and the system drive clock signal SCLK generated by the power management unit and the clock management unit 150.

[0078] In some example embodiments, as shown in FIG. 7, when the display rate of the graphics processor 140 is slower than the frame rate of the display device 300, the main processor 110 may perform performance control based on the performance / power control signal PCONT generated based on the timing information TINF, so that the display rate of the graphics processor 140 increases.

[0079] For example, during a first operation phase DUR11 in an initial operation time, the graphics processor 140 can generate rendering images RIMG1, RIMG2, and RIMG3 by performing rendering operations at each time interval TR11, and the rendering rate of the graphics processor 140 can correspond to the reciprocal of the time interval TR11. The display device 300 can display frame images FIMG1, FIMG2, and FIMG3 corresponding to the rendering images RIMG1, RIMG2, and RIMG3 by performing frame updates at each time interval TF11, and the frame rate of the display device 300 can correspond to the reciprocal of the time interval TF11. The time interval TF11 can be shorter than the time interval TR11, and thus, the rendering rate of the graphics processor 140 can be slower than the frame rate of the display device 300.

[0080] As shown in FIG. 7, since the rendering rate of the graphics processor 140 is slower than the frame rate of the display device 300, there may be a problem that the operation of generating the rendering image by the graphics processor 140 is later than (or relative to the delay) the operation of displaying the frame image by the display device 300. Therefore, to solve this problem, it is necessary to increase the rendering rate to match the rendering rate with the frame rate. The main processor 110 can generate a performance / power control signal PCONT for increasing the rendering rate of the graphics processor 140 based on the timing information TINF, and can perform performance control based on the performance / power control signal PCONT to increase the rendering rate of the graphics processor 140.

[0081] For example, during a second operation phase DUR12 after the first operation phase DUR11, the graphics processor 140 can generate rendering images RIMG4, RIMG5, and RIMG6 by performing rendering operations at each time interval TR12 (shorter than the time interval TR11), and the rendering rate of the graphics processor 140 can correspond to the reciprocal of the time interval TR12. The display device 300 can display frame images FIMG4, FIMG5, and FIMG6 corresponding to the rendering images RIMG4, RIMG5, and RIMG6 by performing frame updates, and can maintain the frame rate of the display device 300 (for example, can also correspond to the reciprocal of the time interval TF11). However, the exemplary embodiments are not limited thereto, and the frame rate can be changed.

[0082] For example, the rendering rate of the graphics processor 140 can be increased by increasing the frequency of the driving clock signal of the graphics processor 140. For example, the graphics driving clock signal GCLK supplied to the graphics processor 140 can have a first cycle TC11 in the first operation period DUR11 and can have a second cycle TC12 in the second operation period DUR12. As shown in FIG. 7, the second cycle TC12 can be shorter than the first cycle TC11, and thus, the frequency of the graphics driving clock signal GCLK can be increased.

[0083] Although FIG. 7 shows only operations for improving or enhancing the performance of the graphics processor 140, the exemplary embodiments are not limited thereto, and operations for improving the performance of the memory associated with or related to the graphics processor 140 can be performed.

[0084] In other exemplary embodiments, as shown in FIG. 8, when the rendering rate of the graphics processor 140 is faster than the frame rate of the display device 300, the main processor 110 can perform power control based on the performance / power control signal PCONT generated based on the timing information TINF, so that the power consumption of the application processor 102 is reduced and / or the rendering rate of the graphics processor 140 is decreased.

[0085] For example, as described with reference to FIG. 7, during the first operation period DUR11 at the initial operation time, the graphics processor 140 can generate the rendered images RIMG1, RIMG2, and RIMG3 by performing rendering operations at each time interval TR11, and the rendering rate of the graphics processor 140 can correspond to the reciprocal of the time interval TR11. Different from that described with reference to FIG. 7, during the first operation period DUR11, the display device 300 can display the frame images FIMG1, FIMG2, and FIMG3 corresponding to the rendered images RIMG1, RIMG2, and RIMG3 by performing frame updates at each time interval TF12, and the frame rate of the display device 300 can correspond to the reciprocal of the time interval TF12. The time interval TF12 can be longer than the time interval TF11 and the time interval TR11, and thus, the rendering rate of the graphics processor 140 can be faster than the frame rate of the display device 300.

[0086] As shown in FIG. 8, since the rendering rate of the graphics processor 140 is faster than the frame rate of the display device 300, there may be a problem that the operation of generating a rendered image by the graphics processor 140 is earlier than the operation of displaying a frame image by the display device 300. Therefore, to solve this problem, it is necessary to reduce power consumption and / or reduce the rendering rate to match the rendering rate with the frame rate. The main processor 110 can generate a performance / power control signal PCONT based on the timing information TINF for reducing power consumption and / or reducing the rendering rate, and can perform power control based on the performance / power control signal PCONT so that the power consumption of the application processor 102 is reduced and / or the rendering rate of the graphics processor 140 is reduced.

[0087] For example, during the third operation period DUR13 after the first operation period DUR11, the graphics processor 140 can generate a rendered image RIMG4 by performing a rendering operation at each time interval TR13 (longer than the time interval TR11), and the rendering rate of the graphics processor 140 can correspond to the reciprocal of the time interval TR13. The display device 300 can display a frame image FIMG4 corresponding to the rendered image RIMG4 by performing a frame update, and can maintain the frame rate of the display device 300. However, the example embodiments are not limited thereto, and the frame rate can be changed.

[0088] For example, the power consumption of the application processor 102 can be reduced by reducing the frequency of the driving clock signal of the graphics processor 140 and / or the system clock signal of the application processor 102. For example, the graphics driving clock signal GCLK supplied to the graphics processor 140 and / or the system driving clock signal SCLK supplied to the application processor 102 can have a first cycle TC11 in the first operation period DUR11 and can have a third cycle TC13 in the third operation period DUR13. As shown in FIG. 8, the third cycle TC13 can be longer than the first cycle TC11, and therefore, the frequency of the graphics driving clock signal GCLK and / or the frequency of the system driving clock signal SCLK can be reduced.

[0089] In still other example embodiments, as shown in FIG. 9, even if the rendering rate of the graphics processor 140 is faster than the frame rate of the display device 300, the main processor 110 may not perform performance control and / or power control. For example, as will be described with reference to FIG. 11, when the display device 300 includes multiple frame buffers, multiple frame data corresponding to multiple frame images may be stored in the multiple frame buffers. Therefore, even if the operation of generating the rendered image by the graphics processor 140 is earlier than the operation of displaying the frame image by the display device 300, the rendered image may be transmitted to the display device 300 and stored in the display device 300 while maintaining the rendering rate of the graphics processor 140.

[0090] Although example embodiments are described based on examples of controlling the rendering performance of the graphics processor 140 and / or the power consumption of the application processor 102 based on the timing information TINF, the example embodiments are not limited thereto. For example, since the display device 300 operates based on a variable frame rate scheme, the frame rate of the display device 300 may be controlled or adjusted based on the timing information TINF. For example, in the example of FIG. 7, the frame rate of the display device 300 may be decreased, or in the example of FIG. 8, the frame rate of the display device 300 may be increased.

[0091] In the application processor 100 and the display system 200 according to the example embodiments, the display controller 120 may provide the timing information TINF indicating the current display hardware state and / or condition to the main processor 110 and / or the operating system (e.g., software) executed by the main processor 110. Using the timing information TINF, the main processor 110 may change the frame rate of the display device 300 and may also perform performance optimization (e.g., the rendering performance of the graphics processor 140) and / or power optimization. Therefore, optimization for the variable frame rate scheme of the display device 300 may be supported and fine-grained frame rate changes may be implemented.

[0092] FIGS. 10 and 11 are block diagrams showing an application processor and a display system including the application processor according to the example embodiments. Descriptions that are repeated with FIGS. 2 and 6 will be omitted.

[0093] Referring to FIG. 10, the display system 202 includes an application processor 102 and a display driver integrated circuit 312. For ease of illustration, the display panel 360 in FIG. 2 is omitted.

[0094] The application processor 102 may include a main processor 110, a display controller 120, a display interface 130, a graphics processor 140, and a power management unit and a clock management unit 150. The application processor 102 may further include a first pin 132. The application processor 102 may be substantially the same as the application processor 102 of FIG. 6.

[0095] The display driver integrated circuit 312 may include a display interface 320, a frame buffer 330, a timing controller 340, and a column / row driver 350. The display driver integrated circuit 312 may further include a second pin 322.

[0096] The display interface 320 may receive a control signal ICONT and frame data FDAT from the application processor 102. For example, the display interface 320 may be implemented based on a display interface standard that is substantially the same as the display interface standard of the display interface 130.

[0097] When an event signal TE is generated and provided outside the application processor 102 (e.g., from the display driver integrated circuit 312), the event signal TE may be transmitted from the display driver integrated circuit 312 to the application processor 102 via the first pin 132 and the second pin 322 and a first channel between the first pin 132 and the second pin 322. For example, the first pin 132, the second pin 322, and the first channel may be formed individually, separately, and / or independently from the display interface 130 and the display interface 320 and a second channel formed for the display interface 130 and the display interface 320. For example, the pins may represent contact pads or contact pins, but are not limited thereto. However, the example embodiments are not limited thereto, and the event signal TE may be generated and provided inside the application processor 102.

[0098] The frame buffer 330 may temporarily store a frame image and frame data FDAT corresponding to the frame image. The display driver integrated circuit 312 may include one frame buffer 330, and the frame buffer 330 may store one frame image and frame data corresponding to one frame image at one time (or simultaneously).

[0099] The timing controller 340 may generate a first control signal CS1, a second control signal CS2, and a data signal DS based on the control signal ICONT and the frame data FDAT. The timing controller 340 may generate the event signal TE.

[0100] The column / row driver 350 can generate a plurality of data voltages VD and a plurality of scan signals SC provided to the display panel 360 based on the first control signal CS1, the second control signal CS2, and the data signal DS. The display panel 360 can display a frame image corresponding to the frame data FDAT based on the plurality of data voltages VD and the plurality of scan signals SC.

[0101] The display system 202 can operate as described with reference to FIGS. 7 and 8. For example, as shown in FIG. 7, when the rendering rate of the graphics processor 140 is slower than the frame rate of the display device 300, the main processor 110 can perform performance control to increase the rendering rate of the graphics processor 140. For example, as shown in FIG. 8, when the rendering rate of the graphics processor 140 is faster than the frame rate of the display device 300, the main processor 110 can perform power control to reduce the power consumption of the application processor 102 and / or reduce the rendering rate of the graphics processor 140. However, the exemplary embodiments are not limited thereto, and the frame rate can be controlled based on the timing information TINF.

[0102] Referring to FIG. 11, the display system 204 includes an application processor 102 and a display driver integrated circuit 314.

[0103] The display system 204 can be substantially the same as the display system 202 of FIG. 10, except for the configuration part of the display driver integrated circuit 314. The description repeated with FIG. 10 will be omitted.

[0104] The display driver integrated circuit 314 can include a display interface 320, a plurality of frame buffers (FB) 334, a timing controller 340, and a column / row driver 350. The display driver integrated circuit 314 can further include a second pin 322.

[0105] The plurality of frame buffers 334 can temporarily store frame images and frame data FDAT corresponding to the frame images. The display driver integrated circuit 314 can include two or more than two frame buffers 334. Since one frame buffer stores one frame image and the frame data corresponding to one frame image at a time, the plurality of frame buffers 334 can store a plurality of frame images and the frame data corresponding to the plurality of frame images simultaneously.

[0106] The display system 204 can operate as described with reference to FIGS. 7 and 8 and can also operate as described with reference to FIG. 9. For example, as shown in FIG. 9, even if the rendering rate of the graphics processor 140 is faster than the frame rate of the display device 300, the main processor 110 can still maintain the rendering rate of the graphics processor 140, and the display driver integrated circuit 314 can store multiple frame images and frame data corresponding to the multiple frame images, where the multiple frame images are received from the application processor 102 in the multiple frame buffers 334.

[0107] FIG. 12 is a block diagram showing an example of a display device included in a display system according to an exemplary embodiment.

[0108] Referring to FIG. 12, the display device 700 includes a display panel 710 and a display driver integrated circuit. The display driver integrated circuit may include a data driver 720, a scan driver 730, a power supply 740, a timing controller 750, and a frame buffer 760.

[0109] The display panel 710 can operate based on the frame data FDAT (e.g., display frame images). The display panel 710 can be connected to the data driver 720 via multiple data lines D1, D2,..., DM, and can be connected to the scan driver 730 via multiple scan lines S1, S2,..., SN. The multiple data lines D1, D2,..., DM can extend in a first direction, and the multiple scan lines S1, S2,..., SN can extend in a second direction that intersects (e.g., is substantially perpendicular to) the first direction.

[0110] The display panel 710 may include multiple pixels PX arranged in a matrix form having multiple columns and multiple rows. As will be described with reference to FIG. 13, each of the multiple pixels PX may include a light-emitting element and at least one transistor for driving the light-emitting element. Each of the multiple pixels PX can be electrically connected to respective ones of the multiple data lines D1, D2,..., DM and respective ones of the multiple scan lines S1, S2,..., SN.

[0111] In some exemplary embodiments, the display panel 710 can be a display panel that operates based on a variable frame rate scheme and is controlled by an application processor according to an exemplary embodiment.

[0112] In some exemplary embodiments, the display panel 710 may be a self-emissive display panel that emits light without using a backlight unit. For example, the display panel 710 may be an organic light-emitting display panel including organic light-emitting diode (OLED) light-emitting elements.

[0113] In some exemplary embodiments, depending on the driving scheme of the display device 700, each of the plurality of pixels PX included in the display panel 710 may have various configurations. For example, the display device 700 may be driven by an analog or digital driving scheme. Although the analog driving scheme uses a variable voltage level corresponding to input data to generate gray levels, the digital driving scheme uses a variable duration of light emission of a light-emitting diode to generate gray levels. The analog driving scheme is difficult to implement because if the display is large and has a high resolution, the analog driving scheme requires a complex driving integrated circuit (IC) to be manufactured. On the other hand, the digital driving scheme can achieve the required high resolution via a simpler IC structure. An example of each of the plurality of pixels PX will be described with reference to FIG. 13.

[0114] The frame buffer 760 may receive frame data FDAT from the application processor 100, temporarily store the frame data FDAT, and output the frame data FDAT. Although only one frame buffer 760 is shown in FIG. 12 for convenience of explanation, the exemplary embodiments are not limited thereto. For example, as described with reference to FIGS. 10 and 11, the number of frame buffers may be determined in different ways according to the exemplary embodiments.

[0115] The timing controller 750 may control all operations of the display device 700. For example, the timing controller 750 may receive a control signal ICONT including a frame rate control signal FCS from the application processor 100, and may provide a pre-determined control signal CS1, a control signal CS2, and a control signal CS3 to the data driver 720, the scan driver 730, and the power supply 740 based on the control signal ICONT to control the operation of the display device 700. For example, the control signal CS1, the control signal CS2, and the control signal CS3 may include a vertical synchronization signal and a horizontal synchronization signal used inside the display device 700.

[0116] The timing controller 750 can receive frame data FDAT received from the application processor 100 from the frame buffer 760, and can generate data signals for displaying frame images based on the frame data FDAT. For example, the frame data FDAT may include red image data, green image data, and blue image data. Additionally, the frame data FDAT may further include white image data. Alternatively, the frame data FDAT may include magenta image data, yellow image data, cyan image data, or the like.

[0117] In addition, the timing controller 750 can generate an event signal TE and transmit the event signal TE to the application processor 100.

[0118] The data driver 720 can generate a plurality of data voltages based on the control signal CS1 and the data signal DS, and can apply the plurality of data voltages to the display panel 710 via a plurality of data lines D1, data line D2,..., data line DM. For example, the data driver 720 may include a digital-to-analog converter (DAC) that converts the data signal DS in digital form into a plurality of data voltages in analog form.

[0119] The scan driver 730 can generate a plurality of scan signals based on the control signal CS2 and can apply the plurality of scan signals to the display panel 710 via a plurality of scan lines S1, scan line S2,..., scan line SN. The plurality of scan lines S1, scan line S2,..., scan line SN can be sequentially activated based on the plurality of scan signals.

[0120] The frame buffer 760 can correspond to the frame buffers 330 and 334 in FIGS. 10 and 11, the timing controller 750 can correspond to the timing controller 340 in FIGS. 10 and 11, and the data driver 720 and the scan driver 730 can correspond to the column / row driver 350 in FIGS. 10 and 11.

[0121] In some exemplary embodiments, the data driver 720, the scan driver 730, and the timing controller 750 can be implemented as one integrated circuit. In other exemplary embodiments, the data driver 720, the scan driver 730, and the timing controller 750 can be implemented as two or more than two integrated circuits. A driving module that includes at least the timing controller 750 and the data driver 720 can be referred to as a timing controller embedded data driver (TED).

[0122] The power supply 740 may supply the first power supply voltage ELVDD and the second power supply voltage ELVSS to the display panel 710 based on the control signal CS3. For example, the first power supply voltage ELVDD may be a high power supply voltage, and the second power supply voltage ELVSS may be a low power supply voltage.

[0123] In some exemplary embodiments, at least some of the components included in the display driver integrated circuit may be disposed (e.g., directly mounted) on the display panel 710 or may be connected to a display panel 710 of a tape carrier package (TCP) type. Alternatively, at least some of the components included in the display driver integrated circuit may be integrated on the display panel 710. In some exemplary embodiments, the components included in the display driver integrated circuit may be implemented separately by individual circuits / modules / chips. In other exemplary embodiments, based on functions, some of the components included in the display driver integrated circuit may be combined into one circuit / modules / chip or may be further separated into multiple circuits / modules / chips.

[0124] FIG. 13 is a circuit diagram showing an example of pixels included in a display panel included in the display device of FIG. 12.

[0125] Referring to FIG. 13, each pixel PX may include a switching transistor TS, a storage capacitor CST, a driving transistor TD, and an organic light emitting diode EL.

[0126] The switching transistor TS may have a first electrode connected to the data line Di, a second electrode connected to the storage capacitor CST, and a gate electrode connected to the scan line Sj. The switching transistor TS may transfer the data voltage VDAT received from the data driver 720 to the storage capacitor CST in response to a scan signal SSC received from the scan driver 730. The scan signal SSC may be one of the multiple scan signals SC of FIGS. 10 and 11.

[0127] The storage capacitor CST may have a first electrode connected to the first power supply voltage ELVDD and a second electrode connected to the gate electrode of the driving transistor TD. The storage capacitor CST may store the data voltage VDAT transferred through the switching transistor TS. The data voltage VDAT may be one of the multiple data voltages VD of FIGS. 10 and 11.

[0128] The driving transistor TD may have a first electrode connected to the first power supply voltage ELVDD, a second electrode connected to the organic light emitting diode EL, and a gate electrode connected to the storage capacitor CST. The driving transistor TD may be turned on or off depending on the data voltage VDAT stored in the storage capacitor CST.

[0129] The organic light emitting diode EL may have an anode electrode connected to the driving transistor TD and a cathode electrode connected to the second power supply voltage ELVSS. When the driving transistor TD is turned on, the organic light emitting diode EL may emit light based on the current flowing from the first power supply voltage ELVDD to the second power supply voltage ELVSS. The brightness of the pixel PX may increase as the current flowing through the organic light emitting diode EL increases.

[0130] Although FIG. 13 shows an organic light emitting diode pixel as an example of each pixel PX that may be included in the display panel 710, it should be understood that the example embodiments are not limited to organic light emitting diode pixels and the example embodiments may be applied to any pixels of various types and configurations.

[0131] FIG. 14 is a flowchart showing a method of operating an application processor according to an example embodiment.

[0132] Referring to FIGS. 1, 2, and 14, in the method of operating an application processor according to an example embodiment, the display controller 120 receives an event signal TE associated with a frame update of the display device 300 (step S100) and adjusts the frame rate of the display device 300 based on the event signal TE (step S200). For example, the event signal TE may be generated and provided outside (e.g., the display device 300) or inside the application processor 100. For example, steps S100 and S200 may be performed as described with reference to FIGS. 3 and 5.

[0133] The display controller 120 records timing information TINF associated with a frame update of the display device 300 based on the event signal TE (step S300), and provides the timing information TINF to the main processor 110 (step S400). For example, step S300 may be performed as described with reference to FIGS. 4 and 5, and step S300 will be described with reference to FIG. 15.

[0134] FIG. 15 is a flowchart showing an example of recording timing information in FIG. 14.

[0135] Referring to FIGS. 4, 5, 14, and 15, when recording timing information TINF (step S300), the frame rate control logic 126 can allocate timer TMR1, timer TMR2, and timer TMR3 to different sub-intervals (step S310), can use timer TMR1, timer TMR2, and timer TMR3 to perform time measurement (step S320), can read and / or obtain the timing information TINF recorded in timer TMR1, timer TMR2, and timer TMR3 (step S330), can output the timing information TINF to the main processor 110 (step S340), and can reset timer TMR1, timer TMR2, and timer TMR3 (step S350).

[0136] FIG. 16 is a flowchart showing a method of operating an application processor according to an exemplary embodiment. Descriptions repeated from FIG. 14 will be omitted.

[0137] Referring to FIGS. 6 and 16, in the method of operating an application processor according to an exemplary embodiment, steps S100, S200, S300, and S400 may be substantially the same as steps S100, S200, S300, and S400 in FIG. 14, respectively.

[0138] The main processor 110 can perform at least one of performance control and power control based on the timing information TINF (step S500). For example, step S500 can be performed as described with reference to FIGS. 7 to 9, and step S500 will be described with reference to FIGS. 17 and 18.

[0139] FIGS. 17 and 18 are flowcharts showing examples of performing at least one of the performance control and power control in FIG. 16.

[0140] Referring to FIGS. 6, 7, 8, 16, and 17, when performing at least one of performance control and power control (step S500), when the rendering rate of the graphics processor 140 is slower than the frame rate of the display device 300 (step S510: Yes), the main processor 110 can perform performance control to increase the rendering rate of the graphics processor 140 (step S520). When the rendering rate of the graphics processor 140 is faster than the frame rate of the display device 300 (step S510: No), the main processor 110 can perform power control to reduce the power consumption of the application processor 102 and / or reduce the rendering rate of the graphics processor 140 (step S530).

[0141] Referring to FIGS. 6, 7, 9, 16, and 18, when performing at least one of performance control and power control (step S500), steps S510 and S520 may be substantially the same as steps S510 and S520 in FIG. 17, respectively. When the rendering rate of the graphics processor 140 is faster than the frame rate of the display device 300 (step S510: No), the main processor 110 may maintain the rendering rate of the graphics processor 140 (step S540).

[0142] As will be understood by those of ordinary skill in the art, the present disclosure may be embodied as a system, method, computer program product, and / or a computer program product embodied in one or more computer-readable media having computer-readable program code embodied thereon. The computer-readable program code may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device. The computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium may be any tangible medium that can contain or store a program for use in or in connection with an instruction execution system, apparatus, or device. For example, the computer-readable medium may be a non-transitory computer-readable medium.

[0143] FIG. 19 is a block diagram showing an electronic system including a display system according to an example embodiment.

[0144] Referring to FIG. 19, the electronic system 1000 may be implemented as a data processing device that uses or supports a Mobile Industry Processor Interface (MIPI). The electronic system 1000 may include an application processor 1110, an image sensor 1140, a display device 1150, etc. The electronic system 1000 may further include a radio frequency (RF) chip 1160, a global positioning system (GPS) 1120, a memory 1170, a microphone (MIC) 1180, a dynamic random access memory (DRAM) 1185, and a speaker 1190. Additionally, the electronic system 1000 may use ultra-wideband (UWB) 1210, wireless local area network (WLAN) 1220, worldwide interoperability for microwave access (WIMAX) 1230, etc. to perform communication.

[0145] The application processor 1110 may be a controller or processor that controls the operations of the image sensor 1140 and the display device 1150.

[0146] The application processor 1110 may include: a display serial interface (DSI) host 1111 that performs serial communication with the DSI device 1151 of the display device 1150; a camera serial interface (CSI) host 1112 that performs serial communication with the CSI device 1141 of the image sensor 1140; a physical layer (PHY) 1113 that performs data communication with the PHY 1161 of the RF chip 1160 based on MIPI DigRF; and a DigRF master device 1114 that controls the data communication of the physical layer 1161. The DigRF slave device 1162 of the RF chip 1160 can be controlled via the DigRF master control device 1114.

[0147] In some example embodiments, the DSI host 1111 may include a serializer (SER), and the DSI device 1151 may include a deserializer (DES). In some example embodiments, the CSI host 1112 may include a deserializer (DES), and the CSI device 1141 may include a serializer (SER).

[0148] The application processor 1110 may be an application processor according to an example embodiment and may operate based on a method of operating an application processor according to an example embodiment. The application processor 1110 and the DSI device 1151 may form a display system according to an example embodiment, and the DSI device 1151 may be a display driver integrated circuit included in a display system according to an example embodiment.

[0149] The present disclosure can be applied to various electronic devices and systems including display devices and display systems. For example, the present disclosure can be applied to systems such as: personal computers (PCs), server computers, data centers, workstations, mobile phones, smartphones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, camcorders, video players, navigation devices, wearable devices, internet of thing (IoT) devices, internet of everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, and the like.

[0150] Since it is traditional in the art, embodiments can be described and illustrated in terms of blocks that perform the described functions. These blocks, which may be referred to herein as units or modules or the like, are implemented physically by: analog circuits and / or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits, and the like, and may be driven by firmware and / or software as appropriate. The circuits can be embodied, for example, in one or more semiconductor wafers or on a substrate support such as a printed circuit board and the like. The circuits constituting the blocks can be implemented by dedicated hardware or by a processor (e.g., one or more programmed microprocessors and associated circuitry) or by a combination of dedicated hardware to perform some of the functions of the block and by the processor to perform other functions of the block. Without departing from the scope of the present disclosure, each block of an embodiment can be physically separated into two or more than two interacting and discrete blocks. Similarly, without departing from the scope of the present disclosure, the blocks of an embodiment can be combined into more complex blocks. Aspects of an embodiment can be realized by instructions stored in a non-transitory storage medium and executed by a processor.

[0151] The foregoing describes example embodiments and is not to be construed as limiting thereof. Although some example embodiments have been described, those of ordinary skill in the art will readily appreciate that many modifications are possible without materially departing from the novel teachings and advantages of the example embodiments. Accordingly, all such modifications are intended to be included within the scope of the example embodiments as defined in the claims. Therefore, it should be understood that the foregoing describes various example embodiments and is not to be construed as limited to the specific example embodiments disclosed, and modifications to the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the appended claims.

[0152] 100, 102, 1110: Application processor 110: Main processor 120: Display controller 122: Trigger logic control 124: Display timer logic 124a, 124b, 124c, TMR1, TMR2, TMR3: Timer 126: Frame rate control logic 128: Image processing logic 130, 320: Display interface 132: First pin 140: Graphics processor 150: Power management unit and clock management unit 200, 202, 204: Display system 300, 700, 1150: Display device 310, 312, 314: Display driver integrated circuit 322: Second pin 330, 334, 760: Frame buffer 340, 750: Timing controller 350: Column / row driver 360, 710: Display panel 720: Data driver 730: Scan driver 740: Power supply 1000: Electronic system 1111: Display serial interface host 1112: Camera serial interface host 1113, 1161: Physical layer 1114: DigRF master device 1120: Global Positioning System 1140: Image Sensor 1141: CSI Device 1151: DSI Device 1160: Radio Frequency Chip 1162: DigRF Slave Device 1170: Memory 1180: Microphone 1185: Dynamic Random Access Memory 1190: Speaker 1210: Ultra Wideband 1220: Wireless Local Area Network 1230: Worldwide Interoperability for Microwave Access CS1: First Control Signal CS2: Second Control Signal CS3, ICONT: Control Signal CST: Storage Capacitor D1, D2, Di……DM: Data Line DCONT: Display Control Signal DES: Deserializer DS: Data Signal DUR11, DUR_FR1: First Operation Phase DUR12, DUR_FR2: Second Operation Phase DUR13, DUR_FR3: Third Operation Phase EL: Organic Light Emitting Diode ELVDD: First Power Supply Voltage ELVSS: Second Power Supply Voltage FCS: Frame Rate Control Signal FDAT: Frame Data FIMG, FIMG1, FIMG2, FIMG3, FIMG4, FIMG5, FIMG6: Frame Image GCLK: Graphics Driving Clock Signal IDAT: Image Data PCONT: Performance / Power Control Signal PX: Pixel RIMG, RIMG1, RIMG2, RIMG3, RIMG4, RIMG5, RIMG6: Rendered Image RINF: Rendered Information RDAT: Rendered Data S1, S2, Sj……SN: Scanning lines S100, S200, S300, S310, S320, S330, S340, S350, S400, S500, S510, S520, S530, S540: Steps SC, SSC: Scanning signals SCLK: System driving clock signal SER: Serializer t1, t2, t3, t4, t5, t6, t7: Time points T1, TSC: First time interval T2, TPT: Second time interval T3, TID: Third time interval TC11: First cycle TC12: Second cycle TC13: Third cycle TD: Driving transistor TE: Event signal TF11, TF12, TR11, TR12, TR13: Time intervals TINF: Timing information TS: Switching transistor TTA: Fourth time interval VD, VDAT: Data voltage

Claims

1. An application processor for variable frame rate, comprising: Main processor; The display controller, controlled by the main processor, includes: trigger control logic; display timer logic, comprising a plurality of timers; and frame rate control logic configured to control the start and end timing of the plurality of timers; wherein the display controller is configured to: control a display device located outside the application processor and operating based on a variable frame rate scheme; receive an event signal associated with a frame update of the display device in the trigger control logic; adjust the frame rate of the display device based on the event signal; record timing information associated with the frame update of the display device based on the event signal; provide the timing information to the main processor; divide a frame interval in which the display device displays a frame image during this period into a plurality of sub-intervals; and configure the frame rate control logic to assign each of the plurality of timers to at least one of the plurality of sub-intervals, such that the plurality of timers measure the length of different sub-intervals.

2. The application processor as described in claim 1, wherein: The first timer of the plurality of timers is assigned to measure the length of the first sub-interval among the plurality of sub-intervals. The time measurement using the first timer starts at the beginning time of the first sub-interval and ends at the end time of the first sub-interval.

3. The application processor as claimed in claim 1, wherein the main processor is configured to perform at least one of performance control and power control based on the timing information.

4. The application processor as described in claim 3, further comprising: A graphics processor configured to display a frame image on the display device, wherein the main processor is configured to perform at least one of the performance control and the power control by comparing the timing information with the display information of the graphics processor.

5. The application processor as claimed in claim 4, wherein in response to a display rate of the graphics processor being slower than the frame rate of the display device, the main processor is configured to perform the performance control to increase the display rate of the graphics processor.

6. The application processor as claimed in claim 5, wherein the display rate of the graphics processor is increased by increasing the frequency of the driving clock signal of the graphics processor.

7. The application processor as claimed in claim 4, wherein in response to a display rate of the graphics processor being faster than the frame rate of the display device, the main processor is configured to perform the power control to reduce the power consumption of the application processor.

8. The application processor as claimed in claim 7, wherein the power consumption of the application processor is reduced by decreasing the frequency of the drive clock signal of the graphics processor or the frequency of the system clock signal of the application processor.

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