Three-dimensional semiconductor device

Abstract

A three-dimensional semiconductor device is provided. The semiconductor device includes: a first active region located on a substrate and including a plurality of lower channel patterns and a plurality of lower source / drain patterns alternately arranged along a first direction; a second active region located on the first active region and including a plurality of upper channel patterns and a plurality of upper source / drain patterns alternately arranged along the first direction; a first gate electrode located on a first lower channel pattern in the lower channel patterns and a first upper channel pattern in the upper channel patterns; and a second gate electrode located on a second lower channel pattern in the lower channel patterns and a second upper channel pattern in the upper channel patterns. The second gate electrode may include a lower gate electrode and an upper gate electrode, with an isolation pattern sandwiched between the lower gate electrode and the upper gate electrode.

Description

Technical Field

[0001] [Cross - Reference to Related Applications]

[0002] This U.S. non - provisional application claims the priority of Korean Patent Application No. 10 - 2021 - 0145770, filed on Oct. 28, 2021, with the Korean Intellectual Property Office, under 35 U.S.C. § 119, and the entire disclosure of the Korean patent application is incorporated herein by reference.

[0003] The inventive concept relates to a three - dimensional semiconductor device and a method of manufacturing the same, and more particularly, to a three - dimensional semiconductor device including a field - effect transistor and a method of manufacturing the same.

Background Art

[0004] Semiconductor devices include integrated circuits containing metal oxide semiconductor field effect transistors (MOSFETs). As the design rules of semiconductor devices decrease with the growing demand for smaller pattern sizes and higher performance of semiconductor devices, the size of MOSFETs has also been scaled down drastically. The scaling down of MOSFETs may deteriorate the operating characteristics of semiconductor devices. Accordingly, various studies have been conducted to develop methods for manufacturing semiconductor devices having excellent performance while overcoming the limitations caused by the high integration of semiconductor devices.

Summary of the Invention

[0005] Embodiments of the inventive concept provide a three - dimensional semiconductor memory device having an increased integration degree.

[0006] Embodiments of the inventive concept provide a method of manufacturing a semiconductor device having an increased integration degree.

[0007] According to an embodiment of the inventive concept, a three-dimensional semiconductor device may include: a first active region located on a substrate, the first active region including a plurality of lower channel patterns and a plurality of lower source / drain patterns alternately arranged in a first direction; a second active region located on the first active region, the second active region including a plurality of upper channel patterns and a plurality of upper source / drain patterns alternately arranged in the first direction; a first gate electrode located on a first lower channel pattern among the lower channel patterns and on a first upper channel pattern among the upper channel patterns; and a second gate electrode located on a second lower channel pattern among the lower channel patterns and on a second upper channel pattern among the upper channel patterns. The first gate electrode may include: a first lower gate electrode located on the first lower channel pattern; and a first upper gate electrode located on the first upper channel pattern. The first lower gate electrode and the first upper gate electrode may be connected to each other. The second gate electrode may include: a second lower gate electrode located on the second lower channel pattern; a second upper gate electrode located on the second upper channel pattern; and an isolation pattern located between the second lower gate electrode and the second upper gate electrode. The second lower gate electrode and the second upper gate electrode are separated from each other by the isolation pattern.

[0008] According to an embodiment of the inventive concept, a three-dimensional semiconductor device may include: a first active region and a second active region, the first active region located on a substrate, the second active region located on the first active region; a first gate electrode and a second gate electrode located on the first active region and the second active region, wherein the first gate electrode includes a first lower gate electrode located on the first active region, a first upper gate electrode located on the second active region, and a first isolation pattern located between the first lower gate electrode and the first upper gate electrode, and wherein the second gate electrode includes a second lower gate electrode located on the first active region, a second upper gate electrode located on the second active region, and a second isolation pattern located between the second lower gate electrode and the second upper gate electrode; a first upper gate contact coupled to the first upper gate electrode; a first lower gate contact coupled to the first lower gate electrode; a second upper gate contact coupled to the second upper gate electrode; a second lower gate contact coupled to the second lower gate electrode; a first wiring trace electrically connected to the first upper gate contact and the second lower gate contact; and a second wiring trace electrically connected to the first lower gate contact and the second upper gate contact.

[0009] According to an embodiment of the inventive concept, a three-dimensional semiconductor device may include: a first active region located on a substrate, the first active region including a lower channel pattern and a lower source / drain pattern connected to the lower channel pattern; a second active region located on the first active region, the second active region including an upper channel pattern and an upper source / drain pattern connected to the upper channel pattern; a dummy channel pattern located between the lower channel pattern and the upper channel pattern; and a gate electrode located on the lower channel pattern, the dummy channel pattern, and the upper channel pattern. The gate electrode may include: a lower gate electrode located on the lower channel pattern; an upper gate electrode located on the upper channel pattern; and a spacer pattern located between the lower gate electrode and the upper gate electrode.

[0010] According to an embodiment of the inventive concept, a method of manufacturing a three-dimensional device may include: forming a stack layer on a substrate, a first active layer, a first sacrificial layer, a second sacrificial layer, a third sacrificial layer, and a second active layer being sequentially stacked in the stack layer; patterning the stack layer to form a stack pattern extending in a first direction, the stack pattern including a lower stack pattern and an upper stack pattern, the lower stack pattern including the first active layer and the first sacrificial layer, and the upper stack pattern including the third sacrificial layer and the second active layer; forming a sacrificial pattern extending in a second direction on the stack pattern; forming an interlayer dielectric layer covering the stack pattern and the sacrificial pattern; selectively removing the sacrificial pattern to form an external region exposing the stack pattern; using the external region to replace the second sacrificial layer of the stack pattern with a dummy channel pattern; removing the first sacrificial layer and the third sacrificial layer of the stack pattern via the external region to respectively form a first internal region and a second internal region; forming a lower gate electrode filling the first internal region; forming a spacer pattern on the lower gate electrode; and forming an upper gate electrode filling the second internal region on the spacer pattern.

Embodiments

[0012] FIG. 1 is a conceptual diagram showing a logic unit of a semiconductor device according to a comparative example of the inventive concept. FIG. 1 shows a logic unit of a two-dimensional device according to a comparative example of the inventive concept.

[0013] Referring to FIG. 1, a single-height cell SHC' can be provided. For example, a first power supply line POR1 and a second power supply line POR2 can be provided on the substrate 100. One of the first power supply line POR1 and the second power supply line POR2 can be provided with a drain voltage (VDD) or a power supply voltage. The other of the first power supply line POR1 and the second power supply line POR2 can be provided with a source voltage (VSS) or a ground voltage. For example, a source voltage (VSS) can be applied to the first power supply line POR1, and a drain voltage (VDD) can be applied to the second power supply line POR2.

[0014] The single-height cell SHC' can be defined between the first power supply line POR1 and the second power supply line POR2. The single-height cell SHC' can include a first active region AR1 and a second active region AR2. One of the first active region AR1 and the second active region AR2 can be a p-channel metal oxide semiconductor field effect transistor (PMOSFET) region, and the other of the first active region AR1 and the second active region AR2 can be an n-channel metal oxide semiconductor field effect transistor (NMOSFET) region. For example, the first active region AR1 can be an NMOSFET region, and the second active region AR2 can be a PMOSFET region. For example, the single-height cell SHC' can have a complementary metal-oxide semiconductor (CMOS) structure disposed between the first power supply line POR1 and the second power supply line POR2 to use complementary and symmetric pairs of PMOSFETs and NMOSFETs for logic functions.

[0015] The semiconductor device according to the comparative example can be a two-dimensional device in which transistors in a front-end-of-line (FEOL) layer are arranged in a two-dimensional manner. For example, the NMOSFET on the first active region AR1 can be spaced apart from the PMOSFET on the second active region AR2 in a first direction D1.

[0016] The first active region AR1 and the second active region AR2 may each have a first width W1 in a first direction D1. According to the comparative example, the first height HE1 may be defined to represent the length of the single-height cell SHC' in the first direction D1. The first height HE1 may be substantially the same as the distance (e.g., pitch) between the first power supply line POR1 and the second power supply line POR2.

[0017] The single-height cell SHC' may constitute a logic cell. In this description, a logic cell may mean a logic device that performs a specific function, such as (by way of example) an AND, OR, exclusive OR (XOR), exclusive NOR (XNOR), or inverter. For example, a logic cell may include transistors for constituting a logic device and may also include wiring traces connecting the transistors to each other.

[0018] Since the two-dimensional device is included in the single-height cell SHC' according to the comparative example, the first active region AR1 and the second active region AR2 may be arranged to be spaced apart from each other in the first direction D1 without overlapping each other. Therefore, it may be necessary to define the first height HE1 of the single-height cell SHC' to include the entirety of the first active region AR1 and the second active region AR2 that are spaced apart from each other in the first direction D1. In this way, the first height HE1 of the single-height cell SHC' according to the comparative example may need to become relatively large. Therefore, the single-height cell SHC' according to the comparative example may have a relatively large area.

[0019] FIG. 2 is a conceptual diagram showing a logic cell of a semiconductor device according to an embodiment of the inventive concept. FIG. 2 illustrates a logic cell of a three-dimensional device according to an embodiment of the inventive concept.

[0020] Referring to FIG. 2, a single-height cell SHC including a three-dimensional device such as stacked transistors may be provided. For example, a first power supply line POR1 and a second power supply line POR2 may be provided on a substrate 100. The single-height cell SHC may be defined between the first power supply line POR1 and the second power supply line POR2.

[0021] The single-height cell SHC may include a first active region AR1 and a second active region AR2. One of the first active region AR1 and the second active region AR2 may be a PMOSFET region, and the other of the first active region AR1 and the second active region AR2 may be an NMOSFET region.

[0022] The semiconductor device according to an embodiment of the inventive concept may be a three-dimensional device in which transistors of a front-end-of-line (FEOL) layer are vertically stacked. A first active region AR1 as a bottom tier may be provided on a substrate 100, and a second active region AR2 as a top tier may be provided on the first active region AR1. For example, an NMOSFET of the first active region AR1 may be provided on the substrate 100, and a PMOSFET of the second active region AR2 may be provided on the NMOSFET. The first active region AR1 and the second active region AR2 may be spaced apart from each other in a vertical direction or a third direction D3.

[0023] The first active region AR1 and the second active region AR2 may each have a first width W1 in a first direction D1. According to an embodiment of the inventive concept, a second height HE2 may be defined to represent the length of a single-height cell SHC in the first direction D1. The second height HE2 of the single-height cell SHC may be substantially the same as the distance (e.g., pitch) between a first power supply line POR1 and a second power supply line POR2.

[0024] Since the single-height cell SHC according to an embodiment of the inventive concept includes a three-dimensional device or stacked transistors, the first active region AR1 and the second active region AR2 may overlap each other. Accordingly, the second height HE2 of the single-height cell SHC may have a size sufficient to cover the first width W1. Thus, the second height HE2 of the single-height cell SHC according to an embodiment of the inventive concept may be smaller than the first height HE1 of the single-height cell SHC' discussed above in FIG. 1. For example, the single-height cell SHC according to an embodiment of the inventive concept may have a relatively small area. For a three-dimensional semiconductor device according to an embodiment of the inventive concept, the area of a logic unit may be reduced to improve the integration degree of the device. For example, compared to the single-height cell SHC' of a two-dimensional device according to a comparative example, the single-height cell SHC of a three-dimensional semiconductor device according to an embodiment of the inventive concept may significantly increase the number of transistors in a package because each region may effectively double the number of the total devices.

[0025] FIG. 3 is a logic circuit diagram of a flip-flop of a semiconductor device according to an embodiment of the inventive concept. FIG. 4 shows the logic circuit constituting the flip-flop of FIG. 3.

[0026] Referring to FIGS. 3 and 4, the flip-flop unit FF may include the logic circuit LC of FIG. 4. For example, the flip-flop unit FF may include a first part PA1 to a fourth part PA4. The first part PA1 may be a core circuit that implements a scan function and a flip-flop function. In response to the scan enable signal SE, the first part PA1 may select one of the external input signal D and the scan input signal SI, and based on the selected signal, the first part PA1 may provide an internal signal to the first node N1. The first part PA1 may be referred to as, for example, a multiplexer, a scan multiplexer, or a selector.

[0027] Each of the second part PA2 and the third part PA3 may be a buffer. The second part PA2 may include a master latch, and the third part PA3 may include a slave latch. A second node N2 may be provided between the second part PA2 and the third part PA3. Based on the clock signal CLK, the master latch of the second part PA2 may latch the internal signal from the first node N1. Based on the clock signal CLK, the slave latch of the third part PA3 may latch the output of the master latch and provide an output signal Q. A third node N3 may be connected to the third part PA3. The fourth part PA4 may include a clock circuit connected to the flip-flop and receiving an external clock signal CK.

[0028] Returning to FIGS. 3 and 4, each of the first part PA1, the second part PA2, and the third part PA3 may include a first element E1 and a second element E2. A first input signal SI1 is input to the first element E1, and a second input signal SI2 is input to the second element E2. The first element E1 and the second element E2 may be connected to each other.

[0029] The first element E1 may include a first transistor to a fourth transistor connected in series. The first transistor to the fourth transistor may be sequentially arranged between the VDD terminal and the VSS terminal. The first transistor and the second transistor may be p-channel metal oxide semiconductor (PMOS) transistors, and the third transistor and the fourth transistor may be n-channel metal oxide semiconductor (NMOS) transistors. The first input signal SI1 may be input to the first transistor and the fourth transistor, a first signal A may be input to the second transistor, and a second signal / A may be input to the third transistor. The second signal / A may be an inverted signal of the first signal A.

[0030] The second element E2 may include a first transistor to a fourth transistor connected in series. The first transistor to the fourth transistor may be sequentially disposed between the VDD terminal and the VSS terminal. The first transistor and the second transistor may be PMOS transistors, and the third transistor and the fourth transistor may be NMOS transistors. The second input signal SI2 may be input to the first transistor and the fourth transistor, the second signal / A may be input to the second transistor, and the first signal A may be input to the third transistor.

[0031] Regarding the first PA1, the first signal A may be a scan enable signal SE, and the second signal / A may be a scan enable inverted signal SI. Regarding the second PA2 and the third PA3, the first signal A may be a clock signal CLK, and the second signal / A may be a clock inverted signal / CLK.

[0032] FIG. 5 is a plan view showing a three-dimensional semiconductor device according to an embodiment of the concept of the present invention. FIGS. 6A, 6B, 6C, 6D, and 6E are cross-sectional views taken along lines A-A', B-B', C-C', D-D', and E-E' of FIG. 5, respectively. The three-dimensional device shown in FIGS. 5 and 6A to 6E may represent a detailed example in which the logic circuit LC of FIG. 4 is implemented in the single-height cell SHC of FIG. 2.

[0033] Referring to FIGS. 5 and 6A to 6E, a logic unit including the logic circuit LC of FIG. 4 may be disposed on the substrate 100. The substrate 100 may be a compound semiconductor substrate or a semiconductor substrate including, for example, silicon (Si), germanium (Ge), or silicon-germanium (SiGe). For example, the substrate 100 may be a silicon substrate. As an alternative, the substrate 100 may include, but is not limited to, silicon-on-insulator (SOI), silicon germanium on insulator (SGOI), indium antimonide (InSb), lead telluride (PbTe) compound, indium arsenide (InAs), indium phosphide (InP), gallium arsenide (GaAs), gallium phosphide (GaP), or gallium antimonide (GaSb). In addition, the substrate 100 may include one or more semiconductor layers or structures and may include the active part or the operable part of the semiconductor device.

[0034] The logic unit may include a first active region AR1 and a second active region AR2 stacked in sequence on the substrate 100. One of the first active region AR1 and the second active region AR2 may be a PMOSFET region, and the other of the first active region AR1 and the second active region AR2 may be an NMOSFET region. The first active region AR1 may be disposed on the bottom layer of the front-end-of-line (FEOL) layer, and the second active region AR2 may be disposed on the top layer of the front-end-of-line (FEOL) layer. The NMOS field-effect transistors and PMOS field-effect transistors of the first active region AR1 and the second active region AR2 may be stacked vertically to form three-dimensional stacked transistors. In an embodiment of the inventive concept, the first active region AR1 may be an NMOSFET region, and the second active region AR2 may be a PMOSFET region.

[0035] The NMOS field-effect transistors and PMOS field-effect transistors of the first active region AR1 and the second active region AR2 may include a first transistor to a fourth transistor that constitute the logic circuit LC of FIG. 4. When observed in a plan view, the stacked first active region AR1 and second active region AR2 may be positioned between a first power line POR1 and a second power line POR2. For example, the first power line POR1, the stacked first active region AR1 and second active region AR2, and the second power line POR2 may be arranged in sequence in a first direction D1.

[0036] The active pattern AP may be defined by a trench TR formed on an upper portion of the substrate 100. The active pattern AP may be a vertically protruding portion of the substrate 100. When observed in a plan view, the active pattern AP may have a bar shape extending in a second direction D2. The first active region AR1 and the second active region AR2 may be stacked in sequence on the active pattern AP.

[0037] The trench TR may be filled with a device isolation layer ST. For example, the device isolation layer ST may be formed on the substrate 100 to define the active pattern AP. The device isolation layer ST may include a silicon oxide (SiO2) layer, and the top surface of the device isolation layer ST may be at the same horizontal height as or at a horizontal height lower than the horizontal height of the top surface of the active pattern AP. The device isolation layer ST may not cover any of the lower channel pattern CH1 and the upper channel pattern CH2 to be described below.

[0038] On the active pattern AP, a first active region AR1 including a lower channel pattern CH1 and a lower source / drain pattern SD1 may be provided. Each of the lower channel patterns CH1 may be sandwiched between a pair of lower source / drain patterns SD1. The lower channel pattern CH1 may connect a pair of lower source / drain patterns SD1 to each other. Referring to FIG. 6A, the first active region AR1 may include a plurality of lower channel patterns CH1 and a plurality of lower source / drain patterns SD1 alternately arranged along the second direction D2.

[0039] The lower channel pattern CH1 may include a first semiconductor pattern SP1 and a second semiconductor pattern SP2 stacked in sequence. The first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be spaced apart from each other in the vertical direction (or the third direction D3). Each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may include, for example, silicon (Si), germanium (Ge), or silicon-germanium (SiGe). In an embodiment of the inventive concept, each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may include crystalline silicon (c-Si).

[0040] The lower source / drain pattern SD1 may be disposed on the top surface of the active pattern AP. Each of the lower source / drain patterns SD1 may be an epitaxial pattern formed by a selective epitaxial growth (SEG) process. For example, the top surface of the lower source / drain pattern SD1 may be higher than the top surface of the second semiconductor pattern SP2 included in the lower channel pattern CH1. For example, each pair of lower source / drain patterns SD1 may be connected to each other by the stacked first semiconductor pattern SP1 and second semiconductor pattern SP2 of the lower channel pattern CH1.

[0041] The lower source / drain pattern SD1 may be doped with impurities to have a first conductivity type. The first conductivity type may be an n-type or a p-type. In an embodiment of the inventive concept, the first conductivity type may be an n-type. The lower source / drain pattern SD1 may include one or more selected from, for example, silicon (Si) and silicon-germanium (SiGe). The lower source / drain pattern SD1 may include an n-type dopant, such as, for example, phosphorus (P), arsenic (As), antimony (Sb), and / or bismuth (Bi).

[0042] A first interlayer dielectric layer 110 may be disposed on the lower source / drain pattern SD1, and the first interlayer dielectric layer 110 may cover the lower source / drain pattern SD1. A second interlayer dielectric layer 120 and a second active region AR2 may be disposed on the first interlayer dielectric layer 110.

[0043] The second active region AR2 may include an upper channel pattern CH2 and an upper source / drain pattern SD2. The upper channel pattern CH2 may overlap perpendicularly with a corresponding lower channel pattern CH1. The upper source / drain pattern SD2 may overlap perpendicularly with a corresponding lower source / drain pattern SD1. Each of the upper channel patterns CH2 may be sandwiched between a pair of upper source / drain patterns SD2. The upper channel patterns CH2 may connect a pair of upper source / drain patterns SD2 to each other. For example, the second active region AR2 may include a plurality of upper channel patterns CH2 and a plurality of upper source / drain patterns SD2 that are alternately arranged along the second direction D2.

[0044] The upper channel pattern CH2 may include a third semiconductor pattern SP3 and a fourth semiconductor pattern SP4 that are stacked in sequence. The third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 may be spaced apart from each other in the third direction D3. The third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 included in the upper channel pattern CH2 may have the same material as the first semiconductor pattern SP1 and the second semiconductor pattern SP2 included in the lower channel pattern CH1.

[0045] At least one dummy channel pattern DSP may be sandwiched between the lower channel pattern CH1 and the upper channel pattern CH2 overlying the lower channel pattern CH1. The dummy channel pattern DSP may be spaced apart from the lower source / drain pattern SD1. In addition, the dummy channel pattern DSP may be spaced apart from the upper source / drain pattern SD2. For example, the dummy channel pattern DSP may not be connected to any of the source / drain patterns. The dummy channel pattern DSP may include a semiconductor material (such as (for example) silicon (Si), germanium (Ge), or silicon-germanium (SiGe)) or a dielectric material (such as (for example) silicon oxide (SiO2) or silicon nitride (Si3N4)).

[0046] The upper source / drain pattern SD2 may be disposed on the top surface of the first interlayer dielectric layer 110. Each of the upper source / drain patterns SD2 may be an epitaxial pattern formed by a selective epitaxial growth (SEG) process. For example, the top surface of the upper source / drain pattern SD2 may be higher than the top surface of the fourth semiconductor pattern SP4 included in the upper channel pattern CH2. For example, each pair of upper source / drain patterns SD2 may be connected to each other by the stacked third semiconductor pattern SP3 and fourth semiconductor pattern SP4 of the upper channel pattern CH2.

[0047] The upper source / drain pattern SD2 may be doped with impurities to have a second conductivity type. The second conductivity type may be different from the first conductivity type of the lower source / drain pattern SD1. The second conductivity type may be a p-type. The upper source / drain pattern SD2 may include one or more selected from, for example, silicon (Si) and silicon-germanium (SiGe). The upper source / drain pattern SD2 may include a p-type dopant such as, for example, boron (B), aluminum (Al), gallium (Ga), and / or indium (In).

[0048] The second interlayer dielectric layer 120 may cover the upper source / drain pattern SD2. The top surface of the second interlayer dielectric layer 120 may be coplanar with the top surface of the gate cap pattern GP which will be described below.

[0049] A gate electrode GE may be disposed on the stacked lower channel pattern CH1 and upper channel pattern CH2. When observed in a plan view, the gate electrode GE may have a bar shape extending in a first direction D1. A plurality of gate electrodes GE may be disposed on the substrate 100, and the plurality of gate electrodes GE may be arranged at a first pitch along a second direction D2. Each of the gate electrodes GE may vertically overlap the stacked lower channel pattern CH1 and upper channel pattern CH2.

[0050] The plurality of gate electrodes GE located on the logic circuit LC according to an embodiment of the inventive concept may include a first gate electrode GE1 and a second gate electrode GE2. The second gate electrode GE2 may be disposed between the first gate electrodes GE1. Each of the first gate electrodes GE1 may be a common gate electrode in which a lower gate electrode LGE and an upper gate electrode UGE are connected to each other. Each of the second gate electrodes GE2 may be a split gate electrode in which a lower gate electrode LGE and an upper gate electrode UGE are separated from each other.

[0051] The first gate electrode GE1 will be further described in detail with reference to FIGS. 6A, 6B, and 6D. The first gate electrode GE1 can extend in the vertical direction (or the third direction D3) from the top surface of the device isolation layer ST (or the active pattern AP) to the gate cap pattern GP to be described below. The first gate electrode GE1 can extend in the third direction D3 from the lower channel pattern CH1 of the first active region AR1 to the upper channel pattern CH2 of the second active region AR2. The first gate electrode GE1 can extend in the third direction D3 from the first semiconductor pattern SP1 to the fourth semiconductor pattern SP4. In an embodiment of the inventive concept, the first gate electrode GE1 can be disposed on the first lower channel pattern in the lower channel pattern CH1 and the first upper channel pattern in the upper channel pattern CH2, and the second gate electrode GE2 can be disposed on the second lower channel pattern in the lower channel pattern CH1 and the second upper channel pattern in the upper channel pattern CH2.

[0052] The first gate electrode GE1 can be disposed on the top surface, bottom surface, and opposite sidewalls of each of the first semiconductor pattern SP1 to the fourth semiconductor pattern SP4. In this sense, the transistor according to an embodiment of the inventive concept can be a three-dimensional field effect transistor in which the first gate electrode GE1 surrounds the channel three-dimensionally (e.g., a multi-bridge channel field effect transistor (MBCFET) or a gate all around field effect transistor (GAAFET)).

[0053] The first gate electrode GE1 can include a lower gate electrode LGE disposed on the bottom layer of the front-end-of-line (FEOL) layer or on the first active region AR1, and can also include an upper gate electrode UGE disposed on the top layer of the front-end-of-line (FEOL) layer or on the second active region AR2. The lower gate electrode LGE and the upper gate electrode UGE can overlap each other vertically. The lower gate electrode LGE and the upper gate electrode UGE of the first gate electrode GE1 can be connected to each other. For example, the first gate electrode GE1 can be a common gate electrode in which the lower gate electrode LGE of the first active region AR1 is connected to the upper gate electrode UGE of the second active region AR2.

[0054] The lower gate electrode LGE of the first gate electrode GE1 can include a first portion PO1 sandwiched between the active pattern AP and the first semiconductor pattern SP1, a second portion PO2 sandwiched between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and a third portion PO3 sandwiched between the second semiconductor pattern SP2 and the dummy channel pattern DSP.

[0055] The upper gate electrode UGE of the first gate electrode GE1 may include a fourth portion PO4 sandwiched between the dummy channel pattern DSP and the third semiconductor pattern SP3, a fifth portion PO5 sandwiched between the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4, and a sixth portion PO6 located on the fourth semiconductor pattern SP4.

[0056] A pair of gate spacers GS may be provided on opposite sidewalls of the first gate electrode GE1. Referring to FIG. 6A, a pair of gate spacers GS may be provided on opposite sidewalls of the sixth portion PO6. The gate spacers GS may extend along the first gate electrode GE1 in the first direction D1, and the top surface of the gate spacers GS may be higher than the top surface of the first gate electrode GE1. The top surface of the gate spacers GS may be coplanar with the top surface of the second interlayer dielectric layer 120. The gate spacers GS may include one or more selected from, for example, silicon carbonitride (SiCN), silicon oxynitride (SiCON), and silicon nitride (Si3N4). As an alternative, each of the gate spacers GS may include multiple layers formed from two or more selected from, for example, a silicon carbonitride (SiCN) layer, a silicon oxynitride (SiCON) layer, and a silicon nitride (Si3N4) layer. A pair of liner layers LIN may be provided on opposite sidewalls of each of the third portion PO3 and the fourth portion PO4 of the first gate electrode GE1.

[0057] A gate cap pattern GP may be provided on the top surface of the first gate electrode GE1. The gate cap pattern GP may extend along the first gate electrode GE1 in the first direction D1. For example, the gate cap pattern GP may include one or more selected from, for example, silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxynitride (SiCON), and silicon nitride (Si3N4).

[0058] A gate dielectric layer UGI and LGI may be sandwiched between the first gate electrode GE1 and the first semiconductor pattern SP1 to the fourth semiconductor pattern SP4. For example, the lower gate dielectric layer LGI may be sandwiched between the lower gate electrode LGE and each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2. The upper gate dielectric layer UGI may be sandwiched between the upper gate electrode UGE and each of the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4.

[0059] Each of the lower gate dielectric layer LGI and the upper gate dielectric layer UGI may include one or more selected from, for example, a silicon oxide (SiO2) layer, a silicon oxynitride (SiON) layer, and a high-k dielectric layer. In an embodiment of the inventive concept, each of the lower gate dielectric layer LGI and the upper gate dielectric layer UGI may include a silicon oxide (SiO2) layer directly covering the corresponding one of the first semiconductor pattern SP1 to the fourth semiconductor pattern SP4, and may also include a high-k dielectric layer located on the silicon oxide (SiO2) layer. For example, each of the lower gate dielectric layer LGI and the upper gate dielectric layer UGI may include multiple layers.

[0060] The high-k dielectric layer may include a high-k dielectric material having a dielectric constant greater than that of the silicon oxide (SiO2) layer. For example, the high-k dielectric material may include one or more selected from, for example, hafnium oxide (HfO2), hafnium silicate (HfSiO4), hafnium zirconate (HfZrO4), hafnium tantalum oxide (Hf2Ta2O9), hafnium aluminate (HfAlO3), lanthanum oxide (La2O3), lanthanum aluminate (LaAlO3), zirconium oxide (ZrO2), zirconium silicate (ZrSiO4), tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanate (BaSrTi2O6), barium titanate (BaTiO3), strontium titanate (SrTiO3), lithium oxide (Li2O), aluminum oxide (Al2O3), lead scandium tantalate (Pb(Sc,Ta)O3), and lead zinc niobate [Pb(Zn1 / 3Nb2 / 3)O3].

[0061] In an embodiment of the inventive concept, the lower gate dielectric layer LGI may include a first dipole element. The first dipole element may include, for example, lanthanum (La), aluminum (Al), or a combination thereof. For example, lanthanum (La), aluminum (Al), or a combination thereof may be contained as an impurity in the lower gate dielectric layer LGI. The lower gate dielectric layer LGI may include a dipole interface formed by the first dipole element between the high-k dielectric layer and the silicon oxide (SiO2) layer.

[0062] When the lower gate dielectric layer LGI contains lanthanum (La), the work function of the lower gate electrode LGE may decrease. Therefore, the threshold voltage of the transistor (e.g., NMOS transistor) located on the first active region AR1 may decrease. As an alternative, when the lower gate dielectric layer LGI contains aluminum (Al), the effective work function of the lower gate electrode LGE may increase. Therefore, the threshold voltage of the transistor (e.g., NMOS transistor) located on the first active region AR1 may increase. For example, the threshold voltage of the NMOS transistor can be adjusted by incorporating a predetermined amount of a first dipole element (e.g., lanthanum (La), aluminum (Al), or a combination thereof) into the lower gate dielectric layer LGI.

[0063] In an embodiment of the inventive concept, the upper gate dielectric layer UGI may not include a dipole element. For example, the maximum concentration of the dipole element in the upper gate dielectric layer UGI may be less than the maximum concentration of the first dipole element in the lower gate dielectric layer LGI. In an embodiment of the inventive concept, the upper gate dielectric layer UGI may include a second dipole element. The second dipole element may be the same as or different from the first dipole element.

[0064] The lower gate electrode LGE of the first gate electrode GE1 may include a first metal pattern MP1 located on the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and may also include a second metal pattern MP2 located on the first metal pattern MP1. The first metal pattern MP1 may include a first work function metal, and the second metal pattern MP2 may include a second work function metal. The compositions of the first work function metal and the second work function metal can be adjusted to achieve the threshold voltage of the transistor located on the first active region AR1.

[0065] The first work function metal of the first metal pattern MP1 may be a p-type work function metal with a relatively high work function. The first metal pattern MP1 may include a metal nitride layer. The first metal pattern MP1 may contain nitrogen (N) and at least one metal selected from metals such as titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). For example, the first metal pattern MP1 may contain, for example, titanium nitride (TiN), tantalum nitride (TaN), titanium oxynitride (TiON), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tungsten carbon nitride (WCN), or molybdenum nitride (MoN).

[0066] The second work function metal of the second metal pattern MP2 can be an n-type work function metal with a relatively low work function. The second metal pattern MP2 can include metal carbides. The second metal pattern MP2 can include metal carbides doped (or containing) one or more selected from, for example, silicon (Si) and aluminum (Al). In an embodiment of the inventive concept, the second metal pattern MP2 can include, for example, titanium aluminum carbide (TiAlC) doped with aluminum, tantalum aluminum carbide (TaAlC) doped with aluminum, vanadium aluminum carbide (VAlC) doped with aluminum, titanium silicon carbide (TiSiC) doped with silicon, or tantalum silicon carbide (TaSiC) doped with silicon. In an embodiment of the inventive concept, the second metal pattern MP2 can include, for example, titanium aluminum silicon carbide (TiAlSiC) or tantalum aluminum silicon carbide (TaAlSiC) doped with aluminum silicon. In an embodiment of the inventive concept, the second metal pattern MP2 can include, for example, titanium doped with aluminum (TiAl). In an embodiment of the inventive concept, the second metal pattern MP2 can include metal nitrides doped with one or more selected from, for example, silicon and aluminum (such as titanium aluminum nitride (TiAlN) doped with aluminum).

[0067] The work function of the second metal pattern MP2 can be controlled by adjusting the concentration of dopants (or impurities) such as silicon or aluminum. For example, the impurities (such as silicon (Si) or aluminum (Al)) in the second metal pattern MP2 can have a concentration in the range of about 0.1 atomic % to about 25 atomic %. As used herein, the term "about" includes the recited value and means within an acceptable deviation range of a particular value determined by one of ordinary skill in the art, taking into account the measured value being discussed and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the recited value.

[0068] Each of the first portion PO1, the second portion PO2, and the third portion PO3 included in the lower gate electrode LGE can include the second metal pattern MP2 and the first metal pattern MP1 surrounding the second metal pattern MP2. For example, the thickness of the second metal pattern MP2 can be greater than the thickness of the first metal pattern MP1. By adjusting the first work function of the first metal pattern MP1 and the second work function of the second metal pattern MP2 included in the first portion PO1, the second portion PO2, and the third portion PO3 sandwiched between the active pattern AP, the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the dummy channel pattern DSP, a well-distributed operating threshold voltage of the transistor located on the first active region AR1 can be achieved. For example, by appropriately adjusting the work function of the lower gate electrode LGE around the lower channel pattern CH1, a threshold voltage suitable for the transistor located on the first active region AR1 can be achieved.

[0069] The lower gate electrode LGE may further include a sixth metal pattern MP6 (see FIG. 6D) at its remaining portion except for the first portion PO1, the second portion PO2, and the third portion PO3. The resistance of the sixth metal pattern MP6 may be lower than the resistances of the first metal pattern MP1 and the second metal pattern MP2. For example, the sixth metal pattern MP6 may include at least one selected from metals with low resistance (e.g., (for example) tungsten (W), ruthenium (Ru), aluminum (Al), titanium (Ti), and tantalum (Ta)).

[0070] Referring to FIG. 6D, the sixth metal pattern MP6 of the first gate electrode GE1 may have a top surface in contact with the bottom surface of the upper gate electrode UGE. The top surface of the sixth metal pattern MP6 may be at a height between the height of the top surface of the dummy channel pattern DSP and the height of the bottom surface of the dummy channel pattern DSP. The sixth metal pattern MP6 may have a first thickness TK1 in the third direction D3.

[0071] The upper gate electrode UGE of the first gate electrode GE1 may include a third metal pattern MP3 located on the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4. The third metal pattern MP3 may surround the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4. The upper gate electrode UGE may further include a fourth metal pattern MP4 and a fifth metal pattern MP5 located on the third metal pattern MP3.

[0072] The third metal pattern MP3 may include a first work function metal, and the fourth metal pattern MP4 may include a second work function metal. The compositions of the first work function metal and the second work function metal may be adjusted to achieve the threshold voltage of the transistor located on the second active region AR2.

[0073] Similar to the first metal pattern MP1, the first work function metal of the third metal pattern MP3 may be a p-type work function metal with a relatively high work function. The third metal pattern MP3 may include a metal nitride layer. The metal nitride layer of the third metal pattern MP3 may be the same as or different from the metal nitride layer of the first metal pattern MP1.

[0074] Similar to the second metal pattern MP2, the second work function metal of the fourth metal pattern MP4 may be an n-type work function metal with a relatively low work function. The fourth metal pattern MP4 may include a metal carbide doped (or containing) one or more selected from, for example, silicon (Si) and aluminum (Al). The fourth metal pattern MP4 may include a material the same as or different from the material of the second metal pattern MP2.

[0075] The fourth part PO4 and the fifth part PO5 of the upper gate electrode UGE may be formed of the third metal pattern MP3. The sixth part PO6 of the upper gate electrode UGE may include the third metal pattern MP3, the fourth metal pattern MP4, and the fifth metal pattern MP5 stacked in sequence.

[0076] In an embodiment of the inventive concept, the fifth metal pattern MP5 may include a first work function metal. For example, the fifth metal pattern MP5 may include the same metal nitride layer as the metal nitride layer of the third metal pattern MP3. In an embodiment of the inventive concept, the fifth metal pattern MP5 may include a metal with low resistance. For example, the fifth metal pattern MP5 may include the same metal as the metal of the sixth metal pattern MP6.

[0077] The second gate electrode GE2 will be further described in detail with reference to FIGS. 6A, 6B, and 6C. In the description of the second gate electrode GE2, features that are the same as those in the first gate electrode GE1 will not be described redundantly, and the differences will be mainly described.

[0078] The second gate electrode GE2 may include a lower gate electrode LGE disposed in the first active region AR1 and an upper gate electrode UGE disposed in the second active region AR2. An isolation pattern ISP may be interposed between the lower gate electrode LGE and the upper gate electrode UGE of the second gate electrode GE2. The isolation pattern ISP may make the second gate electrode GE2 into a split gate electrode in which the lower gate electrode LGE of the first active region AR1 is separated from the upper gate electrode UGE of the second active region AR2. In an embodiment of the inventive concept, the first gate electrode GE1 may include a first lower gate electrode in the lower gate electrode LGE on the first lower channel pattern in the lower channel pattern CH1, and a first upper gate electrode in the upper gate electrode UGE on the first upper channel pattern in the upper channel pattern CH2, wherein the first lower gate electrode and the first upper gate electrode are connected to each other. The second gate electrode may include a second lower gate electrode in the lower gate electrode LGE on the second lower channel pattern in the lower channel pattern CH1, a second upper gate electrode in the upper gate electrode UGE on the second upper channel pattern in the upper channel pattern CH2, and an isolation pattern ISP located between the second lower gate electrode and the second upper gate electrode, wherein the second lower gate electrode and the second upper gate electrode are separated from each other by the isolation pattern ISP. In an embodiment of the inventive concept, each of the first lower gate electrode and the second lower gate electrode may surround the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and each of the first upper gate electrode and the second upper gate electrode may surround the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4.

[0079] Each of a first portion PO1, a second portion PO2, and a third portion PO3 of the first gate electrode GE1, and a first portion PO1, a second portion PO2, and a third portion PO3 of the second gate electrode GE2 may include a first metal pattern MP1 and a second metal pattern MP2. A lower gate electrode LGE of the second gate electrode GE2 may be recessed at a remaining portion other than the first portion PO1, the second portion PO2, and the third portion PO3. An isolation pattern ISP may fill a recessed region of the lower gate electrode LGE.

[0080] Referring to FIG. 6C, a sixth metal pattern MP6 of the second gate electrode GE2 may have a top surface contacting a bottom surface of the isolation pattern ISP. The isolation pattern ISP may have a top surface contacting a bottom surface of an upper gate electrode UGE. A top surface of the isolation pattern ISP may be at a level height between a level height of a top surface of a dummy channel pattern DSP and a level height of a bottom surface of the dummy channel pattern DSP. A top surface of the sixth metal pattern MP6 may be at a level height between a level height of a top surface of a first semiconductor pattern SP1 and a level height of a bottom surface of a second semiconductor pattern SP2.

[0081] The sixth metal pattern MP6 may have a second thickness TK2 in a third direction D3. The isolation pattern ISP may have a third thickness TK3 in the third direction D3. Each of the second thickness TK2 and the third thickness TK3 may be less than a first thickness TK1 of FIG. 6D. For example, a sum of the second thickness TK2 and the third thickness TK3 may be substantially the same as the first thickness TK1. In an embodiment of the inventive concept, the third thickness TK3 may be greater than the second thickness TK2.

[0082] Since the lower gate electrode LGE of the second gate electrode GE2 is separated from an upper gate electrode UGE of the second gate electrode GE2, signals may be individually applied to each of the lower gate electrode LGE and the upper gate electrode UGE. Accordingly, as will be discussed below, the second gate electrode GE2 may be provided with a lower gate contact LGC connected to the lower gate electrode LGE and an upper gate contact UGC connected to the upper gate electrode UGE. Since the lower gate contact LGC and the upper gate contact UGC may be formed to have different depths from each other and may be correspondingly connected to the lower gate electrode LGE and the upper gate electrode UGC, a cross-coupling structure may be achieved using this configuration. Accordingly, in an embodiment of the inventive concept, an integration degree of a semiconductor device may be increased.

[0083] Referring back to FIG. 5, according to an embodiment of the inventive concept, a first cell boundary CB1 may be defined to extend in a second direction D2 over a logic cell of a logic circuit LC. At a position opposite to the position of the first cell boundary CB1, a second cell boundary CB2 may be defined to extend in the second direction D2. A gate cut pattern CT may be provided on the first cell boundary CB1 and the second cell boundary CB2, and the gate cut patterns CT are arranged in the second direction D2. When observed in a plan view, the gate cut patterns CT may be arranged at a first pitch along the first cell boundary CB1. The gate cut patterns CT may be arranged at the first pitch along the second cell boundary CB2. When observed in a plan view, the gate cut patterns CT located on the first cell boundary CB1 and the second cell boundary CB2 may be provided to overlap corresponding to a first gate electrode GE1 and a second gate electrode GE2. For example, portions of the first gate electrode GE1 and the second gate electrode GE2 overlapped by the gate cut pattern CT may be removed and replaced by the gate cut pattern CT (see FIGS. 5 and 6D).

[0084] The gate cut pattern CT may penetrate the first gate electrode GE1 or the second gate electrode GE2. The gate cut pattern CT may separate the first gate electrode GE1 or the second gate electrode GE2 from another adjacent gate electrode in a first direction D1. That is, the gate cut pattern CT may cut one gate electrode into two gate electrodes. For example, referring to FIG. 6D, a pair of gate cut patterns CT may be provided at opposite ends of the first gate electrode GE1. The gate cut pattern CT may include a dielectric material, such as (by way of example) a silicon oxide (SiO2) layer, a silicon nitride (Si3N4) layer, or a combination thereof.

[0085] According to an embodiment of the inventive concept, a third cell boundary CB3 may be defined to extend in a first direction D1 over a logic cell of a logic circuit LC. A fourth cell boundary CB4 may be defined to extend in the first direction D1 at a position opposite to the position of the third cell boundary CB3. A cell isolation pattern DB may be correspondingly provided on the third cell boundary CB3 and the fourth cell boundary CB4. Thus, the pair of cell isolation patterns DB opposite to each other in the second direction D2 may be parallel to the first gate electrode GE1 and the second gate electrode GE2, and may be provided on both sides of the logic cell of FIG. 5. The cell isolation pattern DB may separate the logic cell of FIG. 5 from another adjacent logic cell while extending in the first direction D1.

[0086] The gate contacts UGC and LGC can be configured to penetrate the fourth interlayer dielectric layer 140 and the gate cap pattern GP described below, and can be configured to be electrically connected to the first gate electrode GE1 and the second gate electrode GE2. For example, the upper gate contact UGC can be coupled to the upper gate electrode UGE of each of the first gate electrode GE1 and the second gate electrode GE2. The lower gate contact LGC can be coupled to the lower gate electrode LGE of the second gate electrode GE2. For example, the bottom surface of the lower gate contact LGC can be lower than the bottom surface of the upper gate contact UGC.

[0087] Each of the upper gate contact UGC and the lower gate contact LGC can include at least one metal selected from metals such as, for example (by way of example), copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo). Each of the upper gate contact UGC and the lower gate contact LGC can have a pillar shape extending in the third direction D3. The contact spacer CSP can be configured to surround the outer sidewalls of each of the upper gate contact UGC and the lower gate contact LGC. The contact spacer CSP located on the lower gate contact LGC can insulate the lower gate contact LGC from the upper gate electrode UGE.

[0088] The first active contact AC1 (see FIG. 6E) can be disposed on at least one lower source / drain pattern SD1. The first active contact AC1 can include a vertical extension portion VEP and a horizontal extension portion HEP. The vertical extension portion VEP can have a pillar shape that extends vertically while penetrating the first interlayer dielectric layer 110, the second interlayer dielectric layer 120, and the third interlayer dielectric layer 130. The vertical extension portion VEP of the first active contact AC1 can be horizontally offset from the stacked lower source / drain pattern SD1 and upper source / drain pattern SD2. For example, the vertical extension portion VEP can be spaced apart from the lower source / drain pattern SD1 and the upper source / drain pattern SD2 in the first direction D1. The horizontal extension portion HEP can be disposed on the bottom layer of the front-end-of-line (FEOL) layer. The horizontal extension portion HEP can extend from the vertical extension portion VEP in the first direction D1, thereby coupling to the lower source / drain pattern SD1.

[0089] The horizontal extension portion HEP and the vertical extension portion VEP can be connected to form a single first active contact AC1. For example, the first active contact AC1 can include one or more selected from doped semiconductors and metals. The metals can include one or more selected from, for example, copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0090] A second active contact AC2 (see FIG. 6E) can be disposed on at least one upper source / drain pattern SD2. The second active contact AC2 can be spaced apart from the first active contact AC1 in a first direction D1. The second active contact AC2 can overlap the upper source / drain pattern SD2 perpendicularly.

[0091] The second active contact AC2 can be disposed on the top layer of a front-end-of-line (FEOL) layer. The second active contact AC2 can have a columnar shape extending perpendicularly and can be directly coupled to the upper source / drain pattern SD2. For example, the second active contact AC2 can include the same material as that of the first active contact AC1. When the first active contact AC1 and the second active contact AC2 are formed of metal, silicide patterns can be formed between the first active contact AC1 and the lower source / drain pattern SD1 and between the second active contact AC2 and the upper source / drain pattern SD2 respectively during the formation of the first active contact AC1 and the second active contact AC2 to provide reliable metal-semiconductor contacts.

[0092] A fourth interlayer dielectric layer 140 can be disposed on the third interlayer dielectric layer 130. A first metal layer M1 can be disposed in the fourth interlayer dielectric layer 140. The first metal layer M1 can include a first power supply line POR1, a second power supply line POR2, and first to fourth wiring traces MI1 to MI4.

[0093] When observed in a plan view, the first power supply line POR1 can be disposed on a first cell boundary CB1, and the second power supply line POR2 can be disposed on a second cell boundary CB2. A gate cut pattern CT can overlap the first power supply line POR1 and the second power supply line POR2 perpendicularly. A drain voltage (VDD) can be applied to one of the first power supply line POR1 and the second power supply line POR2, and a source voltage (VSS) can be applied to the other of the first power supply line POR1 and the second power supply line POR2. In an embodiment of the present invention concept, a source voltage (VSS) can be applied to the first power supply line POR1, and a drain voltage (VDD) can be applied to the second power supply line POR2.

[0094] The first wiring trace MI1 to the fourth wiring trace MI4 can be disposed between the first power line POR1 and the second power line POR2. Each of the first wiring trace MI1 to the fourth wiring trace MI4 can have a linear shape or a strip shape extending in the second direction D2. The first power line POR1, the second power line POR2, and the first wiring trace MI1 to the fourth wiring trace MI4 can include at least one metal selected from metals such as, for example (by way of example), copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0095] The first metal layer M1 can further include vias VI disposed thereunder. One of the vias VI can connect one of the first active contact AC1 and the second active contact AC2 to one of the first power line POR1 and the second power line POR2. Another one of the vias VI can connect the adjacent first active contact AC1 and the second active contact AC2 to each other (see FIG. 6E). Still another one of the vias VI can connect one of the lower contact UGC and the upper contact LGC to one of the first wiring trace MI1 to the fourth wiring trace MI4 (see FIG. 6D).

[0096] Additional metal layers can be stacked on the first metal layer M1. The first metal layer M1 and other metal layers located on the first metal layer M1 can constitute the back-end-of-line (BEOL) layers of the semiconductor device. The other metal layers located on the first metal layer M1 can include routing lines for connecting logic units to each other.

[0097] The semiconductor device according to the inventive concept can have a three-dimensional cell structure including an NMOS field-effect transistor and a PMOS field-effect transistor. Among the second gate electrodes GE2 in FIG. 5, one can be the first split gate SGE1 and the other can be the second split gate SGE2.

[0098] Referring to the logic circuit LC of FIG. 4, the first signal A can be input to the first wiring trace MI1. The first signal A can be input to the upper gate electrode UGE of the first split gate SGE1 via the upper gate contact UGC located under the first wiring trace MI1. The first signal A can be input to the lower gate electrode LGE of the second split gate SGE2 via the lower gate contact LGC located under the first wiring trace MI1 (see FIGS. 5 and 6B).

[0099] The second signal / A can be input to the second wiring trace MI2. The second signal / A can be input to the lower gate electrode LGE of the first split gate SGE1 via the lower gate contact LGC located under the second wiring trace MI2. The second signal / A can be input to the upper gate electrode UGE of the second split gate SGE2 via the upper gate contact UGC located under the second wiring trace MI2 (see FIG. 6C). For example, the first wiring trace MI1 can be electrically connected to the upper gate contact UGC coupled to the upper gate electrode UGE of the first split gate SGE1, and the second wiring trace MI2 can be electrically connected to the lower gate contact LGC coupled to the lower gate electrode LGE of the first split gate SGE1 (see FIG. 5).

[0100] The three-dimensional device according to the concept of the present invention can have a split gate structure in which the lower gate electrode LGE and the upper gate electrode UGE are separated from each other, and thus the cross-coupling structure of FIG. 4 can be completed three-dimensionally.

[0101] The first input signal SI1 can be input to the third wiring trace MI3, and the second input signal SI2 can be input to the fourth wiring trace MI4. Therefore, according to an embodiment of the concept of the present invention, the logic circuit LC of FIG. 4 can achieve a three-dimensional cell structure.

[0102] Regarding the three-dimensional device according to an embodiment of the concept of the present invention, only two gates or the first split gate SGE1 and the second split gate SGE2 can implement the cross-coupling structure. Therefore, the cell area for constituting the cross-coupling structure of FIG. 4 can be reduced. Therefore, according to an embodiment of the concept of the present invention, the integration degree of the semiconductor device can be improved.

[0103] FIGS. 7A to 15C are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the concept of the present invention. FIGS. 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, and 15A illustrate cross-sectional views taken along line A-A' of FIG. 5. FIGS. 9B, 10B, 11B, and 12B illustrate cross-sectional views taken along line E-E' of FIG. 5. FIGS. 7B, 8B, 13B, 14B, and 15B illustrate cross-sectional views taken along line C-C' of FIG. 5. FIG. 15C illustrates a cross-sectional view taken along line D-D' of FIG. 5.

[0104] Referring to FIGS. 7A and 7B, a first sacrificial layer SAL1 and a first active layer ACL1 may be alternately stacked on a substrate 100. The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may be a single crystal semiconductor substrate formed of a semiconductor material such as silicon (Si). The first sacrificial layer SAL1 may include one of, for example, silicon (Si), germanium (Ge), or silicon-germanium (SiGe), and the first active layer ACL1 may include the other of, for example, silicon (Si), germanium (Ge), or silicon-germanium (SiGe). For example, the first sacrificial layer SAL1 may include silicon-germanium (SiGe) formed by an epitaxial growth process, and the first active layer ACL1 may include silicon (Si) formed by an epitaxial growth process. Each of the first sacrificial layers SAL1 may have a germanium (Ge) concentration of about 10 atomic % to about 30 atomic %.

[0105] A second sacrificial layer SAL2 may be formed on the uppermost first active layer ACL1. In an embodiment of the inventive concept, the thickness of the second sacrificial layer SAL2 may be substantially the same as the thickness of the first sacrificial layer SAL1. In an embodiment of the inventive concept, the thickness of the second sacrificial layer SAL2 may be greater than the thickness of the first active layer ACL1 and the thickness of the first sacrificial layer SAL1. The second sacrificial layer SAL2 may include silicon (Si) or silicon-germanium (SiGe). When the second sacrificial layer SAL2 includes silicon-germanium (SiGe), the germanium (Ge) concentration of the second sacrificial layer SAL2 may be greater than the germanium (Ge) concentration of the first sacrificial layer SAL1. For example, the second sacrificial layer SAL2 may have a germanium (Ge) concentration of about 40 atomic % to about 90 atomic %.

[0106] A third sacrificial layer SAL3 and a second active layer ACL2 may be alternately stacked on the second sacrificial layer SAL2. Each of the third sacrificial layers SAL3 may include the same material as the material of the first sacrificial layer SAL1, and each of the second active layers ACL2 may include the same material as the material of the first active layer ACL1. The second sacrificial layer SAL2 may be sandwiched between the first sacrificial layer SAL1 and the third sacrificial layer SAL3.

[0107] The stacked pattern STP can be formed by patterning the stacked first sacrificial layer SAL1, second sacrificial layer SAL2, and third sacrificial layer SAL3, as well as the stacked first active layer ACL1 and second active layer ACL2. The formation of the stacked pattern STP can include forming a hard mask pattern on the uppermost second active layer ACL2, and using the hard mask pattern as an etching mask to etch the layers SAL1, SAL2, SAL3, ACL1, and ACL2 stacked on the substrate 100. During the formation of the stacked pattern STP, the upper portion of the substrate 100 can be patterned to form trenches TR that define the active pattern AP. The stacked pattern STP can have a strip shape extending in the second direction D2.

[0108] The stacked pattern STP can include a lower stacked pattern STP1 located on the active pattern AP, an upper stacked pattern STP2 located on the lower stacked pattern STP1, and a second sacrificial layer SAL2 located between the lower stacked pattern STP1 and the upper stacked pattern STP2. The lower stacked pattern STP1 can include the first sacrificial layer SAL1 and the first active layer ACL1 stacked alternately. The upper stacked pattern STP2 can include the third sacrificial layer SAL3 and the second active layer ACL2 stacked alternately.

[0109] A device isolation layer ST can be formed on the substrate 100 to fill the trenches TR. For example, a dielectric layer can be formed on the entire surface of the substrate 100 to cover the active pattern AP and the stacked pattern STP. The dielectric layer can be recessed to form the device isolation layer ST until the stacked pattern STP is exposed. The top surface of the device isolation layer ST can be at a horizontal height that is the same as or lower than the horizontal height of the top surface of the active pattern AP.

[0110] Referring to FIGS. 8A and 8B, a sacrificial pattern PP can be formed to extend over the entire stacked pattern STP. Each of the sacrificial patterns PP can be formed to have a linear shape extending in the first direction D1. The sacrificial patterns PP can be arranged in a first pitch along the second direction D2.

[0111] The formation of the sacrificial pattern PP can include: forming a sacrificial layer on the entire surface of the substrate 100, forming a hard mask pattern MP on the sacrificial layer, and using the hard mask pattern MP as an etching mask to pattern the sacrificial layer. The sacrificial layer can include one or more selected from, for example, amorphous silicon (a-Si) and polycrystalline silicon (p-Si).

[0112] The spacer layer GSL can be conformally formed over the entire surface of the substrate 100. The spacer layer GSL can cover the sacrificial pattern PP and the hard mask pattern MP. For example, the spacer layer GSL can include one or more selected from, for example, silicon carbonitride (SiCN), silicon oxynitride (SiCON), and silicon nitride (Si3N4).

[0113] Referring to FIGS. 9A and 9B, a first etching process can be performed on the stacked pattern STP using the spacer layer GSL and the hard mask pattern MP as an etching mask. The first etching process can form a first recess RS1 in the stacked pattern STP between the sacrificial patterns PP. The first recess RS1 can be formed between a pair of sacrificial patterns PP.

[0114] The first etching process can be an anisotropic etching process. The first etching process can convert the spacer layer GSL into the gate spacer GS covering the sidewalls of the sacrificial pattern PP. The first etching process can continue until the uppermost first sacrificial layer SAL1 of the lower stacked pattern STP1 is exposed. For example, the first recess RS1 can expose the lower stacked pattern STP1.

[0115] A liner layer LIN can be conformally formed over the entire surface of the substrate 100, and the liner layer LIN can cover the gate spacer GS and the hard mask pattern MP. The liner layer LIN can cover the inner walls of the first recess RS1 and the exposed lower stacked pattern STP1. For example, the liner layer LIN can include silicon nitride (Si3N4).

[0116] Referring to FIGS. 10A and 10B, a second etching process can be performed on the stacked pattern STP using the liner layer LIN, the gate spacer GS, and the hard mask pattern MP as an etching mask. The second etching process can remove the lower stacked pattern STP1 between the sacrificial patterns PP, thereby forming a second recess RS2. The second recess RS2 can extend further downward from the first recess RS1.

[0117] The second etching process can be an anisotropic etching process and can be performed until the top surface of the active pattern AP is exposed. For example, the second recess RS2 can expose the top surface of the active pattern AP.

[0118] Referring to FIGS. 11A and 11B, a lower source / drain pattern SD1 can be correspondingly formed in the second groove RS2. For example, the lower source / drain pattern SD1 can be formed by performing a first selective epitaxial growth (SEG) process in which the inner wall of the second groove RS2 is used as a seed layer. The lower source / drain pattern SD1 can grow from the seed, or from the first active layer ACL1 and the substrate 100 exposed to the second groove RS2. For example, the first SEG process can include chemical vapor deposition (CVD) or molecular beam epitaxy (MBE).

[0119] During the first SEG process, the lower source / drain pattern SD1 can be doped with impurities in-situ. As an alternative, after the lower source / drain pattern SD1 is formed, impurities can be implanted into the lower source / drain pattern SD1. The lower source / drain pattern SD1 can be doped to have a first conductivity type (e.g., n-type). In an embodiment of the inventive concept, the lower source / drain pattern SD1 can include a silicon (Si) layer doped with an n-type dopant (e.g., phosphorus (P), arsenic (As), antimony (Sb), and / or bismuth (Bi) for example).

[0120] The lower channel pattern CH1 can be constituted by the first active layer ACL1 sandwiched between a pair of lower source / drain patterns SD1. For example, the first active layer ACL1 can be formed as a first semiconductor pattern SP1 and a second semiconductor pattern SP2 of the lower channel pattern CH1. The first semiconductor pattern SP1 and the second semiconductor pattern SP2 can be connected to the pair of lower source / drain patterns SD1. The lower channel pattern CH1 and the lower source / drain pattern SD1 can constitute a first active region AR1 that is the bottom layer of a three-dimensional device.

[0121] Since the liner layer LIN covers the inner wall of the first groove RS1, no semiconductor layer can be formed independently in the first groove RS1 during the first SEG process.

[0122] Referring to FIGS. 12A and 12B, a first interlayer dielectric layer 110 can be formed to cover the lower source / drain pattern SD1. The first interlayer dielectric layer 110 can be recessed to have a top surface lower than the bottom surface of the lowermost second sacrificial layer SAL2.

[0123] The liner layer LIN exposed to the first groove RS1 can be partially removed. The liner layer LIN covered by the first interlayer dielectric layer 110 can cover the sidewalls of the second sacrificial layer SAL2. For example, the portion of the liner layer LIN covered by the first interlayer dielectric layer 110 may not be removed during this removal process. The removal of the liner layer LIN can enable the first groove RS1 to expose the second active layer ACL2.

[0124] An upper source / drain pattern SD2 can be correspondingly formed in the first groove RS1. For example, the upper source / drain pattern SD2 can be formed by performing a second selective epitaxial growth (SEG) process in which the inner walls of the first groove RS1 serve as a seed layer. The upper source / drain pattern SD2 can grow from the seed or the second active layer ACL2 exposed to the first groove RS1. During the second SEG process, the upper source / drain pattern SD2 can be doped with impurities in situ. As an alternative, after the upper source / drain pattern SD2 is formed, impurities can be implanted into the upper source / drain pattern SD2. The upper source / drain pattern SD2 can be doped to have a second conductivity type different from the first conductivity type (e.g., p-type). In an embodiment of the inventive concept, the upper source / drain pattern SD2 can include a silicon-germanium (SiGe) layer doped with a p-type dopant (e.g., (for example) boron (B), aluminum (Al), gallium (Ga), and / or indium (In)). As an alternative, the upper source / drain pattern SD2 can include a silicon (Si) layer doped with a p-type dopant (e.g., (for example) boron (B), aluminum (Al), gallium (Ga), and / or indium (In)).

[0125] The upper channel pattern CH2 can be composed of the second active layer ACL2 sandwiched between a pair of upper source / drain patterns SD2. For example, the second active layer ACL2 can be formed as a third semiconductor pattern SP3 and a fourth semiconductor pattern SP4 of the upper channel pattern CH2. The third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 can be connected to the pair of upper source / drain patterns SD2. The upper channel pattern CH2 and the upper source / drain pattern SD2 can constitute a second active region AR2 as the top layer of a three-dimensional device.

[0126] Referring to FIGS. 13A and 13B, a second interlayer dielectric layer 120 can be formed to cover the hard mask pattern MP, the gate spacer GS, and the upper source / drain pattern SD2. For example, the second interlayer dielectric layer 120 can include a silicon oxide (SiO2) layer.

[0127] The second interlayer dielectric layer 120 can be planarized until the top surface of the sacrificial pattern PP is exposed. A back-etch or chemical mechanical polishing (CMP) process can be employed to planarize the second interlayer dielectric layer 120. The hard mask pattern MP can be completely removed during the planarization process. Thus, the second interlayer dielectric layer 120 can have a top surface coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

[0128] A gate cut pattern CT can be formed to penetrate the sacrificial pattern PP, and the gate cut pattern CT can be formed on the first cell boundary CB1 and the second cell boundary CB2 of the logic unit. The gate cut pattern CT can include one or more selected from, for example, a silicon oxide (SiO2) layer and a silicon nitride (Si3N4) layer.

[0129] The exposed sacrificial pattern PP can be selectively removed. The removal of the sacrificial pattern PP can form an external region ORG that exposes the lower channel pattern CH1 and the upper channel pattern CH2 (see FIG. 13B). The removal of the sacrificial pattern PP can include performing a wet etching process using an etchant (p-Si) that selectively etches polysilicon.

[0130] A dummy channel pattern DSP can replace the second sacrificial layer SAL2 exposed in the external region ORG. For example, the formation of the dummy channel pattern DSP can include using the external region ORG to selectively remove the second sacrificial layer SAL2 and forming the dummy channel pattern DSP in the region where the second sacrificial layer SAL2 is removed. Since the second sacrificial layer SAL2 can have a high germanium (Ge) concentration of about 40 atomic % to about 90 atomic %, it can have a high etching selectivity relative to other components and can be selectively removed using an etching process. For example, the removal of the second sacrificial layer SAL2 can include performing a wet etching process using an etchant that selectively etches silicon-germanium (SiGe) having a high germanium (Ge) concentration. According to an embodiment of the inventive concept, the dummy channel pattern DSP can include a dielectric material, such as (for example) a silicon oxide (SiO2) layer or a silicon nitride (Si3N4) layer.

[0131] Referring to FIGS. 14A and 14B, the first sacrificial layer SAL1 and the third sacrificial layer SAL3 exposed to the external region ORG are selectively removed to form the first internal region IRG1 to the fifth internal region IRG5 (see FIG. 14B). For example, an etching process in which the first sacrificial layer SAL1 and the third sacrificial layer SAL3 are selectively etched can be performed so that the first sacrificial layer SAL1 and the third sacrificial layer SAL3 can be removed while the first semiconductor pattern SP1 to the fourth semiconductor pattern SP4 can be left. For silicon-germanium (SiGe) having a relatively high germanium (Ge) concentration, the etching process can have a high etching rate. For example, for silicon-germanium (SiGe) having a germanium (Ge) concentration greater than about 10 atomic %, the etching process can have a high etching rate. For example, in order to form the first internal region IRG1 to the fifth internal region IRG5, the first sacrificial layer SAL1 and the third sacrificial layer SAL3 can be selectively etched by utilizing the etching selectivity difference between the first sacrificial layer SAL1 and the first active layer ACL1 (i.e., the first semiconductor pattern SP1 and the second semiconductor pattern SP2) and between the third sacrificial layer SAL3 and the second active layer ACL2 (i.e., the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4). In an embodiment of the inventive concept, the first internal region IRG1 to the fifth internal region IRG5 can be formed by a wet etching process.

[0132] The selective removal of the first sacrificial layer SAL1 and the third sacrificial layer SAL3 can leave the first semiconductor pattern SP1 and the second semiconductor pattern SP2 on the first active region AR1, and can also leave the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 on the second active region AR2. The first internal region IRG1 can be defined to represent the empty space between the active pattern AP and the first semiconductor pattern SP1, the second internal region IRG2 can be defined to represent the empty space between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and the third internal region IRG3 can be defined to represent the empty space between the second semiconductor pattern SP2 and the dummy channel pattern DSP. The fourth internal region IRG4 can be defined to represent the empty space between the dummy channel pattern DSP and the third semiconductor pattern SP3, and the fifth internal region IRG5 can be defined to represent the empty space between the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4.

[0133] Referring to FIGS. 15A, 15B, and 15C, a gate dielectric layer UGI and LGI can be conformally formed on the exposed first semiconductor pattern SP1 to the fourth semiconductor pattern SP4. For example, a lower gate dielectric layer LGI can be formed on the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and an upper gate dielectric layer UGI can be formed on the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4.

[0134] A lower gate electrode LGE can be formed on the lower gate dielectric layer LGI. The formation of the lower gate electrode LGE can include forming a first portion PO1, a second portion PO2, and a third portion PO3 in a first internal region IRG1, a second internal region IRG2, and a third internal region IRG3, respectively. An upper gate electrode UGE can be formed on the upper gate dielectric layer UGI. The formation of the upper gate electrode UGE can include forming a fourth portion PO4 and a fifth portion PO5 in a fourth internal region IRG4 and a fifth internal region IRG5, respectively, and forming a sixth portion PO6 in an external region ORG. The lower gate electrode LGE and the upper gate electrode UGE can be connected to each other to form a single first gate electrode GE1.

[0135] The formation of the second gate electrode GE2 can further include forming an isolation pattern ISP between the lower gate electrode LGE and the upper gate electrode UGE. The isolation pattern ISP can separate the lower gate electrode LGE and the upper gate electrode UGE from each other. For example, in the formation of the second gate electrode, the lower gate electrode LGE filling the first internal region IRG1, the second internal region IRG2, and the third internal region IRG3 can be first formed, and then the isolation pattern ISP can be formed on the lower gate electrode LGE and the isolation pattern ISP can be recessed so that the top surface of the isolation pattern ISP is at a height between the top surface level of the dummy channel pattern DSP and the bottom surface level of the dummy channel pattern DSP, and the upper gate electrode UGE filling the fourth internal region IRG4 and the fifth internal region IRG5 can be formed on the isolation pattern ISP.

[0136] The first gate electrode GE1 and the second gate electrode GE2 can be recessed to have a reduced height. A gate cap pattern GP can be formed on the recessed first gate electrode GE1 and second gate electrode GE2. The gate cap pattern GP can undergo a planarization process such that the gate cap pattern GP has a top surface coplanar with the top surface of the second interlayer dielectric layer 120.

[0137] Referring back to FIGS. 5 and 6A - 6E, the third interlayer dielectric layer 130 may be formed on the second interlayer dielectric layer 120. The first active contact AC1 may be formed to penetrate the first interlayer dielectric layer 110, the second interlayer dielectric layer 120, and the third interlayer dielectric layer 130 and may be coupled to the lower source / drain pattern SD1. The second active contact AC2 may be formed to penetrate the second interlayer dielectric layer 120 and the third interlayer dielectric layer 130 and may be coupled to the upper source / drain pattern SD2.

[0138] The upper gate contact UGC may be formed to penetrate the third interlayer dielectric layer 130 and the gate cap pattern GP and may be coupled to the upper gate electrode UGE. The lower gate contact LGC may be formed to penetrate the third interlayer dielectric layer 130, the gate cap pattern GP, and the upper gate electrode UGE and may be coupled to the lower gate electrode LGE.

[0139] The fourth interlayer dielectric layer 140 may be formed on the third interlayer dielectric layer 130. The first metal layer M1 may be formed in the fourth interlayer dielectric layer 140. The formation of the first metal layer M1 may include forming the first power line POR1, the second power line POR2, and the first wiring traces MI1 to the fourth wiring traces MI4 on the upper portion of the fourth interlayer dielectric layer 140. Each of the first power line POR1, the second power line POR2, and the first wiring traces MI1 to the fourth wiring traces MI4 may extend in the second direction D2 over the logic units of the logic circuit LC.

[0140] The vias VI may be formed under each of the first power line POR1, the second power line POR2, and the first wiring traces MI1 to the fourth wiring traces MI4. The active contacts AC1 and AC2 and the gate contacts UGC and LGC may be electrically connected to the first metal layer M1 via the vias VI.

[0141] In an embodiment of the present inventive concept, the first power line POR1, the second power line POR2, and the first wiring traces MI1 to the fourth wiring traces MI4 may be formed after the vias VI are formed. In an embodiment of the present inventive concept, a dual damascene process may be employed to form the vias VI together with the first power line POR1, the second power line POR2, and the first wiring traces MI1 to the fourth wiring traces MI4.

[0142] Additional metal layers may be formed on the first metal layer M1. The first metal layer M1 and other additional metal layers located on the first metal layer M1 may constitute the back - end - of - line (BEOL) layers of the semiconductor device.

[0143] FIGS. 16 to 20 are cross-sectional views taken along line C-C' of FIG. 5, which illustrate a method of forming a second gate electrode according to an exemplary embodiment of the inventive concept.

[0144] Referring to FIG. 16, a gate dielectric layer UGI and LGI may be conformally formed on the resultant structure of FIG. 14B. The gate dielectric layer UGI and LGI may include a lower gate dielectric layer LGI on the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the dummy channel pattern DSP, and may also include an upper gate dielectric layer UGI on the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4. For example, the lower gate dielectric layer LGI may cover the top surface, the bottom surface, and the opposite side surfaces of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the dummy channel pattern DSP, and the upper gate dielectric layer UGI may cover the top surface, the bottom surface, and the opposite side surfaces of each of the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4.

[0145] The formation of the lower gate dielectric layer LGI and the upper gate dielectric layer UGI may include forming a silicon oxide (SiO2) layer on the surfaces of the first semiconductor pattern SP1 to the fourth semiconductor pattern SP4, and forming a high-k dielectric layer on the silicon oxide (SiO2) layer.

[0146] A dipole-containing layer DPL may be selectively formed only on the lower gate dielectric layer LGI. For example, the dipole-containing layer DPL may be conformally formed on the lower gate dielectric layer LGI and the upper gate dielectric layer UGI. A mask layer MA may be formed to cover the lower gate dielectric layer LGI and expose the upper gate dielectric layer UGI. The top surface of the mask layer MA may be at a horizontal height similar to the top surface of the dummy channel pattern DSP. The mask layer MA may be used as an etching mask to selectively remove the dipole-containing layer DPL on the upper gate dielectric layer UGI. Accordingly, the dipole-containing layer DPL may be selectively retained only on the lower gate dielectric layer LGI and not on the upper gate dielectric layer UGI.

[0147] The dipole-containing layer DPL may include a dipole element. The dipole element may include, for example, lanthanum (La), aluminum (Al), or a combination thereof. For example, the dipole-containing layer DPL may include, for example, a lanthanum oxide (La2O3) layer, an aluminum oxide (Al2O3) layer, or a combination thereof.

[0148] Thereafter, the mask layer MA can be removed, and then the dipole layer DPL-containing layer can undergo an annealing process to diffuse the dipole elements from the dipole layer DPL-containing layer into the lower gate dielectric layer LGI. Accordingly, a dipole interface can be formed between the silicon oxide (SiO2) layer included in the lower gate dielectric layer and the high-k dielectric layer. The dipole elements diffused into the lower gate dielectric layer LGI can adjust the effective work function of the lower gate electrode LGE to be formed subsequently.

[0149] During the annealing process, the dipole layer DPL-containing layer can discharge the dipole elements and can be removed at the same time. The dipole layer DPL-containing layer can be formed to have a very small thickness, such as about 1 nm, and can thus be easily removed.

[0150] Referring to FIG. 17, a first metal pattern MP1 can be conformally formed on the lower gate dielectric layer LGI and the upper gate dielectric layer UGI. The first metal pattern MP1 can surround the first semiconductor pattern SP1 to the fourth semiconductor pattern SP4.

[0151] The first metal pattern MP1 can include a first work function metal (e.g., a p-type work function metal). The formation of the first metal pattern MP1 can include conformally depositing a metal nitride layer on the lower gate dielectric layer LGI and the upper gate dielectric layer UGI. For example, the first metal pattern MP1 can include, for example, titanium nitride (TiN), tantalum nitride (TaN), titanium oxynitride (TiON), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tungsten carbon nitride (WCN), or molybdenum nitride (MoN).

[0152] A second metal pattern MP2 can be formed on the first metal pattern MP1. The second metal pattern MP2 can be formed to completely fill the first internal region IRG1 to the fifth internal region IRG5. The second metal pattern MP2 can also be formed in the external region ORG.

[0153] The second metal pattern MP2 can include a second work function metal (e.g., an n-type work function metal). The formation of the second metal pattern MP2 can include depositing a metal carbide doped (or containing) with one or more selected from, for example, silicon (Si) and aluminum (Al) on the first metal pattern MP1. For example, the second metal pattern MP2 can include, for example, titanium aluminum carbide (TiAlC) doped with aluminum, tantalum aluminum carbide (TaAlC) doped with aluminum, vanadium aluminum carbide (VAlC) doped with aluminum, titanium silicon carbide (TiSiC) doped with silicon, or tantalum silicon carbide (TaSiC) doped with silicon.

[0154] The second metal pattern MP2 may undergo an etching process to selectively remove the second metal pattern MP2 in the outer region ORG. For example, the etching process may remove the second metal pattern MP2 in the outer region ORG and may leave the second metal pattern MP2 in the first inner region IRG1 to the fifth inner region IRG5.

[0155] Referring to FIG. 18, a sixth metal pattern MP6 may be formed in the lower portion of the outer region ORG. For example, the sixth metal pattern MP6 may be formed on the first metal pattern MP1 and the second metal pattern MP2 to fill the outer region ORG. Thereafter, the sixth metal pattern MP6 may be recessed such that its top surface is located at a first horizontal height LV1. For example, the first horizontal height LV1 may be the same as or higher than the top surface of the first semiconductor pattern SP1 and may be the same as or lower than the bottom surface of the second semiconductor pattern SP2. The sixth metal pattern MP6 may include at least one of metals with low resistance (e.g., tungsten (W), ruthenium (Ru), aluminum (Al), titanium (Ti), and tantalum (Ta)).

[0156] Referring to FIG. 19, the sixth metal pattern MP6 may be used as an etching mask to etch and selectively remove the exposed portion of the first metal pattern MP1. The second metal pattern MP2 may not be removed, and thus the first metal pattern MP1 between the second metal pattern MP2 and the first semiconductor pattern SP1 to the fourth semiconductor pattern SP4 may not be removed. In addition, the second metal pattern MP2 located below the top surface of the sixth metal pattern MP6 may also be retained.

[0157] The exposed portion of the first metal pattern MP1 may be removed to form a lower gate electrode LGE. The lower gate electrode LGE may include a first portion PO1, a second portion PO2, and a third portion PO3 formed in the first inner region IRG1, the second inner region IRG2, and the third inner region IRG3, respectively. Each of the first portion PO1, the second portion PO2, and the third portion PO3 may include the first metal pattern MP1 and the second metal pattern MP2. The lower gate electrode LGE may further include the sixth metal pattern MP6 formed in the lower portion of the outer region ORG.

[0158] Referring to FIG. 20, an isolation pattern ISP may be formed on the sixth metal pattern MP6. The isolation pattern ISP may be formed to have a top surface at a horizontal height between the horizontal height of the top surface of the dummy channel pattern DSP and the horizontal height of the bottom surface of the dummy channel pattern DSP.

[0159] The isolation pattern ISP can be used as an etching mask to remove the first metal pattern MP1 and the second metal pattern MP2 formed in the fourth internal region IRG4 and the fifth internal region IRG5. Accordingly, the upper gate dielectric layer UGI can be exposed.

[0160] Referring back to FIG. 15B, a third metal pattern MP3 can be formed on the upper gate dielectric layer UGI. The third metal pattern MP3 can be formed to have a thickness that completely fills the fourth internal region IRG4 and the fifth internal region IRG5. The third metal pattern MP3 can include a metal nitride layer that is the same as or different from the metal nitride layer of the first metal pattern MP1 as a first work function metal.

[0161] A fourth metal pattern MP4 can be formed on the third metal pattern MP3, partially filling the external region ORG. The fourth metal pattern MP4 can include a metal carbide that is the same as or different from the metal carbide of the second metal pattern MP2 as a second work function metal.

[0162] A fifth metal pattern MP5 can be formed on the fourth metal pattern MP4, filling the unoccupied portion of the external region ORG. The fifth metal pattern MP5 can include a first work function metal (e.g., titanium nitride (TiN)) or a low-resistance metal (e.g., tungsten (W)). In an embodiment of the inventive concept, the fifth metal pattern MP5 can include the same metal as the sixth metal pattern MP6.

[0163] The third metal pattern MP3 to the fifth metal pattern MP5 can be formed on the isolation pattern ISP, and thus the upper gate electrode UGE can be formed. The upper gate electrode UGE can include a fourth portion PO4 and a fifth portion PO5 formed in the fourth internal region IRG4 and the fifth internal region IRG5, respectively. Each of the fourth portion PO4 and the fifth portion PO5 can include the third metal pattern MP3. The upper gate electrode UGE can further include a sixth portion PO6 formed in the external region ORG. The sixth portion PO6 can include the third metal pattern MP3, the fourth metal pattern MP4, and the fifth metal pattern MP5 stacked in sequence.

[0164] FIGS. 21 and 22 are cross-sectional views taken along line D-D' of FIG. 5, which illustrate a method of forming a first gate electrode according to an embodiment of the inventive concept.

[0165] Referring to FIG. 21, a sixth metal pattern MP6 can be formed on the resultant structure of FIG. 17. The sixth metal pattern MP6 can be recessed such that its top surface is at a second horizontal height LV2. The second horizontal height LV2 can be higher than the first horizontal height LV1. The second horizontal height LV2 can be positioned between the top surface and the bottom surface of the dummy channel pattern DSP.

[0166] Referring to FIG. 22, the sixth metal pattern MP6 can be used as an etching mask to remove the first metal pattern MP1 and the second metal pattern MP2. The upper gate dielectric layer UGI can thus be exposed.

[0167] The first metal pattern MP1 and the second metal pattern MP2 can be retained below the top surface of the sixth metal pattern MP6 and can thus form a lower gate electrode LGE. The lower gate electrode LGE can include a first portion PO1, a second portion PO2, and a third portion PO3 formed in a first internal region IRG1, a second internal region IRG2, and a third internal region IRG3, respectively. Each of the first portion PO1, the second portion PO2, and the third portion PO3 can include the first metal pattern MP1 and the second metal pattern MP2. The lower gate electrode LGE can further include the sixth metal pattern MP6 formed in a lower portion of the external region ORG.

[0168] Different from the formation of the second gate electrode GE2 shown in FIG. 20, the formation of the first gate electrode GE1 in FIG. 22 may not include the formation of the isolation pattern ISP, or may include a complete removal of the already formed isolation pattern ISP. For example, the first gate electrode GE1 is a shared gate electrode without the isolation pattern ISP, while the second gate electrode GE2 is a separated gate electrode with the isolation pattern ISP.

[0169] Returning to FIG. 15C, a third metal pattern MP3 can be formed on the upper gate dielectric layer UGI. The third metal pattern MP3 can be formed to have a thickness that completely fills the fourth internal region IRG4 and the fifth internal region IRG5. A fourth metal pattern MP4 can be formed on the third metal pattern MP3, partially filling the external region ORG. A fifth metal pattern MP5 can be formed on the fourth metal pattern MP4, filling the unoccupied portion of the external region ORG. The third metal pattern MP3 to the fifth metal pattern MP5 can constitute an upper gate electrode UGE.

[0170] The isolation pattern ISP can be omitted, and thus the upper gate electrode UGE of the first gate electrode GE1 can be directly formed on and connected to the lower gate electrode LGE of the first gate electrode GE1.

[0171] The three-dimensional semiconductor device according to the inventive concept may achieve a cross-coupled structure by using an isolation pattern between a lower gate electrode and an upper gate electrode. Only two separate gates are required to complete the cross-coupled structure, and thus the area of the flip-flop unit may be reduced. Accordingly, the integration degree of the three-dimensional semiconductor device according to the inventive concept may be increased.

[0172] Although the inventive concept has been described in connection with some specific embodiments of the inventive concept illustrated in the accompanying drawings, those of ordinary skill in the art will understand that changes in form and detail may be made thereto without departing from the spirit and scope of the inventive concept as defined in the appended claims. Accordingly, the embodiments of the inventive concept disclosed above should be considered illustrative rather than restrictive.

Brief Description of the Drawings

[0011] The above and other aspects and features of the inventive concept will be more clearly understood by reading the following detailed description in conjunction with the accompanying drawings, in which: FIG. 1 is a conceptual diagram showing a logic unit of a semiconductor device according to a comparative example of the inventive concept. FIG. 2 is a conceptual diagram showing a logic unit of a semiconductor device according to an embodiment of the inventive concept. FIG. 3 is a logic circuit diagram showing a flip-flop of a semiconductor device according to an embodiment of the inventive concept. FIG. 4 shows the logic circuit constituting the flip-flop of FIG. 3. FIG. 5 is a plan view showing a three-dimensional semiconductor device according to an embodiment of the inventive concept. FIGS. 6A, 6B, 6C, 6D, and 6E are cross-sectional views taken along lines A-A', B-B', C-C', D-D', and E-E' of FIG. 5, respectively. FIGS. 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B, and 15A to 15C are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the inventive concept. FIGS. 16 to 20 are cross-sectional views taken along line C-C' of FIG. 5, which show a method of forming a second gate electrode according to an embodiment of the inventive concept. FIGS. 21 and 22 are cross-sectional views taken along line D-D' of FIG. 5, which show a method of forming a first gate electrode according to an embodiment of the inventive concept. Since the drawings in FIGS. 1 to 22 are for illustrative purposes, the elements in the drawings are not necessarily drawn to scale. For example, some of the elements may be enlarged or exaggerated for clarity.

Claims

1. A three-dimensional semiconductor device, comprising: A first active region is located on a substrate, the first active region including a plurality of lower channel patterns and a plurality of lower source / drain patterns alternately arranged along a first direction; a second active region is located on the first active region, the second active region including a plurality of upper channel patterns and a plurality of upper source / drain patterns alternately arranged along the first direction; a first gate electrode is located on a first lower channel pattern in the lower channel patterns and on a first upper channel pattern in the upper channel patterns; The first gate electrode comprises: a first lower gate electrode located on the second lower channel pattern in the lower channel pattern and a first upper gate electrode located on the second upper channel pattern in the upper channel pattern; wherein the first lower gate electrode and the first upper gate electrode are connected to each other; and the second gate electrode comprises: a second lower gate electrode located on the second lower channel pattern; a second upper gate electrode located on the second upper channel pattern; and an isolation pattern located between the second lower gate electrode and the second upper gate electrode, wherein the second lower gate electrode and the second upper gate electrode are separated from each other by the isolation pattern.

2. The three-dimensional semiconductor device of claim 1, wherein the first lower channel pattern overlaps perpendicularly to the first upper channel pattern, and the second lower channel pattern overlaps perpendicularly to the second upper channel pattern.

3. The three-dimensional semiconductor device as claimed in claim 1, further comprising: The first dummy channel pattern is located between the first lower channel pattern and the first upper channel pattern; And a second dummy channel pattern, located between the second lower channel pattern and the second upper channel pattern.

4. The three-dimensional semiconductor device as claimed in claim 3, wherein each of the first dummy channel pattern and the second dummy channel pattern comprises a silicon oxide layer or a silicon nitride layer.

5. The three-dimensional semiconductor device of claim 1, wherein each of the first lower channel pattern and the second lower channel pattern includes a first semiconductor pattern and a second semiconductor pattern located on the first semiconductor pattern, each of the first lower gate electrode and the second lower gate electrode surrounds the first semiconductor pattern and the second semiconductor pattern, each of the first upper channel pattern and the second upper channel pattern includes a third semiconductor pattern and a fourth semiconductor pattern located on the third semiconductor pattern, and each of the first upper gate electrode and the second upper gate electrode surrounds the third semiconductor pattern and the fourth semiconductor pattern.

6. The three-dimensional semiconductor device as claimed in claim 1, wherein each of the first lower gate electrode and the second lower gate electrode comprises: The first metallic pattern contains a metal with a first work function; A second metal pattern is located on the first metal pattern, and the second metal pattern contains a second work function metal; And a third metal pattern located on the second metal pattern, the third metal pattern comprising a low-resistance metal, wherein the thickness of the third metal pattern included in the first lower gate electrode is greater than the thickness of the third metal pattern included in the second lower gate electrode.

7. The three-dimensional semiconductor device as claimed in claim 6, wherein the thickness of the third metal pattern included in the first lower gate electrode is substantially the same as the sum of the thickness of the third metal pattern included in the second lower gate electrode and the thickness of the isolation pattern.

8. The three-dimensional semiconductor device as claimed in claim 1, further comprising: The lower gate dielectric layer is located between the first lower channel pattern and the first lower gate electrode; And an upper gate dielectric layer, located between the first upper channel pattern and the first upper gate electrode, wherein the lower gate dielectric layer contains a dipole element, and wherein the concentration of the dipole element in the lower gate dielectric layer is greater than the concentration of the dipole element in the upper gate dielectric layer.

9. The three-dimensional semiconductor device as claimed in claim 1, further comprising: The upper gate contact is coupled to the second upper gate electrode; the lower gate contact is coupled to the second lower gate electrode. The first wiring trace is electrically connected to the upper gate contact; and the second wiring trace is electrically connected to the lower gate contact.

10. The three-dimensional semiconductor device of claim 9, further comprising a contact spacer located on a sidewall of the lower gate contact, wherein the lower gate contact penetrates the second upper gate electrode and is insulated from the second upper gate electrode by means of the contact spacer.

11. A three-dimensional semiconductor device, comprising: A first active region and a second active region, wherein the first active region is located on the substrate and the second active region is located on the first active region; A first gate electrode and a second gate electrode are located on the first active region and the second active region, respectively. The first gate electrode includes: a first lower gate electrode located on the first active region; a first upper gate electrode located on the second active region; and a first isolation pattern located between the first lower gate electrode and the first upper gate electrode. The second gate electrode includes: a second lower gate electrode located on the first active region; a second upper gate electrode located on the second active region; and a second isolation pattern located between the second lower gate electrode and the second upper gate electrode. A first upper gate contact is coupled to the first upper gate electrode. A first lower gate contact passes through the first upper gate electrode and the first isolation pattern and is coupled to the first lower gate electrode. A second upper gate contact is coupled to the second upper gate electrode. A second lower gate contact passes through the second upper gate electrode and the second isolation pattern and is coupled to the second lower gate electrode. The first wiring trace is electrically connected to the first upper gate contact and the second lower gate contact; and the second wiring trace is electrically connected to the first lower gate contact and the second upper gate contact.

12. The three-dimensional semiconductor device of claim 11, wherein the first wiring trace is configured to allow a first signal to be applied to a first upper gate electrode and a second lower gate electrode via the first wiring trace, the second wiring trace is configured to allow a second signal to be applied to a second upper gate electrode and a first lower gate electrode via the second wiring trace, and the second signal is an inverted signal of the first signal.

13. The three-dimensional semiconductor device of claim 11, wherein the first lower gate electrode and the first upper gate electrode overlap perpendicularly to each other, the first lower gate electrode and the first upper gate electrode are separated from each other by the first isolation pattern, the second lower gate electrode and the second upper gate electrode overlap perpendicularly to each other, and the second lower gate electrode and the second upper gate electrode are separated from each other by the second isolation pattern.

14. The three-dimensional semiconductor device of claim 11, wherein each of the first lower gate electrode and the second lower gate electrode surrounds a plurality of semiconductor patterns of the first active region, and each of the first upper gate electrode and the second upper gate electrode surrounds a plurality of semiconductor patterns of the second active region.

15. The three-dimensional semiconductor device of claim 11, further comprising a dummy channel pattern located between the first active region and the second active region, wherein the top surface of each of the first isolation pattern and the second isolation pattern is located at a horizontal level between the horizontal level of the top surface of the dummy channel pattern and the horizontal level of the bottom surface of the dummy channel pattern.

16. A three-dimensional semiconductor device, comprising: A first active region is located on a substrate. The first active region includes a lower channel pattern and a lower source / drain pattern connected to the lower channel pattern. A second active region is located on top of the first active region. The second active region includes an upper channel pattern and an upper source / drain pattern connected to the upper channel pattern. A dummy channel pattern is located between the lower channel pattern and the upper channel pattern. The gate electrode is located on the lower channel pattern, the dummy channel pattern, and the upper channel pattern. The gate electrode includes: a lower gate electrode located on the lower channel pattern; an upper gate electrode located on the upper channel pattern; and an isolation pattern located between the lower gate electrode and the upper gate electrode. The lower gate electrode includes a first part and a second part, and the isolation pattern is located on the upper surface of the first part and the side surface of the second part.

17. The three-dimensional semiconductor device of claim 16, wherein the lower gate electrode and the upper gate electrode are separated from each other by the isolation pattern.

18. The three-dimensional semiconductor device of claim 16, wherein the top surface of the isolation pattern is located at a horizontal level between the horizontal level of the top surface of the dummy channel pattern and the horizontal level of the bottom surface of the dummy channel pattern.

19. The three-dimensional semiconductor device of claim 16, wherein the lower channel pattern includes a first semiconductor pattern, the upper channel pattern includes a second semiconductor pattern, the dummy channel pattern includes a dielectric material, and the first semiconductor pattern, the second semiconductor pattern, and the dummy channel pattern overlap each other perpendicularly.

20. The three-dimensional semiconductor device as claimed in claim 16, further comprising: An upper gate contact is coupled to the upper gate electrode; a lower gate contact is coupled to the lower gate electrode. The first wiring trace is electrically connected to the upper gate contact; and the second wiring trace is electrically connected to the lower gate contact.

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