Apparatus and method for setting a precise voltage on test circuits

Abstract

This invention discloses an apparatus having a semiconductor wafer loaded with rows and columns of wafers, wherein the rows and columns of wafers are separated by dicing channels. A selection circuit system is located within the dicing channels. The selection circuit system is connected to test circuitry within the dicing channels. The selection circuitry operates to enable voltage control at a single test circuit when all other test circuitry is disabled.

Description

Technical Field

[0001] This invention broadly relates to testing semiconductor wafers. More specifically, this invention relates to setting a precise voltage on a test circuit. Prior Technology

[0002] Figure 1 illustrates a known semiconductor wafer testing system, comprising a test device 100 connected to a probe card 102, which is connected to pads on a wafer 104. Figure 2 illustrates a semiconductor wafer 104 having individual wafers 200. The individual wafers 200 are formed into rows and columns separated by dicing channels 202. Test circuitry 204 exists within the dicing channels 202. Test circuitry 204 is used during wafer-level testing. When testing is complete, a saw is used in the dicing channels to divide the individual wafers for subsequent packaging. This dicing process destroys the test circuitry 204 in the dicing channels. Figure 3 illustrates a simple test circuit having a gate pad 300, a source pad 302, and a drain pad 304. A probe card probe 306 is connected to the drain pad 304.

[0003] Figure 4 illustrates a test setup 100 including source measurement units SMU1 and SMU2. The SMU voltage is connected to the intended circuit via wires from the device cable, probe tip, probe pad, and metal routing on the chip; here, a resistor R9 is shown. It should be understood that the test circuit can be of any complexity.

[0004] Current travels from the SMU to the test circuit, meaning the voltage at resistor R9 will be degraded from the SMU voltage. Resistors R1 through R8 are not properly controlled. Resistors R1, R2, R3, R4, R5, and R6 represent parasitic resistances in the cables, probe cards, probe tips, and / or probe pads. Resistors R7 and R8 represent parasitic resistances from the on-chip wiring routes.

[0005] Each SMU contains two connections: a "force" connection and a "sensing" connection. In this case, a target voltage is applied through the force terminal of the SMU. Current from the force terminal flows through R1, resulting in a voltage drop (called an "IR voltage drop") equal to the resistance of R1 multiplied by the current. Due to the IR voltage drop, the voltage at node N1 differs from the voltage applied in the SMU. The sensing terminal of the SMU measures the voltage. The current through the sensing terminal is designed to be very low, making the IR voltage drop through R2 negligible. The SMU compares the sensed voltage with the expected target voltage and adds the force voltage to achieve the target voltage at the "Kelvin node" N1. The Kelvin nodes N1 and N2, where the force and sensing terminals meet, are typically located at cable connectors, probe cards, probe pads, or on chip 104.

[0006] Figure 5 illustrates a prior art system having a test device 100 and one wafer 104 with multiple test circuits 1 to N. All test circuits in the array share a common Vdd and / or Vss pad for efficient pad utilization. Each test circuit is digitally addressable, allowing only one circuit to be enabled and the remaining circuits to be disabled. Compared to any disabled circuit, the enabled circuit draws several orders of magnitude more current from the common Vdd and Vss pad. This means that the current measured at the SMU is approximately the same as the current drawn by the enabled circuit. This presents two problems.

[0007] First, if the array of test circuits is large, the leakage current from the deactivated circuits can be large enough to cause a significant error in the current measurement of the activated circuits. Second, it is desirable to measure the leakage current on individual test circuits. In this case, all circuits are deactivated, and the current measurement is a combined leakage of all test circuits. It is impossible to measure the leakage current on each test circuit.

[0008] Therefore, it is necessary to improve the power management of the test circuit in the wafer dicing channel. Summary of the Invention

[0009] An apparatus includes a semiconductor wafer loaded with rows and columns of wafers, wherein the rows and columns of wafers are separated by dicing kerfs. A selection circuit system is positioned within the dicing kerfs. The selection circuit system is connected to test circuitry within the dicing kerfs. The selection circuitry operates to enable voltage control at a single test circuit when all other test circuitry is disabled. Simple Explanation of the Diagram

[0010] The invention will be more fully understood by taking into account the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 illustrates one of the semiconductor wafer testing systems known in the prior art.

[0012] Figure 2 illustrates a prior art semiconductor wafer having a diced path for mounting test circuitry.

[0013] Figure 3 illustrates a prior art test circuit and associated probe card probes.

[0014] Figure 4 illustrates a prior art resistor network associated with a test circuit.

[0015] Figure 5 illustrates prior art test equipment and test circuitry on a wafer.

[0016] Figure 6 illustrates a wafer with a test circuit selection circuit system according to one embodiment of the present invention.

[0017] Figure 7 illustrates a wafer of a head switch selection circuit system according to one embodiment of the present invention.

[0018] Figure 8 illustrates a wafer of a foot switch selection circuit system according to one embodiment of the present invention.

[0019] Figure 9 illustrates a selection circuit system according to one embodiment of the present invention.

[0020] Figure 10 illustrates a selection circuit system utilized according to one embodiment of the present invention.

[0021] Figure 11 illustrates a selection circuit system according to one embodiment of the present invention.

[0022] Similar element symbols refer to the corresponding parts that run through several views of a drawing. Implementation

[0023] Cross-reference to related applications

[0024] This application claims priority to U.S. Provisional Patent Application No. 63 / 215,050, filed June 25, 2021, the contents of which are incorporated herein by reference.

[0025] Figure 6 illustrates a one-end switch 600 inserted between the SMU power supply and each test circuit. In the case of a digital circuit such as a ring oscillator, the one-end switch controls the Vdd power supply and the one-end switch 602 controls the Vss power supply.

[0026] Each test circuit in the addressable array has its own head switch and its own foot switch. A digital select line 604 is connected from an external pad to each head switch and foot switch. Digital addressing allows only one circuit to be selected at a time (a value of "1"). The digital select value of all remaining test circuits is set to "0". For example, a digital select signal can be initiated at test device 100 and then applied to the digital select pad via a probe pin.

[0027] The power supply SMU is connected to the common nodes of all head switches and foot switches, as shown in the node markings in the figure. In this example, there are four SMUs (SMU1, SMU2, SMU3, and SMU4), each with force and sensing lines, namely N1F, N1S, N2F, N2S, N3F, N3S, N4F, and N4S. These force and sensing line nodes are connected to head switch 600 and foot switch 602, as shown in Figure 6. In this embodiment, head switch 600 is connected to nodes N1F, N1S, N2F, and N2S, and foot switch 602 is connected to nodes N3F, N3S, N4F, and NFS.

[0028] Using both a one-end switch and a one-foot switch can eliminate or reduce the IR voltage drop between the two power rails.

[0029] One embodiment of the present invention uses only a head switch 600, as shown in Figure 7.

[0030] In this figure, the Kelvin node 700 for Vss (here for force and sensing convergence of SMU3) is shown on chip 104. This Kelvin node can occur elsewhere along the SMU supply line (e.g., off-chip). The advantage of the embodiment in Figure 7 is reduced complexity.

[0031] Figure 8 illustrates one embodiment of the present invention using only the foot switch 602.

[0032] In this diagram, the Kelvin node 800 for Vdd (used here for force and sensing convergence of SMU1) is shown on the chip. This Kelvin node can occur elsewhere along the SMU supply line (e.g., off-chip). The advantage of this implementation is reduced complexity.

[0033] Figure 9 illustrates one embodiment of head switch 600 and foot switch 602. The head and foot switches of each test circuit are controlled by the digital selections S1, S2, ... SN of N items in the test circuit. (The bar above the selection indicates that the selection signal is inverted). For each of the N items, only one selection value is "1" at a time, and all the remaining selections are "0". For example, if one of the logic values ​​of S1 is "1", then the selections S2 to SN must be "0". If S1 is "1", then transistors MNa1, MNb1, MPa1, and MPb1 are turned on, and the power supply of test circuit 1 is connected to the force and sensing of SMU1 (nodes N1F, N1S) and the force and sensing of SMU3 (nodes N3F, N3S). The Kelvin nodes used for the force and sensing of SMU1 are the same as nodes 900 and 902 used for SMU3. These nodes are directly adjacent to test circuit 1 (both physically and schematically). The gates of transistors MNc1, MNd1, MPc1, and MPd1 are disconnected from SMU2 and SMU4 (nodes N2F, N2S, N4F, and N4S). Since S2 to SN are "0", all such test circuits are disconnected from SMU1 and SMU3, but are connected to SMU2 and SMU4.

[0034] The applied voltage on SMU3 is set to be the same as the applied voltage on SMU1, so that there is no voltage drop in the "off" transistors in the jumper and pin switches. Therefore, for the selected transistor, all current from the selected test circuit is transferred to SMU1 and SMU3, and for the unselected test circuit, all current is transferred to SMU2 and SMU4.

[0035] Figure 10 illustrates another embodiment of the head switch 600 and foot switch 602, wherein the Kelvin node for the unselected test circuit is located before the switch. This saves circuit complexity and wiring routing complexity.

[0036] If the leakage current of the unselected test circuits is large enough (i.e., at pins SMU2 and SMU4), this implementation can result in a significant IR voltage drop. If the array of test circuits is large enough, the sum of the leakage currents of the unselected test circuits can be large. Therefore, this implementation limits the number of test circuits that can be placed in the array.

[0037] Figure 11 illustrates another implementation that allows the Kelvin nodes of SMU2 and SMU4 (i.e., the force and sensing connections between each SMU) to be placed outside the head and foot switches (e.g., possibly outside the chip). If S1 is set to "1", then S2 to SN are set to "0", and transistors MPa1, MPb1, MPd1, and MPe1 are turned on, connecting SMU1 (nodes N1F and N1S) to the top side of test circuit 1. Similarly, MNa1, MNb1, MNd1, and MNe1 are turned on, connecting the bottom side of test circuit 1 to SMU3. SMU2 and SMU4 are disconnected from test circuit 1 because transistors MPc1, MPf1, MNc1, and MNf1 are turned off.

[0038] When S1 is still "1", the relative transistor sets are turned on / off in the head and pin switches of test circuit 2 to test circuit N. For the head switch in test circuit 2, SMU2 is not directly connected to the top of the test circuit as in the previous circuit. In this case, the SMU2 connection to nodes Na2 and Nb2 is isolated from the test circuit by the off MPa2 and MPb2.

[0039] For illustrative purposes, the foregoing description uses specific nomenclature to provide a thorough understanding of the invention. However, those skilled in the art will understand that specific details are not required to practice the invention. Therefore, the foregoing description presents specific embodiments of the invention for illustrative and descriptive purposes. These are not intended to be exhaustive or to limit the invention to the precise forms disclosed; clearly, many modifications and variations are possible in light of the foregoing teachings. Embodiments were chosen and described to best illustrate the principles of the invention and its practical application, thereby enabling those skilled in the art to best utilize the invention and various embodiments with various modifications suitable for the contemplated particular uses. The following claims and their equivalents are intended to define the scope of the invention.

[0040] 100: Testing equipment 102: Probe Card 104: Semiconductor wafers / chips 200: Chip 202: Cutting Track 204: Test Circuit 300: Test Circuit 302: Source Pad 304: Drainage Pad 306: Probe card probe 600: Head switch 602: Foot switch 604: Digit Selection Line 700: Kelvin node 800: Kelvin node 900: Node 902: Node MNa1 to MNnN: Transistors MPa1 to MPnN: Transistors N1: Node N1F to N4F: Nodes N1S to N4S: Nodes N2: Node Na1 to NaN: Nodes Nb1 to NbN: Nodes Nc1 to NcN: Nodes Nd1 to NdN: Nodes R1 to R9: Resistors S1 to SN: Digital Selection SMU1 to SUM4: Source Measurement Unit

Claims

1. An apparatus for setting a precise voltage on a test circuit, comprising: A semiconductor wafer having rows and columns of wafers mounted thereon, wherein the rows and columns of wafers are separated by dicing channels; A selection circuit system located within the cutting channels, the selection circuit system being connected to test circuits within the cutting channels, the selection circuit system operating to enable voltage control at a single test circuit while disabling all other test circuits, wherein the selection circuit system includes at least one of a head switch and a foot switch for each test circuit, each of the head switch and the foot switch comprising: a first switch having a first terminal and a second terminal, the first terminal being configured to connect to a force terminal of a source measurement unit, the second terminal being connected to a first terminal of the test circuit; and a second switch having a first terminal and a second terminal, the first terminal being configured to connect to a sensing terminal of the source measurement unit, the second terminal being connected to a second terminal of the test circuit, wherein the source measurement unit applies a first voltage equal to a target voltage; measures a result voltage; compares the result voltage with the target voltage; and increases the first voltage such that a second voltage obtained at a node where the force terminal and the sensing terminal meet equals the target voltage.

2. The apparatus for setting a precise voltage on a test circuit, as claimed in claim 1, wherein the selection circuit system includes the head switch for each test circuit.

3. The device for setting a precise voltage on a test circuit, as claimed in claim 1, wherein the selection circuit system includes the pin switch for each test circuit.

4. The apparatus for setting a precise voltage on a test circuit as described in claim 1, further comprising the source measurement unit.

5. The apparatus for setting a precise voltage on a test circuit, as claimed in claim 1, further includes a digital selection pad for receiving a control signal for a selection circuit system that operates to enable voltage control at the single test circuit while disabling all other test circuits.

6. The apparatus for setting a precise voltage on a test circuit as claimed in claim 1, wherein the first switch includes a first transistor and the second switch includes a second transistor having the same type as the first transistor.

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