Readout architectures for motion blur reduction in indirect time-of-flight sensors

Abstract

A time-of-flight ranging pixel circuit includes a photodiode configured to generate charge in response to modulated light reflected from an object. First and second transfer transistors are coupled to the photodiode. The first transfer transistor transfers a first portion of the charge from the photodiode in response to a first modulation signal, and the second transfer transistor transfers a second portion of the charge from the photodiode in response to a second modulation signal. The second modulation signal is an inverted first modulation signal. A first floating diffuser is coupled to the first transfer transistor to receive the first portion of the charge in response to the first modulation signal. Each of a first plurality of sampling and holding transistors is coupled between each of a first plurality of memory nodes and the first transfer transistor.

Description

[Technical Field]

[0001] The present invention relates generally to image sensors, and specifically, but not exclusively, to time-of-flight ranging sensors. [Previous Technology]

[0002] As the popularity of 3D applications continues to grow in fields such as imaging, film, games, computers, user interfaces, facial recognition, object recognition, augmented reality, and similar applications, interest in 3D cameras is increasing. A typical passive method for creating 3D images is to use multiple cameras to capture stereo or multiple images. Using stereo images, objects in the images can be triangulated to create 3D images. One drawback of this triangulation technique is the difficulty in creating 3D images using small devices, because a minimum separation distance must exist between the cameras to create 3D images. Furthermore, this technique is complex and therefore requires powerful computer processing capabilities to create 3D images in real time.

[0003] For applications that require real-time acquisition of 3D images, active depth imaging systems based on time-of-flight ranging are sometimes used. Time-of-flight ranging cameras typically employ a light source that guides light to an object, a sensor that detects the light reflected from the object, and a processing unit that calculates the distance to the object based on the round-trip time of the light to and from the object.

Implementation Method

[0013] This document describes examples of various embodiments of a time-of-flight ranging pixel circuit included in a pixel array of a time-of-flight ranging sensing system. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. However, those skilled in the art will recognize that the techniques described herein can be practiced without one or more of these specific details or using other methods, components, materials, etc. In other examples, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring certain aspects.

[0014] Throughout this specification, the reference to "an example" or "an embodiment" is used to describe a particular feature, structure, or characteristic in connection with an example, which is included in at least one example of the invention. Therefore, the phrases "in an example" or "in an embodiment" appearing in multiple places throughout this specification do not necessarily refer to the same example. Furthermore, in one or more examples, a particular feature, structure, or characteristic may be combined in any suitable manner.

[0015] For ease of description, spatial relative terms (such as "below," "below," "above," "down," "above," "top," "bottom," "left," "right," "center," "middle," and the like) are used herein to describe the relationship of one element or feature relative to another element(s), as illustrated in the figures. It should be understood that spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. For example, if the device in the figures is rotated or flipped, an element described as "below," "below," or "under" other elements or features will be oriented "above" other elements or features. Thus, the illustrative terms "below" and "under" may cover both the above and below orientations. The device may be oriented in other ways (rotated ninety degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly. In addition, it should be understood that when an element is referred to as being "between" two other elements, it may be the only element between the other two elements, or there may be one or more intermediary elements.

[0016] Throughout this specification, certain terms of the art are used. These terms shall have their ordinary meaning in the art to which they pertain, unless specifically defined herein or otherwise clearly indicated in the context of their use. It should be noted that element names and symbols (e.g., Si to silicon) are used interchangeably throughout this document; however, both have the same meaning.

[0017] As will be discussed, examples of indirect time-of-flight (e.g., iTOF) sensing systems are disclosed, wherein modulated light is emitted from a light source to an object, and then reflected back from the object to a time-of-flight pixel array included in the time-of-flight sensing system. The object distance is determined in response to the measured phase of the modulation sensed by the time-of-flight pixel circuitry, and this object distance can be used to generate a 3D frame.

[0018] In various embodiments, the photodiode of each time-of-flight ranging pixel circuit is coupled to a plurality of respective floating diffusers via a plurality of transfer transistors. In various embodiments, each of the floating diffusers is coupled to a respective reset device and a plurality of memory nodes via a plurality of respective sampling and holding transistors. Thus, each of the plurality of memory nodes is configured to acquire a subframe of a portion of charge information from the photodiode and to store a portion of the charge information during the acquisition of a subsequent subframe of the charge information.

[0019] In various embodiments, the plurality of memory nodes can then be read out in parallel with or after the acquisition and storage of one or more additional portions of charge information from the photodiode. According to the teachings of the present invention, when the plurality of memory nodes are read out in parallel with or after the acquisition and storage of one or more additional portions of charge information from the photodiode, the readout speed requirements of the time-of-flight ranging pixel circuit are significantly relaxed. This allows for a significant improvement in dynamic blur performance with little or no impact on the integration time in an example time-of-flight ranging pixel circuit. Therefore, it should be understood that the example time-of-flight ranging pixel circuit according to the teachings of the present invention provides a time-of-flight ranging pixel array capable of pipelined or clustered operation with increased image resolution, because the example time-of-flight ranging pixel circuit imposes less pressure on readout speed.

[0020] As will be discussed, various examples of time-of-flight ranging pixel circuits are used for phase measurement. When modulated light reflected from an object is sensed, the time-of-flight ranging pixel circuit is modulated in multiple sub-frames using 0° / 180° and 180° / 0° phase modulation signals and 90° / 270° and 270° / 90° phase modulation signals. According to the teachings of the present invention, by modulating the time-of-flight ranging pixel circuit with opposite phases of 0° / 180° and 180° / 0° phase modulation signals and opposite phases of 90° / 270° and 270° / 90° phase modulation signals in multiple sub-frames, offset errors and dark current errors in the time-of-flight ranging pixel circuit are eliminated or removed.

[0021] In various examples, the 0°, 90°, 180°, and 270° phase modulation signals are also modulated at multiple different frequencies in multiple sub-frames. In various examples, the 0°, 90°, 180°, and 270° phase modulation signals are synchronized to have the same frequency as the modulated light emitted by the light source of the time-of-flight ranging sensing system to the object to achieve zero-difference detection by the indirect time-of-flight ranging sensor. Using different phases in the phase modulation signals allows for the reconstruction of the coded distance. Furthermore, measurements using additional frequencies and / or phases improve systematic errors such as harmonic distortion or multipath artifacts.

[0022] It should be noted that phase increments separated by 360° cannot be distinguished, which leads to measurement ambiguity. Therefore, the modulation frequency of the phase modulation signal is selected to not exceed a maximum modulation frequency in order to accommodate the desired depth range. However, a trade-off is that increasing the modulation frequency improves accuracy.

[0023] For illustration purposes, FIG1 is a block diagram showing one example of a time-of-flight (TOF) ranging optical sensing system 100 according to the teachings of the present invention. In the depicted example, the TOF ranging optical sensing system 100 is a 3D camera that calculates image depth information of a scene (e.g., object 106) based on indirect time-of-flight ranging (e.g., iTOF) measurements using an image sensor comprising a time-of-flight ranging pixel array 110. In some examples, it should be understood that although the TOF ranging optical sensing system 100 can sense 3D images, the TOF ranging optical system 100 can also be used to capture 2D images. In various examples, the TOF ranging optical sensing system 100 can also be used to capture high dynamic range (HDR) images.

[0024] As shown in the illustrated example, the time-of-flight ranging optical sensing system 100 includes: a light source 102 synchronized with a time-of-flight ranging sensor including a time-of-flight ranging pixel array 110, the time-of-flight ranging pixel array 110 including a plurality of time-of-flight ranging pixel circuits 112; and a control circuit 114 coupled to control the time-of-flight ranging pixel array 110 and the light source 102 and synchronize the time-of-flight ranging pixel array 110 with the light source 102.

[0025] As illustrated, the light source 102 is configured to emit light 104 toward the object 106 within a distance L. The emitted light 104 is then reflected from the object 106 as reflected light 108 (e.g., reflected light wave / pulse), some of which propagate within distance L toward the time-of-flight ranging pixel array 110 of the time-of-flight ranging optical sensing system 100 and are incident as image light onto the time-of-flight ranging pixel circuits 112 of the time-of-flight ranging pixel array 110. Each time-of-flight ranging pixel circuit 112 included in the time-of-flight ranging pixel array 110 includes a photodetector (e.g., one or more photodiodes, avalanche photodiodes, or single-photon avalanche diodes or similar) to detect the reflected light 108 and convert the reflected light 108 into an electrical signal (e.g., electrons, image charge, etc.).

[0026] It should be noted that, for illustrative purposes, the time-of-flight ranging pixel array 110 and the control circuitry 114 are shown as separate elements in FIG1. ​​However, it should be understood that the combination of the time-of-flight ranging pixel array 110 and the control circuitry 114 can be integrated onto the same integrated circuit chip or wafer in a non-stacked standard planar sensor. In various embodiments, it should also be understood that the time-of-flight ranging pixel array 110 can be implemented in a stacked time-of-flight ranging image sensor.

[0027] Continuing with the described example, each time-of-flight ranging pixel circuit 112 of the time-of-flight ranging pixel array 110 determines the depth information of a corresponding portion of an object 106, thereby generating a 3D image of the object 106. As will be discussed in more detail below, depth information is determined by measuring the delay / phase difference between the emitted light 104 and the received reflected light 108 in multiple sub-frames by modulating the transfer gates of each time-of-flight ranging pixel circuit 112 with 0° / 180° and 180° / 0° phase modulation signals and with opposite 90° / 270° and 270° / 90° phase modulation signals. This indirectly determines the round-trip time of light from the light source 102 to the object 106 and back to the time-of-flight ranging pixel array 110 of the time-of-flight ranging optical sensing system 100. In various examples, the 0°, 90°, 180°, and 270° phase modulation signals are also modulated at various different frequencies in multiple sub-frames. In various examples, each of the plurality of memory nodes included in each time-of-flight (TOF) pixel circuit 112 can capture and store a portion of the charge information from the photodiodes included in the TOF pixel circuit 112 in a sub-frame during or before reading out a portion of the charge information stored in a portion of a previous sub-frame in another memory node of another sub-frame. Therefore, depth information can be based on electrical signals generated by the photodiodes included in each TOF pixel circuit 112, which are subsequently transferred and stored in the plurality of memory nodes in each TOF pixel circuit 112, which are then subsequently read out.

[0028] As shown in the illustrated example, the round-trip time of the emitted light 104 from the light source 102 to the object 106 and then reflected back to the time-of-flight ranging pixel array 110 can be used to determine the distance L using the following relationship in equations (1) and (2) below: where c is the speed of light, which is approximately equal to 3 × 10⁸ m / s, and TTOF corresponds to the round-trip time, which is the amount of time it takes for the light to travel to and from the object 106, as shown in Figure 1. Accordingly, once the round-trip time is known, the distance L can be calculated and then used to determine the depth information of the object 106.

[0029] As shown in the depicted example, control circuitry 114 is coupled to time-of-flight ranging pixel array 110 and light source 102, and includes logic and memory that, when executed, cause time-of-flight ranging optical sensing system 100 to perform operations for determining round-trip time. The round-trip time determination may be based at least in part on timing signals generated by control circuitry 114. For indirect time-of-flight ranging (FTLT) measurements, the timing signals represent the delay / phase difference between the light wave / pulse when light source 102 emits light 104 and the light wave / pulse when the photodetector in time-of-flight ranging pixel circuitry 112 detects reflected light 108.

[0030] In some instances, the time-of-flight ranging optical sensing system 100 may be included in a device (e.g., a mobile phone, a tablet computer, a camera, etc.) that has size and power limitations determined at least in part based on the size of the device. Alternatively or additionally, the time-of-flight ranging optical sensing system 100 may have specific desired device parameters, such as frame rate, depth resolution, lateral resolution, etc.

[0031] Figure 2 is a timing diagram illustrating the timing relationship between the reception of an example light pulse emitted from a light source and a reflected light pulse in an example time-of-flight ranging imaging system according to the teachings of the present invention, as well as between measurements performed using various phase shifts. Specifically, Figure 2 shows the emitted light 204 (which represents a modulated light pulse emitted from the light source 102 to the object 106) and the corresponding pulse reflected light 208 (which represents a reflected light pulse reflected back from the object 106 and received by the time-of-flight ranging pixel circuit 112 of the time-of-flight ranging pixel array 110 of Figure 1).

[0032] The example depicted in Figure 2 also illustrates a measurement pulse containing a 0° phase modulation signal 214A (e.g., a first phase modulation signal) and a 180° phase modulation signal 214B (e.g., a second phase modulation signal), as well as a measurement pulse containing a 90° phase modulation signal 216A (e.g., a third phase modulation signal) and a 270° phase modulation signal 216B (e.g., a fourth phase modulation signal), all of which, as shown, undergo a phase shift relative to the phase of the pulse of the emitted light 204. Furthermore, it should be understood that in the depicted example, the 180° phase modulation signal 214B is out of phase with the 0° phase modulation signal 214A, the 90° phase modulation signal 216A is 90 degrees out of phase with the 0° phase modulation signal 214A, and the 270° phase modulation signal 216B is 90° out of phase with the phase modulation signal 216A.

[0033] Figure 2 also shows that, according to the teachings of the present invention, the 0° phase signal 214A and the 180° phase modulation signal 214B, as well as the 90° phase modulation signal 216A and the 270° phase modulation signal 216B pulses, are all modulated at the same frequency as the modulated emitted light 204 and the reflected light 208 to achieve zero-difference detection of the reflected light 208. In various examples, the phase modulation signal and the modulation frequency of the modulated emitted light may differ across multiple sub-frames in which the phase is measured. It should be understood that measurements performed at additional frequencies and / or phases can improve systematic errors such as, for example, harmonic distortion and / or multipath artifacts. According to the teachings of the present invention, using different phases for the measurement pulses in the illustrated examples allows for the reconstruction of the coded distance in multiple sub-frames.

[0034] As will be discussed, the 0° phase modulation signal 214A, the 180° phase modulation signal 214B, the 90° phase modulation signal 216A, and the 270° phase modulation signal 216B pulses correspond to the switching or modulation of the transfer transistors included in the time-of-flight ranging pixel circuit 112 of the time-of-flight ranging pixel array 110. In operation, the modulation of the transfer transistors in the time-of-flight ranging pixel circuit 112 of the time-of-flight ranging pixel array 110 can be used to measure the photogenerated charge in one or more photodiodes included in the time-of-flight ranging pixel circuit 112 in response to the reflected light 208, thereby measuring the delay or phase difference φ between the pulse of the emitted light 204 and the corresponding pulse of the reflected light 208.

[0035] For example, the example illustrated in Figure 2 shows that in response to reflected light 208, a first portion Q1 of the charge is generated by a pulse of 0° phase modulation signal 214A and a second portion Q2 of the charge is generated by a pulse of 180° phase modulation signal 214B. Similarly, in response to reflected light 208, a third portion Q3 of the charge is generated by a pulse of 90° phase modulation signal 216A and a fourth portion Q4 of the charge is generated by a pulse of 270° phase modulation signal 216B. As will be discussed in more detail below, according to the teachings of the present invention, the measurement of the fourth phase portions of the charges Q1, Q2, Q3 and Q4 can then be used to determine the delay or phase difference φ between the emitted light 204 and the reflected light 208, and thus determine the time-of-flight ranging (TTOF) of light from the light source 102 to the object 106 and then back to the time-of-flight ranging pixel array 110.

[0036] FIG3 is a schematic diagram illustrating one example of a time-of-flight ranging pixel circuit 312 according to the teachings of the present invention. It should be understood that the time-of-flight ranging pixel circuit 312 of FIG3 may be an example of one of the time-of-flight ranging pixel circuits 112 included in the time-of-flight ranging pixel array 110 shown in FIG1, and the similarly named and numbered elements described above are similarly coupled and functioned below.

[0037] As shown in the example depicted in FIG3, the time-of-flight ranging pixel circuit 312 includes a photodiode 318 configured to generate photocharge in response to incident light. In one example, light incident on the photodiode 318 is reflected modulated light 108 from an object 106, as described in FIG1. ​​A first floating diffuser FDA 322A is configured to store a first portion of the photogenerated charge in the photodiode 318, and a second floating diffuser FDB 322B is configured to store a second portion of the photogenerated charge in the photodiode 318. In one example, a first reset transistor 324A is coupled between a power rail and the first floating diffuser FDA 322A. A second reset transistor 324B is coupled between the power rail and the second floating diffuser FDB 322B. In various embodiments, the first reset transistor 334A is configured to reset the first floating diffuser FDA 322A in response to a first reset signal RSTA, and the second reset transistor 334B is configured to reset the second floating diffuser FDB 322B in response to a second reset signal RSTB. In various embodiments, the first reset signal RSTA and the second reset signal RSTB may be the same signal or different signals. In one embodiment, the first reset transistor 334A and the second reset transistor 334B may also be used as overflow transistors. In these embodiments, the first reset transistor 334A and the second reset transistor 334B can be operated in such a way that excess carriers generated by the photodiode 318 can be directed to a power supply by the first reset transistor 334A and / or the second reset transistor 334B, or in such a way that the photosensitivity of the photodiode 318 is deactivated.

[0038] A first transfer transistor 320A is configured to transfer a first portion of charge from a photodiode 318 to a first floating diffuser FDA 322A in response to a first modulation signal TXA. In one example, the first modulation signal TXA may be an example of one of the phase modulation signals described in FIG2. A second transfer transistor 320B is configured to transfer a second portion of charge from a photodiode 318 to a second floating diffuser FDB 322B in response to a second modulation signal TXB. In one example, the second modulation signal TXB may also be an example of one of the phase modulation signals described in FIG2.

[0039] As shown in the illustrated example, the time-of-flight ranging pixel circuit 312 also includes a first plurality of N capacitors 328A1, 328A2, ..., 328AN (which provide a first plurality of N memory nodes C1A 334A1, C2A 334A2, ..., CNA 334AN) and a second plurality of N capacitors 328B1, 328B2, ..., 328BN (which provide a second plurality of N memory nodes C1B 334B1, CBA 334B2, ..., CNA 334BN). In the example, each of the first plurality of N sampling and holding transistors 326A1, 326A2, ..., 326AN is coupled between the first floating diffusion section FDA 322A and each of the first plurality of N memory nodes C1A 334A1, C2A 334A2, ..., CNA 334AN, as shown. Similarly, each of the second plurality of N sampling and holding transistors 326B1, 326B2, ..., 326BN is coupled between the second floating diffusion section FDB 322B and each of the second plurality of N memory nodes C1B 334B1, C2A 334B2, ..., CNA 334BN, as shown.

[0040] As shown in the illustrated example, the time-of-flight ranging pixel circuit 312 further includes a first output source follower transistor 330A and a second output source follower transistor 330B. Each of the first plurality of N readout transistors 336A1, 336A2, ..., 336AN is coupled between one of the first plurality of N memory nodes C1A 334A1, C2A 334A2, ..., CNA 334AN and a gate of the first output source follower transistor 330A. Each of the second plurality of N readout transistors 336B1, 336B2, ..., 336BN is coupled between one of the second plurality of N memory nodes C1B 334B1, CBA 334B2, ..., CNA 334BN and a gate of the second output source follower transistor 330A. A first column selector transistor 332A is coupled to each of a first plurality of N readout transistors 336A1, 336A2, ..., 336AN, and a second column selector transistor 332B is coupled to each of a second plurality of N readout transistors 336B1, 336B2, ..., 336BN. In one example, the output of the first column selector transistor 332A can be considered as a first tap of a time-of-flight ranging pixel circuit 312 from which the output VA of the first output source follower transistor 330A can be read, and the output of the second column selector transistor can be considered as a second tap of a time-of-flight ranging pixel circuit 312 from which the output VB of the second output source follower transistor 330B can be read.

[0041] In one example, the time-of-flight ranging pixel circuit 312 can be configured as a pipelined pixel circuit such that each output tap has two memory nodes (e.g., N=2). For illustration, in one example of a pipelined pixel circuit where N=2, each output tap has two memory nodes (e.g., 334A1 / 334A2, 334B1 / 334B2), two sample-and-hold transistors (e.g., 326A1 / 326A2, 326B1 / 326B2), and two readout transistors (e.g., 336A1 / 336A2, 336B1 / 336B2). In the example pipeline pixel circuit configuration, one of the memory nodes of each output tap can be coupled to its respective floating diffuser via a respective sample and hold transistor to acquire and store (e.g., sample and hold) a portion of the charge from the floating diffuser, while the other memory node is read out, wherein the other memory node is coupled to the gate terminal of its respective output source follower transistor via a respective readout transistor.

[0042] In another example, the time-of-flight ranging pixel circuit 312 can be configured as a cluster pixel circuit with two or more memory nodes per output tap (e.g., N=4 or N=8). In a cluster pixel circuit configuration, according to the teachings of the present invention, a frame depth with, for example, N=4 or N=8 sub-frames can be formed, with N=4 or N=8 memory nodes per output tap, which allows for a significant reduction in the required analog-to-digital converter (ADC) readout speed, chip size, and power consumption requirements. In operation, all memory nodes (e.g., 334A1 / 334B1, 334A2 / 334B2, ..., 334AN / 334BN) are coupled to sample and retain the first and second portions of charge from their respective floating diffusers (e.g., 322A / 322B) through their respective sampling and holding transistors (e.g., 326A1 / 326B1, 326A2 / 326B2, ..., 326AN / 326BN).

[0043] In one embodiment, the first and second portions of the charge from the respective first and second floating diffusers (e.g., 322A / 322B) each include a plurality of sub-frame portions of the first and second portions of the charge. In various embodiments, each of the respective sub-frame portions of the charge responds to first and second modulation signals TXA and TXB having a combination of a specific phase (e.g., 0° / 180°, 90° / 270°, 180° / 0°, 270° / 90°) and a specific frequency setting (e.g., f1, f2) for each sub-frame and is transferred to the respective first and second floating diffusers (e.g., 322A / 322B). In each example, the multiple sub-frame portions of the first and second portions of the charge in each floating diffusion section (e.g., 322A / 322B) are configured to be sampled and held sequentially (e.g., one after another in time) to one of the memory nodes (e.g., 334A1 / 334B1, 334A2 / 326B2, ..., 326AN / 326BN) by means of a sampling and holding transistor (e.g., 326A1 / 326B1, 326A2 / 334B2, ..., 334AN / 334BN).

[0044] After all memory nodes have received multiple sub-frame portions of the first and second parts of the charge from their respective floating diffusion portions, each of the multiple sub-frame portions of the first and second parts of the charge can then be read from the memory node through its respective readout transistor (e.g., 336A1 / 336B1, 336A2 / 336B2, ..., 336AN / 336BN). In one example, each of the plurality of subframe portions of the first and second portions of charge stored in the respective memory nodes (e.g., 334A1 / 334B1, 334A2 / 334B2, ..., 334AN / 334BN) is configured to have sampled and held multiple subframe portions of the first and second portions of charge from the first and second floating diffusers (e.g., 332A / 332B) in all memory nodes, and then read out sequentially (e.g., one after another in time) by one of the first plurality of readout transistors (e.g., 336A1 / 336B1, 336A2 / 336B2, ..., 336AN / 336BN).

[0045] It should be understood that in cases where the readout speed is too slow for a pipelined pixel circuit configuration, a clustered pixel circuit configuration can be used. For example, in an instance where N=8, eight sub-frames of phase charge information can be sampled and stored sequentially in eight memory nodes. After the eight sub-frames of phase charge information have been stored in their respective eight memory nodes, the eight memory nodes can then be read out sequentially at a reduced readout speed after an integration cycle, since there is usually a gap between integration exposure cycles.

[0046] In various embodiments, the first modulation signal TXA and the second modulation signal TXB are configured to modulate the first transfer transistor 320A and the second transfer transistor 320B. In the embodiments, the first modulation signal TXA and the second modulation signal TXB are modulation signals that are 180° out of phase with each other or are inverted versions of each other during the modulation of multiple sub-frames of the time-of-flight ranging pixel circuit 312. For example, in one embodiment, in a first sub-frame, the first modulation signal TXA may be a 0° phase modulation signal 214A, and the second modulation signal TXB is therefore a 180° phase modulation signal 214B. In that embodiment, in another sub-frame, the first modulation signal TXA and the second modulation signal TXB are inverted relative to their respective signals in the first sub-frame. In other words, in that example, in another sub-frame, the first modulation signal TXA is a 180° phase modulation signal 216B, and the second modulation signal TXB is a 0° phase modulation signal 214A. In various examples, it should be understood that the first and second transfer transistors 320A and 320B can also be modulated in multiple sub-frames using 90° / 270° phase modulation signals and the opposite phase of 270° / 90° phase modulation signals.

[0047] According to the teachings of the present invention, by modulating the first transfer transistor 320A and the second transfer transistor 320B in multiple sub-frames with the opposite phases of the 0° / 180° and 180° / 0° phase modulation signals and the opposite phases of the 90° / 270° and 270° / 90° phase modulation signals, as described, offset errors and dark current errors in the time-of-flight ranging pixel circuit are eliminated or removed.

[0048] In various embodiments, according to the teachings of the present invention, the first modulation signal TXA and the second modulation signal TXB can also be modulated at different frequencies in different sub-blocks, which improves systematic errors such as, for example, harmonic distortion or multipath artifacts. For example, in one embodiment, the first modulation signal TXA and the second modulation signal TXB are configured to alternate between two different modulation frequencies f1 and f2 for each sub-block. In other words, in one embodiment, the first modulation signal TXA and the second modulation signal TXB are configured to be modulated at a modulation frequency f1 during a first sub-block, and then modulated at a modulation frequency f2 during a second sub-block. Then, in a third sub-block, the first modulation signal TXA and the second modulation signal TXB are configured to be modulated at a modulation frequency f1, and then, in a fourth sub-block, the first modulation signal TXA and the second modulation signal TXB are configured to be modulated at a modulation frequency f2, and so on.

[0049] For illustration, a detailed example is described below, in which, in an example of a time-of-flight ranging pixel circuit 312 configured as a pipelined pixel circuit with two memory nodes per output tap (e.g., N=2), offset errors and dark current errors are eliminated or removed by modulating the first transfer transistor 320A and the second transfer transistor 320B with opposite 0° / 180° and 180° / 0° phase modulation signals and with 90° / 270° and 270° / 90° phase modulation signals in multiple sub-frames. In the example, the following relationships are given with respect to the time-of-flight ranging pixel circuit 312. In the example, it should be understood that systematic errors such as harmonic distortion or multipath artifacts can also be reduced by alternating frequency modulation between a first modulation frequency f1 and a second modulation frequency f2 for each sub-frame. It should also be noted that a timing diagram illustrating one of the examples described below is provided in Figure 6.

[0050] In equation (3), VSF1-A represents the voltage VA at the output tap on the left side of the time-of-flight ranging pixel circuit 312 during a first sub-frame SF1, oA represents the offset error associated with the output tap on the left side of the time-of-flight ranging pixel circuit 312, CGA1 represents the conversion gain associated with the memory node C1A 334A1 of the time-of-flight ranging pixel circuit 312, Q0-f1 represents the 0° portion of the charge (e.g., Q1) measured at a first modulation frequency f1, and DCA represents the dark current error associated with the output tap on the left side of the time-of-flight ranging pixel circuit 312.

[0051] In equation (4), VSF1-B represents the voltage VB at the output tap on the right side of the time-of-flight ranging pixel circuit 312 during the first sub-frame SF1, oB represents the offset error associated with the output tap on the right side of the time-of-flight ranging pixel circuit 312, CGB1 represents the conversion gain associated with the memory node C1B 334B1 of the time-of-flight ranging pixel circuit 312, Q180-f1 represents the 180° portion of the charge measured at the first modulation frequency f1 (e.g., Q2), and DCB represents the dark current error associated with the output tap on the right side of the time-of-flight ranging pixel circuit 312.

[0052] In equation (5), VSF2-A represents the voltage VA at the output tap on the left side of the time-of-flight ranging pixel circuit 312 during a second sub-frame SF2, oA represents the offset error associated with the output tap on the left side of the time-of-flight ranging pixel circuit 312, CGA1 represents the conversion gain associated with the memory node C1A 334A1 of the time-of-flight ranging pixel circuit 312, Q0-f2 represents the 0° portion of the charge (e.g., Q1) measured at a second modulation frequency f2, and DCA represents the dark current error associated with the output tap on the left side of the time-of-flight ranging pixel circuit 312.

[0053] In equation (6), VSF2-B represents the voltage VB at the output tap on the right side of the time-of-flight ranging pixel circuit 312 during the second sub-frame SF2, oB represents the offset error associated with the output tap on the right side of the time-of-flight ranging pixel circuit 312, CGB1 represents the conversion gain associated with the memory node C1B 334B1 of the time-of-flight ranging pixel circuit 312, Q180-f2 represents the 180° portion of the charge measured at the second modulation frequency f2 (e.g., Q2), and DCB represents the dark current error associated with the output tap on the right side of the time-of-flight ranging pixel circuit 312.

[0054] In equation (7), VSF3-A represents the voltage VA at the output tap on the left side of the time-of-flight ranging pixel circuit 312 during a third sub-frame SF3, oA represents the offset error associated with the output tap on the left side of the time-of-flight ranging pixel circuit 312, CGA2 represents the conversion gain associated with the memory node C2A 334A2 of the time-of-flight ranging pixel circuit 312, Q90-f1 represents the 90° portion of the charge measured at the first modulation frequency f1 (e.g., Q3), and DCA represents the dark current error associated with the output tap on the left side of the time-of-flight ranging pixel circuit 312.

[0055] In equation (8), VSF3-B represents the voltage VB at the output tap on the right side of the time-of-flight ranging pixel circuit 312 during the third sub-frame SF3, oB represents the offset error associated with the output tap on the right side of the time-of-flight ranging pixel circuit 312, CGB2 represents the conversion gain associated with the memory node C2B 334B2 of the time-of-flight ranging pixel circuit 312, Q270-f1 represents the 270° portion of the charge measured at the first modulation frequency f1 (e.g., Q4), and DCB represents the dark current error associated with the output tap on the right side of the time-of-flight ranging pixel circuit 312.

[0056] In equation (9), VSF4-A represents the voltage VA at the output tap on the left side of the time-of-flight ranging pixel circuit 312 during a fourth sub-frame SF4, oA represents the offset error associated with the output tap on the left side of the time-of-flight ranging pixel circuit 312, CGA2 represents the conversion gain associated with the memory node C2A 334A2 of the time-of-flight ranging pixel circuit 312, Q90-f2 represents the 90° portion of the charge measured at the second modulation frequency f2 (e.g., Q3), and DCA represents the dark current error associated with the output tap on the left side of the time-of-flight ranging pixel circuit 312.

[0057] In equation (10), VSF4-B represents the voltage VB at the output tap on the right side of the time-of-flight ranging pixel circuit 312 during the fourth sub-frame SF4, oB represents the offset error associated with the output tap on the right side of the time-of-flight ranging pixel circuit 312, CGB2 represents the conversion gain associated with the memory node C2B 334B2 of the time-of-flight ranging pixel circuit 312, Q270-f2 represents the 270° portion of the charge measured at the second modulation frequency f2 (e.g., Q4), and DCB represents the dark current error associated with the output tap on the right side of the time-of-flight ranging pixel circuit 312.

[0058] In equation (11), VSF5-A represents the voltage VA at the output tap on the left side of the time-of-flight ranging pixel circuit 312 during a fifth sub-frame SF5, oA represents the offset error associated with the output tap on the left side of the time-of-flight ranging pixel circuit 312, CGA1 represents the conversion gain associated with the memory node C1A 334A1 of the time-of-flight ranging pixel circuit 312, Q180-f1 represents the 180° portion of the charge measured at the first modulation frequency f1 (e.g., Q2), and DCA represents the dark current error associated with the output tap on the left side of the time-of-flight ranging pixel circuit 312.

[0059] In equation (12), VSF5-B represents the voltage VB at the output tap on the right side of the time-of-flight ranging pixel circuit 312 during the fifth sub-frame SF5, oB represents the offset error associated with the output tap on the right side of the time-of-flight ranging pixel circuit 312, CGB1 represents the conversion gain associated with the memory node C1B 334B1 of the time-of-flight ranging pixel circuit 312, Q0-f1 represents the 0° portion of the charge measured at the first modulation frequency f1 (e.g., Q1), and DCB represents the dark current error associated with the output tap on the right side of the time-of-flight ranging pixel circuit 312.

[0060] In equation (13), VSF6-A represents the voltage VA at the output tap on the left side of the time-of-flight ranging pixel circuit 312 during a sixth sub-frame SF6, oA represents the offset error associated with the output tap on the left side of the time-of-flight ranging pixel circuit 312, CGA1 represents the conversion gain associated with the memory node C1A 334A1 of the time-of-flight ranging pixel circuit 312, Q180-f2 represents the 180° portion of the charge measured at the second modulation frequency f2 (e.g., Q2), and DCA represents the dark current error associated with the output tap on the left side of the time-of-flight ranging pixel circuit 312.

[0061] In equation (14), VSF6-B represents the voltage VB at the output tap on the right side of the time-of-flight ranging pixel circuit 312 during the sixth sub-frame SF6, oB represents the offset error associated with the output tap on the right side of the time-of-flight ranging pixel circuit 312, CGB1 represents the conversion gain associated with the memory node C1B 334B1 of the time-of-flight ranging pixel circuit 312, Q0-f2 represents the 0° portion of the charge measured at the second modulation frequency f2 (e.g., Q1), and DCB represents the dark current error associated with the output tap on the right side of the time-of-flight ranging pixel circuit 312.

[0062] In equation (15), VSF7-A represents the voltage VA at the output tap on the left side of the time-of-flight ranging pixel circuit 312 during a seventh sub-frame SF7, oA represents the offset error associated with the output tap on the left side of the time-of-flight ranging pixel circuit 312, CGA2 represents the conversion gain associated with the memory nodes C1A 334A2 of the time-of-flight ranging pixel circuit 312, Q270-f1 represents the 270° portion of the charge measured at the first modulation frequency f1 (e.g., Q4), and DCA represents the dark current error associated with the output tap on the left side of the time-of-flight ranging pixel circuit 312.

[0063] In equation (16), VSF7-B represents the voltage VB at the output tap on the right side of the time-of-flight ranging pixel circuit 312 during the seventh sub-frame SF7, oB represents the offset error associated with the output tap on the right side of the time-of-flight ranging pixel circuit 312, CGB2 represents the conversion gain associated with the memory node C2B 334B2 of the time-of-flight ranging pixel circuit 312, Q90-f1 represents the 90° portion of the charge measured at the first modulation frequency f1 (e.g., Q3), and DCB represents the dark current error associated with the output tap on the right side of the time-of-flight ranging pixel circuit 312.

[0064] In equation (17), VSF8-A represents the voltage VA at the output tap on the left side of the time-of-flight ranging pixel circuit 312 during an eighth sub-frame SF8, oA represents the offset error associated with the output tap on the left side of the time-of-flight ranging pixel circuit 312, CGA2 represents the conversion gain associated with the memory node C1A 334A2 of the time-of-flight ranging pixel circuit 312, Q270-f2 represents the 270° portion of the charge measured at the second modulation frequency f2 (e.g., Q4), and DCA represents the dark current error associated with the output tap on the left side of the time-of-flight ranging pixel circuit 312.

[0065] In equation (18), VSF8-B represents the voltage VB at the output tap on the right side of the time-of-flight ranging pixel circuit 312 during the eighth sub-frame SF8, oB represents the offset error associated with the output tap on the right side of the time-of-flight ranging pixel circuit 312, CGB2 represents the conversion gain associated with the memory node C2B 334B2 of the time-of-flight ranging pixel circuit 312, Q90-f2 represents the 90° portion of the charge measured at the second modulation frequency f2 (e.g., Q3), and DCB represents the dark current error associated with the output tap on the right side of the time-of-flight ranging pixel circuit 312.

[0066] Regarding the relationship of the first modulation frequency f1 given in the above equations (3), (4), (7), (8), (11), (12), (15) and (16), the phase φf1 measured by the self-flying ranging pixel array 312 at the first modulation frequency f1 can be determined according to the following equation (19):

[0067] Similarly, regarding the relationship of the second modulation frequency f2 given in the above equations (5), (6), (9), (10), (13), (14), (17) and (18), the phase φf2 measured by the time-of-flight ranging pixel array 312 at the second modulation frequency f2 can be determined according to the following equation (20):

[0068] Regarding the phase measurement performed at the first modulation frequency f1, substituting equations (3), (4), (7), (8), (11), (12), (15) and (16) into equation (19) yields:

[0069] After expanding the above equation (21), all offset error terms (oA-oA), (oA-oA), (oB-oB), and (oB-oB) cancel each other out. Similarly, all dark current error terms (CGA1·DCA) - (CGA1·DCA), (CGA2·DCA) - (CGA2·DCA), (CGB1·DCB) - (CGB1·DCB), and (CGB2·DCB) - (CGB2·DCB) cancel each other out.

[0070] The phase φf1 measured by the self-flying ranging pixel array 312 at the first modulation frequency f1, after eliminating offset error terms (oA, oB) and dark current error terms (CGA1·DCA, CGA2·DCA, CGB1·DCB, CGB2·DCB) shown in the removal equation (21), can be determined according to the following equation (22):

[0071] It should be understood that, after offset errors and dark current errors are removed or compensated using modulated signals with opposite phases in multiple sub-frames, as discussed above, terms (CGA1 / CGA2) and (CGB1 / CGB2) are residual conversion gain errors. Assuming that the relative conversion gain values ​​CGA1, CGB1, CGA2, and CGB2 are acceptable, the residual conversion gain errors terms (CGA1 / CGA2) and (CGB1 / CGB2) are tolerable.

[0072] Similarly, regarding the phase measurement performed at the second modulation frequency f2, substituting equations (5), (6), (9), (10), (13), (14), (17) and (18) into equation (20) yields:

[0073] After expanding equation (23) above, all offset error terms (oA-oA), (oA-oA), (oB-oB), and (oB-oB) cancel each other out. Similarly, all dark current error terms (CGA1·DCA) - (CGA1·DCA), (CGA2·DCA) - (CGA2·DCA), (CGB1·DCB) - (CGB1·DCB), and (CGB2·DCB) - (CGB2·DCB) cancel each other out.

[0074] After eliminating the offset error terms (oA, oB) and dark current error terms (CGA1·DCA, CGA2·DCA, CGB1·DCB, CGB2·DCB) shown in equation (23), the phase φf2 measured by the self-flying ranging pixel array 312 at the first modulation frequency f1 can be determined according to the following equation (24):

[0075] It should be understood that, after offset errors and dark current errors have been removed or compensated using modulated signals with opposite phases in multiple sub-frames, as discussed above, terms (CGA1 / CGA2) and (CGB1 / CGB2) are residual conversion gain errors. Assuming that the relative conversion gain values ​​CGA1, CGB1, CGA2, and CGB2 are acceptable, the residual conversion gain errors terms (CGA1 / CGA2) and (CGB1 / CGB2) are tolerable.

[0076] Figure 4 is a schematic diagram illustrating another example of a time-of-flight ranging pixel circuit 412 according to the teachings of the present invention. It should be understood that the example of time-of-flight ranging pixel circuit 412 illustrated in Figure 4 shares many similarities with the time-of-flight ranging pixel circuit 312 shown in Figure 3 and / or may be an example of the time-of-flight ranging pixel circuit 112 shown in Figure 1, and the similarly named and numbered elements described above are similarly coupled and function in the following text.

[0077] It should be understood that one of the differences between the example of the time-of-flight ranging pixel circuit 412 illustrated in Figure 4 and the example of the time-of-flight ranging pixel circuit 312 shown in Figure 3 is that the example of the time-of-flight ranging pixel circuit 412 in Figure 4 has a single output tap per time-of-flight ranging pixel circuit 412, instead of two output taps per time-of-flight ranging pixel circuit 312 as shown in Figure 3. In this example, the output VA can be read from one of the output taps on the upper left side of the time-of-flight ranging pixel circuit 412. Therefore, the example time-of-flight ranging pixel circuit 412 shown in Figure 4 is a simplified version of the time-of-flight ranging pixel circuit 312 in Figure 3. Compared with the example time-of-flight ranging pixel circuit 312 depicted in Figure 3, it does not include a corresponding second floating diffuser FDB 322B, a second reset transistor 324B, a second plurality of sample and hold transistors 326B1, 326B2, ..., 326BN, a second plurality of memory nodes C1B 334B1, C2B 334B2, ..., CNB 334BN, a second plurality of capacitors 328B1, 328B2, ..., 328BN, a second plurality of readout transistors 336B1, 336B2, ..., 336BN, a second output source follower transistor 330B, or a second column select transistor 332B.

[0078] Therefore, as illustrated in the example depicted in FIG4, the example time-of-flight ranging pixel circuit 412 includes a photodiode 418 configured to generate photocharge in response to incident light. In one example, light incident on the photodiode 418 is reflected modulated light 108 from an object 106, as described in FIG1. ​​A first floating diffuser FDA 422A is configured to store a first portion of the photogenerated charge in the photodiode 418. In one example, a first reset transistor 424A is coupled between a power rail and the first floating diffuser FDA 422A. In various examples, the first reset transistor 424A is configured to reset the first floating diffuser FDA 422A in response to a first reset signal RSTA. In one example, the first reset transistor 424A may also be used as an overflow transistor. In this example, the first reset transistor 424A can be operated in such a way that excess carriers generated by the photodiode 418 can be directed to a power supply, or in such a way that the photosensitivity of the photodiode 418 is deactivated.

[0079] In one example, the first transfer transistor 420A is configured to transfer a first portion of the charge from the photodiode 418 to the first floating diffuser FDA 422A in response to a first modulation signal TXA. In one example, the first modulation signal TXA may be an example of one of the phase modulation signals described in FIG2. A second transfer transistor 420B is configured to transfer a second portion of the charge from the photodiode 418 in response to a second modulation signal TXB. In one example, the second modulation signal TXB may also be an example of one of the phase modulation signals described in FIG2.

[0080] As shown in the illustrated example, the time-of-flight ranging pixel circuit 412 also includes a first plurality of N capacitors 428A1, 428A2, ..., 428AN, which provide a first plurality of N memory nodes C1A 434A1, C2A 434A2, ..., CNA 434AN. In the example, each of the first plurality of N sampling and holding transistors 426A1, 426A2, ..., 426AN is coupled between a first floating diffuser FDA 422A and each of the first plurality of N memory nodes C1A 434A1, C2A 434A2, ..., CNA 434AN, as shown.

[0081] As shown in the illustrated example, the time-of-flight ranging pixel circuit 412 further includes a first output source follower transistor 430A. Each of the first plurality of N readout transistors 436A1, 436A2, ..., 436AN is coupled between one of the first plurality of N memory nodes C1A 434A1, C2A 434A2, ..., CNA 434AN and a gate of the first output source follower transistor 430A. A first column select transistor 432A is coupled to each of the first plurality of N readout transistors 436A1, 436A2, ..., 436AN. In this example, the output of the first column select transistor 432A can be considered as a single output tap of the time-of-flight ranging pixel circuit 412 from which the output VA of the first output source follower transistor 430A can be read.

[0082] Similar to the example time-of-flight ranging pixel circuit 312 in Figure 3, the time-of-flight ranging pixel circuit 412 in Figure 4 can also be configured as a pipelined pixel circuit such that two memory nodes (e.g., N=2) are coupled to the output tap. For illustration, in one pipelined pixel example where N=2, two memory nodes (e.g., 434A1 / 434A2), two sample-and-hold transistors (e.g., 426A1 / 426A2), and two readout transistors (e.g., 436A1 / 436A2) are coupled to the output tap. In the example pipelined pixel circuit configuration, one of the memory nodes can be coupled to the floating diffuser via a respective sample-and-hold transistor to acquire and store (e.g., sample and hold) a portion of the charge from the floating diffuser, while the other memory node is read out, wherein the other memory node is coupled to the gate terminal of the output source follower transistor via a respective readout transistor.

[0083] In another example, the time-of-flight ranging pixel circuit 412 can be configured as a cluster pixel circuit, wherein two or more memory nodes are coupled to an output tap (e.g., N=4 or N=8). In a cluster pixel circuit configuration, according to the teachings of the present invention, a frame depth having, for example, N=4 or N=8 sub-frames and having N=4 or N=8 memory nodes can be formed, which allows for a significant reduction in the required analog-to-digital converter (ADC) readout speed, chip size, and power consumption requirements. In operation, all memory nodes (e.g., 434A1, 434A2, ..., 434AN) are coupled to sample and hold portions of the charge from the floating diffuser (e.g., 422A) through their respective sampling and holding transistors (e.g., 426A1, 426A2, ..., 426AN).

[0084] After all memory nodes have received a portion of the charge from the floating diffuser, the charge portion can then be read from the memory nodes via their respective readout transistors (e.g., 436A1, 436A2, ..., 436AN). It should be understood that in cases where the readout speed is too slow for a pipelined pixel circuit configuration, a clustered pixel circuit configuration can be used. For example, in an instance where N=8, eight sub-frames of phase charge information can be sampled and stored in eight memory nodes. After the eight sub-frames of phase charge information have been stored in their respective eight memory nodes, the eight memory nodes can then be read out at a reduced readout speed after an integration cycle, since there is typically a gap between integration exposure cycles.

[0085] In one example, the charge portion from the floating diffuser 422A comprises a plurality of sub-frame portions. In this example, each of the plurality of sub-frame portions of charge responds to a first modulation signal TXA having a specific phase (e.g., 0°, 90°, 180°, 270°) and a specific frequency setting (e.g., f1, f2) combination for each sub-frame and is transferred to the floating diffuser 422A. In various examples, each of the plurality of sub-frame portions is configured to be sampled and held sequentially (e.g., one after another in time) to one of the memory nodes (e.g., 434A1, 434A2, ..., 434AN) by means of a sampling and holding transistor (e.g., 426A1, 426A2, ..., 426AN).

[0086] After all memory nodes have received a plurality of sub-frame portions of charge from the floating diffuser 422A, each of the plurality of sub-frame portions of charge can then be read from the memory nodes via its respective readout transistor (e.g., 436A1, 436A2, ..., 436AN). In one example, each of the plurality of sub-frame portions of the phase portion of charge stored in the respective memory nodes (e.g., 434A1, 434A2, ..., 434AN) is configured to be read sequentially (e.g., one after another in time) via one of the readout transistors (e.g., 436A1, 436A2, ..., 436AN) after all memory nodes have sampled and held a plurality of sub-frame portions of the phase portion of charge from the floating diffuser (e.g., 422A).

[0087] In operation, the first modulation signal TXA and the second modulation signal TXB are configured to modulate the first transfer transistor 420A and the second transfer transistor 420B. In various embodiments, the first modulation signal TXA and the second modulation signal TXB are modulation signals that are 180° out of phase with each other or are inverted versions of each other during the modulation of multiple sub-frames of the time-of-flight ranging pixel circuit 412. For example, in one embodiment, in a first sub-frame, the first modulation signal TXA may be a 0° phase modulation signal 214A, while the second modulation signal TXB is therefore a 180° phase modulation signal 214B. In that embodiment, in another sub-frame, the first modulation signal TXA and the second modulation signal TXB are inverted relative to their respective signals in the first sub-frame. In other words, in that example, in another sub-frame, the first modulation signal TXA is a 180° phase modulation signal 216B, and the second modulation signal TXB is a 0° phase modulation signal 214A. In various examples, it should be understood that the first and second transfer transistors 420A and 420B can also be modulated in multiple sub-frames using 90° / 270° phase modulation signals and the opposite phase of 270° / 90° phase modulation signals.

[0088] In various embodiments, according to the teachings of the present invention, the first modulation signal TXA and the second modulation signal TXB can also be modulated at different frequencies in different sub-blocks, which improves systematic errors such as, for example, harmonic distortion or multipath artifacts. For example, in one embodiment, the first modulation signal TXA and the second modulation signal TXB are configured to alternate between two different modulation frequencies f1 and f2 for each sub-block. In other words, in one embodiment, the first modulation signal TXA and the second modulation signal TXB are configured to be modulated at a modulation frequency f1 during a first sub-block, and then modulated at a modulation frequency f2 during a second sub-block. Then, in a third sub-block, the first modulation signal TXA and the second modulation signal TXB are configured to be modulated at modulation frequency f1, and then, in a fourth sub-block, the first modulation signal TXA and the second modulation signal TXB are configured to be modulated at modulation frequency f2, and so on.

[0089] Similar to the time-of-flight ranging pixel circuit 312 depicted in FIG3, according to the teachings of the present invention, by modulating the first transfer transistor 420A and the second transfer transistor 420B in multiple sub-frames with the first modulation signal TXA and the second modulation signal TXB having opposite phases of 0° / 180° and 180° / 0° phase modulation signals and opposite phases of 90° / 270° and 270° / 90° phase modulation signals, offset errors and dark current errors in the time-of-flight ranging pixel circuit are eliminated or removed.

[0090] For illustration, an example is described below, where N=2 and offset errors and dark current errors are eliminated or removed by modulating the first transfer transistor 420A and the second transfer transistor 420B with opposite 0° / 180° and 180° / 0° phase modulation signals and with 90° / 270° and 270° / 90° phase modulation signals in multiple sub-frames. In the example, the following relationship is given with respect to the time-of-flight ranging pixel circuit 412.

[0091] In equation (25), VSF1-A represents the voltage VA at the output tap of the time-of-flight ranging pixel circuit 412 during a first subframe SF1, oA represents the offset error associated with the output tap of the time-of-flight ranging pixel circuit 412, CGA1 represents the conversion gain associated with the memory node C1A 434A1 of the time-of-flight ranging pixel circuit 412, Q0 represents the 0° portion of the charge (e.g., Q1), and DCA represents the dark current error associated with the output tap of the pixel circuit 412.

[0092] In equation (26), VSF2-A represents the voltage VA at the output tap of the time-of-flight ranging pixel circuit 412 during a second sub-frame SF2, oA represents the offset error associated with the output tap of the time-of-flight ranging pixel circuit 412, CGA2 represents the conversion gain associated with the memory nodes C2A 434A2 of the time-of-flight ranging pixel circuit 412, Q90 represents the 90° portion of the charge (e.g., Q3), and DCA represents the dark current error associated with the output tap of the time-of-flight ranging pixel circuit 412.

[0093] In equation (27), VSF3-A represents the voltage VA at the output tap of the time-of-flight ranging pixel circuit 412 during a third sub-frame SF3, oA represents the offset error associated with the output tap of the time-of-flight ranging pixel circuit 412, CGA1 represents the conversion gain associated with the memory node C1A 434A1 of the time-of-flight ranging pixel circuit 412, Q180 represents the 180° portion of the charge (e.g., Q2), and DCA represents the dark current error associated with the output tap of the time-of-flight ranging pixel circuit 412.

[0094] In equation (28), VSF4-A represents the voltage VA at the output tap of the time-of-flight ranging pixel circuit 412 during a fourth sub-frame SF4, oA represents the offset error associated with the output tap of the time-of-flight ranging pixel circuit 412, CGA2 represents the conversion gain associated with the memory nodes C2A 434A2 of the time-of-flight ranging pixel circuit 412, Q270 represents the 270° portion of the charge (e.g., Q4), and DCA represents the dark current error associated with the output tap on the right side of the time-of-flight ranging pixel circuit 412.

[0095] Using the relationships given in equations (25) to (28), the measured phase φ from pixel circuit 412 can be determined as follows:

[0096] Substituting equations (27), (25), (26) and (28) into equation (29), we obtain the following equation to determine the measured phase φ from pixel circuit 412:

[0097] After expanding equation (30) above, the offset error terms (oA-oA) and (oA-oA) cancel each other out. Similarly, the dark current error terms (CGA1·DCA) - (CGA1·DCA) and (CGA2·DCA) - (CGA2·DCA) cancel each other out.

[0098] After eliminating the offset error term (oA) and dark current error term (CGA1·DCA, CGA2·DCA) shown in equation (30), the measured phase φ from the pixel circuit 412 can be determined according to the following equation (31):

[0099] It should be understood that after offset errors and dark current errors are removed or compensated using modulated signals with opposite phases in multiple sub-frames, as discussed above, the term (CGA1 / CGA2) is a residual conversion gain error. Assuming that the relative conversion gain values ​​CGA1 and CGA2 are acceptable, the residual conversion gain error term (CGA1 / CGA2) is tolerable.

[0100] Figure 5 is a schematic diagram illustrating yet another example of a time-of-flight ranging pixel circuit 512 according to the teachings of the present invention. It should be understood that the example of time-of-flight ranging pixel circuit 512 illustrated in Figure 5 shares many similarities with the time-of-flight ranging pixel circuit 312 shown in Figure 3 and / or may be an example of the time-of-flight ranging pixel circuit 112 shown in Figure 1, and the similarly named and numbered elements described above are similarly coupled and function in the following text.

[0101] As will be shown, one of the differences between the example of the time-of-flight ranging pixel circuit 512 illustrated in Figure 5 and the example of the time-of-flight ranging pixel circuit 312 shown in Figure 3 is that the example of the time-of-flight ranging pixel circuit 512 in Figure 5 also includes an optional additional amplification stage, which may be included between the floating diffusion node and the sample and hold transistor. In this example, an additional capacitor may also be coupled to the floating diffusion node. Furthermore, an optional output reset transistor may also be coupled to the gate terminal of the output source follower transistor, which is coupled to the output of the readout transistor.

[0102] For illustration, FIG5 shows a time-of-flight ranging pixel circuit 512 including a photodiode 518 configured to generate photocharge in response to incident light. In one example, light incident on the photodiode 518 is reflected modulated light 108 from an object 106, as described in FIG1. ​​In the example depicted in FIG5, a first floating diffusion capacitor 542A is coupled to a first floating diffusion section FDA 522A, and a second floating diffusion capacitor 542B is coupled to a second floating diffusion section 522B, as shown. The first floating diffusion section FDA 522A and the first floating diffusion capacitor 542A are configured to store a first portion of the photogenerated charge in the photodiode 518, and the second floating diffusion section FDA 522B and the second floating diffusion capacitor 542B are configured to store a second portion of the photogenerated charge in the photodiode 518. In one example, a first reset transistor 524A is coupled between a power rail and a first floating diffuser FDA 522A and a first floating diffuser capacitor 542A. A second reset transistor 524B is coupled between a power rail and a second floating diffuser FDB 522B and a second floating diffuser capacitor 542B. In the example depicted in Figure 5, both the first and second reset transistors 524A and 524B are coupled to receive an overflow signal OF as overflow transistors. Therefore, the first reset transistor 534A and the second reset transistor 534B can be operated in such a way that excess carriers generated by the photodiode 518 can be directed to the power supply by the first reset transistor 534A and / or the second reset transistor 534B, or in such a way that the photosensitivity of the photodiode 518 is deactivated. Thus, in various examples, the overflow signal OF can be activated during a period in which no integration occurs.

[0103] A first transfer transistor 520A is configured to transfer a first portion of charge from a photodiode 518 to a first floating diffuser FDA 522A in response to a first modulation signal TXA. In one example, the first modulation signal TXA may be an example of one of the phase modulation signals described in FIG2. A second transfer transistor 520B is configured to transfer a second portion of charge from a photodiode 518 to a second floating diffuser FDB 522B in response to a second modulation signal TXB. In one example, the second modulation signal TXB may also be an example of one of the phase modulation signals described in FIG2.

[0104] As shown in the illustrated example, the time-of-flight ranging pixel circuit 512 also includes a first plurality of N capacitors 528A1, 528A2, ..., 528AN (which provide a first plurality of N memory nodes C1A 534A1, C2A 534A2, ..., CNA 534AN) and a second plurality of N capacitors 528B1, 528B2, ..., 528BN (which provide a second plurality of N memory nodes C1B 534B1, CBA 534B2, ..., CNA 534BN).

[0105] In the example depicted in FIG5, a first amplification stage, for example, a first amplification source follower transistor 544A, is coupled to a first floating diffusion section FDA 522A and a first floating diffusion capacitor 542A. Therefore, the gate of the first amplification source follower transistor 544A is coupled to the first floating diffusion section FDA 522A and the first floating diffusion capacitor 542A, while the source of the first amplification source follower transistor 544A is coupled to a first plurality of N sampling and holding transistors 526A1, 526A2, ..., 526AN. Similarly, a second amplification stage, for example, a second amplification source follower transistor 544B, is coupled to a second floating diffusion section FDB 522B and a second floating diffusion capacitor 542B. Therefore, the gate of the second amplification source follower transistor 544B is coupled to the second floating diffusion section FDB 522B and the second floating diffusion capacitor 542B, while the source of the second amplification source follower transistor 544B is coupled to the second plurality of N sampling and holding transistors 526B1, 526B2, ..., 526BN.

[0106] In operation, it should be understood that the first and second amplification stages, provided with first and second amplification source follower transistors 544A and 544B, serve as decoupling stages between their respective floating diffusers FDA 522A and FDB 522B and their respective sampling and holding transistors 526A1, 526A2, ..., 526AN and 526B1, 526B2, ..., 526BN. For example, a pixel requires a large full-well capacity or charge handling capability, which can be described by the product C x V = Q. A conventional pipelined or cluster-mode pixel will require each memory node C1A, C2A, ..., CNA, C1B, C2B, ..., CNB to have the required C x V full-well capacity. The first and second amplification source follower transistors 544A and 544B provide a voltage buffer / decoupling stage that only requires a large sensing node capacitance (e.g., capacitors 542A / 542B). With the first and second amplification source follower transistors 544A and 544B, the size of the memory node capacitances C1A, C2A, ..., CNA, C1B, C2B, ..., CNB can now be reduced, which can help reduce pixel pitch (e.g., from 500 ke- to 50 ke-). One associated drawback is additive kTC and flicker noise. However, for semiconductor materials such as germanium or III / V technology, dark current noise is dominant and the additional kTC noise is negligible. Furthermore, even for silicon-based technologies where dark current is negligible, readout noise is generally unimportant for time-of-flight ranging applications. Especially for outdoor applications, most photon shot noise may require a significant limiting factor for FWC. Therefore, this decoupling technique provided by the first and second amplification source follower transistors 544A and 544B is helpful, also for silicon. This technique can be helpful if the application is limited by photon shot noise or dark current shot noise.

[0107] In one example, an enable transistor 546A and a bias transistor 548A are coupled between the source of a second amplification source follower transistor 544B and ground, and an enable transistor 546B and a bias transistor 548B are coupled between the source of the second amplification source follower transistor 544B and ground. In this example, the gates of the enable transistors 546A and 546B are coupled to receive an enable signal EN, and the gates of the bias transistors 548A and 548B are coupled to receive a bias signal BIAS.

[0108] In an example, each of the first plurality of N sampling and holding transistors 526A1, 526A2, ..., 526AN is coupled to a first amplification source follower transistor 544A (which is coupled to a first floating diffusion section FDA 522A and a first floating diffusion capacitor 542A) and one of the first plurality of N memory nodes C1A 534A1, C2A 534A2, ..., CNA 534AN, as shown. Similarly, each of the second plurality of N sampling and holding transistors 526B1, 526B2, ..., 526BN is coupled to the second amplification source follower transistor 544B (which is coupled to the second floating diffusion section FDB 522B and the second floating diffusion capacitor 542B) and each of the second plurality of N memory nodes C1B 534B1, C2A 534B2, ..., CNA 534BN, as shown.

[0109] As shown in the example depicted in Figure 5, the time-of-flight ranging pixel circuit 512 further includes a first output source follower transistor 530A and a second output source follower transistor 530B. In the depicted example, a first output reset transistor 550A is coupled between the gate of the first output source follower transistor 530A and the voltage supply, and a second output reset transistor 550B is coupled between the gate of the second output source follower transistor 530B and the voltage supply. In the example, the gate of the first output reset transistor 550A is coupled to receive a reset signal RSTA, and the gate of the second output reset transistor 550B is coupled to receive a reset signal RSTB. During operation, the gates of the first and second output source follower transistors 530A and 530B can be reset or precharged between readouts via the first and second output reset transistors 550A and 550B to reduce noise by enabling, for example, correlated double sampling. In various examples, the reset signal RSTA and the reset signal RSTB can be the same signal.

[0110] As shown in the depicted example, each of the first plurality of N readout transistors 536A1, 536A2, ..., 536AN is coupled between one of the first plurality of N memory nodes C1A 534A1, C2A 534A2, ..., CNA 534AN and the gate of the first output source follower transistor 530A. Each of the second plurality of N readout transistors 536B1, 536B2, ..., 536BN is coupled between one of the second plurality of N memory nodes C1B 534B1, CBA 534B2, ..., CNA 534BN and the gate of the second output source follower transistor 530B. A first column selector transistor 532A is coupled to each of a first plurality of N readout transistors 536A1, 536A2, ..., 536AN, and a second column selector transistor 532B is coupled to each of a second plurality of N readout transistors 536B1, 536B2, ..., 536BN. In one example, the output of the first column selector transistor 532A can be considered as a first tap of a time-of-flight ranging pixel circuit 512 from which the output VA of the first output source follower transistor 530A can be read, and the output of the second column selector transistor can be considered as a second tap of a time-of-flight ranging pixel circuit 512 from which the output VB of the second output source follower transistor 530B can be read.

[0111] In one example, the time-of-flight ranging pixel circuit 512 can be configured as a pipelined pixel circuit such that each output tap has two memory nodes (e.g., N=2). For illustration, in one example of a pipelined pixel circuit where N=2, each output tap has two memory nodes (e.g., 534A1 / 534A2, 534B1 / 534B2), two sample-and-hold transistors (e.g., 526A1 / 526A2, 526B1 / 526B2), and two readout transistors (e.g., 536A1 / 536A2, 536B1 / 536B2). In the example pipelined pixel circuit configuration, one of the memory nodes of each output tap can respond to a portion of the charge from the floating diffuser by coupling to its respective floating diffuser through a respective sample and hold transistor and through a respective amplifying source follower transistor to acquire and store (e.g., sample and hold) the charge, while the other memory node is read out, wherein the other memory node is coupled to the gate terminal of its respective output source follower transistor through a respective readout transistor.

[0112] In another example, the time-of-flight ranging pixel circuit 512 can be configured as a cluster pixel circuit with two or more memory nodes per output tap (e.g., N=4 or N=8). In a cluster pixel circuit configuration, according to the teachings of the present invention, a frame depth with, for example, N=4 or N=8 sub-frames can be formed, with N=4 or N=8 memory nodes per output tap, which allows for a significant reduction in the required analog-to-digital converter (ADC) readout speed, chip size, and power consumption requirements. In operation, all memory nodes (e.g., 534A1 / 534B1, 534A2 / 534B2, ..., 534AN / 534BN) are coupled to respond to the charge from their respective floating diffusers (e.g., 522A / 522B) through their respective sampling and holding transistors (e.g., 526A1 / 526B1, 526A2 / 526B2, ..., 526AN / 526BN) sampling and holding the first and second portions of the charge from their respective amplification stages.

[0113] In one example, the first and second portions of the charge responding to the charge in the respective first and second floating diffusers (e.g., 522A / 522B) each include a plurality of sub-frame portions. In the example, each of the plurality of sub-frame portions of the first and second portions of the charge responds to first and second modulation signals TXA and TXB, the phase and / or modulation frequency of which are different for each sub-frame. In each example, the plurality of sub-frame portions of the first and second portions of the charge are configured to respond to the charge from their respective floating diffusers (e.g., 522A / 522B) by sampling and holding one of the sampling and holding transistors (e.g., 526A1 / 526B1, 526A2 / 526B2, ..., 526AN / 526BN) and one of the first and second amplification source follower transistors 544A / 544B in sequence (e.g., one after another in time) to one of the memory nodes (e.g., 534A1 / 534B1, 534A2 / 534B2, ..., 534AN / 534BN).

[0114] After all memory nodes have received the first and second portions of the charge in their respective sub-frame portions, each of the plurality of sub-frame portions of the first and second portions of the charge can then be read from the memory node by its respective readout transistor (e.g., 536A1 / 536B1, 536A2 / 536B2, ..., 536AN / 536BN). In one example, each of the plurality of subframe portions of the first and second portions of charge stored in the respective memory nodes (e.g., 534A1 / 534B1, 534A2 / 534B2, ..., 534AN / 534BN) is configured to respond to charge sampling from the first and second floating diffusers (e.g., 532A / 532B) in all memory nodes. After the plurality of subframe portions of the first and second portions of charge are stored, they are read out sequentially (e.g., one after another in time) by one of the first plurality of readout transistors (e.g., 536A1 / 536B1, 536A2 / 536B2, ..., 536AN / 536BN).

[0115] It should be understood that in cases where the readout speed is too slow for a pipelined pixel circuit configuration, a clustered pixel circuit configuration can be utilized. For example, in an instance where N=8, eight sub-frames of phase charge information can be sequentially sampled and stored in eight memory nodes. After the eight sub-frames of phase charge information have been stored in their respective eight memory nodes, the eight memory nodes can then be sequentially read out after an integration cycle at a reduced readout speed, since there is typically a gap between integration exposure cycles.

[0116] In various embodiments, the first modulation signal TXA and the second modulation signal TXB are configured to modulate the first transfer transistor 520A and the second transfer transistor 520B. In the embodiments, the first modulation signal TXA and the second modulation signal TXB are modulation signals that are 180° out of phase with each other or are inverted versions of each other during the modulation of multiple sub-frames of the time-of-flight ranging pixel circuit 512. For example, in one embodiment, in a first sub-frame, the first modulation signal TXA may be a 0° phase modulation signal 214A, and the second modulation signal TXB is therefore a 180° phase modulation signal 214B. In that embodiment, in another sub-frame, the first modulation signal TXA and the second modulation signal TXB are inverted relative to their respective signals in the first sub-frame. In other words, in that example, in another sub-frame, the first modulation signal TXA is a 180° phase modulation signal 216B, and the second modulation signal TXB is a 0° phase modulation signal 214A. In various examples, it should be understood that the first and second transfer transistors 520A and 520B can also be modulated in multiple sub-frames using 90° / 270° phase modulation signals and the opposite phase of 270° / 90° phase modulation signals.

[0117] According to the teachings of the present invention, by modulating the first transfer transistor 520A and the second transfer transistor 520B in multiple sub-frames with the first modulation signal TXA and the second modulation signal TXB having opposite phases of 0° / 180° and 180° / 0° phase modulation signals and opposite phases of 90° / 270° and 270° / 90° phase modulation signals, offset errors and dark current errors in the time-of-flight ranging pixel circuit are eliminated or removed.

[0118] In various embodiments, according to the teachings of the present invention, the first modulation signal TXA and the second modulation signal TXB can also be modulated at different frequencies in different sub-blocks, which improves systematic errors such as, for example, harmonic distortion or multipath artifacts. For example, in one embodiment, the first modulation signal TXA and the second modulation signal TXB are configured to alternate between two different modulation frequencies f1 and f2 for each sub-block. In other words, in one embodiment, the first modulation signal TXA and the second modulation signal TXB are configured to be modulated at a modulation frequency f1 during a first sub-block, and then modulated at a modulation frequency f2 during a second sub-block. Then, in a third sub-block, the first modulation signal TXA and the second modulation signal TXB are configured to be modulated at a modulation frequency f1, and then, in a fourth sub-block, the first modulation signal TXA and the second modulation signal TXB are configured to be modulated at a modulation frequency f2, and so on.

[0119] FIG6 is a timing diagram 600 illustrating an example of a signal in a time-of-flight ranging sensing system having a pipelined operation according to the teachings of the present invention. It should be understood that the signal illustrated in the timing diagram 600 of FIG6 may be an example of a signal found during the operation of the time-of-flight ranging sensing system 100 illustrated in FIG1, which includes a pixel array of a pixel array containing the time-of-flight ranging pixels 312 illustrated in FIG3, and the similarly named and numbered elements described above are similarly coupled and functioned below.

[0120] In the example depicted in Figure 6, for illustrative purposes, it is assumed that the time-of-flight ranging pixel circuit 312 is configured as a pipelined pixel circuit such that each output tap has two memory nodes (e.g., N=2). It should be understood that the timing diagram 600 of Figure 6 illustrates the instance signals for the occurrence of the instance used to describe the above equations (3) to (24).

[0121] As shown in the illustrated example, at time T0, a laser-enable (Laser-EN) signal 602 is activated, which enables the light source 102. Consequently, the laser low-voltage differential signal (Laser-LVDS) 603 and the first and second modulation signals (TXA / B) 620 are synchronized and oscillate as shown. At time T0, it should be noted that the reset signal 624 and the sample and hold signals SH1 626-1, SH2 626-2 and readout signals RD1 636-1, RD2 636-2 are also activated, which reset or initialize the first and second floating diffusers (FDA, FDB) and memory nodes (C1A, C2A, C1B, C2B) in the time-of-flight ranging pixel circuit 312.

[0122] Between time T1 and T2, integration of sub-block 1 (SF1) occurs, indicated by integration / readout 640. During the integration period occurring in sub-block SF1, reset signal 624 is deactivated and the first modulation signal TXA is modulated with a 0° phase modulation signal, indicated by phase TXA 614A, and the second modulation signal TXB is modulated with a 180° phase modulation signal, indicated by phase TXB 614B. Additionally, it should be noted that the modulation signals are modulated with a first modulation frequency f1, indicated by fmod 638. During the integration time of sub-block SF1, the 0° portion of the charge (e.g., Q0) is sampled and held in a first memory node (e.g., C1A) of a first output tap, and the 180° portion of the charge (e.g., Q180) is sampled and held in a first memory node (e.g., C1B) of a second output tap.

[0123] After the subframe SF1 is integrated between time T1 and T2, the reset signal RST 624 is activated, the first sample and hold signal SH1 626-1 is deactivated, and the second sample and hold signal SH2 626-2 is activated between time T2 and T3. Therefore, the first and second floating diffusers (FDA, FDB) and the second memory nodes (e.g., C2A, C2B) in the time-of-flight ranging pixel circuit 312 are reset. However, the subframe portion of the charge sampled in the first memory nodes (e.g., C1A, C1B) remains, because the first sample and hold signal SH1 626-1 is deactivated.

[0124] Between time T3 and T4, subframe SF2 integration occurs, and one of the previous integration readouts occurs during subframe SF1, indicated by integration / readout 640 between time T3 and T4. Note that during subframe SF2 integration between time T3 and T4, the modulation signal is modulated at a second modulation frequency f2, as indicated by fmod 638. During subframe SF1 readout between time T3 and T4, the first readout signal RD1 is activated, the second readout signal RD2 is deactivated, and column selection signals RSA 632A and RSB 632B are pulsed to read out the VA and VB signals from the first memory nodes (e.g., C1A, C1B) at the two output taps of the time-of-flight ranging pixel circuit 312. Additionally, during the integration of subframe SF2 between time T3 and T4, the first sample-and-hold signal SH1 626-1 is deactivated, while the second sample-and-hold signal SH2 626-2 is activated. During this integration time, the 0° portion of the charge (e.g., Q0) is sampled and held in a second memory node (e.g., C2A) of a first output tap, and the 180° portion of the charge (e.g., Q180) is sampled and held in a second memory node (e.g., C2B) of a second output tap.

[0125] After the subframe SF2 is integrated and the subframe SF1 is read out between time T3 and T4, the reset signal RST 624 is activated, the first sample and hold signal SH1 626-1 is activated, and the second sample and hold signal SH2 626-2 is deactivated between time T4 and T5. Therefore, the first and second floating diffusers (FDA, FDB) and the first memory nodes (e.g., C1A, C1B) in the time-of-flight ranging pixel circuit 312 are reset. However, the subframe portion of the charge sampled in the second memory nodes (e.g., C2A, C2B) remains, because the second sample and hold signal SH2 626-2 is deactivated.

[0126] Between time T5 and T6, subframe SF3 integration occurs and subframe SF2 readout occurs, as indicated by Integration / Readout 640 between time T5 and T6. During the integration period occurring during subframe SF3, the first modulation signal TXA is modulated with a 90° phase modulation signal, as indicated by Phase TXA 614A, and the second modulation signal TXB is modulated with a 270° phase modulation signal, as indicated by Phase TXB 614B. Additionally, it should be noted that during the integration period of subframe SF3 occurring between time T5 and T6, the modulation signal is modulated with a first modulation frequency f1, as indicated by fmod 638. During the SF3 integration time, the 90° portion of the charge (e.g., Q90) is sampled and held in a first memory node (e.g., C1A) at a first output tap, and the 270° portion of the charge (e.g., Q270) is sampled and held in a first memory node (e.g., C1B) at a second output tap. During the sub-frame SF2 readout that occurs between time T5 and T6, the first readout signal RD1 is deactivated, the second readout signal RD2 is activated, and the column selection signals RSA 632A and RSB 632B are pulsed to read out the VA and VB signals from the second memory nodes (e.g., C2A and C2B) at the two output taps of the time-of-flight ranging pixel circuit 312.

[0127] After the integration of subframe SF3 and the readout of subframe SF2 between times T5 and T6, the reset signal RST 624 is activated, the first sample and hold signal SH1 626-1 is deactivated, and the second sample and hold signal SH2 626-2 is activated between times T6 and T7. Therefore, the first and second floating diffusers (FDA, FDB) and the second memory nodes (e.g., C2A, C2B) in the time-of-flight ranging pixel circuit 312 are reset. However, the subframe portion of the charge sampled in the first memory nodes (e.g., C1A, C1B) remains, because the first sample and hold signal SH1 626-1 is deactivated.

[0128] Between time T7 and T8, subframe SF4 integration and subframe SF3 readout occur, as indicated by Integration / Readout 640 between time T7 and T8. Note that during the subframe SF4 integration between time T7 and T8, the modulation signal is modulated at the second modulation frequency f2, as indicated by fmod 638. During the subframe SF3 readout between time T7 and T8, the first readout signal RD1 is activated, the second readout signal RD2 is deactivated, and the column selection signals RSA 632A and RSB 632B are pulsed to read out the VA and VB signals from the first memory nodes (e.g., C1A, C1B) at the two output taps of the self-flying ranging pixel circuit 312. Additionally, during the integration of subframe SF4 between times T7 and T8, the first sample-and-hold signal SH1 626-1 is deactivated, while the second sample-and-hold signal SH2 626-2 is activated. During this integration time, the 90° portion of the charge (e.g., Q90) is sampled and held in a second memory node (e.g., C2A) of a first output tap, and the 270° portion of the charge (e.g., Q270) is sampled and held in a second memory node (e.g., C2B) of a second output tap.

[0129] After the subframe SF4 integration and subframe SF3 readout between time T7 and T8, the reset signal RST 624 is activated, the first sample and hold signal SH1 626-1 is activated, and the second sample and hold signal SH2 626-2 is deactivated between time T8 and T9. Therefore, the first and second floating diffusers (FDA, FDB) and the first memory nodes (e.g., C1A, C1B) in the time-of-flight ranging pixel circuit 312 are reset. However, the subframe portion of the charge sampled in the second memory nodes (e.g., C2A, C2B) remains, because the second sample and hold signal SH2 626-2 is deactivated.

[0130] Between time T9 and T10, subframe SF5 integration occurs and subframe SF4 readout occurs, as indicated by Integration / Readout between time T9 and T10 640. During the integration period occurring during subframe SF5, the first modulation signal TXA is modulated with a 180° phase modulation signal, as indicated by Phase TXA 614A, and the second modulation signal TXB is modulated with a 0° phase modulation signal, as indicated by Phase TXB 614B. Additionally, it should be noted that during the integration period of subframe SF5 occurring between time T9 and T10, the modulation signal is modulated with a first modulation frequency f1, as indicated by fmod 638. During the SF5 integration time, the 180° portion of the charge (e.g., Q180) is sampled and held in a first memory node (e.g., C1A) at a first output tap, and the 0° portion of the charge (e.g., Q0) is sampled and held in a first memory node (e.g., C1B) at a second output tap. During the sub-frame SF4 readout that occurs between time T9 and T10, the first readout signal RD1 is deactivated, the second readout signal RD2 is activated, and the column selection signals RSA 632A and RSB 632B are pulsed to read out the VA and VB signals from the second memory nodes (e.g., C2A and C2B) at the two output taps of the time-of-flight ranging pixel circuit 312.

[0131] After the subframe SF5 is integrated and the subframe SF4 is read out between times T9 and T10, the reset signal RST 624 is activated, the first sample and hold signal SH1 626-1 is deactivated, and the second sample and hold signal SH2 626-2 is activated between times T10 and T11. Therefore, the first and second floating diffusers (FDA, FDB) and the second memory nodes (e.g., C2A, C2B) in the time-of-flight ranging pixel circuit 312 are reset. However, the subframe portion of the charge sampled in the first memory nodes (e.g., C1A, C1B) remains, because the first sample and hold signal SH1 626-1 is deactivated.

[0132] Between time T11 and T12, subframe SF6 integration and SF5 readout occur, as indicated by integration / readout 640 between time T11 and T12. Note that during the subframe SF6 integration between time T11 and T12, the modulation signal is modulated at the second modulation frequency f2, as indicated by fmod 638. During the subframe SF5 readout between time T11 and T12, the first readout signal RD1 is activated, the second readout signal RD2 is deactivated, and the column selection signals RSA 632A and RSB 632B are pulsed to read out the VA and VB signals from the first memory nodes (e.g., C1A, C1B) at the two output taps of the self-flying ranging pixel circuit 312. Additionally, during the integration of subframe SF6 between times T11 and T12, the first sample-and-hold signal SH1 626-1 is deactivated, while the second sample-and-hold signal SH2 626-2 is activated. During this integration time, the 180° portion of the charge (e.g., Q180) is sampled and held in a second memory node (e.g., C2A) of a first output tap, and the 0° portion of the charge (e.g., Q0) is sampled and held in a second memory node (e.g., C2B) of a second output tap.

[0133] After the subframe SF6 is integrated and the subframe SF5 is read out between times T11 and T12, the reset signal RST 624 is activated, the first sample and hold signal SH1 626-1 is activated, and the second sample and hold signal SH2 626-2 is deactivated between times T12 and T13. Therefore, the first and second floating diffusers (FDA, FDB) and the first memory nodes (e.g., C1A, C1B) in the time-of-flight ranging pixel circuit 312 are reset. However, the subframe portion of the charge sampled in the second memory nodes (e.g., C2A, C2B) remains, because the second sample and hold signal SH2 626-2 is deactivated.

[0134] Between times T13 and T14, subframe SF7 integration occurs and subframe SF6 readout occurs, as indicated by Integration / Readout 640 between times T13 and T14. During the integration period occurring during subframe SF7, the first modulation signal TXA is modulated with a 270° phase modulation signal, as indicated by Phase TXA 614A, and the second modulation signal TXB is modulated with a 90° phase modulation signal, as indicated by Phase TXB 614B. Additionally, it should be noted that during the integration period of subframe SF7 occurring between times T13 and T14, the modulation signal is modulated with a first modulation frequency f1, as indicated by fmod 638. During the SF7 integration time, the 270° portion of the charge (e.g., Q270) is sampled and held in a first memory node (e.g., C1A) at a first output tap, and the 90° portion of the charge (e.g., Q90) is sampled and held in a first memory node (e.g., C1B) at a second output tap. During the sub-frame SF6 readout that occurs between times T13 and T14, the first readout signal RD1 is deactivated, the second readout signal RD2 is activated, and the column selection signals RSA 632A and RSB 632B are pulsed to read out the VA and VB signals from the second memory nodes (e.g., C2A and C2B) at the two output taps of the time-of-flight ranging pixel circuit 312.

[0135] After the subframe SF7 is integrated and the subframe SF6 is read out between times T13 and T14, the reset signal RST 624 is activated, the first sample and hold signal SH1 626-1 is deactivated, and the second sample and hold signal SH2 626-2 is activated between times T14 and T15. Therefore, the first and second floating diffusers (FDA, FDB) and the second memory nodes (e.g., C2A, C2B) in the time-of-flight ranging pixel circuit 312 are reset. However, the subframe portion of the charge sampled in the first memory nodes (e.g., C1A, C1B) remains, because the first sample and hold signal SH1 626-1 is deactivated.

[0136] Between time T15 and T16, subframe SF8 integration and SF7 readout occur, as indicated by integration / readout 640 between time T15 and T16. Note that during the subframe SF8 integration between time T15 and T16, the modulation signal is modulated at the second modulation frequency f2, as indicated by fmod 638. During the subframe SF7 readout between time T15 and T16, the first readout signal RD1 is activated, the second readout signal RD2 is deactivated, and the column selection signals RSA 632A and RSB 632B are pulsed to read out the VA and VB signals from the first memory nodes (e.g., C1A, C1B) at the two output taps of the self-flying ranging pixel circuit 312. Additionally, during the integration of subframe SF8 between times T15 and T16, the first sample-and-hold signal SH1 626-1 is deactivated, while the second sample-and-hold signal SH2 626-2 is activated. During this integration time, the 270° portion of the charge (e.g., Q270) is sampled and held in a second memory node (e.g., C2A) of a first output tap, and the 90° portion of the charge (e.g., Q90) is sampled and held in a second memory node (e.g., C2B) of a second output tap.

[0137] After the subframe SF8 integration and subframe SF7 readout between times T15 and T16, the reset signal RST 624 is activated, the first sample and hold signal SH1 626-1 is activated, and the second sample and hold signal SH2 626-2 is deactivated between times T16 and T17. Therefore, the first and second floating diffusers (FDA, FDB) and the first memory nodes (e.g., C1A, C1B) in the time-of-flight ranging pixel circuit 312 are reset. However, the subframe portion of the charge sampled in the second memory nodes (e.g., C2A, C2B) remains, because the second sample and hold signal SH2 626-2 is deactivated.

[0138] Between time T17 and T18, no integration occurs and sub-frame SF8 readout occurs, as indicated by integration / readout 640 between time T17 and T18. During the sub-frame SF8 readout that occurs between time T17 and T18, the first readout signal RD1 is deactivated, the second readout signal RD2 is activated, and the column selection signals RSA 632A and RSB 632B are pulsed to read out the VA and VB signals from the second memory nodes (e.g., C2A, C2B) at the two output taps of the self-flying ranging pixel circuit 312.

[0139] FIG7 is a timing diagram 700 illustrating another example of a signal in a time-of-flight ranging sensing system having a cluster operation according to the teachings of the present invention. It should be understood that the signal illustrated in the timing diagram 700 of FIG7 may be an example of a signal found during the operation of the time-of-flight ranging sensing system 100 illustrated in FIG1, which includes a pixel array of one pixel array of time-of-flight ranging pixels 512 illustrated in FIG5, and the similarly named and numbered elements described above are similarly coupled and functioned below.

[0140] In the example depicted in Figure 7, for illustrative purposes, it is assumed that the time-of-flight ranging pixel circuit 512 is configured as a cluster pixel circuit such that each output tap has eight memory nodes (e.g., N=8). It should be understood that the timing diagram 700 of Figure 7 also illustrates the instance signals for the occurrence of instances used to describe the above equations (3) to (24).

[0141] As shown in the illustrated example, at time T0, a laser-enable (Laser-EN) signal 702 is activated, which enables the light source 102. Consequently, the laser low-voltage differential signal (Laser-LVDS) 703 and the first and second modulation signals (TXA / B) 720 are synchronized and oscillate as shown. At time T0, note that the overflow signal OF 724, the sample and hold signals SH1 726-1 to SH8 726-8, the readout signals RD1 636-1 to RD8 636-8, and the reset signal RST 750 reset or initialize the first and second floating diffusers (FDA, FDB) and memory nodes (C1A to C8A and C1B to C8B) in the time-of-flight ranging pixel circuit 512.

[0142] As will be shown in Figure 7, an integration period occurs between time T1 and time T16, and the TXA and TXB portions of the charge from photodiode 518 respond to the charge in their respective floating diffusers (e.g., 522A / 522B) through their respective sampling and holding transistors (e.g., 526A1 / 526B1, 526A2 / 526B2, 526A3 / 526B3, 526A4 / 526B4, 526A5 / 526B5, 526A6 / 526B6, 526A7). The transistors (526B7, 526A8, 526B8) are sampled and stored sequentially (e.g., one after another in time) from the first and second amplification source follower transistors (e.g., 544A / 544B) into their respective memory nodes (e.g., 534A1 / 534B1, 534A2 / 534B2, 534A3 / 534B3, 534A4 / 534B4, 534A5 / 534B5, 534A6 / 534B6, 534A7 / 534B7, 534A8 / 534B8).

[0143] Specifically, at time T1, the integration period begins as the overflow signal OF 724, sample and hold signals SH2 726-2 to SH8 726-8, readout signals RD1 736-1 to RD8 736-8, and reset signal RST 750 are all deactivated. Between time T1 and T2, sub-block 1 (SF1) integration occurs, indicated by integration 740, and the sample and hold signal SH1 726-1 remains active. During the integration period occurring in sub-block SF1, the first modulation signal TXA is modulated with a 0° phase modulation signal, indicated by phase TXA 714A, and the second modulation signal TXB is modulated with a 180° phase modulation signal, indicated by phase TXB 714B. It should also be noted that the modulation signals are modulated at a first modulation frequency f1, indicated by fmod 738. During the integration time of this subframe SF1, the 0° portion of the charge (e.g., Q0) is sampled and held in a first memory node (e.g., C1A) of a first output tap, and the 180° portion of the charge (e.g., Q180) is sampled and held in a first memory node (e.g., C1B) of a second output tap.

[0144] After the subframe SF1 is integrated between time T1 and T2, the overflow signal OF 724 can be activated, the first sample and hold signal SH1 726-1 is deactivated, and the second sample and hold signal SH2 726-2 is activated between time T2 and T3. Therefore, the first and second floating diffusers (FDA, FDB) and the second memory nodes (e.g., C2A, C2B) in the time-of-flight ranging pixel circuit 512 are reset. However, the subframe portion of the charge sampled in the first memory nodes (e.g., C1A, C1B) remains because the first sample and hold signal SH1 726-1 is deactivated.

[0145] Between time T3 and T4, subframe SF2 integration occurs, indicated by integration between time T3 and T4 740. It should be noted that during subframe SF2 integration between time T3 and T4, the modulation signal is modulated at a second modulation frequency f2, as indicated by fmod 738. During subframe SF2 integration between time T3 and T4, the second sample and hold signal SH2 726-2 is activated and the overflow signal OF 724 is deactivated. During this integration time, the 0° portion of the charge (e.g., Q0) is sampled and held in a second memory node (e.g., C2A) of a first output tap, and the 180° portion of the charge (e.g., Q180) is sampled and held in a second memory node (e.g., C2B) of a second output tap.

[0146] After the subframe SF2 is integrated between time T3 and T4, the overflow signal OF 724 can be activated, the second sample and hold signal SH2 726-2 is deactivated, and the third sample and hold signal SH3 726-3 is activated between time T4 and T5. Therefore, the first and second floating diffusers (FDA, FDB) and the third memory node (e.g., C3A, C3B) in the time-of-flight ranging pixel circuit 512 are reset. However, the subframe portion of the charge sampled in the first and second memory nodes (e.g., C1A / C1B, C2A / C2B) remains because the first and second sample and hold signals SH1 726-1 and SH2 726-2 are deactivated.

[0147] Between time T5 and T6, subframe SF3 integration occurs, indicated by integration 740 between time T5 and T6. It should be noted that during subframe SF3 integration between time T5 and T6, the modulation signal is modulated at a first modulation frequency f1, as indicated by fmod 738. During subframe SF3 integration between time T5 and T6, the third sample and hold signal SH3 726-3 is activated and the overflow signal OF 724 is deactivated. During this integration time, a 90° portion of the charge (e.g., Q90) is sampled and held in a third memory node (e.g., C3A) of a first output tap, and a 270° portion of the charge (e.g., Q270) is sampled and held in a third memory node (e.g., C3B) of a second output tap.

[0148] After the subframe SF3 is integrated between time T5 and T6, the overflow signal OF 724 can be activated, the third sample and hold signal SH3 726-3 is deactivated, and the fourth sample and hold signal SH4 726-4 is activated between time T6 and T7. Therefore, the first and second floating diffusers (FDA, FDB) and the fourth memory node (e.g., C4A, C4B) in the time-of-flight ranging pixel circuit 512 are reset. However, the subframe portion of the charge sampled in the first to third memory nodes (e.g., C1A / C1B to C3A / C3B) remains intact because the first to third sample and hold signals SH1 726-1 to SH3 726-3 are deactivated.

[0149] Between time T7 and T8, subframe SF4 integration occurs, indicated by integration 740 between time T7 and T8. It should be noted that during subframe SF4 integration between time T7 and T8, the modulation signal is modulated at a second modulation frequency f2, as indicated by fmod 738. During subframe SF4 integration between time T7 and T8, the fourth sample and hold signal SH4 726-4 is activated and the overflow signal OF 724 is deactivated. During this integration time, the 90° portion of the charge (e.g., Q90) is sampled and held in a fourth memory node (e.g., C4A) of a first output tap, and the 270° portion of the charge (e.g., Q270) is sampled and held in a fourth memory node (e.g., C4B) of a second output tap.

[0150] After the subframe SF4 is integrated between time T7 and T8, the overflow signal OF 724 can be activated, the fourth sample and hold signal SH4 726-4 is deactivated, and the fifth sample and hold signal SH5 726-5 is activated between time T8 and T9. Therefore, the first and second floating diffusers (FDA, FDB) and the fifth memory node (e.g., C5A, C5B) in the time-of-flight ranging pixel circuit 512 are reset. However, the subframe portion of the charge sampled in the first to fourth memory nodes (e.g., C1A / C1B to C4A / C4B) remains intact because the first to fourth sample and hold signals SH1 726-1 to SH4 726-4 are deactivated.

[0151] Between time T9 and T10, subframe SF5 integration occurs, indicated by integration 740 between time T9 and T10. It should be noted that during subframe SF5 integration between time T9 and T10, the modulation signal is modulated at a first modulation frequency f1, indicated by fmod 738. During subframe SF5 integration between time T9 and T10, the fifth sample and hold signal SH5 726-5 is activated and the overflow signal OF 724 is deactivated. During this integration time, the 180° portion of the charge (e.g., Q180) is sampled and held in the fifth memory node (e.g., C5A) of the first output tap, and the 0° portion of the charge (e.g., Q0) is sampled and held in the fifth memory node (e.g., C5B) of a second output tap.

[0152] After the subframe SF5 is integrated between time T9 and T10, the overflow signal OF 724 can be activated, the fifth sample and hold signal SH5 726-5 is deactivated, and the sixth sample and hold signal SH6 726-6 is activated between time T10 and T11. Therefore, the first and second floating diffusers (FDA, FDB) and the sixth memory node (e.g., C6A, C6B) in the time-of-flight ranging pixel circuit 512 are reset. However, the subframe portion of the charge sampled in the first to fifth memory nodes (e.g., C1A / C1B to C5A / C5B) remains, because the first to fifth sample and hold signals SH1 726-1 to SH5 726-5 are deactivated.

[0153] Between time T11 and T12, subframe SF6 integration occurs, indicated by integration 740 between time T11 and T12. It should be noted that during subframe SF6 integration between time T11 and T12, the modulation signal is modulated at a second modulation frequency f2, indicated by fmod 738. During subframe SF6 integration between time T11 and T12, the sixth sample and hold signal SH6 726-6 is activated and the overflow signal OF 724 is deactivated. During this integration time, the 180° portion of the charge (e.g., Q180) is sampled and held in a sixth memory node (e.g., C6A) of a first output tap, and the 0° portion of the charge (e.g., Q0) is sampled and held in a sixth memory node (e.g., C6B) of a second output tap.

[0154] After the subframe SF6 is integrated between time T11 and T12, the overflow signal OF 724 can be activated, the sixth sample and hold signal SH6 726-6 is deactivated, and the seventh sample and hold signal SH7 726-7 is activated between time T12 and T13. Therefore, the first and second floating diffusers (FDA, FDB) and the seventh memory node (e.g., C7A, C7B) in the time-of-flight ranging pixel circuit 512 are reset. However, the subframe portion of the charge sampled in the first to sixth memory nodes (e.g., C1A / C1B to C6A / C6B) remains intact because the first to sixth sample and hold signals SH1 726-1 to SH6 726-6 are deactivated.

[0155] Between time T13 and T14, subframe SF7 integration occurs, indicated by integration 740 between time T13 and T14. It should be noted that during subframe SF7 integration between time T13 and T14, the modulation signal is modulated at a first modulation frequency f1, as indicated by fmod 738. During subframe SF7 integration between time T13 and T14, the seventh sample and hold signal SH7 726-7 is activated and the overflow signal OF 724 is deactivated. During this integration time, the 270° portion of the charge (e.g., Q270) is sampled and held in a seventh memory node (e.g., C7A) of a first output tap, and the 90° portion of the charge (e.g., Q90) is sampled and held in a seventh memory node (e.g., C7B) of a second output tap.

[0156] After the subframe SF7 is integrated between time T13 and T14, the overflow signal OF 724 can be activated, the seventh sample and hold signal SH7 726-7 is deactivated, and the eighth sample and hold signal SH8 726-8 is activated between time T14 and T15. Therefore, the first and second floating diffusers (FDA, FDB) and the eighth memory node (e.g., C8A, C8B) in the time-of-flight ranging pixel circuit 512 are reset. However, the subframe portion of the charge sampled in the first to seventh memory nodes (e.g., C1A / C1B to C7A / C7B) remains, because the first to sixth sample and hold signals SH1 726-1 to SH6 726-6 are deactivated.

[0157] Between time T15 and T16, subframe SF8 integration occurs, indicated by integration 740 between time T15 and T16. It should be noted that during subframe SF8 integration between time T15 and T16, the modulation signal is modulated at a second modulation frequency f2, indicated by fmod 738. During subframe SF8 integration between time T15 and T16, the eighth sample and hold signal SH8 726-8 is activated and the overflow signal OF 724 is deactivated. During this integration time, the 270° portion of the charge (e.g., Q270) is sampled and held in one of the eighth memory nodes (e.g., C8A) of a first output tap, and the 90° portion of the charge (e.g., Q90) is sampled and held in one of the eighth memory nodes (e.g., C8B) of a second output tap.

[0158] As shown in the illustrated example, after the integration cycle occurring between time T1 and time T16, all memory nodes C1A to C8A and C1B to C8B are sequentially sampled and held for their respective sub-frame portions of the charge, as discussed above. Therefore, the overflow signal OF 724 is activated after time T16. As will be shown, the respective sub-frame portions of the charge are then read sequentially (e.g., one after another in time) via their respective readout transistors during a readout cycle occurring between time T17 and T33. Therefore, the column select signal RS 732 is activated between time T17 and T33.

[0159] At time T17, the reset signal RST 750 is activated, which resets or precharges the other gate of the source follower 530A / 530B. At time T18, the reset signal RST 750 is deactivated and the first read signal RD1 736-1 is activated, which enables the sampled and held SF1 portion in the first memory node (e.g., C1A / C1B) to be read through the source follower 530A / 530B.

[0160] At time T19, the first read signal RD1 736-1 is deactivated and the reset signal RST 750 is activated, which resets or precharges the other gate of the source follower 530A / 530B. At time T20, the reset signal RST 750 is deactivated and the second read signal RD2 736-2 is activated, which enables the SF2 portion sampled and held in the second memory node (e.g., C2A / C2B) to be read through the source follower 530A / 530B.

[0161] At time T21, the second read signal RD2 736-2 is deactivated and the reset signal RST 750 is activated, which resets or precharges the other gate of the source follower 530A / 530B. At time T22, the reset signal RST 750 is deactivated and the third read signal RD3 736-3 is activated, which enables ground to read the sampled and held portion of SF3 in the third memory node (e.g., C3A / C3B) via the source follower 530A / 530B.

[0162] At time T23, the third read signal RD3 736-3 is deactivated and the reset signal RST 750 is activated, which resets or precharges the other gate of the source follower 530A / 530B. At time T24, the reset signal RST 750 is deactivated and the fourth read signal RD4 736-4 is activated, which enables the SF4 portion sampled and held in the fourth memory node (e.g., C4A / C4B) to be read through the source follower 530A / 530B.

[0163] At time T25, the fourth read signal RD4 736-4 is deactivated and the reset signal RST 750 is activated, which resets or precharges the other gate of the source follower 530A / 530B. At time T26, the reset signal RST 750 is deactivated and the fifth read signal RD5 736-5 is activated, which enables the sampled and held SF5 portion in the fifth memory node (e.g., C5A / C5B) to be read through the source follower 530A / 530B.

[0164] At time T27, the fifth read signal RD5 736-5 is deactivated and the reset signal RST 750 is activated, which resets or precharges the other gate of the source follower 530A / 530B. At time T28, the reset signal RST 750 is deactivated and the sixth read signal RD6 736-6 is activated, which enables the sampled and held SF6 portion in the sixth memory node (e.g., C6A / C6B) to be read through the source follower 530A / 530B.

[0165] At time T29, the sixth read signal RD6 736-6 is deactivated and the reset signal RST 750 is activated, which resets or precharges the other gate of the source follower 530A / 530B. At time T30, the reset signal RST 750 is deactivated and the seventh read signal RD7 736-7 is activated, which enables the sampled and held SF7 portion in the seventh memory node (e.g., C7A / C7B) to be read through the source follower 530A / 530B.

[0166] At time T31, the seventh read signal RD7 736-7 is deactivated and the reset signal RST 750 is activated, which resets or precharges the other gate of the source follower 530A / 530B. At time T32, the reset signal RST 750 is deactivated and the eighth read signal RD8 736-8 is activated, which enables the sampled and held SF8 portion in the eighth memory node (e.g., C8A / C8B) to be read through the source follower 530A / 530B.

[0167] As shown in the example depicted, after the readout cycle that occurs between time T17 and time T22, the sub-frame portions of the charge sampled and held in all memory nodes C1A to C8A and C1B to C8B are now read out sequentially as described above.

[0168] Therefore, the overflow signal OF 724, the sampling and holding signals SH1 726-1 to SH8 726-8, the readout signals RD1 636-1 to RD8 636-8 and the reset signal RST 750 can all be restarted after time T34 to reset or reinitialize the first and second floating diffusers (FDA, FDB) and memory nodes (C1A to C8A and C1B to C8B) in the time-of-flight ranging pixel circuit 512.

[0169] The above description of the examples illustrated in this invention includes the content described in the abstract of the invention, and is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Although specific examples of the invention have been described herein for illustrative purposes, those skilled in the art will recognize that various modifications are possible within the scope of this invention.

[0170] In view of the detailed description above, such modifications may be made to examples of the present invention. The terminology used in the appended claims should not be construed as limiting the invention to the specific examples disclosed in the specification. Rather, the scope of the invention shall be determined entirely by the appended claims, which shall be interpreted in accordance with the established principles for interpreting claims. [Simplified Explanation of the Diagram]

[0004] Non-limiting and non-exhaustive embodiments of the invention are described with reference to the accompanying drawings, wherein similar reference numerals refer to similar parts throughout the various views unless otherwise specified.

[0005] Figure 1 is a block diagram illustrating one example of a time-of-flight ranging optical sensing system according to the teachings of the present invention.

[0006] Figure 2 is a timing diagram illustrating an example of a time-of-flight ranging sensing system according to an embodiment of the teachings of the present invention, showing the reception of a light pulse emitted from a light source relative to a reflected light pulse and an example of measurement using various phase shifts.

[0007] Figure 3 is a schematic diagram illustrating one example of a time-of-flight ranging pixel circuit according to the teachings of the present invention.

[0008] Figure 4 is a schematic diagram illustrating another example of a time-of-flight ranging pixel circuit according to the teachings of the present invention.

[0009] Figure 5 is a schematic diagram illustrating yet another example of a time-of-flight ranging pixel circuit according to the teachings of the present invention.

[0010] Figure 6 is a timing diagram illustrating an example of a signal in a time-of-flight ranging sensing system having a pipeline operation according to the teachings of the present invention.

[0011] Figure 7 is a timing diagram illustrating another example of a signal in a time-of-flight ranging sensing system having a cluster operation according to the teachings of the present invention.

[0012] Throughout the various views, corresponding reference numerals indicate the corresponding components. Those skilled in the art will understand that the elements in the figures are drawn for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to aid in understanding the various embodiments of the invention. Furthermore, common but easily understood elements that are useful or necessary in a commercially viable embodiment are generally not depicted to facilitate a more intuitive understanding of these various embodiments of the invention.

Claims

1. A time-of-flight ranging pixel circuit, comprising: A photodiode configured to generate charge in response to modulated light emitted from a light source and reflected from an object; A first transfer transistor coupled to the photodiode; a second transfer transistor coupled to the photodiode, wherein the first transfer transistor is configured to transfer a first portion of the charge from the photodiode in response to a first modulation signal, wherein the second transfer transistor is configured to transfer a second portion of the charge from the photodiode in response to a second modulation signal, wherein the second modulation signal is an inverted first modulation signal; a first floating diffuser coupled to the first transfer transistor to receive the first portion of the charge in response to the first modulation signal; a first plurality of memory nodes; and a first plurality of sample-and-hold transistors, wherein each of the first plurality of sample-and-hold transistors is coupled between one of the first plurality of memory nodes and the first transfer transistor.

2. The time-of-flight ranging pixel circuit of claim 1, further comprising: A first output source follower transistor; A first plurality of readout transistors, wherein each of the first plurality of readout transistors is coupled between its respective memory node and a gate of the first output source follower transistor; and a first column select transistor coupled to the first output source follower transistor.

3. The time-of-flight ranging pixel circuit of claim 2, wherein a first of the first plurality of memory nodes is coupled to the first floating diffuser via a first of the first plurality of sample and hold transistors during a first subframe, wherein a second of the first plurality of memory nodes is coupled to the first floating diffuser via a second of the first plurality of sample and hold transistors during a second subframe, wherein the first of the first plurality of memory nodes is coupled to the gate of the first output source follower transistor via a first of the first plurality of readout transistors during the second subframe.

4. The time-of-flight ranging pixel circuit of claim 3, wherein the second of the first plurality of memory nodes is coupled to the gate of the first output source follower transistor via one of the second of the first plurality of readout transistors during a third subframe, wherein the first of the first plurality of memory nodes is coupled to the first floating diffuser via one of the first plurality of sample and hold transistors during the third subframe.

5. The time-of-flight ranging pixel circuit of claim 4, wherein the first modulation signal and the second modulation signal are configured to be modulated at a first modulation frequency during the first sub-frame and the third sub-frame, wherein the first modulation signal and the second modulation signal are further configured to be modulated at a second modulation frequency during the second sub-frame and a fourth sub-frame.

6. The time-of-flight ranging pixel circuit of claim 5, wherein the first modulation signal is configured to be in phase with the modulated light emitted from the light source during the first sub-frame and the second sub-frame, wherein the first modulation signal is further configured to be 90 degrees out of phase with the modulated light emitted from the light source during the third sub-frame and the fourth sub-frame.

7. The time-of-flight ranging pixel circuit of claim 6, wherein the first modulation signal is further configured to be 180 degrees out of phase with the modulated light emitted from the light source during a fifth sub-frame and a sixth sub-frame, wherein the first modulation signal is further configured to be 270 degrees out of phase with the modulated light emitted from the light source during a seventh sub-frame and an eighth sub-frame, wherein the first modulation signal and the second modulation signal are further configured to be modulated at the first modulation frequency during the fifth sub-frame and the seventh sub-frame, wherein the first modulation signal and the second modulation signal are further configured to be modulated at the second modulation frequency during the sixth sub-frame and the eighth sub-frame.

8. The time-of-flight ranging pixel circuit of claim 7, further comprising a first reset transistor coupled between a power rail and the first floating diffuser, wherein the first reset transistor is configured to reset the first floating diffuser.

9. The time-of-flight ranging pixel circuit of claim 8, wherein the first reset transistor is coupled to receive an overflow signal.

10. The time-of-flight ranging pixel circuit of claim 9 further includes a first output reset transistor coupled between the power rail and the gate of the first output source follower transistor.

11. The time-of-flight ranging pixel circuit of claim 9, further comprising: A first floating diffusion capacitor is coupled to the first floating diffusion section; and a first amplification stage coupled between the first floating diffuser and the first plurality of sampling and holding transistors.

12. The time-of-flight ranging pixel circuit of claim 11, wherein the first amplification stage includes: A first amplification source follower transistor having a gate coupled to the first floating diffusion section and a source coupled to the first plurality of sampling and holding transistors; a first enable transistor; and a first bias transistor coupled to the first enable transistor, wherein the first enable transistor and the first bias transistor are coupled between the source of the first amplification source follower transistor and ground.

13. The time-of-flight ranging pixel circuit of claim 8, further comprising: A second floating diffusion section coupled to the second transfer transistor to receive the second portion of the charge in response to the second modulation signal; A second plurality of memory nodes; and a second plurality of sample and hold transistors, wherein each of the second plurality of sample and hold transistors is coupled between one of the second plurality of memory nodes and the second transfer transistor.

14. The time-of-flight ranging pixel circuit of claim 13, further comprising: A second output source follower transistor; A second plurality of readout transistors, wherein each of the second plurality of readout transistors is coupled between its respective memory node and a gate of the second output source follower transistor; and a second column select transistor coupled to the second output source follower transistor.

15. The time-of-flight ranging pixel circuit of claim 14, wherein a first of one of the second plurality of memory nodes is coupled to the second floating diffuser via a first of one of the second plurality of sample and hold transistors during the first subframe, wherein a second of one of the second plurality of memory nodes is coupled to the second floating diffuser via a second of one of the second plurality of sample and hold transistors during the second subframe, wherein the first of the second plurality of memory nodes is coupled to the gate of the second output source follower transistor via a second of one of the first plurality of readout transistors during the second subframe.

16. The time-of-flight ranging pixel circuit of claim 15, wherein the second of the second plurality of memory nodes is coupled to the gate of the second output source follower transistor via one of the second plurality of readout transistors during the third subframe, wherein the first of the second plurality of memory nodes is coupled to the second floating diffuser via one of the second plurality of sample and hold transistors during the third subframe.

17. The time-of-flight ranging pixel circuit of claim 16, further comprising a second reset transistor coupled between the power rail and the second floating diffuser, wherein the second reset transistor is configured to reset the second floating diffuser.

18. The time-of-flight ranging pixel circuit of claim 17, wherein the second reset transistor is coupled to receive an overflow signal.

19. The time-of-flight ranging pixel circuit of claim 18, further comprising a second output reset transistor coupled between the power rail and the gate of the second output source follower transistor.

20. The time-of-flight ranging pixel circuit of claim 18, further comprising: A second floating diffusion capacitor is coupled to the second floating diffusion section; And a second amplification stage coupled between the second floating diffusion section and the second plurality of sampling and holding transistors.

21. The time-of-flight ranging pixel circuit of claim 20, wherein the second amplification stage includes: A second amplification source follower transistor having a gate coupled to the second floating diffusion section and a source coupled to the second plurality of sampling and holding transistors; a second enable transistor; and a second bias transistor coupled to the second enable transistor, wherein the second enable transistor and the second bias transistor are coupled between the source of the second amplification source follower transistor and ground.

22. The time-of-flight ranging pixel circuit of claim 2, wherein each of the first plurality of memory nodes is coupled to sample and hold one of the plurality of sub-frame portions of the first portion of charge from the first floating diffuser via one of the first plurality of sampling and holding transistors, wherein each of the plurality of sub-frame portions of the first portion of charge is coupled to be read from the respective of the first plurality of memory nodes via one of the first plurality of readout transistors after all the first plurality of memory nodes have sampled and held the plurality of sub-frame portions of the first portion of charge from the first floating diffuser.

23. The time-of-flight ranging pixel circuit of claim 22, wherein the first modulation signal is configured to be a first phase modulation signal during the period of a first sub-frame and a second sub-frame, wherein the first modulation signal is further configured to be a third phase modulation signal during the period of a third sub-frame and a fourth sub-frame, wherein the first modulation signal is further configured to be a second phase modulation signal during the period of a fifth sub-frame and a sixth sub-frame, and wherein the first modulation signal is further configured to be a fourth phase modulation signal during the period of a seventh sub-frame and an eighth sub-frame.

24. The time-of-flight ranging pixel circuit of claim 23, wherein the first modulation signal is configured to be modulated at a first modulation frequency during the first, third, fifth and seventh periods of the plurality of sub-frames, wherein the first modulation signal is configured to be modulated at a second modulation frequency during the second, fourth, sixth and eighth periods of the plurality of sub-frames.

25. The time-of-flight ranging pixel circuit of claim 24, further comprising: A second floating diffusion section coupled to the second transfer transistor to receive the second portion of the charge in response to the second modulation signal; A second plurality of memory nodes; and a second plurality of sample and hold transistors, wherein each of the second plurality of sample and hold transistors is coupled between one of the second plurality of memory nodes and the second transfer transistor.

26. The time-of-flight ranging pixel circuit of claim 25, further comprising: A second output source follower transistor; A second plurality of readout transistors, wherein each of the second plurality of readout transistors is coupled between its respective memory node and a gate of the second output source follower transistor; and a second column select transistor coupled to the second output source follower transistor.

27. The time-of-flight ranging pixel circuit of claim 26, wherein each of the second plurality of memory nodes is coupled to sample and hold one of the plurality of sub-frame portions of the second portion of charge from the second floating diffuser via one of the second plurality of sampling and holding transistors, wherein each of the plurality of sub-frame portions of the second portion of charge is coupled to be read from the respective of the second plurality of memory nodes via one of the second plurality of readout transistors after all the second plurality of memory nodes have sampled and held the plurality of sub-frame portions of the second portion of charge from the second floating diffuser.

28. The time-of-flight ranging pixel circuit of claim 27, wherein the second modulation signal is configured to be the second phase modulation signal during the first and second periods of the plurality of sub-frames, wherein the second modulation signal is further configured to be the fourth phase modulation signal during the third and fourth periods of the plurality of sub-frames, wherein the second modulation signal is further configured to be the first phase modulation signal during the fifth and sixth periods of the plurality of sub-frames, and wherein the second modulation signal is further configured to be the third phase modulation signal during the seventh and eighth periods of the plurality of sub-frames.

29. The time-of-flight ranging pixel circuit of claim 28, wherein the second modulation signal is configured to be modulated at the first modulation frequency during the first, third, fifth and seventh periods of the plurality of sub-frames, wherein the second modulation signal is configured to be modulated at the second modulation frequency during the second, fourth, sixth and eighth periods of the plurality of sub-frames.

30. The time-of-flight ranging pixel circuit of claim 29, wherein the first phase modulation signal is configured to be in phase with the modulated light emitted from the light source, wherein the second phase modulation signal is configured to be 90 degrees out of phase with the modulated light emitted from the light source, wherein the third phase modulation signal is configured to be 180 degrees out of phase with the modulated light emitted from the light source, and wherein the fourth phase modulation signal is configured to be 270 degrees out of phase with the modulated light emitted from the light source.

31. A time-of-flight ranging sensing system, comprising: A light source configured to emit modulated light toward an object; and a time-of-flight ranging pixel array configured to illuminate with the modulated light reflected from the object, wherein the time-of-flight ranging pixel array includes a plurality of time-of-flight ranging pixel circuits, wherein each of the plurality of time-of-flight ranging pixel circuits includes: a photodiode configured to generate charge in response to the modulated light reflected from the object to the photodiode; A first transfer transistor coupled to the photodiode; a second transfer transistor coupled to the photodiode, wherein the first transfer transistor is configured to transfer a first portion of the charge from the photodiode in response to a first modulation signal, wherein the second transfer transistor is configured to transfer a second portion of the charge from the photodiode in response to a second modulation signal, wherein the second modulation signal is an inverted first modulation signal; a first floating diffuser coupled to the first transfer transistor to receive the first portion of the charge in response to the first modulation signal; a first plurality of memory nodes; and a first plurality of sample-and-hold transistors, wherein each of the first plurality of sample-and-hold transistors is coupled between one of the first plurality of memory nodes and the first transfer transistor.

32. The time-of-flight ranging sensing system of claim 31, wherein each of the plurality of time-of-flight ranging pixel circuits further includes: A first output source follower transistor; a first plurality of readout transistors, wherein each of the first plurality of readout transistors is coupled between its respective memory node and a gate of the first output source follower transistor; and a first column select transistor coupled to the first output source follower transistor.

33. The time-of-flight ranging sensing system of claim 32, wherein a first of the first plurality of memory nodes is coupled to the first floating diffuser via a first of the first plurality of sample and hold transistors during a first subframe, wherein a second of the first plurality of memory nodes is coupled to the first floating diffuser via a second of the first plurality of sample and hold transistors during a second subframe, wherein the first of the first plurality of memory nodes is coupled to the gate of the first output source follower transistor via a first of the first plurality of readout transistors during the second subframe.

34. The time-of-flight ranging sensing system of claim 33, wherein the second of the first plurality of memory nodes is coupled to the gate of the first output source follower transistor via one of the second of the first plurality of readout transistors during a third subframe, wherein the first of the first plurality of memory nodes is coupled to the first of the first plurality of sample and hold transistors during the third subframe.

35. The time-of-flight ranging sensing system of claim 34, wherein the first modulation signal and the second modulation signal are configured to be modulated at a first modulation frequency during the first sub-frame and the third sub-frame, wherein the first modulation signal and the second modulation signal are further configured to be modulated at a second modulation frequency during the second sub-frame and a fourth sub-frame.

36. The time-of-flight ranging sensing system of claim 35, wherein the first modulation signal is configured to be in phase with the modulated light emitted from the light source during the first sub-frame and the second sub-frame, wherein the first modulation signal is further configured to be 90 degrees out of phase with the modulated light emitted from the light source during the third sub-frame and the fourth sub-frame.

37. The time-of-flight ranging sensing system of claim 36, wherein the first modulation signal is further configured to be 180 degrees out of phase with the modulated light emitted from the light source during a fifth sub-frame and a sixth sub-frame, wherein the first modulation signal is further configured to be 270 degrees out of phase with the modulated light emitted from the light source during a seventh sub-frame and an eighth sub-frame, wherein the first modulation signal and the second modulation signal are further configured to be modulated at the first modulation frequency during the fifth sub-frame and the seventh sub-frame, wherein the first modulation signal and the second modulation signal are further configured to be modulated at the second modulation frequency during the sixth sub-frame and the eighth sub-frame.

38. The time-of-flight ranging sensing system of claim 37, wherein each of the plurality of time-of-flight ranging pixel circuits further includes a first reset transistor coupled between a power rail and the first floating diffuser, wherein the first reset transistor is configured to reset the first floating diffuser.

39. The time-of-flight ranging sensing system of claim 38, wherein the first reset transistor is coupled to receive an overflow signal.

40. The time-of-flight ranging sensing system of claim 39, wherein each of the plurality of time-of-flight ranging pixel circuits further includes a first output reset transistor coupled between the power rail and the gate of the first output source follower transistor.

41. The time-of-flight ranging sensing system of claim 40, wherein each of the plurality of time-of-flight ranging pixel circuits further includes: A first floating diffusion capacitor is coupled to the first floating diffusion section; and a first amplification stage coupled between the first floating diffuser and the first plurality of sampling and holding transistors.

42. The time-of-flight ranging sensing system of claim 41, wherein the first amplification stage includes: A first amplification source follower transistor having a gate coupled to the first floating diffusion section and a source coupled to the first plurality of sampling and holding transistors; a first enable transistor; and a first bias transistor coupled to the first enable transistor, wherein the first enable transistor and the first bias transistor are coupled between the source of the first amplification source follower transistor and ground.

43. The time-of-flight ranging sensing system of claim 38, further comprising: A second floating diffusion section coupled to the second transfer transistor to receive the second portion of the charge in response to the second modulation signal; A second plurality of memory nodes; and a second plurality of sample and hold transistors, wherein each of the second plurality of sample and hold transistors is coupled between one of the second plurality of memory nodes and the second transfer transistor.

44. The time-of-flight ranging sensing system of claim 43, further comprising: A second output source follower transistor; A second plurality of readout transistors, wherein each of the second plurality of readout transistors is coupled between its respective memory node and a gate of the second output source follower transistor; and a second column select transistor coupled to the second output source follower transistor.

45. The time-of-flight ranging sensing system of claim 44, wherein a first of one of the second plurality of memory nodes is coupled to the second floating diffuser via a first of one of the second plurality of sample and hold transistors during the first subframe, wherein a second of one of the second plurality of memory nodes is coupled to the second floating diffuser via a second of one of the second plurality of sample and hold transistors during the second subframe, wherein the first of the second plurality of memory nodes is coupled to the gate of the second output source follower transistor via a second of one of the first plurality of readout transistors during the second subframe.

46. ​​The time-of-flight ranging sensing system of claim 45, wherein the second of the second plurality of memory nodes is coupled to the gate of the second output source follower transistor via one of the second plurality of readout transistors during the third subframe, wherein the first of the second plurality of memory nodes is coupled to the second floating diffuser via one of the second plurality of sample and hold transistors during the third subframe.

47. The time-of-flight ranging sensing system of claim 46, wherein each of the plurality of time-of-flight ranging pixel circuits further includes a second reset transistor coupled between the power rail and the second floating diffuser, wherein the second reset transistor is configured to reset the second floating diffuser.

48. The time-of-flight ranging sensing system of claim 47, wherein the second reset transistor is coupled to receive an overflow signal.

49. The time-of-flight ranging sensing system of claim 48, wherein each of the plurality of time-of-flight ranging pixel circuits further includes a second output reset transistor coupled between the power rail and the gate of the second output source follower transistor.

50. The time-of-flight ranging sensing system of claim 48, wherein each of the plurality of time-of-flight ranging pixel circuits further includes: A second floating diffusion capacitor is coupled to the second floating diffusion section; And a second amplification stage coupled between the second floating diffusion section and the second plurality of sampling and holding transistors.

51. The time-of-flight ranging sensing system of claim 50, wherein the second amplification stage includes: A second amplification source follower transistor having a gate coupled to the second floating diffusion section and a source coupled to the second plurality of sampling and holding transistors; a second enable transistor; and a second bias transistor coupled to the second enable transistor, wherein the second enable transistor and the second bias transistor are coupled between the source of the second amplification source follower transistor and ground.

52. The time-of-flight ranging sensing system of claim 32, wherein each of the first plurality of memory nodes is coupled to sample and hold one of a plurality of sub-frame portions of the first portion of charge from the first floating diffuser via one of the first plurality of sampling and holding transistors, wherein each of the plurality of sub-frame portions of the first portion of charge is coupled to be read from the first plurality of memory nodes via one of the first plurality of readout transistors after all the first plurality of memory nodes have sampled and held the plurality of sub-frame portions of the first portion of charge from the first floating diffuser.

53. The time-of-flight ranging sensing system of claim 52, wherein the first modulation signal is configured to be a first phase modulation signal during the period of a first sub-frame and a second sub-frame, wherein the first modulation signal is further configured to be a third phase modulation signal during the period of a third sub-frame and a fourth sub-frame, wherein the first modulation signal is further configured to be a second phase modulation signal during the period of a fifth sub-frame and a sixth sub-frame, and wherein the first modulation signal is further configured to be a fourth phase modulation signal during the period of a seventh sub-frame and an eighth sub-frame.

54. The time-of-flight ranging sensing system of claim 53, wherein the first modulation signal is configured to be modulated at a first modulation frequency during the first, third, fifth and seventh periods of the plurality of sub-frames, wherein the first modulation signal is configured to be modulated at a second modulation frequency during the second, fourth, sixth and eighth periods of the plurality of sub-frames.

55. The time-of-flight ranging sensing system of claim 54, further comprising: A second floating diffusion section coupled to the second transfer transistor to receive the second portion of the charge in response to the second modulation signal; A second plurality of memory nodes; and a second plurality of sample and hold transistors, wherein each of the second plurality of sample and hold transistors is coupled between one of the second plurality of memory nodes and the second transfer transistor.

56. The time-of-flight ranging sensing system of claim 55, further comprising: A second output source follower transistor; A second plurality of readout transistors, wherein each of the second plurality of readout transistors is coupled between its respective memory node and a gate of the second output source follower transistor; and a second column select transistor coupled to the second output source follower transistor.

57. The time-of-flight ranging sensing system of claim 56, wherein each of the second plurality of memory nodes is coupled to sample and hold one of the plurality of sub-frame portions of the second portion of charge from the second floating diffuser via one of the second plurality of sampling and holding transistors, wherein each of the plurality of sub-frame portions of the second portion of charge is coupled to be read from the respective of the second plurality of memory nodes via one of the second plurality of readout transistors after all the second plurality of memory nodes have sampled and held the plurality of sub-frame portions of the second portion of charge from the second floating diffuser.

58. The time-of-flight ranging sensing system of claim 57, wherein the second modulation signal is configured to be the second phase modulation signal during the first and second periods of the plurality of sub-frames, wherein the second modulation signal is further configured to be the fourth phase modulation signal during the third and fourth periods of the plurality of sub-frames, wherein the second modulation signal is further configured to be the first phase modulation signal during the fifth and sixth periods of the plurality of sub-frames, and wherein the second modulation signal is further configured to be the third phase modulation signal during the seventh and eighth periods of the plurality of sub-frames.

59. The time-of-flight ranging sensing system of claim 58, wherein the second modulation signal is configured to be modulated at the first modulation frequency during the first, third, fifth and seventh periods of the plurality of sub-frames, wherein the second modulation signal is configured to be modulated at the second modulation frequency during the second, fourth, sixth and eighth periods of the plurality of sub-frames.

60. The time-of-flight ranging sensing system of claim 59, wherein the first phase modulation signal is configured to be in phase with the modulated light emitted from the light source, wherein the second phase modulation signal is configured to be 90 degrees out of phase with the modulated light emitted from the light source, wherein the third phase modulation signal is configured to be 180 degrees out of phase with the modulated light emitted from the light source, and wherein the fourth phase modulation signal is configured to be 270 degrees out of phase with the modulated light emitted from the light source.

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