Microelectronic assemblies having backside die-to-package interconnects

Abstract

This document discloses microelectronic components, related devices, and methods. In some embodiments, the microelectronic component may include a first die in a first layer having a first surface and an opposing second surface, and includes a first metallization stack at the first surface; a device layer on the first metallization stack; a second metallization stack on the device layer; and interconnections on the first surface of the die electrically coupled to the first metallization stack; a conductive pillar in the first layer; and a second die in a second layer on the first layer having a first surface and an opposing second surface, wherein the first surface of the second die is coupled to the conductive pillar and the second surface of the first die through a hybrid bonding region.

Description

[Technical Field]

[0001] This invention relates to a microelectronic component having a back-side die-to-package interconnect. [Previous Technology]

[0002] In order to ensure reliable operation of integrated circuit (IC) packages, as well as increase the production yield of components and reduce costs, IC chips and subassemblies can be tested before being coupled to the package substrate or to each other, so that only known good chips and subassemblies can be used. [Summary of the Invention]

[0003] and

Implementation Method

[0020] This document discloses microelectronic components, related devices, and methods. For example, in some embodiments, a microelectronic component may include a first die in a first layer having a first surface and an opposing second surface, and including a first metallization stack at the first surface; a device layer on the first metallization stack; a second metallization stack on the device layer; and a die-to-package interconnect on the first surface of the die, electrically coupled to the first metallization stack; a conductive pillar in the first layer; and a second die in a second layer on the first layer having a first surface and an opposing second surface, wherein the first surface of the second die is coupled to the conductive pillar and the second surface of the first die through a hybrid bonding region.

[0021] Directly coupling two or more components in a multi-die IC package is challenging, especially given the decreasing size and thickness of these components, the finer spacing of interconnects, and the reduced thickness of the bonding interfaces between components (e.g., the z-height of the die-to-die spacing). Traditional methods for testing die functionality (e.g., identifying known good dies (KGD) during manufacturing) involve placing the die pads using standard probing techniques. However, once the die is integrated into the sub-assembly, the die pads may not be available for testing until the sub-assembly is integrated into the IC package and a thick metal layer (e.g., back-side connection) is formed to connect to the board. In one example, a fine-pitch bonding layer can be fabricated between a top and bottom wafer. This fine-pitch bonding layer can be attached using a wafer-to-wafer technique. The back side of the bottom wafer can then be thinned to expose the TSV (Transient Viaductor Device) within the bottom die, and a thick metal layer can be formed and electrically coupled to the TSV for functional testing. In another example, the fine-pitch bonding layer between the top and bottom wafers can be attached using a die-to-wafer technique. The back side of the bottom wafer can then be thinned to expose the TSV within the bottom die, and a thick metal layer can be formed and electrically coupled to the TSV for functional testing. In many such cases, the addition of a faulty or non-functional sub-component to the package increases manufacturing defective cells and costs. Compared to conventional methods, the various microelectronic components disclosed herein exhibit better assembly yields during manufacturing and improved performance and reliability during use by providing integrated interconnects to the back side of the die that can be used to test die functionality within the sub-component. For example, the microelectronic components disclosed herein can match high-performance base dies with high-performance top dies to achieve optimal potential performance, can customize the back-side power grid for each base die to reduce cost or improve performance, and can separate the requirements for base die signal vias (e.g., back-to-front vias) from the requirements for base die power delivery vias to optimize performance.

[0022] In the following detailed description, reference is made to the accompanying drawings, which form a part of this document, wherein like reference numerals designate like parts throughout, and wherein illustrative embodiments that may be practiced are shown. It should be understood that other embodiments may be used, and structural or logical changes may be made without departing from the scope of this disclosure. Therefore, the following detailed description should not be construed as limiting.

[0023] Various operations can be described sequentially as a plurality of discrete actions or operations in a manner most conducive to understanding the subject matter of the claim. However, the order of description should not be construed as implying that these operations must be order-dependent. In particular, these operations may not be performed in the order presented. The described operations may be performed in an order different from that of the described embodiments. Various additional operations may be performed, and / or the described operations may be omitted in additional embodiments.

[0024] For the purposes of this disclosure, the phrase "A and / or B" refers to (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" refers to (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The drawings are not necessarily drawn to scale. Although many drawings illustrate straight-line structures with flat walls and right-angle corners, this is only for illustrative purposes; actual devices manufactured using these techniques will exhibit rounded corners, surface roughness, and other features.

[0025] The description uses the phrases "in one embodiment" or "in an embodiment," each of which may refer to one or more identical or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used with respect to embodiments of this disclosure are synonyms. As used herein, "package" and "IC package" are synonyms, as are "die" and "IC die." The terms "top" and "bottom" may be used herein to interpret various features of the figures, but these terms are for ease of discussion only and do not imply a desired or required direction. As used herein, the term "insulating" means "electrically insulating" unless otherwise stated. Throughout the specification and within the scope of the claims, the term "coupled" refers to a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between connected things or an indirect connection through one or more passive or active intermediate elements. The meanings of "a," "an," and "the" include plural references. The meaning of "in" includes both "in" and "on".

[0026] When used to describe a range of dimensions, the phrase "between X and Y" indicates a range that includes both X and Y. For convenience, the phrase "Figure 8" may be used to refer to the set of figures 8A-8J, the phrase "Figure 9" may be used to refer to the set of figures 9A-9D, and so on. Although some elements may be referred to in the singular form herein, these elements may include multiple sub-elements. For example, "insulating material" may include one or more insulating materials.

[0027] FIG1 is a side cross-sectional view of an exemplary microelectronic component according to various embodiments. The microelectronic component 100 may include a multilayer die sub-component 104 having an integrated back-side die-to-package (DTP) interconnect 150. As used herein, the term "multilayer die sub-component" 104 may refer to a composite die having two or more stacked dielectric layers, each layer having one or more dies, and conductive interconnects and / or conductive paths connecting one or more dies (including dies in non-adjacent layers). As used herein, the terms "multilayer die sub-component" and "composite die" are used interchangeably. As shown in FIG1, the multilayer die sub-component 104 may include a first layer 104-1 having dies 114-1 and conductive pillars 152, and a second layer 104-2 having dies 114-2 and dies 114-3. The first layer 104-1 may include a first surface 170-1 and an opposing second surface 170-2. In particular, the multilayer die sub-assembly 104 may include a first die 114-1 in a first dielectric layer 104-1, a second die 114-2 in a second dielectric layer 104-2 coupled to the first die 114-1 through a first hybrid bonding region 130-1, and a third die 114-3 in the second dielectric layer 104-2 coupled to the first die 114-1 through a second hybrid bonding region 130-2. The die 114-1 may include a first metallization stack 126 at a first surface 170-1, a substrate layer 120 on the first metallization stack 126, a device layer 124 on the substrate layer 120 having a device 125, a second metallization stack 122 on the device layer (e.g., at the second surface 170-2), and a DTP interconnect 150 coupled to the first metallization stack 126 at the first surface 170-1 of the die 114-1. The first and second metallization stacks 126, 122 may include a plurality of layers, each including an insulating material formed in the layers and a plurality of conductive paths formed through the insulating material. The conductive paths in the first and second metallization stacks 126, 122 may include conductive traces and / or conductive vias. The first metallization stack 126 may be referred to herein as a "back-side metallization layer," a "thick metallization layer," or other similar terms, while the second metallization stack 122 may be referred to herein as an "active-side metallization layer," a "thin metallization layer," or other similar terms, wherein the conductive structure of the first metallization stack 126 may be thicker than the conductive structure of the second metallization stack 122. Device layer 124 may include active and passive devices (e.g., transistors, diodes, resistors, inductors, and capacitors). In some embodiments, device layer 124 may include one or more device layers including transistors (e.g., as discussed below with reference to FIG13).For example, device layer 124 may include first and second transistors, wherein the first transistor may be a p-type metal-oxide-semiconductor (PMOS) and the second transistor may be an n-type metal-oxide-semiconductor (NMOS). Substrate layer 120 may include micro-through silicon vias (µTSVs) 123. µTSVs 123 may connect a first metallization stack 126 to devices 125 in device layer 124 via a second metallization stack 122. In some embodiments, µTSVs 123 have a spacing between 0.01 micrometers and 0.5 micrometers. In some embodiments, substrate layer 120 may be omitted.

[0028] Die 114-1 may be coupled to package substrate 102 via back-side DTP interconnect 150. As used herein, the term "back-side DTP interconnect" or "DTP interconnect" may include conductive contacts 132 on the multilayer die subassembly 104 at the first surface 170-1 of die 114-1, coupled to the first metallization stack 126 of die 114-1 (e.g., back-side metallization layer), and may further include solder 134, or other interconnect structures, and may further include conductive contacts 136 on the surface of a substrate (e.g., silicon or glass interposer, package substrate 102, or a circuit board in the absence of a package substrate 102 between the multilayer die subassembly 104 and a circuit board (not shown). As used herein, "conductive contact" may refer to a portion of an electrical material (e.g., metal) serving as an electrical interface between different components; conductive interconnects may be recessed into the surface of a component, flush with the surface of a component, or protrude away from the surface of a component, and may take any suitable form (e.g., a conductive pad or via, or a portion of a conductive wire or through-hole). The conductive contacts 132 on the surface of die 114-1 can be further coupled to conductive paths within die 114-1 (e.g., via µTSV 123 in substrate layer 120 and / or via second metallization stack 122 to device 125 in device layer 124). DTP interconnect 150 can be configured to route power or signals to or from die 114 in multilayer die subassembly 104 via conductive contacts 132, conductive pillars 152, and / or first metallization stack 126 in die 114-1.

[0029] Dies 114-2 and 114-3 in the second layer 104-2 can be coupled to the package substrate 102 via conductive posts 152 to form a multi-level (ML) interconnect. Specifically, dies 114-2 and 114-3 can be coupled to the package substrate 102 via conductive posts 152, conductive contacts 132 on the multilayer die subassembly 104 (e.g., at the first surface 170-1), solder 134, and conductive contacts 136 on the package substrate 102. ML interconnects can be power delivery interconnects or high-speed signal interconnects. As used herein, the term "ML interconnect" can refer to an interconnect including conductive posts between a first assembly and a second assembly, wherein the first assembly and the second assembly are not in adjacent layers, or can refer to an interconnect spanning one or more layers (e.g., an interconnect between a first die in a first layer and a second die in a third layer, or an interconnect between a package substrate and dies in a second layer). Die 114 may include other conductive paths (e.g., including wires and vias) and / or other circuitry (not shown) coupled to individual conductive contacts (e.g., conductive contact 132 on die 114-1 and / or conductive contact 110 on dies 114-1, 114-2, 114-3).

[0030] The microelectronic component 100 may include a second die 114-2 coupled to the first die 114-1 through a hybrid bonding (HB) region 130-1. Specifically, as shown in FIG2, the HB region 130-1 may include an HB interface 180-1A at the top surface of the first die 114-1, wherein the HB interface 180-1A includes a set of conductive HB contacts 110 and an HB dielectric 108 surrounding the HB contacts 110 of the HB interface 180-1A. The HB region 130-1 may also include an HB interface 180-1B at the bottom surface of the die 114-2, wherein the HB interface 180-1B includes a set of HB contacts 110 and an HB dielectric 108 surrounding the HB contacts 110 of the HB interface 180-1B. The HB contact 110 of the HB interface 180-1A of die 114-1 can be aligned with the HB contact 110 of the HB interface 180-1B of die 114-2, such that in the microelectronic assembly 100, the HB contact 110 of die 114-2 contacts the HB contact 110 of die 114-1. In the microelectronic assembly 100 of FIG. 1, the HB interface 180-1A of die 114-1 can be coupled (e.g., electrically and mechanically) to the HB interface 180-1B of die 114-2 to form an HB region 130-1 coupling die 114-1 and die 114-2. The second die 114-2 can be further coupled to the conductive pillar 152 through the HB region 130-1.

[0031] The microelectronic component 100 may further include a third die 114-3 coupled to the first die 114-1 through a hybrid bonding (HB) region 130-2. Specifically, as shown in FIG2, the HB region 130-2 may include an HB interface 180-2A at the top surface of the first die 114-1, wherein the HB interface 180-2A includes a set of conductive HB contacts 110 and an HB dielectric 108 surrounding the HB contacts 110 of the HB interface 180-2A. The HB region 130-2 may also include an HB interface 180-2B at the bottom surface of the die 114-3, wherein the HB interface 180-2B includes a set of HB contacts 110 and an HB dielectric 108 surrounding the HB contacts 110 of the HB interface 180-2B. The HB contact 110 of the HB interface 180-2A of die 114-1 can be aligned with the HB contact 110 of the HB interface 180-2B of die 114-3, such that in the microelectronic assembly 100, the HB contact 110 of die 114-3 contacts the HB contact 110 of die 114-1. In the microelectronic assembly 100 of FIG. 1, the HB interface 180-2A of die 114-1 can be joined (e.g., electrically and mechanically) with the HB interface 180-2B of die 114-3 to form an HB region 130-2 coupling die 114-1 and die 114-3. More generally, the HB region 130 disclosed herein may include two complementary HB interfaces 180 joined together; for ease of illustration, the designation of the HB interfaces 180 may be omitted in many subsequent figures to improve clarity. The third die 114-3 can be further coupled to the conductive pillar 152 through the HB region 130-2. In some embodiments, the second die 114-2 and / or the third die 114-3 may not be coupled to the conductive pillar through the HB region. In this case, the second die 114-2 and / or the third die 114-3 may be coupled to the conductive pillar through other interconnects, such as metal-to-metal.

[0032] As used herein, the term "hybrid bonding" is used to include techniques that first bring the HB dielectric 108 of opposing HB interfaces 180 into contact, and then subject them to heat and sometimes compression, or techniques that bring the HB contacts 110 and HB dielectric 108 of opposing HB interfaces 180 into substantially simultaneous contact, and then subject them to heat and compression. In such techniques, the HB contacts 110 and HB dielectric 108 at one HB interface 180 are brought into contact with the HB contacts 110 and HB dielectric 108 at another HB interface 180, respectively, and elevated pressure and / or temperature may be applied to bond the contacting HB contacts 110 and / or contacting HB dielectric 108. HB interconnects may be more reliably capable of conducting higher currents than other types of interconnects; for example, some conventional soldered interconnects may form a large amount of brittle IMC when current flows, and the maximum current supplied through such interconnects may be limited to mitigate mechanical failure. Although Figures 1 and 2 show that the HB dielectric 108 extends completely along the entire top surface of the first dielectric layer 104-1, the HB dielectric 108 may extend only along a portion of the bottom surface of the second and third grains 114-2, 114-3, where the second and third grains 114-2, 114-3 overlap with the first grain 114-1.

[0033] The HB dielectric 108 may include one or more dielectric materials, such as one or more inorganic dielectric materials. For example, the HB dielectric 108 may include silicon and nitrogen (e.g., in the form of silicon nitride), silicon and oxygen (e.g., in the form of silicon oxide); silicon, carbon and nitrogen (e.g., in the form of silicon carbon nitride); silicon, carbon and oxygen (e.g., in the form of carbon-doped silicon oxide); silicon, oxygen and nitrogen (e.g., in the form of silicon oxynitride); aluminum and oxygen (e.g., in the form of aluminum oxide); titanium and oxygen (e.g., in the form of titanium oxide); hafnium and oxygen (e.g., in the form of hafnium oxide); silicon, oxygen, carbon and hydrogen (e.g., in the form of tetraethyl orthosilicate (TEOS)); zirconium and oxygen (e.g., in the form of zirconium oxide); niobium and oxygen (e.g., in the form of niobium oxide); tantalum and oxygen (e.g., in the form of tantalum oxide); and combinations thereof.

[0034] The HB contact 110 may include pillars, pads, or other structures. Although the HB contacts 110 are shown in the same manner at both HB interfaces 180 of the HB region 130 in the figures, the HB contacts 110 may have the same structure at both HB interfaces 180, or the HB contacts 110 at different HB interfaces 180 may have different structures. For example, in some embodiments, the HB contact 110 in one HB interface 180 may include a metal pillar (e.g., a copper pillar), and the complementary HB contact 110 in the complementary HB interface 180 may include a metal pad (e.g., a copper pad) recessed in the dielectric. The HB pad may also have different shapes (e.g., a larger regular polygon on the HB interface and a smaller regular polygon on the complementary HB interface). HB contact 110 may comprise any one or more conductive materials, such as copper, manganese, titanium, gold, silver, palladium, nickel, copper and aluminum (e.g., in the form of a copper-aluminum alloy), tantalum (e.g., tantalum metal, or tantalum and nitrogen in the form of tantalum nitride), cobalt, cobalt and iron (e.g., in the form of a cobalt-iron alloy), or any alloy of the foregoing materials (e.g., copper, manganese, and nickel in the form of a manganese-nickel-copper alloy). The pad structure may also comprise multiple metals (e.g., may comprise highly conductive metals, such as copper or aluminum, coated with a corrosion-resistant metal such as titanium or gold, or a corrosion-resistant alloy such as a manganese-nickel-copper alloy). In some embodiments, the HB dielectric 108 of the HB interface 180 and the HB contact 110 may be fabricated using a low-temperature deposition technique (e.g., a technique in which deposition occurs at temperatures below 250 degrees Celsius or below 200 degrees Celsius), such as low-temperature plasma-enhanced chemical vapor deposition (PECVD).

[0035] FIG1 also shows die 114-1 coupled to package substrate 102 via back-side DTP interconnect 150. Although FIG1 depicts a specific number of dies 114 coupled to package substrate 102 and to other dies 114 via HB region 130, this number and arrangement are merely illustrative, and microelectronic component 100 may include any desired number and arrangement of dies 114 coupled to package substrate 102 and to other dies 114 via HB region 130. Although a single reference numeral "108" is used to refer to multiple different HB interfaces 180 (and different HB regions 130) of HB dielectric, this is only for illustrative purposes, and the HB dielectric 108 of different HB interfaces 180 (even within a single HB region 130) may have different materials and / or structures. Similarly, although a single reference numeral "110" is used to refer to multiple different HB interfaces 180 (and different HB regions 130), this is only for illustrative purposes, and the HB contacts 110 of different HB interfaces 180 (or even within a single HB region 130) can have different materials and / or structures.

[0036] The grain 114 disclosed herein may include an insulating material (e.g., a dielectric material formed in a multilayer, as known in the art) and multiple conductive paths formed through the insulating material. In some embodiments, the insulating material of the grain 114 may include a dielectric material, such as silicon dioxide, silicon nitride, oxynitride, polyimide material, glass-reinforced epoxy matrix material, or low-k or ultra-low-k dielectric (e.g., carbon-doped dielectric, fluorine-doped dielectric, porous dielectric, organic polymer dielectric, photoimageable dielectric, and / or benzocyclobutene-based polymer). In some embodiments, the insulating material of the grain 114 may include a semiconductor material, such as silicon, germanium, or a III-V group material (e.g., gallium nitride), and one or more additional materials. For example, the insulating material may include silicon oxide or silicon nitride. The conductive paths in die 114 may include conductive traces and / or conductive vias, and may connect any conductive contacts in die 114 in any suitable manner (e.g., multiple conductive contacts connected on the same or different surfaces of die 114). Exemplary structures that may be included in die 114 disclosed herein are discussed below with reference to FIG13. The conductive paths in die 114 may be delimited by padding materials such as adhesive pads and / or barrier pads, where appropriate. In some embodiments, die 114 is a wafer. In some embodiments, die 114 is a single-crystal silicon, fan-out, or fan-in package die or die stack (e.g., wafer stack, die stack, or multilayer die stack).

[0037] In some embodiments, die 114 may include conductive paths for routing power, ground, and / or signals to / from other dies 114 included in the microelectronic component 100. For example, die 114-1 may include a TSV, which includes a conductive material via, such as a metal via, through which it is isolated from surrounding silicon or other semiconductor materials by blocking oxides, or other conductive paths through which power, ground, and / or signals can be transmitted between the package substrate 102 and one or more dies "114" "on top" of die 114-1 (e.g., dies 114-2 and / or 114-3 in the embodiment of FIG. 1). In some embodiments, die 114-1 may not route power and / or ground to dies 114-2 and 114-3; instead, dies 114-2 and 114-3 may be directly coupled to power lines and / or ground lines in the package substrate 102 via ML interconnects (e.g., through conductive contacts 132 and conductive posts 152). In some embodiments, the die 114-1 in the first layer 104-1, also referred to herein as a "base die," "interposer die," or "bridge die," may be thicker than the dies 114-2 and 114-3 in the second layer 104-2. In some embodiments, the die 114 may span multiple layers of the multilayer die sub-assembly 104 (e.g., it may span the first and second layers 104-1 and 104-2). The die 114-1 of the microelectronic assembly 100 may be a single-sided die (in the sense that the die 114-1 has conductive contacts on only a single surface), or, as shown, a double-sided die (in the sense that the die 114-1 has conductive contacts on two surfaces (e.g., a top surface and a bottom surface), and may be a mixed-pitch die (in the sense that the die 114-1 has groups of conductive contacts with different pitches). In some embodiments, dies 114-2 and / or 114-3 may not include active devices or routing and may only provide thermal and / or mechanical support. In this embodiment, HB regions 130-1 and / or 130-2 may not include HB contacts 110. In some embodiments, dies 114-2, 114-3 may include elements of die 114-1 (e.g., a first metallization stack 126, a device layer 124 having means 125, and a second metallization stack 122). In some embodiments, die 114-1 may be a memory device (e.g., as described below with reference to die 1502 of FIG. 12), a high-frequency sequencer and deserializer (SerDes), such as a Fast Peripheral Component Interconnect (PCI). In some embodiments, die 114-1 may be a processing die, an RF chip, a power converter, a network processor, a workload accelerator, or a security cipher.In some embodiments, grains 114-2 and / or grains 114-3 may be processed grains.

[0038] The multilayer grain subassembly 104 may include an insulating material 133 (e.g., a dielectric material formed in a multilayer, as known in the art) to form a multilayer and embed one or more grains in one layer. In some embodiments, the insulating material 133 of the multilayer grain subassembly 104 may be a dielectric material, such as an organic dielectric material, a flame-retardant grade 4 material (FR-4), a bismaleimide triazine (BT) resin, a polyimide material, a glass-reinforced epoxy matrix material, or a low-k and ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, and an organic polymer dielectric). In some embodiments, the grains 114 may be embedded in a heterogeneous dielectric, such as stacked dielectric layers (e.g., alternating layers of different inorganic dielectrics). In some embodiments, the insulating material 133 of the multilayer grain subassembly 104 may be a molding material, such as an organic polymer having inorganic silica particles. The multilayer grain subassembly 104 may include one or more ML interconnects (e.g., including conductive vias and / or conductive pillars, as shown) via a dielectric material. The multilayer grain subassembly 104 may have any suitable size. For example, in some embodiments, the thickness of the multilayer grain subassembly 104 may be between 100 μm and 2000 μm. In some embodiments, the multilayer grain subassembly 104 may be a composite grain, such as a stacked grain. The multilayer grain subassembly 104 may have any suitable number of layers, any suitable number of grains, and any suitable grain arrangement. For example, in some embodiments, the multilayer grain subassembly 104 may have 3 to 20 grain layers. In some embodiments, the multilayer grain subassembly 104 may include layers having 2 to 50 grains.

[0039] The package substrate 102 may include an insulating material (e.g., a dielectric material formed in a multilayer, as known in the art) and one or more conductive paths (e.g., including conductive traces and / or conductive vias, as shown) for routing power, ground, and signals through the dielectric material. In some embodiments, the insulating material of the package substrate 102 may be a dielectric material, such as an organic dielectric material, a flame-retardant grade 4 material (FR-4), BT resin, polyimide material, glass-reinforced epoxy resin matrix material, an organic dielectric with inorganic fillers, or low-k and ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymer dielectrics). In particular, when the package substrate 102 is formed using a standard printed circuit board (PCB) process, the package substrate 102 may include FR-4, and the conductive paths in the package substrate 102 may be formed by patterned copper sheets separated by stacked layers through FR-4. The conductive paths in the encapsulation substrate 102 may be delimited by padding materials such as adhesive pads and / or barrier pads, as appropriate. In some embodiments, the encapsulation substrate 102 may be formed using a photolithography-defined via encapsulation process. In some embodiments, the encapsulation substrate 102 may be manufactured using standard organic encapsulation manufacturing processes, thus the encapsulation substrate 102 may be in the form of an organic package. In some embodiments, the encapsulation substrate 102 may be a set of redistribution layers formed on a panel carrier by laminating or spinning on a dielectric material and forming conductive vias and lines through laser drilling and electroplating. In some embodiments, the encapsulation substrate 102 may be formed on a removable carrier using any suitable technique, such as redistribution layer technology. Any method known in the art for manufacturing the encapsulation substrate 102 may be used, and for the sake of brevity, such methods will not be discussed in further detail herein.

[0040] In some embodiments, the package substrate 102 may be a lower-density dielectric, while the die 114 may be a higher-density dielectric or a region having a higher-density dielectric. As used herein, the terms "lower density" and "higher density" are relative terms, meaning that conductive paths (e.g., including conductive interconnects, conductive lines, and conductive vias) in the lower-density dielectric are larger and / or have greater spacing than conductive paths in the higher-density dielectric. In some embodiments, the higher-density dielectric may be manufactured using a modified semi-additive process or a semi-additive build-up process with advanced lithography (having small vertical interconnect features formed by advanced laser or lithography processes), while the lower-density dielectric may be a PCB manufactured using standard PCB processes (e.g., a standard subtractive process using etch chemistry to remove unwanted copper areas, and having coarse vertical interconnect features formed by standard laser processes). In other embodiments, the higher-density dielectric may be manufactured using semiconductor manufacturing processes, such as single-damascene or dual-damascene processes. In some embodiments, additional dies may be disposed on the top surface of dies 114-2 and 114-3. In some embodiments, additional components may be disposed on the top surface of dies 114-2 and 114-3. The additional passive components, such as surface-mount resistors, capacitors and / or inductors, may be disposed on the top or bottom surface of the package substrate 102, or may be embedded in the package substrate 102.

[0041] The back-side DTP interconnect 150 disclosed herein can take any suitable form. In some embodiments, the back-side DTP interconnect 150 may include solder 134 (e.g., solder bumps or solder balls subjected to thermal reflow to form the interconnect), as shown. In some embodiments, the back-side DTP interconnect 150 may include anisotropic conductive material, such as anisotropic conductive film or anisotropic conductive paste. The anisotropic conductive material may include a conductive material dispersed in a non-conductive material. The DTP interconnect 150 may be a direct metal-to-metal bond, such as a copper-to-copper bond. In some embodiments, for example when the package is a silicon interposer, the DTP interconnect 150 may include a hybrid bond.

[0042] The microelectronic component 100 of FIG. 1 may also include an underfill material 127. In some embodiments, the underfill material 127 may extend between the die 114-1 and the package substrate 102 around the associated back-side DTP interconnect 150. The underfill material 127 may be an insulating material, such as a suitable epoxy resin material. In some embodiments, the underfill material 127 may include a capillary underfill, a non-conductive film (NCF), or a molded underfill. In some embodiments, the underfill material 127 may include an epoxy flux that helps to solder the die 114-1 to the package substrate 102 during the formation of the back-side DTP interconnect 150, and then polymerizes and encapsulates the back-side DTP interconnect 150. The underfill material 127 may be selected to have a coefficient of thermal expansion (CTE) that can mitigate or minimize stress caused by non-uniform thermal expansion in the microelectronic component 100 between the multilayer die sub-component 104 and the package substrate 102. In some embodiments, the CTE of the underfill material 127 may have a value between the CTE of the package substrate 102 (e.g., the CTE of the dielectric material of the package substrate 102) and the CTE of the multilayer die subassembly 104.

[0043] The microelectronic component 100 of FIG. 1 may further include a circuit board (not shown). A package substrate 102 may be coupled to the circuit board via a second-level interconnect at the bottom surface of the package substrate 102. The second-level interconnect may be any suitable second-level interconnect, including solder balls for a ball grid array arrangement, pins in a pin grid array arrangement, or pads in a planar grid array arrangement. The circuit board may be, for example, a motherboard and may have other components attached thereto. The circuit board may include conductive paths and other conductive contacts for routing power, ground, and signals through the circuit board, as known in the art. In some embodiments, the second-level interconnect may not couple the package substrate 102 to the circuit board, but may instead couple the package substrate 102 to another IC package, interposer, or any other suitable component. In some embodiments, the multilayer die sub-component 104 may not be coupled to the package substrate 102, but may instead be coupled to the circuit board, such as a PCB.

[0044] Many elements of the microelectronic component 100 of FIG1 are included in other figures; the discussion of these elements will not be repeated when discussing these figures, and any of these elements may take any form disclosed herein. Furthermore, many elements are shown in FIG1 as included in the microelectronic component 100, but many of these elements may not be present in the microelectronic component 100. For example, in various embodiments, the underfill material 127 and the package substrate 102 may be omitted. In some embodiments, individual microelectronic components in the microelectronic component 100 disclosed herein may be used as a system-in-package (SiP), comprising multiple dies 114 with different functions. In such embodiments, the microelectronic component 100 may be referred to as a SiP.

[0045] FIG3 is a side cross-sectional view of another exemplary microelectronic component according to various embodiments. The microelectronic component 100 may include a multilayer die sub-component 104 having an integrated back-side DTP interconnect 150. As shown in FIG3, the multilayer die sub-component 104 may include a first layer 104-1 having a die 114-1 and a conductive pillar 152, and a second layer 104-2 having a die 114-2. In particular, the multilayer die sub-component 104 may include a first die 114-1 in the first dielectric layer 104-1 and a second die 114-2 in the second dielectric layer 104-2, which is coupled to the first die 114-1 through a first hybrid bonding region 130. Die 114-1 may include a first metallization stack 126 at a first surface 170-1, a substrate layer 120 on the first metallization stack 126, a device layer 124 having means 125 on the substrate layer 120, a second metallization stack 122 on the device layer (e.g., at the second surface 170-2), and a DTP interconnect 150 coupled to the first metallization stack 126 at the first surface 170-1 of die 114-1. In some embodiments, the substrate layer 120 may be omitted. Die 114-1 may be coupled to the package substrate 102 via the back-side DTP interconnect 150, and die 114-2 in the second layer 104-2 may be coupled to the package substrate 102 via an ML interconnect.

[0046] FIG4 is a side cross-sectional view of another exemplary microelectronic component according to various embodiments. The microelectronic component 100 may include a multilayer die sub-component 104 coupled to a die 114-3 at a first surface 170-1 and having an integrated back-side DTP interconnect 150. As shown in FIG4, the multilayer die sub-component 104 may include a first layer 104-1 having a die 114-1 and conductive pillars 152, and a second layer 104-2 having a die 114-2. Specifically, the multilayer die subassembly 104 may include a first die 114-1 in a first dielectric layer 104-1, a second die 114-2 in a second dielectric layer 104-2, coupled to the first die 114-1 through a first hybrid bonding region 130-1, and a third die 114-3 coupled to the first surface 170-1 of the first dielectric layer 104-1 through a second hybrid bonding region 130-2, with DTP interconnects 150 at the bottom surface of the die 114-3. The die 114-1 may include a first metallization stack 126 at the first surface 170-1, a substrate layer 120 on the first metallization stack 126, a device layer 124 having a device 125 on the substrate layer 120, and a second metallization stack 122 on the device layer (e.g., at the second surface 170-2). In some embodiments, the substrate layer 120 may be omitted. Die 114-3 may be a double-sided die and may include TSV 121 and / or other conductive paths (not shown) for coupling to package substrate 102 and multilayer die subassemblies 104. DTP interconnect 150 at the bottom surface of die 114-3 may be coupled to the first metallization stack 126 in die 114-1 via conductive paths in die 114-3 (e.g., TSV 121). Die 114-1 may be coupled to package substrate 102 via die 114-3 and the back-side DTP interconnect 150, while die 114-2 in the second layer 104-2 may be coupled to package substrate 102 via conductive pillars 152 for forming ML interconnects and conductive paths in die 114-3. In some embodiments, die 114-2 may be non-functional and may provide mechanical and / or thermal support. In this embodiment, the first hybrid bonding region 130-1 may not include HB contacts 110. In addition, die 114-3 can be a passive die that includes pass-through and redistribution routing.

[0047] FIG5 is a side cross-sectional view of an exemplary microelectronic component according to various embodiments. The microelectronic component 100 may include a multilayer die sub-component 104 having an integrated back-side DTP interconnect 150. As shown in FIG5, the multilayer die sub-component 104 may include a first layer 104-1 having a die 114-1 and conductive pillars 152, and a second layer 104-2 having dies 114-2 and dies 114-3. The first layer 104-1 may include a first surface 170-1 and an opposing second surface 170-2. In particular, the multilayer die subassembly 104 may include a first die 114-1 in the first dielectric layer 104-1, a second die 114-2 in the second dielectric layer 104-2 coupled to the first die 114-1 through the first hybrid bonding region 130-1, and a third die 114-3 in the second dielectric layer 104-2 coupled to the first die 114-1 through the second hybrid bonding region 130-2. Die 114-1 may include a first substrate layer 128 having TSV 118 at a first surface 170-1, a first metallization stack 126 on the first substrate layer 128, a second substrate layer 120 on the first metallization stack 126, a device layer 124 having a device 125 on the substrate layer 120, a second metallization stack 122 on the device layer (e.g., at the second surface 170-2), and a DTP interconnect 150 at the first surface 170-1, which is coupled to the first metallization stack 126 in the first die 114-1 via the TSV 118 in the first substrate layer 128. In some embodiments, the TSV 118 in the first substrate layer 128 may have a spacing between 5 micrometers and 100 micrometers. In some embodiments, the second substrate layer 120 may be omitted. Die 114-1 can be coupled to the package substrate 102 via the back-side DTP interconnect 150, while dies 114-2 and 114-3 in the second layer 104-2 can be coupled to the package substrate 102 via ML interconnect.

[0048] FIG6 is a side cross-sectional view of an exemplary microelectronic component according to various embodiments. The microelectronic component 100 may include a multilayer die sub-component 104 having an integrated back-side DTP interconnect 150. As shown in FIG6, the multilayer die sub-component 104 may include a first layer 104-1 having a die 114-1 and a conductive pillar 152, and a second layer 104-2 having a die 114-2. The first layer 104-1 may include a first surface 170-1 and an opposing second surface 170-2. In particular, the multilayer die sub-component 104 may include a first die 114-1 in the first dielectric layer 104-1 and a second die 114-2 in the second dielectric layer 104-2, which are coupled to the first die 114-1 through a hybrid bonding region 130. Die 114-1 may include a first substrate layer 128 having a TSV 118 at a first surface 170-1, a first metallization stack 126 on the first substrate layer 128, a second substrate layer 120 on the first metallization stack 126, a device layer 124 having a device 125 on the substrate layer 120, a second metallization stack 122 on the device layer (e.g., at the second surface 170-2), and a DTP interconnect 150 at the first surface 170-1, which is coupled to the first metallization stack 126 in the first die 114-1 via the TSV 118 in the first substrate layer 128. In some embodiments, the second substrate layer 120 may be omitted. Die 114-1 may be coupled to the package substrate 102 via the back-side DTP interconnect 150, while die 114-2 in the second layer 104-2 may be coupled to the package substrate 102 via an ML interconnect.

[0049] FIG7 is a side cross-sectional view of an exemplary microelectronic component according to various embodiments. The microelectronic component 100 may include a multilayer die sub-component 104 having an integrated back-side DTP interconnect 150. As shown in FIG7, the multilayer die sub-component 104 may include a redistribution layer (RDL) 148 having DTP interconnect 150 on a bottom surface, a first layer 104-1 on a top surface of the RDL 148, and a second layer 104-2 on the first layer 104-1. The first layer 104-1 may include a first surface 170-1 and an opposing second surface 170-2. In particular, the multilayer die sub-component 104 may include a first dielectric layer 104-1, an RDL 148 coupled to the first surface 170-1 of the first layer 104-1, and a second dielectric layer 104-2 coupled to the second surface 170-2 of the first dielectric layer 104-1. The first dielectric layer 104-1 may include a first die 114-1, a second die 114-2, and a conductive pillar 152 embedded therein, while the second dielectric layer 104-2 may include a third die 114-3 embedded therein, which is coupled to the first die 114-1 and the second die 114-2 through a hybrid bonding region 130. Dies 114-1 and 114-2 may include a first substrate layer 128 having a TSV 118 at a first surface 170-1, a first metallization stack 126 on the first substrate layer 128, a second substrate layer 120 on the first metallization stack 126, a device layer 124 having a device 125 on the substrate layer 120, and a second metallization stack 122 on the device layer (e.g., at the second surface 170-2). In some embodiments, the second substrate layer 120 may be omitted. The first metallization stack 126 in individual dies 114-1 and 114-2 can be coupled to the DTP interconnect 150 on the bottom surface of the RDL 148 via conductive paths in the TSV 118 and RDL 148 in the first substrate layer 128. Dies 114-1 and 114-2 can be coupled to the package substrate 102 via the back-side DTP interconnect 150, while die 114-3 in the second layer 104-2 can be coupled to the package substrate 102 via the DTP interconnect 150 through conductive pillars 152 of the ML interconnect. Although FIG7 shows a specific number and arrangement of the microelectronic component 100, including a plurality of embedded first, second, and third dies 114 and a single RDL 148, the microelectronic component 100 can include any number and arrangement of dies 114 and RDL 148, including two or more RDL 148 and including one RDL 148 at the second surface 170-2 of the first dielectric layer 104-1.

[0050] The microelectronic component 100 disclosed herein can be manufactured using any suitable technique. For example, Figures 8A-8J are side cross-sectional views of various stages in an exemplary process for manufacturing the microelectronic component 100 of Figure 3 according to various embodiments. Although the operations discussed below with reference to Figures 8A-8J (and other figures illustrating the manufacturing process) are shown in a particular order, these operations can be performed in any suitable order.

[0051] FIG8A illustrates the assembly after the first die 114-1 is placed on the first carrier 105-1, wherein the active surface (e.g., metallization stack 122) faces the first carrier 105-1. The first die 114-1 may include the active-side metallization stack 122, a device layer 124 having means 125, and a substrate 120 having µTSV 123 (e.g., on the back side opposite the active surface), wherein the substrate 120 includes a non-electrical material on or above the µTSV 123. The non-electrical material, which is the inactive portion of the die 114-1, may include silicon, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, other materials classified as group III-V, or insulating materials such as silicon dioxide (glass), ceramics, or quartz. The carrier 105 may comprise any suitable material, and in some embodiments may comprise a semiconductor wafer (e.g., a silicon wafer) or glass (e.g., a glass panel). The first die 114-1 may be attached to the first carrier 105-1 using any suitable technique, including a temporary adhesive layer or a die attach film (DAF).

[0052] FIG8B shows the assembly after the non-electric material has been removed from the top surface of the substrate 120, exposing the top surface of the µTSV 123. Any suitable technique can be used to remove the non-electric material, including, for example, grinding, etching, such as reactive ion etching (RIE) or chemical etching. In some embodiments, the top surface of the substrate 120 may be polished to expose the top surface of the µTSV 123. In some embodiments, when the assembly of FIG8A does not include the µTSV 123, the µTSV 123 may be formed in the substrate material 120 after thinning the non-electric material at the top surface of the substrate 120. In some embodiments, the first grain 114-1 may be processed at the wafer level and subsequently singulated.

[0053] FIG8C shows the assembly after a back-side metallization stack 126 is formed on the top surface of the assembly of FIG8B, the back-side metallization stack 126 and the active-side metallization stack 122 are electrically coupled through µTSV 123 in the substrate 120, and a conductive pad 142 is formed on the top surface of the back-side metallization stack 126. The die 114-1 can be functionally tested using the conductive pad 142 or the top metal layer in the stack 126 to determine whether the die 114-1 is KGD before performing further processing.

[0054] Figure 8D shows the assembly after the second carrier 105-2 has been mounted onto the top surface of the assembly in Figure 8C.

[0055] Figure 8E shows the components after reversing the components of Figure 8D and removing the first carrier 105-1.

[0056] FIG8F shows the assembly after an exposed HB interface 180 is formed on the top surface of the assembly of FIG8E (e.g., on the active-side metallization stack 122), wherein the HB interface 180 includes an HB contact 110 surrounded by an HB dielectric 108.

[0057] FIG8G shows the assembly after the second grain 114-2 is mixed and bonded to the top surface of the assembly of FIG8F. In particular, the HB interface 180 (not labeled) of the second grain 114-2 can be made to contact the HB interface of the first grain 114-1, and heat and / or pressure can be applied to bond the contacting HB interface 180 to form the HB region 130.

[0058] Figure 8H shows the components after reversing the components of Figure 8G and removing the second carrier 105-2.

[0059] Figure 8I illustrates the assembly following the formation of conductive pillars 152, the deposition of insulating material 133 on and around the first die 114-1 and conductive pillars 152, and the formation of conductive contacts 132 for DTP interconnection on the top surfaces of the first die 114-1 and conductive pillars 152. The conductive pillars 152 can be formed using any suitable technique, such as lithography or additive processes like cold spraying or 3D printing. For example, the conductive pillars 152 can be formed by depositing, exposing, and developing a photoresist layer on the top surface of the die 114-2. The photoresist layer can be patterned to form cavities in the shape of conductive pillars. A conductive material such as copper can be deposited in the openings in the patterned photoresist layer to form the conductive pillars 152. Any suitable process can be used to deposit the conductive material, such as electroplating, sputtering, or electroless plating. The photoresist can be removed to expose the conductive pillars 152. In another example, a photoimageable dielectric can be used to form the conductive pillars 152. In some embodiments, insulating material 133 may initially be deposited on and above the top surfaces of the first grain 114-1 and conductive pillar 152, and then back-polished to expose the top surfaces of the first grain 114-1 and conductive pillar 152. Any suitable process can be used to form insulating material 133, including lamination or slot coating and curing. If insulating material 133 is formed to completely cover the first grain 114-1 and conductive pillar 152, any suitable technique can be used to remove insulating material 133, including grinding or etching, such as wet etching, dry etching (e.g., plasma etching), wet blasting, or laser ablation (e.g., using an excimer laser). In some embodiments, the thickness of insulating material 133 can be minimized to reduce the required etching time. Functional testing of grain 114-1 and / or grain 114-2 can be performed using conductive contacts 132 to determine if grains 114-1 and 114-2 are KGD before performing further processing.

[0060] Figure 8J shows the component after the component of Figure 8I has been reversed. The component of Figure 8J can be a microelectronic component 100, as shown, or further manufacturing operations can be performed on the microelectronic component 100 of Figure 8J to form other microelectronic components 100, for example, as shown in Figure 3. For example, the component of Figure 8J can be electrically coupled to a package substrate via a DTP interconnect, which is achieved by printing solder paste on conductive contacts 132, placing the component of Figure 8J on the package substrate using a pick-and-place tool, subjecting the solder paste to thermal reflow, and cleaning.

[0061] Figures 9A-9D are side cross-sectional views of various stages in an exemplary process for manufacturing the microelectronic component of Figure 1 according to various embodiments. Figure 9A shows the component of Figure 8E after performing the process described above with reference to Figures 8A-8E.

[0062] FIG9B illustrates an assembly after forming conductive pillars 152 on a second carrier 105-2, depositing insulating material 133 on and around the first die 114-1 and conductive pillars 152, and forming an exposed HB interface 180 on the top surface of the insulating material 133, conductive pillars 152, and die 114-1 (e.g., on the active-side metallization stack 122), wherein the HB interface 180 includes HB contacts 110 surrounded by HB dielectric 108. The conductive pillars 152 and insulating material 133 can be formed as described above with reference to FIG8I.

[0063] FIG9C shows the assembly after the second grain 114-2 and the third grain 114-3 are mixed and bonded to the top surface of the assembly of FIG9B, and after an insulating material 133 is deposited on and around the second and third grains 114-2, 114-3. In particular, the HB interfaces 180 (not labeled) of the second grain 114-2 and the third grain 114-3 can be made to contact the HB interface of the first grain 114-1, and heat and / or pressure can be applied to bond the contacting HB interfaces 180 to form HB regions 130-1 and 130-2, respectively. The insulating material 133 can be deposited as described above with reference to FIG8I. In some embodiments, the insulating material 133 on and around the second and third grains 114-2, 114-3 can be omitted. In this embodiment, the second and third grains 114-2, 114-3 can be supported by an underlying structure (e.g., the assembly of FIG9B). In some embodiments, a mechanical support substrate, such as a permanent carrier (not shown), may be attached to the top surface of the component of FIG9C (e.g., the top surface of the second and third grains 114-2, 114-3) to provide further mechanical support.

[0064] FIG9D shows the assembly after the second carrier 105-2 has been removed and conductive contacts 132 for DTP interconnection have been formed on the bottom surface of the assembly of FIG9C. The conductive contacts 132 can be used to perform functional testing on the dies 114-1, 114-2, and 114-3 to determine that the dies 114-1, 114-2, and 114-3 are KGD before performing further processing. The assembly of FIG9D can be a microelectronic assembly 100, as shown, or further manufacturing operations can be performed on the microelectronic assembly 100 of FIG9D to form other microelectronic assemblies 100, for example, as shown in FIG1. ​​For example, the assembly of FIG9D can be electrically coupled to a package substrate via DTP interconnection by printing solder paste on the conductive contacts 132, placing the assembly of FIG9D on the package substrate using a pick-and-place tool, subjecting the solder paste to thermal reflow, and cleaning.

[0065] Figures 10A-10G are side cross-sectional views of various stages in an exemplary process for manufacturing the microelectronic component of Figure 5 according to various embodiments. Figure 10A shows the component of Figure 8D after performing the process as described above with reference to Figures 8A-8D, wherein the second carrier 105-2 mounted to the top surface includes a substrate 128 and a TSV 118 (e.g., the second carrier 105-2 becomes a permanent part of the microelectronic component 100 of Figure 5).

[0066] FIG10B shows the assembly after reversing the assembly of FIG10A, removing the first carrier 105-1, and forming an exposed HB interface 180 on the top surface of the die 114-1 (e.g., on the active side metallization stack 122), wherein the HB interface 180 includes an HB contact 110 surrounded by an HB dielectric 108.

[0067] FIG10C illustrates an assembly with a second die 114-2 and a third die 114-3 placed on a third carrier 105-3, with their back sides (e.g., non-active sides) facing the third carrier 105-3. The top surfaces of the second and third dies 114-2, 114-3 may each include exposed HB interfaces 180-1, 180-2, wherein the HB interface 180 includes an HB contact 110 surrounded by an HB dielectric 108. In some embodiments, an insulating material 133 (not shown) may be deposited on and around the second and third dies 114-2, 114-3, as described above with reference to FIG8I.

[0068] FIG10D shows an assembly after a first die 114-1 (e.g., the assembly of FIG10B in reverse) has been co-bonded to a second die 114-2 and a third die 114-3 (e.g., co-bonded to the top surface of the assembly of FIG10C). In particular, the HB interface 180 (not labeled) of the first die 114-1 can be made to contact the HB interfaces of the second die 114-2 and the third die 114-3, and heat and / or pressure can be applied to bond the contacting HB interfaces 180 to form HB regions 130-1 and 130-2, respectively.

[0069] FIG10E shows the assembly after the non-electric material has been removed from the back side (e.g., top surface) of the substrate 128 and the top surface of the TSV 118 has been exposed. Any suitable technique can be used to remove the non-electric material, including, for example, those described above with reference to FIG8B.

[0070] Figure 10F illustrates an assembly after conductive pillars 152 are formed on the second and third dies 114-2, 114-3, insulating material 133 is deposited on and around the first die 114-1 and conductive pillars 152, and conductive contacts 132 for DTP interconnection are formed on the top surface of the assembly. The conductive contacts 132 can be used to perform functional testing on the dies 114-1, 114-2, 114-3 to determine if the dies 114-1, 114-2, 114-3 are KGD (Knowledge-Growth Die-Done) before performing further processing. In some embodiments, insulating material 133 can be deposited on and around the second and third dies 114-2, 114-3.

[0071] Figure 10G shows the component after inverting the component of Figure 10F and removing the third carrier 105-3. The component of Figure 10G can be a microelectronic component 100, as shown, or further manufacturing operations can be performed on the microelectronic component 100 of Figure 10G to form other microelectronic components 100, for example, as shown in Figure 5. For example, the component of Figure 10G can be electrically coupled to a package substrate via a DTP interconnect, which is achieved by printing solder paste on conductive contacts 132, placing the component of Figure 10G on the package substrate using a pick-and-place tool, subjecting the solder paste to thermal reflow, and cleaning.

[0072] Figures 11A-11D are side cross-sectional views of various stages in an exemplary process for manufacturing the microelectronic component of Figure 7 according to various embodiments.

[0073] FIG11A is an assembly after the process described above with reference to FIG10A-10B is performed on the first and second dies 114-1, 114-2 and the first and second dies 114-1, 114-2 are mixed and bonded to the third die 114-3. In particular, the HB interface 180 (not labeled) of the first die 114-1 and the second die 114-2 can be brought into contact with the HB interface of the third die 114-3, and heat and / or pressure can be applied to bond the contacting HB interfaces 180 to form HB regions 130-1 and 130-2, respectively.

[0074] FIG11B illustrates an assembly after removing non-electrical material from the top surface (e.g., back side) of the substrate 128 of the first and second grains 114-1, 114-2 to expose the top surface of the TSV 118, forming conductive pillars 152 on the top surface of the third grain 114-3, and depositing insulating material 133 on and around the first grain 114-1, the second grain 114-2, and the conductive pillars 152. In some embodiments, non-electrical material may be removed from the top surface of the substrate 128 of the first and second grains 114-1, 114-2 along with the insulating material 133. The conductive pillars 152 and the insulating material 133 may be formed using any suitable technique, including those described above with reference to FIG8I. The insulating material 133 may be removed using any suitable technique, including those described above with reference to FIG8I. Non-electrical material of the substrate 128 may be removed using any suitable technique, including those described above with reference to FIG8B.

[0075] FIG11C shows the assembly after RDL 148 has been formed on the top surface of the assembly of FIG11B. RDL 148 may include conductive contacts on the bottom surface coupled to first and second dies 114-1, 114-2 through TSV 118 in substrate 128, and conductive contacts 132 on the top surface for coupling to the package substrate through DTP interconnect. RDL 148 may be manufactured using any suitable technology, such as PCB technology, redistribution layer technology, or damascene process.

[0076] Figure 11D shows the assembly after reversing the assembly of Figure 11C. The assembly of Figure 11D itself can be a microelectronic assembly 100, as shown. Further manufacturing operations can be performed on the microelectronic assembly 100 of Figure 11D to form other microelectronic assemblies 100, such as those shown in Figure 7. For example, further processing may include depositing a solder mask layer, attaching solder balls, and electrically coupling a package substrate 102 to the bottom surface of the assembly of Figure 11D via DTP interconnects 150. The dies 114-1, 114-2, and 114-3 can be functionally tested using conductive contacts 132 to determine that the dies 114-1, 114-2, and 114-3 are KGDs before performing further processing.

[0077] The microelectronic component 100 disclosed herein can be used in any suitable application. For example, in some embodiments, the microelectronic component 100 can be used to implement very small voltage regulation for a field-programmable gate array (FPGA) or processing unit (e.g., central processing unit, graphics processing unit, FPGA, modem, application processor, etc.) (especially in mobile devices and small-size devices). In another example, the die 114 in the microelectronic component 100 can be a processing device (e.g., central processing unit, graphics processing unit, FPGA, modem, application processor, etc.).

[0078] The microelectronic component 100 disclosed herein may be included in any suitable electronic component. Figures 12-15 illustrate various examples of devices that may be included in or incorporated into any microelectronic component 100 disclosed herein.

[0079] FIG12 is a top view of a wafer 1500 and a die 1502 that may be included in any microelectronic component 100 disclosed herein (e.g., as any suitable die 114). The wafer 1500 may be made of semiconductor material and may include one or more dies 1502 having an IC structure formed on the surface of the wafer 1500. Each die 1502 may be a repeating unit of a semiconductor product including any suitable IC. After the semiconductor product is manufactured, the wafer 1500 may undergo a monolithization process in which the dies 1502 are separated from each other to provide discrete "wafers" of the semiconductor product. The die 1502 may be any die 114 disclosed herein. The die 1502 may include one or more transistors (e.g., some transistors 1640 of FIG13, discussed below), support circuitry for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other IC components. In some embodiments, wafer 1500 or die 1502 may include memory elements (e.g., random access memory (RAM) elements, such as static RAM (SRAM), magnetic RAM (MRAM), resistive RAM (RRAM), bridge RAM (CBRAM), etc.), logic elements (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple elements of these elements may be combined on a single die 1502. For example, a memory array formed by multiple memory elements may be formed on the same die 1502 as a processing device (e.g., processing device 1802 of FIG. 15) or other logic configured to store information in the memory elements or execute instructions stored in the memory array. In some embodiments, die 1502 (e.g., die 114) may be a central processing unit, a radio frequency chip, a power converter, or a network processor. The various microelectronic components 100 disclosed herein can be manufactured using a die-to-wafer level assembly technique in which some dies 114 are attached to a wafer 1500 that includes other dies 114, and the wafer 1500 is subsequently monolithized.

[0080] FIG. 13 is a cross-sectional side view of an IC device 1600 that may be included in any microelectronic component 100 disclosed herein (e.g., in any die 114). One or more IC devices 1600 may be included in one or more dies 1502 (FIG. 12). IC devices 1600 may be formed on a die substrate 1602 (e.g., wafer 1500 of FIG. 12) and may be included in a die (e.g., die 1502 of FIG. 12). Die substrate 1602 may be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination of both). Die substrate 1602 may include, for example, a crystal substrate formed using bulk silicon or silicon-on-insulator (SOI) substructures. In some embodiments, the die substrate 1602 may be formed using alternative materials, which may or may not be bonded to silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Groups II-VI, III-V, or IV may also be used to form the die substrate 1602. While several examples of materials that can form the die substrate 1602 have been described herein, any material that can serve as the basis for the IC device 1600 may be used. The die substrate 1602 may be a single-cut die (e.g., die 1502 of FIG. 12) or a portion of a wafer (e.g., wafer 1500 of FIG. 12).

[0081] The IC device 1600 may include one or more device layers 1604 disposed on a die substrate 1602. Device layer 1604 may include features of one or more transistors 1640 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1602. Device layer 1604 may include, for example, one or more source and / or drain (S / D) regions 1620, gates 1622 controlling current flow in the transistors 1640 between the S / D regions 1620, and one or more S / D contacts 1624 routing electrical signals to / from the S / D regions 1620. Transistors 1640 may include additional features not shown for clarity, such as device isolation regions, gate contacts, etc. Transistors 1640 are not limited to the types and configurations shown in FIG. 13, and may include a variety of other types and configurations, such as, for example, planar transistors, non-planar transistors, or combinations of both. Non-planar transistors can include FinFET transistors, such as dual-gate or triple-gate transistors, and wrap-around or all-around gate transistors, such as nanoband and nanowire transistors.

[0082] Each transistor 1640 may include a gate 1622 formed of at least two layers, a gate dielectric, and a gate electrode. The gate dielectric may include a single layer or a stack of layers. The single or multiple layers may include silicon oxide, silicon dioxide, silicon carbide, and / or high-k dielectric materials. High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used in gate dielectrics include, but are not limited to: hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminate, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when using high-k materials, the gate dielectric may be annealed to improve its quality.

[0083] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or an n-type work function metal, depending on whether the transistor 1640 is a PMOS or an NMOS transistor. In some embodiments, the gate electrode may consist of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a filler metal layer. Other metal layers, such as barrier layers, may be included for other purposes. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any metals discussed below with reference to NMOS transistors (e.g., for work function adjustment). For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any metals discussed above with reference to PMOS transistors (e.g., for work function adjustment).

[0084] In some embodiments, when considered as a cross-section of the transistor 1640 along the source-channel-drain direction, the gate electrode may be composed of a U-shaped structure including a bottom portion substantially parallel to the surface of the die substrate 1602 and two sidewall portions substantially perpendicular to the top surface of the die substrate 1602. In other embodiments, at least one of the metal layers forming the gate electrode may be merely a planar layer substantially parallel to the top surface of the die substrate 1602 and does not include sidewall portions substantially perpendicular to the top surface of the die substrate 1602. In other embodiments, the gate electrode may be composed of a combination of U-shaped structures and planar non-U-shaped structures. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on one or more planar non-U-shaped layers.

[0085] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to support the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming the sidewall spacers are well known in the art and typically include deposition and etching steps. In some embodiments, a plurality of spacer pairs may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0086] The S / D region 1620 may be formed within the die substrate 1602, adjacent to the gate 1622 of each transistor 1640. The S / D region 1620 can be formed using, for example, an implantation / diffusion process or an etching / deposition process. In the former process, dopant ions such as boron, aluminum, antimony, phosphorus, or arsenic can be implanted into the die substrate 1602 to form the S / D region 1620. Following the ion implantation process, an annealing process can be performed to activate the dopant and further diffuse it into the die substrate 1602. In the latter process, the die substrate 1602 can be etched first to form a groove at the location of the S / D region 1620. An epitaxial deposition process can then be performed to fabricate the material-filled grooves of the S / D region 1620. In some embodiments, the S / D region 1620 can be fabricated using a silicon alloy such as germanium silicon or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy can be in-situ doped using dopants such as boron, arsenic, or phosphorus. In some embodiments, the S / D region 1620 can be formed using one or more alternative semiconductor materials such as germanium or group III-V materials or alloys. In further embodiments, one or more layers of metal and / or metal alloys can be used to form the S / D region 1620.

[0087] Electrical signals, such as power and / or input / output (I / O) signals, can be routed to and / or from devices (e.g., transistor 1640) on device layer 1604 through one or more interconnect layers (shown as interconnect layers 1606-1610 in FIG. 13). For example, conductive features of device layer 1604 (e.g., gate 1622 and S / D contact 1624) can be electrically coupled to interconnect structure 1628 of interconnect layers 1606-1610. One or more interconnect layers 1606-1610 can form a metallization stack (also referred to as an "ILD stack") 1619 of IC device 1600.

[0088] Interconnect structure 1628 may be arranged within interconnect layers 1606-1610 to route electrical signals according to a variety of designs; in particular, the arrangement is not limited to the specific configuration of interconnect structure 1628 depicted in FIG13. Although a specific number of interconnect layers 1606-1610 are depicted in FIG13, embodiments of this disclosure include IC devices having more or fewer interconnect layers than depicted.

[0089] In some embodiments, the interconnect structure 1628 may include lines 1628a and / or vias 1628b filled with a conductive material such as metal. Lines 1628a may be arranged to route electrical signals in a direction parallel to a plane substantially parallel to the surface of the die substrate 1602 on which the device layer 1604 is formed. For example, from the perspective view of FIG. 13, lines 1628a may route electrical signals in a direction in and out of a page. Vias 1628b may be arranged to route electrical signals in a direction substantially perpendicular to a plane substantially perpendicular to the surface of the die substrate 1602 on which the device layer 1604 is formed. In some embodiments, vias 1628b may electrically couple lines 1628a of different interconnect layers 1606-1610 together.

[0090] Interconnect layers 1606-1610 may include dielectric material 1626 disposed between interconnect structures 1628, as shown in FIG13. In some embodiments, the dielectric material 1626 disposed between interconnect structures 1628 in different interconnect layers 1606-1610 may have different compositions; in other embodiments, the composition of the dielectric material 1626 between different interconnect layers 1606-1610 may be the same.

[0091] The first interconnect layer 1606 (referred to as metal 1 or "M1") may be formed directly on the device layer 1604. In some embodiments, the first interconnect layer 1606 may include a line 1628a and / or a via 1628b, as shown. The line 1628a of the first interconnect layer 1606 may be coupled to a contact (e.g., S / D contact 1624) of the device layer 1604.

[0092] The second interconnect layer 1608 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include a via 1628b for coupling lines 1628a of the second interconnect layer 1608 to lines 1628a of the first interconnect layer 1606. Although for clarity, lines 1628a and vias 1628b are structurally depicted as lines within each interconnect layer (e.g., within the second interconnect layer 1608), in some embodiments, lines 1628a and vias 1628b may be continuous in structure and / or material (e.g., simultaneously filled during a dual damascene process).

[0093] The third interconnect layer 1610 (referred to as metal 3 or "M3") (and additional interconnect layers, as needed) may be formed sequentially on the second interconnect layer 1608 according to a similar technique and configuration as described in conjunction with the second interconnect layer 1608 or the first interconnect layer 1606. In some embodiments, the interconnect layers that are "higher" (i.e., further away from the device layer 1604) in the metallization stack 1619 in the IC device 1600 may be thicker.

[0094] The IC device 1600 may include a solder resist 1634 (e.g., polyimide or a similar material) and one or more conductive contacts 1636 formed on interconnect layers 1606-1610. In FIG. 13, the conductive contacts 1636 are shown in the form of bond pads. The conductive contacts 1636 may be electrically coupled to interconnect structure 1628 and configured to route electrical signals from transistor 1640 to other external devices. For example, solder joints may be formed on one or more conductive contacts 1636 to mechanically and / or electrically couple a die including the IC device 1600 to another component (e.g., a circuit board). The IC device 1600 may include additional or alternative structures to route electrical signals from interconnect layers 1606-1610; for example, the conductive contacts 1636 may include other similar features (e.g., pillars) to route electrical signals to external components.

[0095] In some embodiments where the IC device 1600 is a double-sided die (e.g., like die 114-1), the IC device 1600 may include another metallization stack (not shown) on the opposite side of the device layer 1604. This metallization stack may include multiple interconnect layers as discussed above with reference to interconnect layers 1606-1610 to provide a conductive path (e.g., including conductive lines and vias) between the device layer 1604 and additional conductive contacts (not shown) on the side of the IC device 1600 opposite to the conductive contact 1636.

[0096] In other embodiments where the IC device 1600 is a double-sided die (e.g., like die 114-1), the IC device 1600 may include one or more TSVs through the die substrate 1602; these TSVs may contact the device layer 1604 and may provide a conductive path between the device layer 1604 and an additional conductive contact (not shown) on the side of the IC device 1600 opposite to the conductive contact 1636.

[0097] FIG14 is a cross-sectional side view of an IC device assembly 1700 that may include any microelectronic component 100 disclosed herein. In some embodiments, the IC device assembly 1700 may be the microelectronic component 100. The IC device assembly 1700 includes a plurality of elements disposed on a circuit board 1702 (which may be, for example, a motherboard). The IC device assembly 1700 includes elements disposed on a first surface 1740 of the circuit board 1702 and on an opposing second surface 1742 of the circuit board 1702; typically, the elements may be disposed on one or both of surfaces 1740 and 1742. Any IC package discussed below with reference to the IC device assembly 1700 may take the form of any suitable embodiment of the microelectronic component 100 disclosed herein.

[0098] In some embodiments, the circuit board 1702 may be a PCB, comprising a plurality of metal layers separated from each other by dielectric material layers and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to the circuit board 1702 (optionally combined with other metal layers). In other embodiments, the circuit board 1702 may be a non-PCB substrate. In some embodiments, the circuit board 1702 may be, for example, a circuit board.

[0099] The IC device assembly 1700 shown in FIG. 14 includes an interposer-on-agent package structure 1736, which is coupled to a first side 1740 of a circuit board 1702 via a coupling element 1716. The coupling element 1716 can electrically and mechanically couple the interposer-on-agent package structure 1736 to the circuit board 1702, and may include solder balls (e.g., as shown in FIG. 14), male and female portions of a socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0100] The interposer-on-package structure 1736 may include an IC package 1720 coupled to the interposer 1704 via a coupling element 1718. The coupling element 1718 may take any form suitable for the application, such as the form discussed above with reference to coupling element 1716. Although a single IC package 1720 is shown in FIG. 14, multiple IC packages may be coupled to the interposer 1704; in fact, additional interposers may be coupled to the interposer 1704. The interposer 1704 may provide an intermediate substrate for bridging the circuit board 1702 and the IC package 1720. The IC package 1720 may be or include, for example, a die (die 1502 of FIG. 12), an IC device (e.g., IC device 1600 of FIG. 13), or any other suitable element. Typically, the interposer 1704 may extend connections to a wider pitch or reroute connections to different connections. For example, interposer 1704 can couple IC package 1720 (e.g., a die) to a set of ball grid array (BGA) conductive contacts of coupling element 1716 for coupling to circuit board 1702. In the embodiment shown in FIG. 14, IC package 1720 and circuit board 1702 are attached to opposite sides of interposer 1704; in other embodiments, IC package 1720 and circuit board 1702 may be attached to the same side of interposer 1704. In some embodiments, three or more components may be interconnected through interposer 1704.

[0101] In some embodiments, the interposer 1704 may be formed as a PCB, comprising a plurality of metal layers separated from each other by dielectric material layers and interconnected by conductive vias. In some embodiments, the interposer 1704 may be formed of epoxy resin, glass fiber reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic materials, or polymeric materials such as polyimide. In some embodiments, the interposer 1704 may be formed of alternative rigid or flexible materials, which may include the same materials as those described above for semiconductor substrates, such as silicon, germanium, and other group III-V and IV materials. The interposer 1704 may include metal interconnects 1708 and vias 1710, including but not limited to TSV 1706. The interposer 1704 may also include embedded devices 1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, can also be formed on the interposer 1704. The interposer-on-package structure 1736 can take the form of any interposer-on-package structure known in the art.

[0102] The IC device assembly 1700 may include an IC package 1724 coupled to a first side 1740 of the circuit board 1702 via a coupling element 1722. The coupling element 1722 may take the form of any embodiment discussed above with reference to coupling element 1716, and the IC package 1724 may take the form of any embodiment discussed above with reference to IC package 1720.

[0103] The IC device assembly 1700 shown in FIG. 14 includes a package-on-package structure 1734 coupled to a second side 1742 of a circuit board 1702 via a coupling element 1728. The package-on-package structure 1734 may include IC package 1726 and IC package 1732 coupled together via a coupling element 1730, such that IC package 1726 is disposed between the circuit board 1702 and IC package 1732. The coupling elements 1728 and 1730 may take the form of any embodiment of the coupling element 1716 discussed above, while IC packages 1726 and 1732 may take the form of any embodiment of the IC package 1720 discussed above. The package-on-package structure 1734 may be configured according to any stacked encapsulation structure known in the art.

[0104] FIG15 is a block diagram of an exemplary electronic device 1800 that may include one or more microelectronic components 100 disclosed herein. For example, any suitable element of electronic device 1800 may include one or more of the IC device assembly 1700, IC device 1600, or die 1502 disclosed herein, and may be arranged within any microelectronic component 100 disclosed herein. Many elements are shown in FIG15 as included in electronic device 1800, but any one or more of these elements may be omitted or repeated to suit the application. In some embodiments, some or all of the elements included in electronic device 1800 may be attached to one or more motherboards. In some embodiments, some or all of these elements are manufactured on a single system-on-a-chip (SoC) die.

[0105] Furthermore, in various embodiments, electronic device 1800 may not include one or more of the elements shown in FIG. 15, but electronic device 1800 may include interface circuitry for coupling to the one or more elements. For example, electronic device 1800 may not include display device 1806, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which display device 1806 may be coupled. In another set of examples, electronic device 1800 may not include audio input device 1824 or audio output device 1808, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which audio input device 1824 or audio output device 1808 may be coupled.

[0106] Electronic device 1800 may include processing device 1802 (e.g., one or more processing devices). As used herein, the terms "processing device" or "processor" may refer to any means or part of a means of processing electronic data from a register and / or memory to convert the electronic data into other electronic data that can be stored in the register and / or memory. Processing device 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing means. Electronic device 1800 may include memory 1804, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard disks. In some embodiments, memory 1804 may include memory that shares a die with processing device 1802. This memory can be used as cache memory and can include embedded dynamic random access memory (eDRAM) or spin torque magnetic random access memory (STT-MRAM).

[0107] In some embodiments, electronic device 1800 may include a communication chip 1812 (e.g., one or more communication chips). For example, communication chip 1812 may be configured to manage wireless communications to transmit data to and from electronic device 1800. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc., which can transmit data using modulated electromagnetic radiation through a non-solid medium. This term does not imply that the associated device does not contain any wires, although they may not in some embodiments.

[0108] The communication chip 1812 can implement any of a variety of wireless standards or protocols, including but not limited to IEEE standards, such as Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 revision), Long Term Evolution (LTE) initiatives, and any revisions, updates, and / or modifications (e.g., Advanced LTE initiatives, Ultra Mobile Broadband (UMB) initiatives (also known as "3GPP2"), etc.). IEEE 802.16 compliant broadband wireless access (BWA) networks are commonly referred to as WiMAX networks, which is an abbreviation for Worldwide Interoperability for Microwave Access, a certification mark for products that have passed conformance and interoperability testing of the IEEE 802.16 standard. The communication chip 1812 can operate according to Global System for Mobile Communications (GSM), Universal Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication chip 1812 can operate according to GSM Evolution Enhanced Data (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1812 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Wireless Telecommunications (DECT), Evolved Data Optimization (EV-DO) and its derivatives, and any other wireless protocol designated as 3G, 4G, 5G, or higher. In other embodiments, the communication chip 1812 can operate according to other wireless protocols. The electronic device 1800 may include an antenna 1822 for facilitating wireless communication and / or receiving other wireless communications (such as AM or FM radio transmissions).

[0109] In some embodiments, the communication chip 1812 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 1812 may include multiple communication chips. For example, a first communication chip 1812 may be dedicated to short-range wireless communications, such as Wi-Fi or Bluetooth, while a second communication chip 1812 may be dedicated to long-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication chip 1812 may be dedicated to wireless communications, while the second communication chip 1812 may be dedicated to wired communications.

[0110] Electronic device 1800 may include battery / power circuit 1814. Battery / power circuit 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling elements of electronic device 1800 to an energy source (e.g., AC line power) separate from electronic device 1800.

[0111] Electronic device 1800 may include display device 1806 (or corresponding interface circuitry, as described above). Display device 1806 may include any visual indicator, such as a head-up display, computer screen display, projector, touch screen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0112] Electronic device 1800 may include audio output device 1808 (or corresponding interface circuitry, as described above). Audio output device 1808 may include any device that generates sound indication, such as a speaker, headphones, or earphones.

[0113] Electronic device 1800 may include audio input device 1824 (or corresponding interface circuitry, as described above). Audio input device 1824 may include any means of generating signals representing sound, such as a microphone, microphone array, or digital musical instrument (e.g., a musical instrument with a Musical Instrument Digital Interface (MIDI) output).

[0114] Electronic device 1800 may include GPS device 1818 (or corresponding interface circuitry, as described above). GPS device 1818 may communicate with satellite-based systems and may receive the location of electronic device 1800, as is known in the art.

[0115] Electronic device 1800 may include other output devices 1810 (or corresponding interface circuitry, as described above). Examples of other output devices 1810 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0116] Electronic device 1800 may include other input devices 1820 (or corresponding interface circuitry, as described above). Examples of other input devices 1820 may include accelerometers, gyroscopes, compasses, image capturing devices, keyboards, cursor control devices such as mice, styluses, touchpads, barcode readers, quick-response (QR) code readers, any sensors, or radio frequency identification (RFID) readers.

[0117] The electronic device 1800 may have any desired form factor, such as a computing device or a handheld, portable, or mobile computing device (e.g., a mobile phone, smartphone, mobile network device, music player, tablet computer, laptop, lightweight notebook computer, ultrathin notebook computer, personal digital assistant (PDA), supercomputer, etc.), desktop electronic device, server, or other network computing element, printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable computing device. In some embodiments, the electronic device 1800 may be any other electronic device for processing data.

[0118] The following paragraphs provide various examples of the embodiments disclosed herein.

[0119] Example 1 is a microelectronic component including a first die in a first layer having a first surface and an opposing second surface, the first die including a first metallization stack at the first surface; a device layer on the first metallization stack including devices; a second metallization stack on the device layer; and an interconnect at the first surface electrically coupled to the first metallization stack; a conductive pillar in the first layer; and a second die in a second layer on the first layer having a first surface and an opposing second surface, wherein the first surface of the second die is coupled to the second surface of the first die and to the conductive pillar through a hybrid bonding region.

[0120] Example 2 may include the subject matter of Example 1, and may also specify that the hybrid bonding region is a first hybrid bonding region, and may further include a third grain in the second layer having a first surface and an opposing second surface, wherein the first surface of the third grain is coupled to the second surface of the first grain through the second hybrid bonding region.

[0121] Example 3 may include the subject matter of Example 1 or 2, and may also specify that the interconnection is part of a power transmission network.

[0122] Example 4 may include the subject matter of any one of Examples 1 to 3, and may also include a substrate layer between the first metallization stack and the device layer, the substrate layer including microsilicon through-holes (µTSV).

[0123] Example 5 may include the subject matter of Example 4 and may also specify that the µTSV electrically couples the device in the device layer to the first metallization stack.

[0124] Example 6 may include the subject matter of any one of Examples 1 to 5, and may also include a packaging substrate electrically coupled to the first surface of the first die through the interconnect, and electrically coupled to the first surface of the second die through the conductive pillar.

[0125] Example 7 may include the subject matter of any one of Examples 1 to 6, and may also specify that the interconnect is a first interconnect, and may further include a third die having a first surface with a second interconnect and an opposing second surface, which is electrically coupled to the first surface of the first die through the first interconnect, and electrically coupled to the first surface of the second die through the conductive pillar.

[0126] Example 8 may include the subject matter of Example 7 and may also specify that the second interconnection is part of a power transmission network.

[0127] Example 9 may include the subject matter of Example 7 and may also include a packaging substrate that is electrically coupled to the first surface of the third die through the second interconnect.

[0128] Example 10 may include the subject matter of any one of Examples 1 to 9, and may also specify that the conductive structure of the first metallization stack is thicker than the conductive structure of the second metallization stack.

[0129] Example 11 is a microelectronic component including a first die in a first layer having a first surface and an opposing second surface, the first die including a substrate at the first surface including a through-substrate via (TSV); a first metallization stack on the substrate; a device layer on the first metallization stack including devices; a second metallization stack on the device layer; and an interconnect at the first surface electrically coupled to the first metallization stack through the TSV in the substrate; a conductive pillar in the first layer; and a second die in a second layer on the first layer having a first surface and an opposing second surface, wherein the first surface of the second die is coupled to the conductive pillar and the second surface of the first die through a hybrid bonding region.

[0130] Example 12 may include the subject matter of Example 11, and may also specify that the hybrid bonding region is a first hybrid bonding region, and may further include a third grain in the second layer having a first surface and an opposing second surface, wherein the first surface of the third grain is coupled to the second surface of the first grain through the second hybrid bonding region.

[0131] Example 13 may include the subject matter of Example 11 or 12, and may also specify that the interconnection is part of a power transmission network.

[0132] Example 14 may include the subject matter of any one of Examples 11 to 13, and may also specify that the substrate is a first substrate, and may further include a second substrate between the first metallization stack and the device layer, the second substrate including microsilicon through-holes (µTSV).

[0133] Example 15 may include the subject matter of Example 14 and may also specify that the µTSV electrically couples the device in the device layer to the first metallization stack.

[0134] Example 16 may include the subject matter of any one of Examples 11 to 15, and may also include a packaging substrate electrically coupled to the first surface of the first die through the interconnect and electrically coupled to the first surface of the second die through the conductive pillar.

[0135] Example 17 may include the subject matter of any one of Examples 11 to 16, and may also specify that the interconnect is a first interconnect, and may further include a third die having a first surface with a second interconnect and an opposing second surface electrically coupled to the first surface of the first die through the first interconnect, and electrically coupled to the first surface of the second die through the conductive pillar.

[0136] Example 18 may include the subject matter of Example 17 and may also specify that the second interconnection is part of a power transmission network.

[0137] Example 19 may include the subject matter of Example 17 and may also include a packaging substrate that is electrically coupled to the first surface of the third die through the second interconnect.

[0138] Example 20 may include the subject matter of any one of Examples 11 to 19, and may also specify that the conductive structure of the first metallization stack is thicker than the conductive structure of the second metallization stack.

[0139] Example 21 is a microelectronic component including a first die in a first dielectric layer having a first surface and an opposing second surface, and the first die including a substrate at the first surface including a substrate through-hole (TSV); a first metallization stack on the substrate; a device layer on the first metallization stack including devices; a second metallization stack on the device layer; and a first interconnect at the first surface electrically coupled to the first metallization stack through the TSV in the substrate; a second die in the first dielectric layer including a substrate at the first surface including a substrate through-hole (TSV); a first metallization stack on the substrate; a device layer on the first metallization stack including devices; a second metallization stack on the device layer; and a first interconnect at the first surface electrically coupled to the first metallization stack through the TSV in the substrate; and a second die in the first dielectric layer including a substrate at the first surface including a substrate through-hole (TSV); a first metallization stack on the substrate; a device layer on the first metallization stack including devices; a second metallization stack on the device layer; and a first interconnect at the first surface electrically coupled to the first metallization stack through the TSV in the substrate; and a second interconnect at the first surface electrically coupled to the first metallization stack through the TSV in the substrate. The first interconnect is a second interconnect on the surface of the substrate, electrically coupled to the first metallization stack via the TSV in the substrate; a conductive pillar in the first dielectric layer; a third die in the second dielectric layer on the second surface of the first dielectric layer, electrically coupled to the conductive pillar, electrically coupled to the first die via a first hybrid bonding region on the second surface of the first dielectric layer, and electrically coupled to the second die via a second hybrid bonding region on the second surface of the first dielectric layer; and a redistribution layer (RDL) on the first surface of the first dielectric layer, having a first surface and an opposing second surface, wherein the second surface of the RDL is electrically coupled to the first surface of the first dielectric layer, and wherein the first surface of the RDL includes a third interconnect electrically coupled to the conductive pillar, the first interconnect, and the second interconnect via a conductive path in the RDL.

[0140] Example 22 may include the subject matter of Example 21, and may also specify that the first interconnect, the second interconnect and the third interconnect are part of a power transmission network.

[0141] Example 23 may include the subject matter of Example 21 or 22, and may also specify that the substrate of the first die is a first substrate, and may further include a second substrate between the first metallization stack and the device layer, the second substrate including microsilicon through-holes (µTSV), wherein the µTSV electrically couples the device in the device layer to the first metallization stack.

[0142] Example 24 may include the subject matter of any one of Examples 21 to 23, and may also specify that the substrate of the second die is the first substrate, and may further include a second substrate between the first metallization stack and the device layer, which includes µTSV, wherein the µTSV electrically couples the device in the device layer to the first metallization stack.

[0143] Example 25 may include the subject matter of any one of Examples 21 to 24, and may also include a packaging substrate electrically coupled to the first surface of the RDL through the third interconnect. [Simplified Explanation of the Diagram]

[0004] The embodiments will be readily understood through the following detailed description taken in conjunction with the accompanying drawings. For ease of description, the same reference numerals denote the same structural elements. In the accompanying drawings, embodiments are illustrated by way of example rather than limitation.

[0005] [Figure 1] is a side cross-sectional view of an exemplary microelectronic component according to various embodiments.

[0006] [Figure 2] is an exploded side view cross-section of a portion of the microelectronic component of Figure 1 according to various embodiments.

[0007] [Figure 3] is a side cross-sectional view of an exemplary microelectronic component according to various embodiments.

[0008] [Figure 4] is a side cross-sectional view of an exemplary microelectronic component according to various embodiments.

[0009] [Figure 5] is a side cross-sectional view of an exemplary microelectronic component according to various embodiments.

[0010] [Figure 6] is a side cross-sectional view of an exemplary microelectronic component according to various embodiments.

[0011] [Figure 7] is a side cross-sectional view of an exemplary microelectronic component according to various embodiments.

[0012] [Figures 8A-8J] are side cross-sectional views of various stages in an exemplary process for manufacturing the microelectronic component of Figure 3 according to various embodiments.

[0013] [Figures 9A-9D] are side cross-sectional views of various stages in an exemplary process for manufacturing the microelectronic component of FIG1 according to various embodiments.

[0014] [Figures 10A-10G] are side cross-sectional views of various stages in an exemplary process for manufacturing the microelectronic component of FIG5 according to various embodiments.

[0015] [Figures 11A-11D] are side cross-sectional views of various stages in an exemplary process for manufacturing the microelectronic component of FIG7 according to various embodiments.

[0016] [Figure 12] is a top view of a wafer and die that may be included in a microelectronic assembly according to any embodiment disclosed herein.

[0017] [Figure 13] is a cross-sectional side view of an IC device that may be included in a microelectronic assembly according to any embodiment disclosed herein.

[0018] [Figure 14] is a cross-sectional side view of an IC device assembly that may be included in a microelectronic assembly according to any embodiment disclosed herein.

[0019] [Figure 15] is a block diagram of an exemplary electronic device that may include microelectronic components according to any embodiment disclosed herein.

Claims

1. A microelectronic component, comprising: A first grain in a first layer having a first surface and an opposing second surface, the first grain comprising: a first metallization stack at the first surface; a device layer on the first metallization stack including devices; a second metallization stack on the device layer; and an interconnect at the first surface electrically coupled to the first metallization stack; a conductive pillar in the first layer; and a second grain in a second layer on the first layer having a first surface and an opposing second surface, wherein the first surface of the second grain is coupled to the second surface of the first grain through a hybrid bonding region and is coupled to the conductive pillar.

2. The microelectronic assembly of claim 1, wherein the hybrid bonding region is a first hybrid bonding region, and further includes: The third grain in the second layer has a first surface and an opposing second surface, wherein the first surface of the third grain is coupled to the second surface of the first grain through a second hybrid bonding region.

3. The microelectronic component of claim 1, wherein the interconnection is part of a power transmission network.

4. The microelectronic component as described in claim 1 also includes: A substrate layer between the first metallization stack and the device layer, the substrate layer including micro-through silicon vias (µTSV).

5. The microelectronic component of claim 4, wherein the µTSV electrically couples the device in the device layer to the first metallization stack.

6. The microelectronic component of any one of claims 1 to 5 further includes: The packaging substrate is electrically coupled to the first surface of the first die through the interconnect and electrically coupled to the first surface of the second die through the conductive pillar.

7. A microelectronic component as claimed in any one of claims 1 to 5, wherein the conductive structure of the first metallization stack is thicker than the conductive structure of the second metallization stack.

8. A microelectronic component, comprising: A first grain in a first layer having a first surface and an opposing second surface, the first grain comprising: a substrate at the first surface including a through-substrate via (TSV); a first metallization stack on the substrate; a device layer on the first metallization stack including devices; a second metallization stack on the device layer; and an interconnect at the first surface electrically coupled to the first metallization stack via the TSV in the substrate; a conductive pillar in the first layer; and a second grain in a second layer on the first layer having a first surface and an opposing second surface, wherein the first surface of the second grain is coupled to the conductive pillar and the second surface of the first grain via a hybrid bonding region.

9. The microelectronic component of claim 8, wherein the interconnect is part of a power transmission network.

10. The microelectronic assembly of claim 8, wherein the substrate is a first substrate, and further comprises: A second substrate between the first metallization stack and the device layer, the second substrate including microsilicon through-holes (µTSV).

11. The microelectronic component of claim 10, wherein the µTSV electrically couples the device in the device layer to the first metallization stack.

12. The microelectronic component as described in claim 8 also includes: The packaging substrate is electrically coupled to the first surface of the first die through the interconnect and electrically coupled to the first surface of the second die through the conductive pillar.

13. The microelectronic component as described in claim 8 also includes: A third grain having a first surface and an opposing second surface, wherein the second surface of the third grain is electrically coupled to the first surface of the first grain through the interconnect, and electrically coupled to the first surface of the second grain through the conductive pillar.

14. The microelectronic component of claim 13, wherein the first surface of the third die further includes a second interconnect, and the microelectronic component further includes: The packaging substrate is electrically coupled to the first surface of the third die through the second interconnect.

15. The microelectronic component of claim 14, wherein the second interconnect is part of a power transmission network.

16. A microelectronic component of any one of claims 8 to 15, wherein the conductive structure of the first metallization stack is thicker than the conductive structure of the second metallization stack.

17. A microelectronic component, comprising: A first die in a first dielectric layer, the first dielectric layer having a first surface and an opposing second surface, and the first die comprising: a substrate at the first surface, including a substrate through-hole (TSV); a first metallization stack on the substrate; a device layer on the first metallization stack, including devices; a second metallization stack on the device layer; and a first interconnect at the first surface, electrically coupled to the first metallization stack via the TSV in the substrate; and a second die in the first dielectric layer, the second die comprising: a substrate at the first surface, including a substrate through-hole (TSV); a first metallization stack on the substrate; and a first interconnect at the first surface, electrically coupled to the first metallization stack via the TSV in the substrate; and a first interconnect at the first surface, electrically coupled to the first metallization stack via the TSV in the substrate; and a second interconnect at the first surface, electrically coupled to the first metallization stack via the TSV in the substrate; and a first ... A device layer on a stack, comprising devices; a second metallized stack on the device layer; and a second interconnect at a first surface electrically coupled to the first metallized stack via a TSV in the substrate; a conductive pillar in a first dielectric layer; a third die in a second dielectric layer on a second surface of the first dielectric layer, electrically coupled to the conductive pillar, electrically coupled to the first die via a first hybrid bonding region at the second surface of the first dielectric layer, and electrically coupled to the second die via a second hybrid bonding region at the second surface of the first dielectric layer; and a redistribution layer (RDL) at the first surface of the first dielectric layer, having a first surface and an opposing second surface, wherein the second surface of the RDL is electrically coupled to the first surface of the first dielectric layer, and wherein the first surface of the RDL includes a third interconnect electrically coupled to the conductive pillar, the first interconnect, and the second interconnect via a conductive path in the RDL.

18. The microelectronic component of claim 17, wherein the first interconnect, the second interconnect and the third interconnect are part of a power transmission network.

19. The microelectronic component of claim 17 or 18, wherein the substrate of the first die is a first substrate, and further includes: A second substrate between the first metallization stack and the device layer, the second substrate including micro-silicon through-vessels (µTSVs), wherein the µTSVs electrically couple the device in the device layer to the first metallization stack.

20. The microelectronic components of claims 17 or 18 also include: The packaging substrate is electrically coupled to the first surface of the RDL through the third interconnect.

21. The microelectronic component of claim 17, wherein the substrate of the second die is a first substrate, and further comprises: A second substrate between the first metallization stack and the device layer, the second substrate including micro-silicon through-vessels (µTSVs), wherein the µTSVs electrically couple the device in the device layer to the first metallization stack.

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