Fan-out package、chip package structure and method of fomring the same

Abstract

A fan-out package includes: a redistribution structure, a plurality of semiconductor dies, and an underfill material portion. The semiconductor dies include a set of die-side bonding structures attached to a respective subset of the redistribution side bonding structure via a respective set of solder material portions. The underfill material portion laterally surrounds the redistribution side bonding structure and the die-side bonding structures of the semiconductor dies. A subset of the redistribution side bonding structures is not bonded to any die-side bonding structure of the semiconductor dies and is laterally surrounded by the underfill material portion to provide a uniform distribution of the underfill material during the formation of the underfill material portion.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor structure, and more particularly to a dummy metal bonding pad for underfill applications in semiconductor die packaging and a method thereof for forming the same. [Previous Technology]

[0002] The interface between the fan-out wafer level package (FOWLP) and the molding compound material portion is subjected to mechanical stress during subsequent processing of the fan-out wafer level package, the underfill material portion, and the package substrate assembly (e.g., attachment of the package substrate to a printed circuit board, PCB). Furthermore, the interface between the fan-out wafer level package and the underfill material portion is subjected to mechanical stress during use within the computing device, for example, when the fan-out wafer level package heats up during use and thermal expansion mismatch of the fan-out wafer level package assembly causes thermal stress, or when the mobile device is accidentally dropped during use, causing mechanical impact. Cracks can form in the underfill material and may cause additional cracks in the semiconductor die, solder material portion, redistribution structure, and / or various dielectric layers within the semiconductor die or package substrate. Therefore, it is necessary to suppress crack formation in the underfill material. [Summary of the Invention]

[0003] According to some embodiments of this disclosure, a fan-out package includes: a redistribution structure, a plurality of semiconductor dies, and an underfill material portion. The redistribution structure includes a plurality of first metal bonding structures on one side. The plurality of semiconductor dies include a plurality of second metal bonding structures attached to the first metal bonding structures through a plurality of bump portions. The underfill material portion laterally surrounds the first metal bonding structure and the second metal bonding structures of the semiconductor dies. A subset of the first metal bonding structures includes at least one dummy metal bonding structure surrounded by the underfill material portion and electrically isolated from the semiconductor dies and the second metal bonding structures by the underfill material portion.

[0004] According to other embodiments of the present disclosure, a chip package structure includes: a fan-out package and a package substrate. The fan-out package includes a redistribution structure, a plurality of semiconductor dies, and a first underfill material portion. The redistribution structure includes a plurality of redistribution side bonding structures. The semiconductor dies include each of the plurality of die-side bonding structures as a set. The die-side bonding structures are attached to each subset of the redistribution side bonding structures via each of the plurality of first solder material portions. The first underfill material portions laterally surround the redistribution side bonding structures and the die-side bonding structures of the semiconductor dies. In a planar view, a subset of the redistribution side bonding structures is located between a pair of adjacent semiconductor dies selected from the semiconductor dies. The package substrate is attached to the fan-out package via an array of a plurality of second solder material portions.

[0005] According to further embodiments of the present disclosure, a method of forming a wafer package structure includes: providing a redistribution structure including a plurality of redistribution side bonding structures thereon; providing a plurality of semiconductor dies, including each of a plurality of die-side bonding structures; bonding the semiconductor dies to the redistribution structure using a plurality of first solder material portions, the first solder material portions being bonded to each of a redistribution side bonding structure in a first subset of the redistribution side bonding structures and to each of the die-side bonding structures, wherein a second subset of the redistribution side bonding structures is not bonded to any of the semiconductor dies; and forming a first underfill material portion around the first solder material portions, the redistribution side bonding structures and the die-side bonding structures.

Implementation Method

[0007] The following disclosure provides many different embodiments or examples to implement the different features of this invention. The following disclosure describes specific examples of the various components and their arrangements for simplification. Of course, these specific examples are not intended to be limiting. For example, if this disclosure describes a first feature formed on or above a second feature, it means that it may include embodiments where the first feature and the second feature are in direct contact, or it may include embodiments where an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the same reference numerals and / or markings may be used repeatedly in different examples of the following disclosure. These repetitions are for simplification and clarity and are not intended to limit the specific relationship between the different embodiments and / or structures discussed.

[0008] Furthermore, spatially related terms, such as "below," "below," "lower," "above," "higher," and similar terms, are used to facilitate the description of the relationship between one element or feature in the illustration and another element(s) or feature(s). In addition to the orientation shown in the illustrations, these spatially related terms are intended to encompass different orientations of the device in use or operation. The device may be rotated to different orientations (90 degrees or other orientations), and the spatially related terms used herein may be interpreted in the same way. Unless otherwise expressly specified, each element having the same reference numeral is assumed to have the same material composition and a thickness within the same thickness range.

[0009] This disclosure relates to semiconductor devices, particularly the uniform application of underfill material in semiconductor die packaging. Generally, the methods and structures of this disclosure can be used to provide a wafer package structure, such as a fan-out wafer-level package (FOWLP) or a fan-out panel-level package (FOPLP). Although this disclosure is described using a fan-out wafer-level package configuration, the methods and structures of this disclosure can be applied to a fan-out panel-level package configuration or any other fan-out or fan-in package configuration.

[0010] Metal bonding structures on semiconductor grains and redistribution structures can increase capillary forces during the application of underfill material. The increased capillary forces can advantageously enhance the uniformity of underfill material distribution around metal bonding structures in grain-to-grain gaps or grain-to-package gaps (e.g., grain-to-wafer-scale package gaps). According to one embodiment of this disclosure, dummy metal bonding structures and / or dummy solder material portions can be used to enhance the flow uniformity of the underfill material. By using dummy structures that enhance capillary forces in the inter-grain region according to embodiments of this disclosure, void formation within underfill material portions in grain-to-grain gaps or grain-to-package gaps can be avoided or reduced.

[0011] For example, a high-performance computing (HPC) package may include multiple semiconductor dies, including at least one system-on-chip (SoC) die and at least one high-bandwidth memory (HBM) die within a wafer, such as a fan-out wafer-level package. Die-to-die gaps and / or die-to-wafer-scale package gaps increase the complexity of the underfill material distribution steps. In the case of uneven underfill material flow, voids may form within portions of the underfill material in the gap regions. Such voids in the underfill material can lead to solder bridging or "popcorn" phenomena, where solder material portions are firmly attached to the metal bonding structure. The dummy structures of the embodiments disclosed herein can be used to avoid or reduce void formation in the underfill material. Various types and embodiments of the methods and structures disclosed herein are described with reference to the accompanying drawings.

[0012] Referring to Figure 1, an exemplary structure according to an embodiment of the present disclosure includes a first carrier substrate 300 and a plurality of redistribution structures 920 formed on the front surface of the first carrier substrate 300. The first carrier substrate 300 may include a light-transmitting substrate, such as a glass substrate or a sapphire substrate. The diameter of the first carrier substrate 300 may be in the range of 150 mm to 290 mm, and the thickness of the first carrier substrate 300 may be in the range of 500 micrometers to 2000 micrometers, but smaller and larger thicknesses are also possible. Alternatively, the first carrier substrate 300 may be provided in the form of a rectangular panel.

[0013] The first adhesive layer 301 may be applied to the front surface of the first carrier substrate 300. In one embodiment, the first adhesive layer 301 may be a light-to-heat conversion (LTHC) layer. The LTHC layer may be a solvent-based coating applied using a spin coating method. The LTHC layer can convert ultraviolet light into heat, which may cause the material of the LTHC layer to lose its adhesiveness. Alternatively, the first adhesive layer 301 may include a thermally decomposable adhesive material. For example, the first adhesive layer 301 may include an acrylic pressure-sensitive adhesive that decomposes at high temperatures. The debonding temperature of the thermally decomposable adhesive material may be in the range of 150 to 200 degrees Celsius.

[0014] The redistribution structure 920 may be formed over the first adhesive layer 301. Specifically, the redistribution structure 920 may be formed within each unit area UA, where the unit area UA is the area of ​​repeating cells in a two-dimensional array over the first carrier substrate 300. Each redistribution structure 920 may include a plurality of redistribution dielectric layers 922 and a plurality of redistribution wiring interconnects 924. The redistribution dielectric layers 922 include respective dielectric polymer materials such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable materials are within the scope of the embodiments disclosed herein. Each redistribution dielectric layer 922 may be formed by spin-coating and drying its respective dielectric polymer material. The thickness of each redistribution dielectric layer 922 may range from 2 micrometers to 40 micrometers, for example, from 4 micrometers to 20 micrometers. Each redistribution dielectric layer 922 can be patterned, for example, by applying and patterning a respective photoresist layer above it, and by transferring the pattern in the photoresist layer to the redistribution dielectric layer 922 using an etching process (e.g., anisotropic etching). The photoresist layer can then be removed (e.g., by ashing).

[0015] Each redistribution interconnect 924 may be formed by sputtering a metal seed layer, applying and patterning a photoresist layer above the metal seed layer to form an opening pattern through the photoresist layer, electroplating a metal filler material (e.g., copper, nickel, or a stack of copper and nickel), removing the photoresist layer (e.g., by ashing), and etching portions of the metal seed layer located between the electroplated metal filler material portions. The aforementioned metal seed layer may include, for example, a stack of a titanium barrier layer and a copper seed layer. The titanium barrier layer may have a thickness ranging from 50 nanometers to 400 nanometers, and the copper seed layer may have a thickness ranging from 100 nanometers to 500 nanometers. The metal filler material used for the redistribution interconnect 924 may include copper, nickel, or copper and nickel. The thickness of the metal filler material deposited for each redistribution interconnect 924 may range from 2 micrometers to 40 micrometers, for example, 4 micrometers to 10 micrometers, but may also be smaller or larger. The total number of wiring levels in each redistribution structure 920 (i.e., the number of levels of redistribution wiring interconnects 924) can range from 1 to 10. Other suitable materials are within the scope of the embodiments disclosed herein. A periodic two-dimensional array (e.g., a rectangular array) of redistribution structures 920 can be formed over the first carrier substrate 300. The layer comprising all redistribution structures 920 is referred to herein as a redistribution structure layer. The redistribution structure layer comprises a two-dimensional array of redistribution structures 920.

[0016] Referring to Figures 2A and 2B, at least one metallic material and a first material may be sequentially deposited on the front surface of the redistribution structure 920. The at least one metallic material includes a material suitable for metallic bumps, such as copper. The thickness of the at least one metallic material may range from 5 micrometers to 60 micrometers, for example, 10 micrometers to 30 micrometers, but may also be smaller or larger. The first material may include a first material suitable for C2 bonding, such as for microbump bonding. The thickness of the first material may range from 2 micrometers to 30 micrometers, for example, 4 micrometers to 15 micrometers, but may also be smaller or larger.

[0017] The first material and at least one metallic material may be patterned into a discrete array of first solder material portions 940 and an array of metallic bonding structures, referred herein as an array of redistribution side bonding structures 938. Each array of redistribution side bonding structures 938 is formed within its respective unit area UA. Each array of first solder material portions 940 is formed within its respective unit area UA. Each first solder material portion 940 may have the same horizontal cross-sectional shape as the redistribution side bonding structures 938 below.

[0018] In one embodiment, the redistribution side bonding structure 938 may include copper and copper-containing alloys and / or may be substantially composed of copper and copper-containing alloys. Other suitable materials are within the scope of the embodiments disclosed herein. The thickness of the redistribution side bonding structure 938 may range from 5 micrometers to 60 micrometers, but may also be smaller or larger. The redistribution side bonding structure 938 may have a horizontal cross-sectional shape that is rectangular, rounded rectangle, circular, regular polygon, irregular polygon, or any other two-dimensional curved shape with a closed perimeter. In one embodiment, the redistribution side bonding structure 938 may be configured for microbump bonding (i.e., C2 bonding) and may have a thickness ranging from 10 micrometers to 30 micrometers, but may also be smaller or larger. In this embodiment, each array of redistribution side bonding structures 938 may be formed as an array of microbumps (e.g., copper pillars) having a lateral dimension ranging from 10 micrometers to 25 micrometers and a pitch ranging from 20 micrometers to 50 micrometers.

[0019] Referring to Figures 3A and 3B, a group of at least one semiconductor die (semiconductor die 700, semiconductor die 800) may be incorporated into each redistribution structure 920. In one embodiment, the redistribution structure 920 may be arranged in a two-dimensional periodic array, and multiple groups of at least one semiconductor die (semiconductor die 700, semiconductor die 800) may be incorporated into the redistribution structure 920 as a two-dimensional periodic rectangular array of multiple groups of at least one semiconductor die (semiconductor die 700, semiconductor die 800). Each group of at least one semiconductor die (semiconductor die 700, semiconductor die 800) includes at least one semiconductor die. Each group of at least one semiconductor die (semiconductor die 700, semiconductor die 800) may include a group of at least one semiconductor die known in the art. In one embodiment, each group of at least one semiconductor die (semiconductor die 700, semiconductor die 800) may include a plurality of semiconductor dies (semiconductor die 700, semiconductor die 800). For example, each group of at least one semiconductor die (semiconductor die 700, semiconductor die 800) may include at least one system-on-a-chip (SoC) die 700 and / or at least one memory die 800. Each SoC die 700 may include an application processor die, a central processing unit die, or an image processing unit die. In one embodiment, at least one memory die 800 may include a high-bandwidth memory (HBM) die, comprising a vertically stacked static random access memory (SRAM) die. In one embodiment, at least one semiconductor die (semiconductor die 700, semiconductor die 800) may include at least one SoC die and a vertically stacked high-bandwidth memory (HBM) die including static random access memory (SRAM), interconnected with each other through microbumps and laterally surrounded by an epoxy molding compound enclosure.

[0020] Referring to Figures 3A and 3B, each semiconductor die (semiconductor die 700, semiconductor die 800) may include an array of die-side bonding structures (die-side bonding structures 780, die-side bonding structures 880). For example, each single-chip system die 700 may include an array of single-chip system metal bonding structures 780, and each semiconductor die 800 may include an array of memory die metal bonding structures 880. Each semiconductor die (semiconductor die 700, semiconductor die 800) may be positioned downwards such that the die-side bonding structures (die-side bonding structures 780, die-side bonding structures 880) face the first solder material portion 940. Each group of a plurality of semiconductor dies (semiconductor dies 700, semiconductor 800) may be placed within its respective unit area UA. The placement of semiconductor dies (semiconductor die 700, semiconductor die 800) can be performed using a pick-and-place device, such that each die-side bonding structure (die-side bonding structure 780, die-side bonding structure 880) is placed on the top surface of each of the first solder material portions 940.

[0021] Generally, a redistribution structure 920 may be provided, including a redistribution-side bonding structure 938 thereon, and a plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800) may be provided, each including a set of die-side bonding structures (die-side bonding structures 780, die-side bonding structures 880). The plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800) may be bonded to the redistribution structure 920 using a first solder material portion 940, the first solder material portion 940 being bonded to each of the redistribution-side bonding structures 938 in a first subset of the redistribution-side bonding structures 938, and to each of the die-side bonding structures (die-side bonding structures 780, die-side bonding structures 880). A second subset of the redistribution-side bonding structures 938 is not bonded to any semiconductor die (semiconductor die 700, semiconductor dies 800).

[0022] A first subset of the redistribution side bonding structure 938 may be bonded to a first subset of the first solder material portion 940, and a second subset of the redistribution side bonding structure 938 may be bonded to a second subset of the first solder material portion 940. The second subset of the redistribution side bonding structure 938 is referred to herein as a dummy redistribution side bonding structure 938D. The second subset of the redistribution side bonding structure 938 (including the dummy redistribution side bonding structure 938D) does not have any bonding of any grain-side bonding structure (grain-side bonding structure 780, grain-side bonding structure 880) of up to a plurality of semiconductor grains (semiconductor grains 700, semiconductor grains 800). In other words, the second subset of the redistribution side bonding structure 938 (including the dummy redistribution side bonding structure 938D) is not bonded to any grain-side bonding structure (grain-side bonding structure 780, grain-side bonding structure 880) of the plurality of semiconductor dies (semiconductor die 700, semiconductor die 800).

[0023] Each redistribution side bonding structure 938 within the first subset of the redistribution side bonding structures 938 may, in a planar view (e.g., top view), have an area overlapping with one of the plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800), and may, in a planar view, be completely located within the area of ​​one of the plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800). Each dummy redistribution side bonding structure 938D, in a planar view, does not overlap with any area of ​​the plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800), and may, in a planar view, be completely located between the areas of a pair of adjacent semiconductor dies (semiconductor dies 700, semiconductor dies 800) within the plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800).

[0024] Each of the first solder material portions 940 within the first subset of the first solder material portions 940 may, in a planar view, have an area overlapping with one of the plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800), and in a planar view, may be completely located within the area of ​​one of the plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800). Each dummy solder material portion 940D, in a planar view, does not overlap with any area of ​​the plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800), and in a planar view, may be completely located between the areas of a pair of adjacent semiconductor dies (semiconductor dies 700, semiconductor dies 800) within the plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800).

[0025] Generally, a first solder material portion 940 (e.g., a first subset of the first solder material portion 940) may be formed on a first subset of the redistribution side bonding structure 938, and an additional first solder material portion 940 (e.g., a dummy solder material portion 940D) may be formed on a second subset of the redistribution side bonding structure 938 (i.e., on the dummy redistribution side bonding structure 938D). The additional first solder material portion (e.g., the dummy solder material portion 940D) is not bonded to any grain-side bonding structure (grain-side bonding structure 780, grain-side bonding structure 880). The additional first solder material portion (e.g., the dummy solder material portion 940D) does not have any bonding with the grain-side bonding structures (grain-side bonding structure 780, grain-side bonding structure 880).

[0026] In one embodiment, the dummy solder material portion 940D may be located on each of the dummy redistribution side bonding structures 938D selected from a second subset of the redistribution side bonding structures 938, and does not contact any semiconductor die (semiconductor die 700, semiconductor die 800). In one embodiment, the dummy solder material portion 940D includes at least one row of dummy solder material portions 940D arranged along a direction parallel to a pair of sidewalls of a pair of adjacent semiconductor dies (semiconductor dies 700, semiconductor dies 800) selected from the semiconductor dies (semiconductor dies 700, semiconductor dies 800), and disposed between adjacent semiconductor dies (semiconductor dies 700, semiconductor dies 800). Each dummy solder material portion 940D has the same material composition as the multiple sets of first solder material portions 940 bonded to each pair of redistribution side bonding structures 938 and die-side bonding structures (die-side bonding structures 780, die-side bonding structures 880).

[0027] Generally, the dummy redistribution side bonding structure 938D and the dummy solder material portion 940D do not overlap with any region of the plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800) in each unit area UA in a planar view (e.g., the top view of Figure 3B). In one embodiment, in a planar view, a row of dummy redistribution side bonding structures 938D and a row of dummy solder material portions 940D may be located between the areas of a pair of adjacent semiconductor dies (semiconductor dies 700, semiconductor dies 800) within the plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800). The arrangement of the dummy redistribution side bonding structures 938D and the dummy solder material portion 940D may vary depending on the arrangement of the plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800) in each unit area UA.

[0028] Figures 4A to 4C illustrate alternative configurations of the exemplary structure, derived from the exemplary structures of Figures 3A and 3B, changing the arrangement of the semiconductor dies (semiconductor dies 700, semiconductor dies 800) and / or the total number and / or type of semiconductor dies (semiconductor dies 700, semiconductor dies 800). The semiconductor dies (first semiconductor die 701, second semiconductor die 702, third semiconductor die 703, fourth semiconductor die 704) in the alternative configurations of the exemplary structures in Figures 4A to 4C include a first semiconductor die 701, a second semiconductor die 702, and optionally a third semiconductor die 703 and / or a fourth semiconductor die 704. Each semiconductor die (first semiconductor die 701, second semiconductor die 702, third semiconductor die 703, fourth semiconductor die 704) may include a single-chip system die 700 or a memory die 800. The patterns of the dummy redistribution side bonding structure 938D and the dummy solder material portion 940D may include a single-column pattern as shown in Figure 4A, a multi-column pattern as shown in Figure 4B, and / or a cross pattern as shown in Figure 4C. Generally, any pattern may be used for the arrangement of the dummy redistribution side bonding structure 938D and the dummy solder material portion 940D, provided that at least one dummy redistribution side bonding structure 938D and at least one dummy solder material portion 940D are placed between adjacent pairs of semiconductor dies {(semiconductor die 700, semiconductor die 800) or (first semiconductor die 701, second semiconductor die 702, third semiconductor die 703, fourth semiconductor die 704)}.

[0029] Although Figures 3A, 3B and 4A to 4C illustrate the configuration of the dummy solder material portion 940D and the dummy redistribution side bonding structure 938D having their respective rectangular horizontal cross-sectional shapes, in general, the dummy solder material portion 940D and the dummy redistribution side bonding structure 938D can have any horizontal cross-sectional shape with a two-dimensional curved shape having a closed perimeter.

[0030] Referring to Figure 5A, an alternative shape for the dummy solder material portion 940D (and the redistribution side bonding structure 938) is shown, which may include a regular polygon with equal side lengths.

[0031] Referring to Figure 5B, an additional alternative shape for the dummy solder material portion 940D (and the redistribution side bonding structure 938) is shown, which may include an irregular polygon.

[0032] Alternatively, the dummy solder material portion 940D (and the redistribution side bonding structure 938) may have a horizontal cross-sectional shape that is circular, elliptical, oval, or has a curved two-dimensional shape with a closed perimeter.

[0033] Referring to Figure 6, a high-bandwidth memory (HBM) die 810 is illustrated, which can be used as the semiconductor die 800 in Figures 3A, 3B, 4A, 4B and / or 4C. The high-bandwidth memory die 810 includes a vertically stacked static random access memory (SRAM) dies (SRAM 811, SRAM 812, SRAM 813, SRAM 814, SRAM 815), interconnected by microbumps 820, and laterally surrounded by an epoxy molding material enclosure 816. The gaps between vertically adjacent pairs of static random access memory (SRAM) dies (SRAM 811, SRAM 812, SRAM 813, SRAM 814, and SRAM 815) can be filled with high-bandwidth memory underfill material portions 822, which laterally surround each of a set of microbumps 820. High-bandwidth memory dies 810 may include an array of memory die metal bonding structures 880 configured to bond to a subset of an array of redistribution-side bonding structures 938 per unit area UA. High-bandwidth memory dies 810 can be configured to provide high bandwidth as defined by JEDEC standards, i.e., by the standards defined by the JEDEC Solid State Technology Association.

[0034] Referring to Figures 7A and 7B, a first underfill material can be applied to each gap between the redistribution structure 920 and a group of semiconductor dies (semiconductor dies 700, semiconductor dies 800) bonded to the redistribution structure 920. The first underfill material may include any underfill material known in the art. A first underfill material portion 950 may be formed within each unit area UA between the redistribution structure 920 and the group of multiple semiconductor dies (semiconductor dies 700, semiconductor dies 800) above it. The first underfill material portion 950 may be formed by injecting the first underfill material around each array of first solder material portions 940 in each unit area UA. Any known underfill material application method may be used, for example, capillary underfill method, molding underfill method, or printing underfill method.

[0035] Within each unit area UA, a first underfill material portion 950 laterally surrounds and contacts each first solder material portion 940 within the unit area UA, including a first subset of first solder material portions 940 that can be bonded to each pair of redistribution side bonding structures 938 and grain-side bonding structures (grain-side bonding structure 780, grain-side bonding structure 880), and a second subset of first solder material portions 940 that are not bonded to any grain-side bonding structure (grain-side bonding structure 780, grain-side bonding structure 880) (i.e., dummy solder material portions 940D). The first underfill material portion 950 may form around and contact the first solder material portions 940, redistribution side bonding structures 938, and grain-side bonding structures (grain-side bonding structures 780, grain-side bonding structure 880) within the unit area UA. In each unit area UA, a subset of any grain-side bonding structures (grain-side bonding structure 780, grain-side bonding structure 880) of any plurality of semiconductor grains (semiconductor grains 700, semiconductor grains 800) with dummy redistribution side bonding structures 938D (i.e., redistribution side bonding structures 938 are not bonded (i.e., have no bonding)) can be laterally surrounded by and contacted by the first bottom filler portion 950.

[0036] Each redistribution structure 920 in a unit area UA may include a redistribution side bonding structure 938. A plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800) including their respective sets of die-side bonding structures (die-side bonding structures 780, die-side bonding structures 880) may be attached to a respective subset of the redistribution side bonding structure 938 via a respective set of first solder material portions 940 (including a first subset of the first solder material portions 940). Within each unit area UA, a first bottom filler portion 950 laterally surrounds the redistribution side bonding structure 938 and the die-side bonding structures (die-side bonding structures 780, die-side bonding structures 880) of the plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800). A subset of the redistribution side bonding structure 938 (i.e., the dummy redistribution side bonding structure 938D) is not bonded to any of the grain-side bonding structures (grain-side bonding structure 780, grain-side bonding structure 880) of the plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800) and can be laterally surrounded by the first bottom filler material portion 950.

[0037] Referring to Figures 8A and 8B, an epoxy molding compound (EMC) may be applied to the gap between adjacent components of each of the semiconductor dies (semiconductor die 700, semiconductor die 800) and the first underfill material portion 950. The epoxy molding compound may include an epoxy resin-containing compound that can be cured (i.e., hardened) to provide a dielectric material portion with sufficient hardness and mechanical strength. The epoxy molding compound may include epoxy resin, a hardener, silicon dioxide (as a filler), and other additives. The epoxy molding compound may be provided in liquid or solid form, depending on viscosity and flowability. Liquid epoxy molding compounds provide better handling, good flowability, fewer voids, better filling, and fewer flow marks. Solid epoxy molding compounds provide less curing shrinkage, better stand-off, and less grain drift. A higher filler content (e.g., 85% by weight) in the epoxy molding compound reduces time spent in the mold, decreases mold shrinkage, and reduces mold warpage. A uniform filler size distribution in the epoxy molding compound reduces flow marks and enhances flowability. If the adhesive layer includes a thermally release agent, the curing temperature of the epoxy molding compound can be lower than the release (debonding) temperature of the first adhesive layer 301. For example, the curing temperature of the epoxy molding compound can be in the range of 125°C to 150°C.

[0038] The epoxy molding compound can be cured at a curing temperature to form an epoxy molding compound matrix 910M, which laterally surrounds and embeds each of a set of semiconductor dies (semiconductor dies 700, semiconductor dies 800) and a first underfill material portion 950. The epoxy molding compound matrix 910M may include a plurality of epoxy molding compound (EMC) die frames laterally adjacent to each other. Each epoxy molding compound die frame may be a part of the epoxy molding compound matrix 910M, located within its respective unit area UA. Therefore, each epoxy molding compound die frame may laterally surround and embed its respective set of semiconductor dies (semiconductor dies 700, semiconductor dies 800) and its respective first underfill material portion 950.

[0039] A portion of the epoxy molding compound matrix 910M covering the top surface of the semiconductor dies (semiconductor dies 700, semiconductor dies 800) can be removed by a planarization process. For example, a portion of the epoxy molding compound matrix 910M covering the horizontal plane can be removed using chemical mechanical planarization. The combination of the remaining portion of the epoxy molding compound matrix 910M, the semiconductor dies (semiconductor dies 700, semiconductor dies 800), the first underfill material portion 950, and the two-dimensional array of the redistribution structure 920 comprises a reconstituted wafer 900W. Each portion of the epoxy molding compound matrix 910M located within a unit area UA constitutes an epoxy molding compound die frame.

[0040] Referring to Figure 9, the second adhesive layer 401 may be applied to the solid exposed planar surface of the reconstituted wafer 900W, namely, the solid exposed surface of the epoxy molding compound matrix 910M, the semiconductor grains (semiconductor grains 700 and 800), and the first underfill material portion 950. In one embodiment, the second adhesive layer 401 may include a material that is the same as or different from the material of the first adhesive layer 301. If the first adhesive layer 301 includes a thermally decomposable adhesive material, then the second adhesive layer 401 may include another thermally decomposable adhesive material that decomposes at a higher temperature, or may include a photothermal conversion material.

[0041] The second carrier substrate 400 may be attached to the second adhesive layer 401. The second carrier substrate 400 may be attached to the opposite side of the reconstituted wafer 900W relative to the first carrier substrate 300. Generally, the second carrier substrate 400 may comprise any material that can be used with the first carrier substrate 300. The thickness of the second carrier substrate 400 may be in the range of 500 micrometers to 2000 micrometers, but may also be smaller or larger.

[0042] The first adhesive layer 301 can be decomposed by ultraviolet light irradiation or thermal annealing at the dejunction temperature. In embodiments where the first carrier substrate 300 includes a light-transmitting material and the first adhesive layer 301 includes a photothermal conversion layer, the first adhesive layer 301 can be decomposed by ultraviolet light radiation transmitted through the transparent carrier substrate. The photothermal conversion layer can absorb ultraviolet light irradiation and generate heat, decomposing the material of the photothermal conversion layer and causing the transparent first carrier substrate 300 to detach from the reconstituted wafer 900W. In embodiments where the first adhesive layer 301 includes a thermally decomposable adhesive material, a thermal annealing process can be performed at the dejunction temperature to detach the first carrier substrate 300 from the reconstituted wafer 900W.

[0043] Referring to Figure 10, a fan-out bonding pad 928 and a second solder material portion 290 can be formed by depositing and patterning a stack of at least one metal material, the stack of at least one metal material serving as a metal bump and a solder material layer. The metal filler material used for the fan-out bonding pad 928 may include copper. Other suitable materials are within the scope of the embodiments disclosed herein. The thickness of the fan-out bonding pad 928 may range from 5 micrometers to 100 micrometers, but may also be smaller or larger. The fan-out bonding pad 928 and the second solder material portion 290 may have a rectangular, rounded rectangular, or circular horizontal cross-sectional shape. Other suitable shapes are within the scope of the embodiments disclosed herein. In embodiments where the fan-out bonding pad 928 is formed as a controlled collapse chip connection (C4) pad, the thickness of the fan-out bonding pad 928 may range from 5 micrometers to 50 micrometers, but may also be smaller or larger. In some embodiments, the fan-out bonding pad 928 may be or may include an under bump metallurgy (UBM) structure. The configuration of the fan-out bonding pad 928 is not limited to a fan-out structure. Alternatively, the fan-out bonding pad 928 may be configured as a microbump bond (i.e., C2 bond) and may have a thickness in the range of 30 micrometers to 100 micrometers, but may also be smaller or larger. In this embodiment, the fan-out bonding pad 928 may be formed as an array of microbumps (e.g., copper pillars) having a lateral dimension in the range of 10 micrometers to 25 micrometers and a pitch in the range of 20 micrometers to 50 micrometers. In some embodiments, the second solder material portion 290 may be micro- or may include copper pillars.

[0044] The fan-out bonding pad 928 and the second solder material portion 290 may be formed on opposite sides of the two-dimensional array of epoxy molding compound matrix 910M and multiple sets of semiconductor dies (semiconductor dies 700, semiconductor dies 800) relative to the redistribution structure layer. The redistribution structure layer includes a three-dimensional array of redistribution structures 920. Each redistribution structure 920 may be located within its respective unit area UA. Each redistribution structure 920 may include a redistribution dielectric layer 922, redistribution wiring interconnects 924 embedded in the redistribution dielectric layer 922, and a fan-out bonding pad 928. The fan-out bonding pad 928 may be located on opposite sides of the redistribution side bonding structure 938 relative to the redistribution dielectric layer 922, and may be electrically connected to each of the redistribution side bonding structures 938.

[0045] Referring to Figure 11, the second adhesive layer 401 can be decomposed by ultraviolet light irradiation or by thermal annealing at the dejunction temperature. In embodiments where the second carrier substrate 400 includes a light-transmitting material and the second adhesive layer 401 includes a photothermal conversion layer, the second adhesive layer 401 can be decomposed by ultraviolet light radiation transmitted through the transparent carrier substrate. In embodiments where the second adhesive layer 401 includes a thermally decomposable adhesive material, a thermal annealing process can be performed at the dejunction temperature to detach the second carrier substrate 400 from the reconstituted wafer 900W.

[0046] Referring to Figure 12, the reconstituted wafer 900W, including the fan-out bonding pad 928, can be subsequently diced along a dicing channel by performing a dicing process. The dicing channel corresponds to the boundary between an adjacent pair of unit areas UA. Each dicing unit diced from the reconstituted wafer 900W includes a fan-out package 900. In other words, each dicing portion of the assembly of a two-dimensional array of multiple sets of semiconductor dies (semiconductor dies 700, semiconductor dies 800), a two-dimensional array of a first underfill material portion 950, an epoxy molding compound matrix 910M, and a two-dimensional array of a redistribution structure 920 includes a fan-out package 900. Each dicing portion of the epoxy molding compound matrix 910M includes a molding compound die frame 910. Each dicing portion of the redistribution structure layer (including a two-dimensional array of redistribution structures 920) includes a redistribution structure 920.

[0047] Referring to Figure 13, a fan-out package 900 obtained by cutting an exemplary structure in the process steps of Figure 12 is illustrated. The fan-out package 900 includes a redistribution structure 920, including a redistribution side bonding structure 938, a plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800), and a first underfill material portion 950. Each semiconductor die (semiconductor die 700, semiconductor die 800) includes a set of die-side bonding structures (die-side bonding structure 780, die-side bonding structure 880), and the die-side bonding structures (die-side bonding structure 780, die-side bonding structure 880) are attached to a subset of the redistribution side bonding structure 938 through a first solder material portion 940. A first underfill material portion 950 laterally surrounds a redistribution side bonding structure 938 and a plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800) and their respective die-side bonding structures (die-side bonding structures 780, die-side bonding structures 880). A subset of the redistribution side bonding structures 938, in a planar view (i.e., along a direction perpendicular to the bonding surface between the redistribution structure 920 and the first underfill material portion 950), is located between adjacent pairs of semiconductor dies (semiconductor dies 700, semiconductor dies 800). A fan-out package 900 may include a molded compound die frame 910 laterally surrounding the plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800) and comprising a molded compound material. In one embodiment, the molded compound die frame 910 may include a sidewall that is perpendicularly coincident with the sidewall of the redistribution structure 920, i.e., it lies in the same vertical plane as the sidewall of the redistribution structure 920. Generally, after forming a first underfill material portion 950 within each fan-out package 900, the molded compound die frame 910 may be formed around a plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800). The molded compound material contacts the peripheral portion of the planar surface of the redistribution structure 920.

[0048] Referring to Figure 14, the package substrate 200 can be bonded to the fan-out package 900 through the second solder material portion 290. The package substrate 200 may be a core-type package substrate, including a core substrate 210, or it may be a coreless package substrate, excluding a package core. Alternatively, the package substrate 200 may include a system-on-integrated package substrate (SoIS), including a redistribution and / or dielectric interface layer, and at least one embedded interposer layer (e.g., a silicon interposer). Such a system-on-integrated package substrate may include layer-to-layer interconnections achieved using solder material portions, microbumps, underfill material portions (e.g., molded underfill material portions), and / or adhesive films. Although the embodiments disclosed herein are described using exemplary substrate packages, it should be understood that the scope of the embodiments disclosed herein is not limited to any particular type of substrate package and may include system-on-integrated package substrates. The core substrate 210 may include a glass epoxy resin plate, including an array of through-holes. An array of through-hole structures 214, comprising metallic material, may be provided in the holes of the through-plate. Each through-hole structure 214 may or may not include a cylindrical hollow portion therein. Optionally, a dielectric pad 212 may be used to electrically isolate the through-hole structures 214 from the core substrate 210.

[0049] The packaging substrate 200 may include a surface laminate circuit (SLC) 240 and a wafer-side surface laminate circuit (SLC) 260. The surface laminate circuit 240 may include a surface insulating layer 242, on which surface wiring interconnects 244 are embedded. The wafer-side surface laminate circuit 260 may include a wafer insulating layer 262, on which wafer wiring interconnects 264 are embedded. The surface insulating layer 242 and the wafer insulating layer 262 may include a photosensitive epoxy resin material, which may be photolithographically patterned and subsequently cured. The surface wiring interconnects 244 and the wafer wiring interconnects 264 may include copper, which may be deposited within the pattern in the surface insulating layer 242 or the wafer insulating layer 262 by electroplating.

[0050] In one embodiment, the packaging substrate 200 includes wafer-side surface-addition (SLA) wiring 260 and board-side SLA wiring 240. The wafer-side SLA wiring 260 includes an array of wafer-side wiring interconnects 264 connected to an array of wafer-side bonding pads 268. The wafer-side bonding pads 268 are bonded to an array of second solder material portions 290. The board-side SLA wiring 240 includes an array of board-side wiring interconnects 244 connected to an array of board-side bonding pads 248. The array of board-side bonding pads 248 is configured to allow bonding via solder balls. The array of wafer-side bonding pads 268 is configured to allow bonding via controlled-collapse die-connected solder balls. Generally, any type of packaging substrate 200 can be used. Although this disclosure is described using one embodiment, wherein the package substrate 200 includes a wafer-side surface-addition line 260 and a board-side surface-addition line 240, various embodiments are expressly contemplated herein in which either the wafer-side surface-addition line 260 or the board-side surface-addition line 240 is omitted, or replaced by an array of bonding structures (e.g., microbumps). In one illustrative example, the wafer-side surface-addition line 260 may be replaced by an array of microbumps or any other array of bonding structures.

[0051] A second solder material portion 290 attached to the fan-out bonding pad 928 of the fan-out package 900 may be disposed on an array of wafer-side bonding pads 268 of the package substrate 200. A reflow process may be performed to reflow the second solder material portion 290, thereby resulting in bonding between the fan-out package 900 and the package substrate 200. In one embodiment, the second solder material portion 290 may include controlled-collapse die-connecting solder balls, and the fan-out package 900 may be attached to the package substrate 200 using an array of controlled-collapse die-connecting solder balls.

[0052] Referring to Figure 15, a second underfill material portion 292 can be formed around the second solder material portion 290 by applying and shaping the second underfill material. After reflowing the second solder material portion 290, the second underfill material portion 292 can be formed by injecting the second underfill material in an array around the second solder material portion 290. Any known underfill material application method can be used, for example, a capillary underfill method, a molding underfill method, or a printing underfill method.

[0053] The second underfill material portion 292 can contact each of the second solder material portions 290 (which may be a controlled-collapse chip bonding solder ball or a C2 solder cap) and can contact the vertical sidewalls of the fan-out package 900. The second underfill material portion 292 is formed between the redistribution structure 920 and the package substrate 200. The second underfill material portion 292 laterally surrounds and contacts the array of second solder material portions 290 and the fan-out package 900.

[0054] Optionally, the stabilizing structure 294 (e.g., a cover structure or a ring structure) may be attached to the assembly of the fan-out package 900 and the package substrate 200 to reduce deformation of the assembly during subsequent process steps and / or during the use of the assembly.

[0055] Referring to Figure 16, a printed circuit board (PCB) 100 may be provided, including a printed circuit board substrate 110 and a plurality of printed circuit board bonding pads 180. The PCB 100 includes a printed circuit (not shown) on at least one side of the PCB substrate 110. An array of solder contacts 190 may be formed to bond an array of board-side bonding pads 248 to the array of PCB bonding pads 180. The solder contacts 190 may be formed by disposing an array of solder balls between the array of board-side bonding pads 248 and the array of PCB bonding pads 180, and then reflowing the array of solder balls. An underfill portion 192 may be formed around the solder contacts 190 by applying and shaping an underfill material. A package substrate 200 is attached to the PCB 100 through the array of solder contacts 190.

[0056] Referring to Figure 17, a flowchart of steps for forming an exemplary structure is illustrated according to an embodiment of the present disclosure.

[0057] Referring to step 1710 and Figures 1, 2A and 2B, a redistribution structure 920 can be provided, including a redistribution side bonding structure 938 thereon.

[0058] Referring to step 1720 and Figures 3A to 6, a plurality of semiconductor dies (semiconductor die 700, semiconductor die 800) may be provided, including each of a set of die-side bonding structures (die-side bonding structure 780, die-side bonding structure 880).

[0059] Referring to step 1730 and Figures 3A to 6, using the first solder material portion 940, a plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800) can be bonded to the redistribution structure 920. The first solder material portion 940 is bonded to a redistribution-side bonding structure 938 and a die-side bonding structure (die-side bonding structure 780, die-side bonding structure 880) within the first subset of the redistribution-side bonding structures 938. The second subset of the redistribution-side bonding structures 938 (e.g., a dummy redistribution-side bonding structure 938D) is not bonded to any semiconductor die (semiconductor die 700, semiconductor dies 800).

[0060] Referring to step 1740 and Figures 7A and 7B, a first bottom filler material portion 950 can be formed around the first solder material portion 940, the redistribution side bonding structure 938, and the grain side bonding structure (grain side bonding structure 780, grain side bonding structure 880).

[0061] Referring to all the drawings and various embodiments of the present disclosure, a fan-out package is provided, including a redistribution structure 920, a plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800), and an underfill material portion (e.g., a first underfill material portion 950). The redistribution structure 920 includes a plurality of first metal bonding structures (e.g., redistribution side bonding structures 938) on one side. The semiconductor dies (semiconductor dies 700, semiconductor dies 800) include a plurality of second metal bonding structures (e.g., die-side bonding structures (die-side bonding structures 780, die-side bonding structures 880)) attached to the first metal bonding structure 938 through bump portions (e.g., first solder material portions 940). The underfill material portion laterally surrounds the first metal bonding structure 938 and the die-side bonding structures (die-side bonding structure 780, die-side bonding structure 880) of a plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800). A subset of the first metal bonding structure 938 includes at least one dummy metal bonding structure 938D, which is surrounded by the underfill material portion 950 and electrically isolated from the semiconductor dies (semiconductor dies 700, semiconductor dies 800) and the second metal bonding structures (die-side bonding structures 780, die-side bonding structures 880) by the underfill material portion 950. Generally, the first metal bonding structure and the second metal bonding structure can include any type of bonding structure, such as a controlled-collapse wafer bonding pad or a C2 bonding pillar or any other type of metal structure to which solder material can be bonded.

[0062] In one embodiment, in a planar view, at least one dummy metal bonding structure 938D is located between an adjacent pair of semiconductor grains (semiconductor grains 700, semiconductor grains 800) selected from a plurality of semiconductor grains (semiconductor grains 700, semiconductor grains 800). In one embodiment, in a planar view, at least one dummy metal bonding structure 938D does not have any regional overlap with the plurality of semiconductor grains (semiconductor grains 700, semiconductor grains 800).

[0063] In one embodiment, the fan-out package includes at least one dummy bump portion (e.g., at least one dummy solder material portion 940D) located on each of at least one dummy metal bonding structure 938D and not in contact with any second metal bonding structure (die-side bonding structure 780, die-side bonding structure 880). In one embodiment, all surfaces of the at least one dummy bump portion 938D are in contact with the underfill material portion 950 or the at least one dummy bump bonding portion 938D.

[0064] In one embodiment, at least one dummy bump portion 938D includes at least one row of dummy bump portions 938Ds arranged along a pair of sidewalls parallel to and between adjacent pairs of semiconductor grains (semiconductor grains 700, semiconductor grains 800) selected from a plurality of semiconductor grains (semiconductor grains 700, semiconductor grains 800). In one embodiment, each at least one dummy bump portion 938D has the same material composition as the bump portion 938.

[0065] In one embodiment, the fan-out package 900 may include a molded compound die frame 910 laterally surrounding a plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800) and comprising a molded compound material. In one embodiment, the molded compound die frame 910 may include sidewalls that are re-core perpendicular to the sidewalls of the redistribution structure 920.

[0066] In one embodiment, the redistribution structure 920 may include: a redistribution wiring interconnect 924 and a fan-out bonding pad 928. The redistribution wiring interconnect 924 is embedded in the redistribution dielectric layer 922 and electrically connected to a respective redistribution side bonding structure 938. The fan-out bonding pad 928 is located on the opposite side of the redistribution side bonding structure 938 and electrically connected to a respective redistribution side bonding structure 938.

[0067] In one embodiment, a plurality of semiconductor dies (semiconductor die 700, semiconductor die 800) include at least one system-on-a-chip (SoC) die 700 and a memory die 800. The memory die 800 is, for example, a high-bandwidth memory (HBM) die 810, comprising a vertically stacked static random access memory (SRAM) dies (SRAM dies 811, SRAM dies 812, SRAM dies 813, SRAM dies 814, SRAM dies 815), interconnected by microbumps 820, and laterally surrounded by an epoxy molding material enclosure 816.

[0068] According to one embodiment of the present disclosure, a structure including a fan-out package 900 may be provided, which may include: a redistribution structure 920, a plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800), and an underfill material portion 950. The redistribution structure 920 may include redistribution side bonding structures 938. Each semiconductor die (semiconductor die 700, semiconductor die 800) may include a respective set of die-side bonding structures (die-side bonding structures 780, die-side bonding structures 880) attached to a respective subset of the redistribution side bonding structures 938 via a respective set of solder material portions 940. The underfill material portion 950 laterally surrounds the redistribution side bonding structure 938 and the die-side bonding structures (die-side bonding structures 780, die-side bonding structures 880) of the plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800). A subset of the redistribution side bonding structures 938 (e.g., dummy redistribution side bonding structures 938D) is not bonded to any of the grain-side bonding structures (grain-side bonding structures 780, grain-side bonding structures 880) of the plurality of semiconductor grains (semiconductor grains 700, semiconductor grains 800), and is laterally surrounded by the first bottom filler material portion 950.

[0069] In one embodiment, in a planar view, a subset of the redistribution-side bonding structure 938 (e.g., a dummy redistribution-side bonding structure 938D) is located between adjacent pairs of semiconductor dies (semiconductor dies 700, semiconductor dies 800) selected from a plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800). In one embodiment, in a planar view, a subset of the redistribution-side bonding structure 938 (e.g., a dummy redistribution-side bonding structure 938D) does not have regional overlap with any of the plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800).

[0070] In one embodiment, the fan-out package may include a dummy solder material portion 940D located on a redistribution side bonding structure 938 (e.g., a dummy redistribution side bonding structure 938D) selected from a subset of redistribution side bonding structures 938. In some embodiments, the dummy solder material portion 940D and the dummy redistribution side bonding structure 938D may be non-contact and / or electrically connected to any one of a plurality of semiconductor dies (semiconductor die 700, semiconductor die 800).

[0071] In one embodiment, all surfaces of the dummy solder material portion 940D may contact a subset of the first underfill material portion 950 or the redistribution side bonding structure 938 (e.g., dummy redistribution side bonding structure 938D). In one embodiment, the dummy solder material portion 940D may include at least one row of dummy solder material portions 940D arranged along a pair of sidewalls parallel to and between adjacent pairs of semiconductor grains (semiconductor grains 700, semiconductor grains 800) selected from a plurality of semiconductor grains (semiconductor grains 700, semiconductor grains 800). In one embodiment, each dummy solder material portion 940D may have the same material composition as the plurality of sets of solder material portions 940.

[0072] According to one embodiment of the present disclosure, a chip package structure is provided, which may include: a fan-out package 900, a plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800), a first underfill material portion 950, and a package substrate 200. The fan-out package 900 includes a redistribution structure 920, which includes a redistribution side bonding structure 938. Each semiconductor die (semiconductor die 700, semiconductor die 800) may include a set of die-side bonding structures (die-side bonding structures 780, die-side bonding structures 880), which may be attached to a subset of the redistribution side bonding structure 938 through a set of first solder material portions 940. The first underfill material portion 950 laterally surrounds the redistribution side bonding structure 938 and the die-side bonding structures (die-side bonding structures 780, die-side bonding structures 880) of the plurality of semiconductor dies (semiconductor dies 700, semiconductor 800). In a planar view, a subset of the redistribution-side bonding structure 938 (e.g., a dummy redistribution-side bonding structure 938D) may be located between adjacent pairs of semiconductor dies (semiconductor dies 700, semiconductor dies 800) selected from a plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800). The package substrate 200 is attached to the fan-out package 900 via an array of second solder material portions 290.

[0073] In one embodiment, the wafer packaging structure may include a molded compound die frame 910 that laterally surrounds a plurality of semiconductor dies (semiconductor dies 700, semiconductor dies 800) and may include a molded compound material that contacts the periphery of the planar surface of the redistribution structure 920.

[0074] In one embodiment, the wafer package structure may include a second underfill material portion 292 that laterally surrounds an array of second solder material portions 290 and a fan-out package 900.

[0075] In one embodiment, a subset of the redistribution side bonding structure 938 (e.g., a dummy redistribution side bonding structure 938D) is not bonded to any of the grain-side bonding structures (grain-side bonding structure 780, grain-side bonding structure 880) of the plurality of semiconductor grains (semiconductor grains 700, semiconductor grains 800), and can be laterally surrounded and contacted by the first bottom filler portion 950.

[0076] Various structures and methods disclosed in this embodiment can be used to provide a wafer packaging structure, including a fan-out package 900. The fan-out package 900 includes a dummy redistribution side bonding structure 938D and a dummy solder material portion 940D, modifies the pattern of the conduit for the underfill material, and increases the capillary force on the underfill material. Various methods and structures disclosed in this embodiment can be used to reduce or eliminate voids in the first underfill material portion 950 and increase the reliability of the fan-out package 900.

[0077] According to some embodiments of this disclosure, a fan-out package includes: a redistribution structure, a plurality of semiconductor dies, and an underfill material portion. The redistribution structure includes a plurality of first metal bonding structures on one side. The plurality of semiconductor dies include a plurality of second metal bonding structures attached to the first metal bonding structures through a plurality of bump portions. The underfill material portion laterally surrounds the first metal bonding structure and the second metal bonding structures of the semiconductor dies. A subset of the first metal bonding structures includes at least one dummy metal bonding structure surrounded by the underfill material portion and electrically isolated from the semiconductor dies and the second metal bonding structures by the underfill material portion.

[0078] In some embodiments, in a planar view, at least one dummy metal structure is located between a pair of adjacent semiconductor dies selected from semiconductor dies. In some embodiments, in a planar view, at least one dummy metal structure does not have a region overlapping with any semiconductor die. In some embodiments, the fan-out package further includes at least one dummy bump portion positioned on each of the at least one dummy metal structure and not in contact with any second metal bonding structure. In some embodiments, all surfaces of the at least one dummy bump portion are in contact with an underfill material portion or with at least one dummy metal bonding structure. In some embodiments, the at least one dummy bump portion includes at least one row of dummy solder material portions arranged along a direction parallel to a pair of sidewalls of a pair of adjacent semiconductor dies selected from semiconductor dies and located between these pair of sidewalls. In some embodiments, each of the at least one dummy bump portion has the same material composition as the bump portion. In some embodiments, the fan-out package further includes a molded compound die frame laterally surrounding the semiconductor die and including a molded compound material. In some embodiments, the molded compound die frame includes a plurality of sidewalls perpendicularly overlapping with a plurality of sidewalls of the redistribution structure. In some embodiments, the redistribution structure includes: a plurality of redistribution wiring interconnects and a plurality of fan-out metal bonding structures. The plurality of redistribution wiring interconnects are embedded in a plurality of redistribution dielectric layers and electrically connected to each of the plurality of redistribution side bonding structures. The plurality of fan-out metal bonding structures are located on an opposite side of the redistribution side bonding structures and electrically connected to each of the redistribution side bonding structures. In some embodiments, the semiconductor die includes: at least one single-chip system die and a high-bandwidth memory die. The high-bandwidth memory die includes a vertically stacked plurality of static random access memory (SRAM) dies interconnected by a plurality of microbumps and laterally surrounded by an epoxy molding compound enclosure.

[0079] According to some other embodiments of the present disclosure, a chip package structure includes: a fan-out package and a package substrate. The fan-out package includes a redistribution structure, a plurality of semiconductor dies, and a first underfill material portion. The redistribution structure includes a plurality of redistribution side bonding structures. The semiconductor dies include each of the plurality of die-side bonding structures as a set. The die-side bonding structures are attached to each subset of the redistribution side bonding structures via each of the plurality of first solder material portions. The first underfill material portions laterally surround the redistribution side bonding structure and the die-side bonding structures of the semiconductor dies. In a planar view, a subset of the redistribution side bonding structures is located between a pair of adjacent semiconductor dies selected from the semiconductor dies. The package substrate is attached to the fan-out package via an array of a plurality of second solder material portions.

[0080] In some embodiments, the wafer package structure further includes a molded compound die frame laterally surrounding the semiconductor die and including a molded compound material contacting a surrounding portion of a planar surface of the redistribution structure. In some embodiments, the wafer package structure further includes a second underfill material portion laterally surrounding an array of second solder material portions and a fan-out package. In some embodiments, a subset of the redistribution-side bonding structures is not bonded to any of the die-side bonding structures of the semiconductor die and is laterally surrounded by and in contact with the first underfill material portion.

[0081] According to some other embodiments of the present disclosure, a method of forming a wafer package structure includes: providing a redistribution structure including a plurality of redistribution side bonding structures thereon; providing a plurality of semiconductor dies, including each of a plurality of die-side bonding structures; bonding the semiconductor dies to the redistribution structure using a plurality of first solder material portions, the first solder material portions being bonded to each of a redistribution side bonding structure in a first subset of the redistribution side bonding structures and to each of the die-side bonding structures, wherein a second subset of the redistribution side bonding structures is not bonded to any of the semiconductor dies; and forming a first underfill material portion around the first solder material portions, the redistribution side bonding structures and the die-side bonding structures.

[0082] In some embodiments, the method further includes: forming a first solder material portion on a first subset of the redistribution-side bonding structure; and forming a plurality of additional first solder material portions on a second subset of the redistribution-side bonding structure, wherein the additional first solder material portions are not bonded to any die-side bonding structure. In some embodiments, a first underfill material portion laterally surrounds and contacts each of the additional first solder material portions. In some embodiments, the method further includes forming a molded compound die frame around a semiconductor die after forming the first underfill material portions. In some embodiments, the method further includes: attaching the redistribution structure to a package substrate using an array of a plurality of second solder material portions; and forming a second underfill material portion around the array of second solder material portions between the redistribution structure and the package substrate.

[0083] The foregoing outlines features of numerous embodiments, enabling those skilled in the art to better understand this disclosure from various aspects. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on this disclosure to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the inventive spirit and scope of this disclosure. Various changes, substitutions, or modifications can be made to this disclosure without departing from the inventive spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0006] The following detailed description, in conjunction with the accompanying drawings, provides a complete disclosure. It should be emphasized that, in accordance with the general practice of the industry, the illustrations are not necessarily drawn to scale. In fact, the dimensions of components may be arbitrarily enlarged or reduced for clarity. Figure 1 is a vertical cross-sectional view of a region of an exemplary structure according to one embodiment of the present disclosure, including a first carrier substrate and a redistribution structure. Figure 2A is a vertical cross-sectional view of a region of the exemplary structure after the redistribution side bonding structure and the first solder material portion have been formed, according to one embodiment of the present disclosure. Figure 2B is a top view of a region of the exemplary structure in Figure 2A. Figure 3A is a vertical cross-sectional view of a region of the exemplary structure after a semiconductor die has been attached, according to one embodiment of the present disclosure. Figure 3B is a top view of a region of the exemplary structure in Figure 3A. Figure 4A is a top view of a region of a first alternative configuration of the exemplary structure after a semiconductor die has been attached, according to one embodiment of the present disclosure. Figure 4B is a top view of a region of a second alternative configuration of the exemplary structure after a semiconductor die has been attached, according to one embodiment of the present disclosure. Figure 4C is a top view of a region of a third alternative configuration of an exemplary structure after attaching a semiconductor die, according to one embodiment of the present disclosure. Figure 5A illustrates a top view of an alternative shape of the first solder material portion according to one embodiment of the present disclosure. Figure 5B illustrates a top view of an additional alternative shape of the first solder material portion according to one embodiment of the present disclosure. Figure 6 is an enlarged vertical cross-sectional view of a high-bandwidth memory die. Figure 7A is a vertical cross-sectional view of a region of an exemplary structure after forming a first underfill material portion, according to one embodiment of the present disclosure. Figure 7B is a top view of a region of the exemplary structure in Figure 7A. Figure 8A is a vertical cross-sectional view of a region of an exemplary structure after forming an epoxy molding compound (EMC) matrix, according to one embodiment of the present disclosure. Figure 8B is a top view of a region of the exemplary structure in Figure 8A. Figure 9 is a vertical cross-sectional view of a region of an exemplary structure after attaching a second carrier substrate and removing the first carrier substrate, according to one embodiment of the present disclosure. Figure 10 is a vertical cross-sectional view of a region of an exemplary structure after the fan-out bonding pad has been formed, according to one embodiment of the present disclosure. Figure 11 is a vertical cross-sectional view of a region of an exemplary structure after the second carrier substrate has been removed, according to one embodiment of the present disclosure. Figure 12 is a vertical cross-sectional view of a region of an exemplary structure during the dicing of the reconstituted wafer and epoxy molding compound matrix, according to one embodiment of the present disclosure. Figure 13 is a vertical cross-sectional view of a fan-out package, according to one embodiment of the present disclosure. Figure 14 is a vertical cross-sectional view of an exemplary structure after the fan-out package has been attached to a package substrate, according to one embodiment of the present disclosure.Figure 15 is a vertical cross-sectional view of an exemplary structure after the formation of the second underfill material portion, according to one embodiment of the present disclosure. Figure 16 is a vertical cross-sectional view of an exemplary structure after the package substrate is attached to a printed circuit board (PCB), according to one embodiment of the present disclosure. Figure 17 is a flowchart illustrating the steps for forming the exemplary structure, according to one embodiment of the present disclosure.

Claims

1. A fan-out package, comprising: A single-distribution structure, comprising a plurality of first metal bonding structures on one side; A plurality of semiconductor dies, including a plurality of second metal bonding structures attached to the first metal bonding structures through a plurality of solder material portions, wherein the semiconductor dies include a first semiconductor die having a first sidewall and being separately disposed from a second semiconductor die having a second sidewall, thereby, in a planar view along a vertical direction, a gap region laterally exists between the first semiconductor die and the second semiconductor die, wherein the gap region laterally is formed by four vertical planes connecting two vertically extending edges of the first sidewall and two vertically extending edges of the second sidewall. The planar definition includes a bottom filler portion comprising a horizontal extension that laterally surrounds the first metal bonding structures and the second metal bonding structures of the semiconductor dies and contacts each of the solder material portions, the bottom filler portion further comprising a vertical extension adjacent to the horizontal extension, contacting the first sidewall and the second sidewall and filling the entire volume of the gap region, the gap region being vertically defined by a horizontal plane including the top surfaces of the first semiconductor dies and the second semiconductor dies and the horizontal extension portion, and laterally defined by the four vertical planes; wherein a subset of the first metal bonding structures includes a dummy metal bonding structure that is surrounded by the bottom filler portion and electrically isolated from the semiconductor dies and the second metal bonding structures by the bottom filler portion, and is in direct contact with a dummy solder material portion, and is located entirely within the area of ​​the vertical extension portion of the bottom filler portion in the plan view.

2. The fan-out package as claimed in claim 1, wherein the dummy solder material portion is located on the dummy metal bonding structure and does not contact any of the second metal bonding structures.

3. A fan-out package, comprising: A single-distribution structure, comprising a plurality of first metal bonding structures on one side; A plurality of semiconductor dies, including a plurality of second metal bonding structures attached to the first metal bonding structures through a plurality of solder material portions, wherein the semiconductor dies include a first semiconductor die having a first sidewall and being separately disposed from a second semiconductor die having a second sidewall, thereby, in a planar view along a vertical direction, a gap region laterally exists between the first semiconductor die and the second semiconductor die, wherein the gap region laterally is formed by four vertical planes connecting two vertically extending edges of the first sidewall and two vertically extending edges of the second sidewall. The planar definition includes a bottom filler portion comprising a horizontal extension that laterally surrounds the first metal bonding structures and the second metal bonding structures of the semiconductor dies and contacts each of the solder material portions, the bottom filler portion further comprising a vertical extension that adjoins the horizontal extension, contacts the first sidewall and the second sidewall and fills the entire volume of the gap region, the gap region being vertically defined by a horizontal plane including the top surfaces of the first semiconductor dies and the second semiconductor dies and the horizontal extension, and laterally defined by the four vertical planes; wherein a subset of the first metal bonding structures includes a dummy metal bonding structure having a top surface and being entirely located within the area of ​​the vertical extension of the bottom filler portion in the plan view, and wherein the entire area of ​​the top surface of the dummy metal bonding structure is in direct contact with a dummy solder material portion.

4. A fan-out package, comprising: A single-distribution structure, comprising a plurality of first metal bonding structures on one side; A plurality of semiconductor dies, including a plurality of second metal bonding structures attached to the first metal bonding structures through a plurality of solder material portions, wherein the semiconductor dies include a first semiconductor die having a first sidewall and being separately disposed from a second semiconductor die having a second sidewall, thereby, in a planar view along a vertical direction, a gap region laterally exists between the first semiconductor die and the second semiconductor die, wherein the gap region laterally is formed by four vertical planes connecting two vertically extending edges of the first sidewall and two vertically extending edges of the second sidewall. The planar definition includes a bottom filler portion comprising a horizontal extension that laterally surrounds the first metal bonding structures and the second metal bonding structures of the semiconductor dies and contacts each of the solder material portions, the bottom filler portion further comprising a vertical extension adjacent to the horizontal extension, contacting the first sidewall and the second sidewall and filling the entire volume of the gap region, the gap region being vertically defined by a horizontal plane including the top surfaces of the first semiconductor dies and the second semiconductor dies and the horizontal extension, and laterally defined by the four vertical planes; wherein a subset of the first metal bonding structures includes a dummy metal bonding structure that is electrically isolated from and electrically floating of the semiconductor dies and the second metal bonding structures, and directly contacts a dummy solder material portion, and is located entirely within the area of ​​the vertical extension of the bottom filler portion in the plan view.

5. A chip packaging structure, comprising: A fan-out package includes a redistribution structure, a plurality of semiconductor dies, and a first underfill material portion. The redistribution structure includes a plurality of redistribution side bonding structures. The semiconductor dies include a corresponding set of die-side bonding structures attached to a corresponding subset of the redistribution side bonding structures via a corresponding set of first solder material portions. The first underfill material portion laterally surrounds the redistribution side bonding structures and the die-side bonding structures of the semiconductor dies. A subset of the redistribution side bonding structures is located in a plan view between adjacent pairs of semiconductor dies selected from the semiconductor dies. A package substrate is attached to the fan-out package via an array of a plurality of second solder material portions.

6. A chip packaging structure, comprising: A fan-out package includes a redistribution structure, a plurality of semiconductor dies, and a first underfill portion. The redistribution structure includes a plurality of first metal bonding structures on one side. The semiconductor dies include a plurality of second metal bonding structures attached to the first metal bonding structures via an array of a plurality of first solder portions. The first underfill portion laterally surrounds the first solder portions. A subset of the first metal bonding structures includes at least one dummy metal bonding structure surrounded by the first underfill portion and electrically isolated from the semiconductor dies and the second metal bonding structures by the first underfill portion. A package substrate is attached to the fan-out package via an array of a plurality of second solder portions.

7. The wafer package structure of claim 6, wherein the at least one dummy metal bonding structure is located in a plan view between an adjacent pair of semiconductor dies selected from the semiconductor dies.

8. The wafer package structure of claim 7, wherein the at least one dummy metal bonding structure does not have regional overlap with any of the semiconductor dies in the plan view.

9. The wafer package structure of claim 6 further includes at least one dummy solder material portion located on the counterpart of the at least one dummy metal bonding structure and not in contact with any of the second metal bonding structures.

10. A chip packaging structure, comprising: A fan-out package includes a redistribution structure, a plurality of semiconductor dies, and a first underfill material portion. The redistribution structure includes a plurality of first metal bonding structures on one side. The semiconductor dies include a plurality of second metal bonding structures attached to the first metal bonding structures via a plurality of first solder material portions. The first underfill material portion laterally surrounds the first metal bonding structures and the second metal bonding structures of the semiconductor dies. A subset of the first metal bonding structures includes at least one dummy metal bonding structure having a corresponding top surface, the entire area of ​​which is positioned by a corresponding dummy solder material portion. A package substrate is attached to the fan-out package via an array of a plurality of second solder material portions.

11. A method for forming a wafer package structure, the method comprising: Provide a redistribution structure, including a plurality of redistribution side-binding structures thereon; Provides a plurality of semiconductor dies, including a corresponding set of die-side bonding structures; bonds the semiconductor dies to the redistribution structure using a plurality of first solder material portions, the first solder material portions being bonded to corresponding redistribution side bonding structures in a first subset of the redistribution side bonding structures and to corresponding die-side bonding structures, wherein a second subset of the redistribution side bonding structures is not bonded to any of the die-side bonding structures of the semiconductor dies; and forms a first underfill material portion around the first solder material portions, the redistribution side bonding structures and the die-side bonding structures.

12. The method of request item 11 further includes: The first solder material portions are formed on the first subset of the redistributed side bonding structures; And a plurality of additional first solder material portions are formed on the second subset of the redistributed side bonding structures, wherein the additional first solder material portions are not bonded to any of the grain-side bonding structures.

13. A method for forming a wafer package structure, the method comprising: Provide a redistribution structure, including a plurality of redistribution side-binding structures; And a plurality of semiconductor dies including a corresponding set of die-side bonding structures are attached, wherein the corresponding set of die-side bonding structures is bonded to a corresponding set of redistribution side bonding structures through a first solder material portion of the corresponding set, wherein a subset of the redistribution side bonding structures is located in a plan view between adjacent pairs of semiconductor dies selected from the semiconductor dies, and does not overlap with any region of the semiconductor dies in the plan view.

14. As in request item 13, wherein: The subset of the redistributed side bonding structures is not bonded to any of the grain-side bonding structures of the semiconductor grains, and the method further includes forming a first underfill material directly on the subset of the redistributed side bonding structures, wherein the first underfill material is formed directly on a plurality of sidewalls of the subset of the redistributed side bonding structures.

15. A method for forming a wafer package structure, the method comprising: A redistribution structure is provided, comprising a plurality of first metal bonding structures on a first side; a plurality of semiconductor dies comprising a plurality of second metal bonding structures are attached to the redistribution structure, wherein the second metal bonding structures are attached to a first subset of the first metal bonding structures through a plurality of solder material portions, wherein a gap region exists between adjacent pairs of semiconductor dies, and a second subset of the first metal bonding structures comprising a dummy metal bonding structure is located in the gap region in a plan view and does not overlap with any region of the semiconductor dies; and an underfill material is formed around the solder material portions, wherein the underfill material includes a horizontal extension that laterally surrounds the second metal bonding structures of the first metal bonding structures and the semiconductor dies and contacts each of the solder material portions, and the underfill material portion also includes a vertical extension that fills the gap region.

Images