Three-dimensional (3D) metal-insulator-metal capacitor (mimcap) including stacked vertical metal studs for increased capacitance density and related fabrication methods

Abstract

A three-dimensional (3D) metal-insulator-metal capacitor (MIMCAP) includes a plurality of central bolts disposed within the cavity walls of a plurality of cavities in a top plate. The central bolts and cavity walls are oriented orthogonal to a first metal layer and extend through a first through-hole layer and a second metal layer. Each central bolt includes a metal layer bolt in the second metal layer stacked on top of through-hole layer bolts in the first through-hole layer. A dielectric layer is disposed between the cavity walls of the plurality of cavities in the top plate and the central bolts. The central bolts are coupled to a first electrode, and the top plate is coupled to a second electrode in an interconnect layer. In some examples, the central bolts may be formed as vertically oriented cylindrical capacitor elements positioned for high capacitance density.

Description

Technical Field

[0001] The field of this disclosure relates to capacitors formed on integrated circuits, and more particularly to metal-insulator-metal (MIM) capacitors (MIMCAPs) formed in back-end process (BEOL) processes. Prior Technology

[0002] Capacitors are critical components in radio frequency (RF) and analog circuits. Parallel-plate capacitors (known as MIMCAPs) can be formed on integrated circuits (ICs) in front-end online (FEOL) and back-end online (BEOL) processes. The capacitance between metal plates can be increased by reducing the distance between the plates and by increasing the dielectric constant (k) of the dielectric layer between the metal plates; however, both methods rely on developing dielectrics that can increase the dielectric constant while avoiding leakage current that can be transferred from one plate to another through the dielectric. A third method for increasing plate capacitance is to increase the surface area of ​​the plates. To increase the surface area of ​​the plates without increasing the die area (e.g., horizontal area) of the IC, IC designers have explored techniques for forming capacitors whose metal plates extend orthogonally (e.g., vertically) to the surface of the semiconductor die. FEOL processes for developing MIMCAPs include, for example, forming metal plates for the capacitor on the sidewalls of trenches in the semiconductor die; however, this method occupies valuable surface area on the semiconductor die that could be used for active (transistor) circuitry, and minimizing die size has always been desirable. As trench depths increase to increase capacitor surface area, the process for forming MIMCAPs within semiconductor dies faces challenges. The BEOL process involves forming MIMCAPs with horizontal plates within the metal interconnect layers of an integrated circuit. While such MIMCAPs avoid occupying semiconductor die surface area, the area occupied by the metal plates cannot be used for vertical interconnect take-ups (vias). Furthermore, horizontal metal interconnects on the same metal layer as the MIMCAP must be routed around it, increasing wiring congestion and metal trace length. Additionally, increasing the MIMCAP area to increase capacitance exacerbates wiring problems. One BEOL process is similar to the aforementioned FEOL process, where trenches are created in the interlayer dielectric between metal wiring layers. Further improvements to BEOL MIMCAP technology are needed to increase capacitance density in ICs. Summary of the Invention

[0003] The exemplary embodiments disclosed in the detailed description include a three-dimensional (3D) metal-insulator-metal (MIM) capacitor (MIMCAP) comprising vertically stacked metal bolts for increased capacitance density. Related methods for manufacturing 3D MIMCAPs are also disclosed. MIMCAPs are important components in radio frequency (RF) and analog circuits. During back-end processing (BEOL) of integrated circuits (ICs), MIMCAPs can be formed in interconnect layers including through-hole layers interleaved with metal layers on semiconductor dies. MIMCAPs comprise parallel metal plates separated by thin dielectric layers, and the capacitance provided by the MIMCAP increases with the area of ​​the parallel metal plates. To reduce the area occupied by the MIMCAP in the interconnect layer, at least some of the metal plates of the MIMCAP are oriented orthogonally (e.g., perpendicular) to the semiconductor surface, and high capacitance density can be achieved by closely spacing the orthogonally oriented metal plates. In the exemplary embodiment, the 3D MIMCAP includes a plurality of central bolts disposed within the cavity walls of a cavity in a top plate. The central bolt and cavity wall are oriented orthogonal to the first metal layer and extend through the first through-hole layer and the second metal layer. Each central bolt includes a metal layer bolt in the second metal layer stacked on a through-hole layer bolt in the first through-hole layer. A dielectric layer is disposed between the cavity wall of the cavity and the bolt sidewall in the top plate. A plurality of central bolts are coupled to a first electrode, and the top plate is coupled to a second electrode to form a MIMCAP with high capacitance density in the interconnect layer. In some examples, the central bolt and cavity wall are formed as vertically oriented cylindrical capacitor elements positioned for high capacitance density. In such examples, the central bolt is a solid metal cylindrical element, and the cavity wall of the cavity in the top plate forms a metal cylinder concentric with the central bolt. In some examples, the three-electrode capacitor includes a conformal metal layer between the cavity wall of the cavity and the bolt sidewall of the central bolt, such that the conformal metal layer can be the third electrode. The three-electrode capacitor includes a dielectric layer between the conformal metal layer and the cavity wall, and another dielectric layer between the conformal metal layer and the bolt sidewall. In some examples, a first cylindrical capacitor element is formed in a first through-hole layer and a second metal layer, and a second cylindrical capacitor element is formed in a second through-hole layer and a third metal layer stacked on the first cylindrical capacitor element to increase capacitance density.

[0004] In a first exemplary embodiment, a 3D MIMCAP is disclosed. The 3D MIMCAP includes a plurality of central bolts, each of the central bolts including a bolt sidewall orthogonal to a first surface of a first metal layer and extending through a first through-hole layer and a second metal layer. The 3D MIMCAP includes a top plate including a plurality of cavities, each of the cavities including a cavity wall surrounding the bolt sidewall of each of the central bolts. The 3D MIMCAP further includes a dielectric layer disposed between the cavity wall of each of the cavities in the top plate and the bolt sidewall of the corresponding central bolt among the cavities.

[0005] In another exemplary embodiment, a method for manufacturing a 3D MIMCAP is disclosed. The method includes forming a plurality of central bolts, each of the plurality of central bolts including a bolt sidewall orthogonal to a first surface of a first metal layer and extending through a first through-hole layer and a second metal layer. The method includes forming a top plate including a plurality of cavities, each of the plurality of cavities including a cavity wall surrounding the bolt sidewall of each of the plurality of central bolts. The method further includes forming a dielectric layer between the cavity wall of each of the plurality of cavities of the top plate and the bolt sidewall of the corresponding central bolt of the plurality of central bolts.

[0006] In another exemplary embodiment, a 3D MIMCAP is disclosed. The 3D MIMCAP includes a base plate in a first metal layer, the base plate including a first surface. The 3D MIMCAP includes a plurality of central bolts extending from the first surface of the base plate through a first through-hole layer and a second metal layer. The plurality of central bolts includes bolt sidewalls orthogonal to the first surface of the base plate, a bottom bolt end on the first surface of the base plate, and a top bolt end opposite to the bottom bolt end. The 3D MIMCAP includes a top plate including a plurality of cavities, each cavity including a cavity wall surrounding the bolt sidewalls of the plurality of central bolts. The 3D MIMCAP includes a conformal metal layer disposed between the cavity walls of the plurality of cavities of the top plate and the bolt sidewalls of the plurality of central bolts, and disposed on the top bolt ends of the plurality of central bolts. The 3D MIMCAP includes a first dielectric layer disposed between the conformal metal layer and the plurality of central bolts on the top bolt ends and bolt sidewalls, and a second dielectric layer disposed between the conformal metal layer and the top plate.

[0007] In another exemplary embodiment, a method for manufacturing a 3D MIMCAP is disclosed. The method includes forming a base plate in a first metal layer, the base plate including a first surface. The method includes forming a plurality of central bolts extending from the first surface of the base plate through a first through-hole layer and a second metal layer, the plurality of central bolts including bolt sidewalls orthogonal to the first surface of the base plate, a bottom bolt end on the first surface of the base plate, and a top bolt end opposite to the bottom bolt end. The method includes forming a top plate including a plurality of cavities, the cavities including cavity walls surrounding the bolt sidewalls of the plurality of central bolts. The method includes forming a conformal metal layer between the cavity walls of the plurality of cavities of the top plate and the bolt sidewalls of the plurality of central bolts and disposed on the top bolt ends of the plurality of central bolts. The method includes forming a first dielectric layer between the conformal metal layer and the plurality of central bolts on the top bolt ends and bolt sidewalls, and forming a second dielectric layer between the conformal metal layer and the top plate. Simple Explanation of the Diagram

[0008] Figure 1 is a perspective view of a three-dimensional (3D) metal-insulator-metal (MIM) capacitor (MIMCAP), which includes a plurality of vertically oriented central bolts disposed in a plurality of cavities in a top plate to provide high-density capacitance;

[0009] Figure 2 is a cross-sectional side view of a semiconductor die, corresponding to the cross-section taken along line A-A' in Figure 1. The semiconductor die includes a transistor and an overlay interconnect layer, which includes a dual-electrode MIMCAP formed by central bolts disposed in a plurality of cavities in a top plate.

[0010] Figure 3 is a flowchart of the process of manufacturing the MIMCAP in the example of Figure 2, which is formed by central bolts provided in a plurality of cavities in the top plate;

[0011] Figure 4 is a cross-sectional side view of the semiconductor die and the overlying interconnect layer, including a three-electrode MIMCAP formed by central bolts disposed in a plurality of cavities in the top plate;

[0012] Figure 5 is a flowchart of the process of manufacturing the MIMCAP in the example of Figure 2, which is formed by central bolts disposed in a plurality of cavities in the top plate;

[0013] Figure 6 is a cross-sectional side view of a semiconductor die and an overlying interconnect layer, including a first plurality of central bolts disposed in a first top plate in a first through-hole layer and a second metal layer, and a second plurality of central bolts disposed in a second top plate in a second through-hole layer and a third metal layer;

[0014] Figures 7A-7E are cross-sectional side views illustrating the MIMCAP as shown in Figure 2 at various stages of the manufacturing process;

[0015] Figures 8A-8E are flowcharts of the manufacturing process of MIMCAP, which include the stages shown in Figures 7A-7E.

[0016] Figure 9 is a block diagram of an exemplary wireless communication device including an integrated circuit (IC). The IC includes a MIMCAP formed in an interconnect layer. The MIMCAP includes a center bolt orthogonal to a first metal layer in a cavity of a top plate disposed in a first through-hole layer and a second metal layer to provide high capacitance density, as shown in Figures 1, 2, 4, and 6; and

[0017] Figure 10 is a block diagram of an exemplary processor-based system that may include an IC including a MIMCAP formed in an interconnect layer. The MIMCAP includes a central bolt orthogonal to a first metal layer in a cavity of a top plate disposed in a first through-hole layer and a second metal layer to provide high capacitance density, as shown in Figures 1, 2, 4 and 6 and as may be disclosed herein. Implementation

[0018] Referring now to the diagrams, several exemplary forms of this disclosure are described. The word “exemplary” is used herein to mean “as an example, instance, or illustration.” Any form described herein as “exemplary” is not necessarily to be construed as superior to or more advantageous than other forms.

[0019] The exemplary specimens disclosed in the detailed description include a three-dimensional (3D) metal-insulator-metal (MIM) capacitor (MIMCAP) comprising vertically stacked metal bolts for increased capacitance density. Related methods for manufacturing 3D MIMCAPs are also disclosed. MIMCAPs are important components in radio frequency (RF) and analog circuits. During back-end processing (BEOL) of integrated circuits (ICs), MIMCAPs can be formed in interconnect layers including through-via layers interleaved with metal layers on semiconductor dies. MIMCAPs comprise parallel metal plates separated by thin dielectric layers, and the capacitance provided by the MIMCAP increases with the area of ​​the parallel metal plates. To reduce the area occupied by the MIMCAP in the interconnect layer, at least some of the metal plates of the MIMCAP are oriented orthogonally (e.g., perpendicular) to the semiconductor surface, and high capacitance density can be achieved by closely spacing the orthogonally oriented metal plates. In the exemplary specimen, the 3D MIMCAP includes a plurality of central bolts disposed within the cavity walls of cavities in a top plate. The central bolt and cavity wall are oriented orthogonal to the first metal layer and extend through the first through-hole layer and the second metal layer. Each central bolt includes a metal layer bolt in the second metal layer, which is stacked on top of the through-hole bolt in the first through-hole layer. A dielectric layer is disposed between the bolt sidewall and the cavity wall of the cavity in the top plate. A plurality of central bolts are coupled to a first electrode, and the top plate is coupled to a second electrode to form a MIMCAP with high capacitance density in the interconnect layer. In some examples, the central bolt and cavity wall form a vertically oriented cylindrical capacitor element positioned for high capacitance density. In such examples, the central bolt is a solid metal cylindrical element, and the cavity wall of the cavity in the top plate forms a metal cylinder concentric with the central bolt. In some examples, the three-electrode capacitor includes a conformal metal layer between the cavity wall of the cavity and the bolt sidewall of the central bolt, such that the conformal metal layer can be the third electrode. The three-electrode capacitor includes a dielectric layer between the conformal metal layer and the cavity wall, and another dielectric layer between the conformal metal layer and the bolt sidewall. In some examples, a first cylindrical capacitor element is formed in a first through-hole layer and a second metal layer, and a second cylindrical capacitor element is formed in a second through-hole layer and a third metal layer stacked on the first cylindrical capacitor element to increase capacitance density.

[0020] Figure 1 is a perspective view of the MIMCAP 100, which provides high capacitance density to the substrate 102 by employing a plurality of central bolts 104 disposed in a cavity 106 of the top plate 108. The central bolts 104 have bolt sidewalls 110 (in the Z-axis direction) orthogonal to the first metal layer 112. Orthogonality may be referred to herein as "perpendicular," but is not intended to be limited to a specific spatial orientation other than that relative to the first metal layer 112 (which extends in the X and Y axes). Having perpendicular bolt sidewalls 110 reduces the area used in the first metal layer 112 to provide quantitative capacitance. Specifically, as shown in the example in Figure 1, the central bolts 104 may be cylindrical, and corresponding to the cavity walls 114 in the cavity 106, the cavity 106 is also cylindrical to increase the density of the capacitor plate area.

[0021] Here, the center bolt 104 has a first end 116 and a second end 120 opposite to the first end 116. The first end 116 is on the first surface 118 of the base plates 122A and 122B in the first metal layer 112. In this example, the base plates 122A and 122B are metal interconnects 124 formed in the metal rails 126 of the first metal layer 112. Therefore, the first surface 118 of the base plates 122A and 122B is also the first surface 118 of the first metal layer 112. The center distance DY (in the Y-axis direction) between the center bolts 104 on the different base plates 122A and 122B corresponds to the rail spacing P 126 of the metal rails 126. The base plates 122A and 122B can be electrically coupled to each other to include the center bolts 104 on the base plate 122A and the center bolts 104 on the base plate 122B in the same MIMCAP 100. Alternatively, the base plates 122A and 122B can be electrically decoupled to form a separate MIMCAP 100. The center bolt 104 extends orthogonally to the first surface 118, and in this respect, increasing the capacitance provided by the MIMCAP 100 does not increase the area occupied in the first metal layer 112. Instead, the capacitance increases with the height H 104 (in the Z-axis direction) of the center bolt 104 and the corresponding cavity wall 114. The center bolt 104 extends from the first surface 118 of the base plates 122A and 122B through the first through-hole layer 128 and also through the second metal layer 130. In this respect, the center bolt 104 includes a through-hole bolt 132 in the first through-hole layer 128 and a metal layer bolt 134 in the second metal layer 130. The first metal layer 112, the first through-hole layer 128 and the second metal layer 130 are continuous layers on the substrate 102 in FIG1, but can be any continuous layer formed on the substrate 102, and FIG1 should not be construed as limiting the location of MIMCAP 100 in this respect.

[0022] A top plate 108 is also formed in the first through-hole layer 128 and the second metal layer 130. The top plate 108 is formed of metal 136, which includes a cavity 106 in which a central bolt 104 is disposed. The cavity 106 is a void in the metal 136 and is shaped according to the central bolt 104. A cavity wall 114 is the inner surface of the cavity 106, which extends around the bolt sidewall 110 of each central bolt 104 in the first through-hole layer 128 and the second metal layer 130. The cavity wall 114 is separated from the bolt sidewall 110 by a dielectric layer 138 disposed between the cavity wall 114 of each cavity 106 in the top plate 108 and the bolt sidewall 110 of the central bolt 104. The cavity 106 does not include a surface corresponding to the second end 120 of the central bolt 104. When a voltage difference exists between the top plate 108 and the center bolt 104 (in this example, they are electrically coupled to each other via the base plates 122A and 122B), a capacitance is generated between the bolt sidewall 110 and the cavity wall 114. In this respect, the base plates 122A and 122B may contain the first electrode 140 of the MIMCAP 100, and the top plate 108 may contain the second electrode 142. In an alternative example, the MIMCAP may not include the base plates 122A and 122B, and a plurality of center bolts 104 may be coupled together in different ways (not shown) such that all center bolts 104 are electrically coupled to the same voltage.

[0023] Figure 1 is a simplified illustration provided for illustrative purposes, and a 3D perspective view is provided to aid understanding of the two-dimensional (2D) view in Figure 2. Figure 2 is a cross-sectional side view of an IC die 200, which includes a substrate 202 and an interconnect layer 204 in which MIMCAP 206 is formed. The view of interconnect layer 204 in Figure 2 corresponds to a cross section taken along line A-A' through MIMCAP 100 in Figure 1. The substrate 202 is separated from the interconnect layer 204 to show that MIMCAP 206 can be formed in any coherent interconnect layer 204. The substrate 202 may include any number of transistors 207 for use in radio frequency (RF) circuitry, to which MIMCAP 206 may also be coupled. Although MIMCAP 206 generally corresponds to MIMCAP 100 in Figure 1, the cross-sectional view of Figure 2 includes additional details not visible in the perspective view of Figure 1.

[0024] MIMCAP 206 includes a plurality of center bolts 208 disposed in a cavity 210 of a top plate 212. The center bolts 208 are orthogonal to a first surface 214 of a first metal layer 216 including a bottom plate 218. Features such as the bottom plate 218 and the center bolts 208 include forming an intermetallic dielectric (IMD) 219, slotting or etching patterns in the IMD 219, and depositing metal (e.g., copper). In this example, a bottom bolt end 220 of each center bolt 208 is disposed on the bottom plate 218 to electrically couple all the center bolts 208. The center bolts 208 extend orthogonally to the first surface 214 as through-hole bolts 221 in a first through-hole layer 222. The center bolts 208 continue through a second metal layer 224 as metal layer bolts 226 stacked on top of the through-hole bolts 221. The center bolt 208 may have a height H 208 in the Z-axis direction, which corresponds to the thickness T 222 (e.g., 1000 nm) of the first through-hole layer and the thickness T 224 of the second metal layer 224. The height H 208 of the center bolt 208 is one of the factors determining the total capacitance of the MIMCAP 206. Therefore, for example, forming a center bolt 208 with both through-hole layer bolt 221 and metal layer bolt 226 increases the total capacitance and capacitance density of the MIMCAP 206 compared to forming a capacitor element only in the first through-hole layer 222.

[0025] On the first surface 214 of the first metal layer 216, a diffusion barrier layer 228 (such as, for example, silicon carbonitride (SiCN)) is disposed around the central bolt 208 to reduce or prevent atomic diffusion from the first metal layer 216 into the IMD layer 219. The first metal layer 216 is a conductive metal and may be copper, which can diffuse if not treated with a diffusion barrier. On the diffusion barrier layer 228, an etch stop layer 230 is disposed around the central bolt 208 for manufacturing-related reasons, as explained below. In this example, the etch stop layer 230 is silicon nitride (SiN), but is not limited in this respect. The diffusion barrier layer 228 and the etch stop layer 230 are disposed on the first surface 214 between the bolt sidewalls 232 of adjacent central bolts 208.

[0026] The center bolt 208 is formed of a conductive metal such as copper, which can diffuse through other materials if left unconstrained. Therefore, a diffusion barrier layer 234, such as titanium nitride (TiN) and / or tantalum nitride (TaN), is provided on the center bolt 208 and also on the etch stop layer 230. A dielectric layer 236 is formed on the bolt sidewall 232 and on the diffusion barrier layer 234 on the etch stop layer 230. The top plate 212 contains metal (such as copper) deposited on the dielectric layer 236 to fill the space between the bolt sidewalls 232 of the respective center bolts 208 in the first through-hole layer 222 and the second metal layer 224. A cavity wall 237 is formed therein, closest to the dielectric layer 236. Since the top plate 212 is also a conductive metal and can be copper, a diffusion barrier layer 238 is disposed between the dielectric layer 236 and the top plate 212. The second through-hole layer 240 and the third metal layer 242 are shown in FIG. 2. The top plate 212 is coupled to a metal interconnect 246 in the third metal layer 242 through a plurality of through holes 244 in the second through-hole layer 240. The bottom plate 218 may be a first electrode 248 for the MIMCAP 206, and the metal interconnect 246 may be a second electrode 250. The capacitance of the MIMCAP 206 can be doubled by replicating the structure of the MIMCAP 206 (e.g., the top plate 212, dielectric layer 236, and center bolt 208) in the second through-hole layer 240 and the third metal layer 242. In this way, the center bolt 208 can extend upward from the first through-hole layer 222 and through the third metal layer 242, and the top plate 212 can be coupled to the replicated top plate for parallel connection of the MIMCAP 206 and the replicated one. In this case, the through holes 244 may be formed in the third through-hole layer (not shown).

[0027] Figure 3 is a flowchart illustrating a method 300 for manufacturing the MIMCAP 206 of Figure 2. Method 300 includes forming a plurality of center bolts (208), each of the plurality of center bolts (208) including a bolt sidewall (232) orthogonal to a first surface (214) of a first metal layer (216) and extending through a first through-hole layer (222) and a second metal layer (224) (block 302). The method also includes forming a top plate (212) including a plurality of cavities (210), each of the plurality of cavities (210) including a cavity wall (237) surrounding the bolt sidewall (232) of each of the plurality of center bolts (208) (block 304). The method further includes forming a dielectric layer (236) (block 306) between the cavity wall (237) of each of the plurality of cavities (210) in the top plate (212) and the bolt sidewall (232) of the corresponding center bolt (208) among the plurality of center bolts (208).

[0028] The MIMCAP 206 in Figure 2 is an example of a dual-electrode MIMCAP according to the exemplary pattern disclosed herein. As shown in Figure 4, in another example, the IC die 400 includes a three-electrode MIMCAP 402 formed according to the disclosed exemplary pattern. The MIMCAP 402 in Figure 4 is similar to the MIMCAP 206 in Figure 2 in many respects. The MIMCAP 402 is formed in interconnect layers 404, in a coherent set of interconnect layers 404 (e.g., MX, VX, MX+1, VX+1, MX+2). Common patterns are identified, and the differences between MIMCAP 206 and MIMCAP 402 are described in more detail.

[0029] MIMCAP 402 includes a central bolt 406 disposed on a base plate 408 in a first metal layer 410. As further described below, the central bolt 406 is formed in a trench 412 in an intermetallic dielectric (IMD) layer 414 in a first through-hole layer 416 and a second metal layer 418. The central bolt 406 extends from a bottom bolt end 420 through the first through-hole layer 416, orthogonal to a first surface 422 of the base plate 408. In the first through-hole layer 416, the central bolt 406 includes a through-hole layer bolt 424. The central bolt 406 extends in the second metal layer 418, including a metal layer bolt 426 stacked on the through-hole layer bolt 424. The IMD layer 414 is etched around the central bolt 406 in the first through-hole layer 416 and the second metal layer 418 to form a top plate 427. A diffusion barrier 428 (e.g., SiCN) is formed on the first surface 422, and an etch stop layer 430 (e.g., SiN) is formed on the diffusion barrier 428 around the central bolts 406 (between the bolt sidewalls 432 of each central bolt 406). A first dielectric layer 434 (e.g., SiN or a high-k dielectric film (HfOx, ZnOx)) is formed (e.g., deposited) on the diffusion barrier 428, on the bolt sidewalls 432, and on the etch stop layer 430 between the central bolts 406. A conformal metal layer 436 and a second dielectric layer 438 are formed on the first dielectric layer 434. A conformal metal layer 436 is formed on the bolt sidewalls 432 and on the top bolt end 437 of the central bolt 406, the top bolt end 437 being opposite to the bottom bolt end 419. A second dielectric layer 438 is formed on the bolt sidewall 432 but not on the top bolt end 437 of the center bolt 406, exposing the conformal metal layer 436 on the top bolt end 437. To prevent molecules of the conformal metal layer 436 from diffusing into the first dielectric layer 434 and the second dielectric layer 438, a diffusion barrier 440 is included between the first dielectric layer 434 and the conformal metal layer 436, and another diffusion barrier 442 is included between the conformal metal layer 436 and the second dielectric layer 438. Depositing the conformal metal layer 436 may also include depositing a seed layer 444 (e.g., copper) on the diffusion barrier 440 before depositing the conformal metal layer 436. The diffusion barriers 440 and 442 may be TiN. Another diffusion barrier 446 and the seed layer 448 are formed on the second dielectric layer 438, allowing the space between the bolt sidewalls 432 to be filled with metal 450 to form a top plate 427. The cavity wall 452 of the cavity 454 of the top plate 427 is formed by metal 450 surrounding the central bolt 406. The metal 450 is arranged around the central bolt 406 and against the diffusion barrier 446 (i.e., on the bolt sidewall 432).

[0030] In the second through-hole layer 456, the first through-hole 458 couples the top plate 427 to the metal interconnect 460 in the third metal layer 462, and the second through-hole 464 couples the conformal metal layer 436 to the metal interconnect 466 in the third metal layer 462. In this respect, the base plate 408 provides the first electrode 468, the metal interconnect 460 provides the second electrode 470, and the metal interconnect 466 provides the third electrode 472.

[0031] The 3D MIMCAP 402 can be manufactured by method 500 shown in the flowchart of FIG5. The method forms a base plate (408) in a first metal layer (410), the base plate (408) including a first surface (422) (block 502). The method further includes forming a plurality of central bolts (406) extending from the first surface (422) of the base plate (408) through a first through-hole layer (416) and a second metal layer (418), the plurality of central bolts including bolt sidewalls (432) orthogonal to the first surface (422) of the base plate (408), a bottom bolt end (419) on the first surface (422) of the base plate (408), and a top bolt end (437) opposite to the bottom bolt end (419) (block 504). The method includes forming a top plate (427) comprising a plurality of cavities (454), the plurality of cavities (454) comprising cavity walls (452) surrounding bolt sidewalls (432) of a plurality of central bolts (406) (block 506). The method includes forming a conformal metal layer (436) between the cavity walls (452) of the cavities (454) of the top plate (427) and the bolt sidewalls (432) of the central bolts (406), and disposed on the top bolt ends (437) of the plurality of central bolts (406) (block 508). The method includes forming a first dielectric layer (434) between the conformal metal layer (436) and the central bolts (406), on the top bolt ends (437) and on the bolt sidewalls (432) (block 510). The method further includes forming a second dielectric layer (438) (block 512) between the cavity wall (452) of the cavity (454) in the conformal metal layer (436) and the top plate (437).

[0032] In Figure 4, the central bolt 406 and the top plate 437 of the 3D MIMCAP 402 are formed within the first through-hole layer 416 and the second metal layer 418. Without increasing the area (in the X and Y planes), more capacitance can be achieved through vertical stacking, thus achieving a greater capacitance density. Specifically, as shown in Figure 6, the 3D MIMCAP 600 may include a first plurality of capacitor elements 602, each including a central bolt 604 disposed in the cavity 606 of the top plate 608 within the first through-hole layer 610 and the second metal layer 612, and also includes a second plurality of capacitor elements 614, each including a central bolt 604 disposed in the cavity 606 of the top plate 616 within the second through-hole layer 618 and the second metal layer 620. As shown in Figure 6, the central bolts 604 of the second plurality of capacitor elements 614 are coupled to the conformal metal layer 622 of the first plurality of capacitor elements 602.

[0033] In the manner described above, the total capacitance of the 3D MIMCAP 600 in Figure 6 is twice that of the MIMCAP 402 in Figure 4, within the same area, which corresponds to doubling the capacitance density. The capacitance density of the MIMCAP 600 can be further doubled in the same manner (not shown here) by forming a third plurality of capacitor elements in the third and fourth via layers and a fourth plurality of capacitor elements in the fourth and fifth via layers.

[0034] Figures 7A-7E are cross-sectional side views illustrating MIMCAP 700 in manufacturing stages 700A-700E of manufacturing process 800 as shown in the flowcharts in the corresponding Figures 8A-8E. MIMCAP 700 corresponds to MIMCAP 206 in Figure 2.

[0035] Figure 7A is a cross-sectional side view of MIMCAP 700 in stage 700A, showing the IMD layer IMD X-1, where a substrate 702 is formed in the first metal layer 704. The IMD layer IMD X-1 can be any layer above the semiconductor substrate 708. A diffusion barrier 712, comprising, for example, SiCN, is deposited on the first surface 714 of the first metal layer 704. The method 800 in Figure 8A includes: forming a substrate (702) in the first metal layer (704) and depositing a diffusion barrier (712) (block 802) on the first surface (714) of the first metal layer (704).

[0036] Figure 7B is a cross-sectional side view of MIMCAP 700 in stage 700B, showing a patterned etch stop layer (716) (e.g., SiN) formed on the diffusion barrier 712 and including an opening 718, wherein the bottom bolt end of the center bolt (see Figure 7C) will be formed on the first surface 714 of the base plate 702. The method in Figure 8B includes depositing the etch stop layer (716) on the diffusion barrier (712) and patterning the etch stop layer (716) to create the opening (718) for the bottom bolt end (block 804).

[0037] Figure 7C is a cross-sectional side view of MIMCAP 700 in stage 700C, showing the next IMD layer IMD X deposited on MIMCAP 700 as shown in stage 700B. A first via layer 720 and a second metal layer 722 can be formed in the IMD layer IMD X. Using a dual damascene process, a trench 724 is formed, extending through the IMD layer IMD X to an opening 718 in the etch stop layer 716, and metal 726 (e.g., copper) is deposited into the trench 724 to form a center bolt 728, which includes a via bolt 730 in the first via layer 720 and a metal bolt 732 in the second metal layer 722. A bottom bolt end 734 is disposed on the first surface 714 through the opening 718. However, to prevent the metal 726 from diffusing into the IMD layer IMD X, a barrier metal 736 (e.g., TiN / TaN) is deposited on the IMD layer IMD X in the trench 724. Next, to improve adhesion, a seed layer 738 (e.g., made of copper) is deposited on the barrier metal 736. The metal 726 can be deposited via a plating process.

[0038] The method in Figure 8C includes forming an IMD layer IMD X, slotting the IMD layer IMD X to an opening (718), forming a barrier metal (736) on the IMD layer IMD X in a trench (724), forming a seed layer (738) on the barrier metal (736), and forming a center bolt (728) on the seed layer (738) in the trench (724) (block 806).

[0039] Figure 7D is a cross-sectional side view of MIMCAP 700 in stage 700D, showing a top plate 740 formed around the central bolt 728, with a cavity 742 created in the metal 744 of the top plate 740. Figure 7C also shows a dielectric layer 746 disposed between the cavity wall 748 of the top plate 740 and the bolt sidewall 750 of the central bolt 728. Before forming the dielectric layer 746, a barrier metal 752 is disposed on the bolt sidewall 750 of the central bolt 728. Before depositing the metal 744 for the top plate 740, another barrier metal 754 and a seed layer 756 are formed on the dielectric layer 746.

[0040] The method in Figure 8D includes etching the IMD layer IMD X in the first through-hole layer (720) and the second metal layer (722). Figure 8D further includes depositing a barrier metal (752) on the bolt sidewall (750) of the central bolt (728) to form a dielectric layer (746) (e.g., TiN), and forming a barrier metal (754) on the dielectric layer (742). Figure 8D further includes depositing a seed layer (756) on the barrier metal (754), and forming a top plate (740) metal (744) between the bolt sidewalls (750) of the central bolt (728) (e.g., by plating). Figure 8D further includes CMP for removing unwanted layers (block 808) on top of the IMD layer IMD X.

[0041] Figure 7E is a cross-sectional side view of MIMCAP 700 in stage 700E, showing another IMD layer IMD X+1 separated from IMD layer IMD X by diffusion barrier 760. A second via layer 762 and a third metal layer 764 are formed in IMD layer IMD X+1. Through-holes 766 in the second via layer 762 couple the top plate 740 to metal interconnects 768 in the third metal layer 764. Barrier metal 770 on IMD layer IMD X reduces diffusion of metal 772 of top plate 740.

[0042] The method in Figure 8E includes depositing a diffusion barrier (760) and a deposited IMD layer IMD X+1. The method includes etching the IMD layer IMD X+1 in a second via layer (762) for via 766 and in a third metal layer (764) for the metal interconnect (768). The dual damascene process includes depositing a barrier metal (770) on the IMD layer IMD X+1 before adding metal (772) to form the via (766) and the metal interconnect (768). The method further includes depositing a top diffusion barrier (774) (SiCN) (block 810).

[0043] Figure 9 illustrates an exemplary wireless communication device 900, which includes an RF component formed by one or more ICs 902, and may include a MIMCAP formed in an interconnect layer. The MIMCAP includes a central bolt orthogonal to a first metal layer in a cavity disposed in a first through-hole layer and a second metal layer to provide high capacitance density, as shown in Figures 1, 2, 4, and 6 and as disclosed herein in any manner. As an example, the wireless communication device 900 may include or be provided in any of the aforementioned devices. As shown in Figure 9, the wireless communication device 900 includes a transceiver 904 and a data processor 906. The data processor 906 may include memory for storing data and code. The transceiver 904 includes a transmitter 908 and a receiver 910 supporting bidirectional communication. Generally, the wireless communication device 900 may include any number of transmitters 908 and / or receivers 910 for any number of communication systems and frequency bands. All or part of the transceiver 904 may be implemented on one or more analog ICs, RF ICs, mixed-signal ICs, etc.

[0044] Transmitter 908 or receiver 910 can be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes frequency conversion between RF and baseband in multiple stages, for example, from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct conversion architecture, the signal undergoes frequency conversion between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. In the wireless communication device 900 in Figure 9, transmitter 908 and receiver 910 are implemented using a direct conversion architecture.

[0045] In the transmission path, the data processor 906 processes the data to be transmitted and provides I and Q analog output signals to the transmitter 908. In the exemplary wireless communication device 900, the data processor 906 includes digital-to-analog converters (DACs) 912(1) and 912(2), which convert the digital signals generated by the data processor 906 into I and Q analog output signals, such as I and Q output currents, for further processing.

[0046] Within transmitter 908, low-pass filters 914(1) and 914(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 916(1) and 916(2) amplify the signals from low-pass filters 914(1) and 914(2), respectively, and provide I and Q baseband signals. Upconverter 918 uses mixers 920(1) and 920(2) to upconvert the I and Q baseband signals from transmit (TX) local oscillator (LO) signal generator 922 to provide upconverted signal 924. Filter 926 filters upconverted signal 924 to remove unwanted signals caused by upconversion and noise in the receive band. Power amplifier (PA) 928 amplifies upconverted signal 924 from filter 926 to obtain the desired output power level and provide the transmit RF signal. The RF signal is routed through a duplexer or switch 930 and transmitted via antenna 932.

[0047] In the receiving path, antenna 932 receives signals transmitted from the base station and provides the received RF signal, which is routed through duplexer or switch 930 and provided to low-noise amplifier (LNA) 934. Duplexer or switch 930 is designed to operate with a specific receive (RX) to TX duplexer frequency separation to isolate the RX signal from the TX signal. The received RF signal is amplified by LNA 934 and filtered by filter 936 to obtain the desired RF input signal. Down-conversion mixers 938(1) and 938(2) mix the output of filter 936 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 940 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMP 942(1) and 942(2) and further filtered by low-pass filters 944(1) and 944(2) to obtain I and Q analog input signals, which are provided to data processor 906. In this example, the data processor 906 includes analog-to-digital converters (ADCs) 946(1) and 946(2) for converting analog input signals into digital signals for further processing by the data processor 906.

[0048] In the wireless communication device 900 of Figure 9, a TX LO signal generator 922 generates I and Q TX LO signals for frequency upscaling, while an RX LO signal generator 940 generates I and Q RX LO signals for frequency downscaling. Each LO signal is a periodic signal with a specific base frequency. A TX phase-locked loop (PLL) circuit 948 receives timing information from a data processor 906 and generates a control signal to adjust the frequency and / or phase of the TX LO signals from the TX LO signal generator 922. Similarly, an RX PLL circuit 950 receives timing information from a data processor 906 and generates a control signal to adjust the frequency and / or phase of the RX LO signals from the RX LO signal generator 940.

[0049] The wireless communication device 900 can be provided or integrated into any processor-based device. Each wireless communication device 900 includes an IC that includes a MIMCAP formed in an interconnect layer. The MIMCAP includes a central bolt orthogonal to a first metal layer in a cavity of a top plate disposed in a first through-hole layer and a second metal layer to provide high capacitance density, as shown in Figures 1, 2, 4 and 6 and as in any manner disclosed herein. Examples (but not limitations) include set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet computers, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), displays, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, motor vehicles, vehicle components, avionics systems, unmanned aerial vehicles (UAVs), and multi-rotor aircraft.

[0050] In this regard, Figure 10 illustrates an example of a processor-based system 1000 including an IC comprising a MIMCAP formed in an interconnect layer. The MIMCAP includes a central bolt orthogonal to a first metal layer in a cavity disposed in a first via layer and a second metal layer to provide high capacitance density, as shown in Figures 1, 2, 4, and 6 and as disclosed herein. In this example, the processor-based system 1000 includes one or more central processing units (CPUs) 1002, which may also be referred to as CPUs or processor cores. Each CPU 1002 includes one or more processors 1004. Each CPU 1002 may have a cache memory 1006 coupled to the processors 1004 for fast access to temporarily stored data. Each CPU 1002 is coupled to a system bus 1008 and may be mutually coupled to master and slave devices included in the processor-based system 1000. As is well known, CPUs 1002 communicate with other devices by exchanging address, control, and data information on system buses 1008. For example, CPUs 1002 can transmit bus transaction requests to memory controllers 1010, which is an example of a slave device. Although not shown in Figure 10, multiple system buses 1008 may be provided, each of which constitutes a different architecture.

[0051] Other master and slave devices may be connected to system bus 1008. As shown in FIG10, as an example, these devices may include a memory system 1012 comprising a memory controller 1010 and one or more memory arrays 1014, one or more input devices 1016, one or more output devices 1018, one or more network interface devices 1020, and one or more display controllers 1022. Either output device 1018 and network interface device 1020 may include an IC comprising a MIMCAP formed in an interconnect layer, the MIMCAP comprising a center bolt orthogonal to a first metal layer in a cavity of a top plate disposed in a first through-hole layer and a second metal layer to provide high capacitance density, as shown in FIG1, FIG2, FIG4, and FIG10 and as in any manner disclosed herein. Input devices 1016 may include any type of input device, including but not limited to input keys, switchers, voice processors, etc. Output devices 1018 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. (All) Network interface device 1020 can be any device configured to allow data exchange with network 1024. Network 1024 can be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), BLUETOOTH™ networks, and the Internet. (All) Network interface device 1020 can be configured to support any type of communication protocol desired.

[0052] The CPU 1002 can also be configured to access the display controller 1022 via the system bus 1008 to control information sent to one or more displays 1026. The display controller 1022 sends information to the displays 1026 for display via one or more video processors 1028, which process the information to be displayed into a format suitable for the displays 1026. The displays 1026 can include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc.

[0053] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the various forms disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. As an example, the master and slave devices described herein can be employed in any circuit, hardware component, IC, or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally according to their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the entire system. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as departing from the scope of this disclosure.

[0054] The various illustrative logic blocks, modules, and circuits described in conjunction with the various forms disclosed herein can be implemented or performed using processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but alternatively, it may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0055] The various forms disclosed herein can be embodied in hardware and instructions stored in the hardware, and can reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable media known in the art. An exemplary storage medium is coupled to a processor, allowing the processor to read information from and write information to the storage medium. Alternatively, the storage medium can be integrated into the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and storage medium can reside as discrete components in a remote station, base station, or server.

[0056] It should also be noted that the operational steps described in any of the exemplary embodiments herein are described to provide examples and for discussion. The described operations can be performed in many different orders other than those shown. Furthermore, the operations described in a single operational step can actually be performed in several different steps. Additionally, one or more operational steps discussed in the exemplary embodiments can be combined. It should be understood that the operational steps shown in the flowcharts can be modified in many different ways, which will be apparent to those skilled in the art. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0057] The foregoing description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0058] Examples of implementation methods are described in the following numbered clauses: 1. A three-dimensional (3D) metal-insulator-metal (MIM) capacitor (MIMCAP), comprising: A plurality of central bolts, each of the plurality of central bolts comprising a bolt sidewall orthogonal to a first surface of a first metal layer and extending through a first through-hole layer and a second metal layer; A top plate comprising a plurality of cavities, each of the plurality of cavities comprising a cavity wall that surrounds the bolt sidewall of each of a first plurality of central bolts; and A dielectric layer is disposed between the cavity wall of each of the plurality of cavities in the top plate and the bolt sidewall of the corresponding central bolt among the plurality of central bolts. 2. As in Clause 1, 3D MIMCAP, where each of the plurality of center bolts comprises: Through-hole bolts, the metal contained in the first through-hole layer; and Metal bolts, containing metal in a second metal layer, are stacked on top of through-hole bolts. 3. As in Clause 1 or Clause 2 of 3D MIMCAP, wherein the top plate comprises metal extending around each of the plurality of center bolts. 4. The 3D MIMCAP of any of Clauses 1 to 3 further includes a base plate that includes a first metal layer. 5. 3D MIMCAP as described in any of Clauses 1 through 4, further including: An etch stop layer is disposed on a first surface of a first metal layer around a plurality of central bolts, wherein a dielectric layer is further disposed on the etch stop layer. 6. 3D MIMCAP as described in any of Clauses 1 through 5, further including: A first through hole is formed in a second through hole layer on a second metal layer, and a plurality of central bolts are coupled to a third metal layer; and A second through hole is provided in the second through hole layer and couples the top plate to the third metal layer. 7. 3D MIMCAP as described in any of Clauses 1 through 6, further includes: The second plurality of central bolts are located in the second through-hole layer and the third metal layer; and The second top plate is located within the second through-hole layer and the third metal layer; in: The plurality of central bolts in the first through-hole layer and the second metal layer are coupled to the second plurality of central bolts; and The top plate in the first through-hole layer and the second metal layer is coupled to the second top plate. 8. A method for manufacturing a three-dimensional (3D) metal-insulator-metal (MIM) capacitor (MIMCAP), comprising: A plurality of central bolts are formed, each of the plurality of central bolts including a bolt sidewall orthogonal to a first surface of a first metal layer and extending through a first through-hole layer and a second metal layer; A top plate comprising a plurality of cavities, each cavity comprising a cavity wall surrounding the bolt sidewall of each of a plurality of central bolts; and A dielectric layer is formed between the cavity wall of each of the plurality of cavities in the top plate and the bolt sidewall of the corresponding central bolt among the plurality of central bolts. 9. The method as described in Clause 8, wherein forming a plurality of center bolts further comprises: A diffusion barrier layer is formed on the first surface of the first metal layer; An etch stop layer is formed on the diffusion barrier layer; An intermetallic dielectric (IMD) is formed in the first through-hole layer and the second metal layer; Forming a trench through the IMD; and Metal is deposited in the first perforated layer and in the trenches of the second metal layer. 10. The method of Clause 9, wherein forming the dielectric layer further comprises: Remove the IMD (In-Mesh Deposit) of the plurality of central bolts surrounding the first through-hole layer and the second metal layer down to the etch stop layer; A barrier metal layer is formed on the bolt sidewalls of the plurality of central bolts and on the etch stop layer; and A dielectric layer is deposited on the barrier metal layer. 11. The method as described in Clause 10, wherein forming the top plate further comprises: A second barrier metal layer is formed on the dielectric layer; A seed layer is formed on the second barrier metal layer; and Deposited metal is used to fill the space between the bolt sidewalls of a plurality of central bolts, which are in a first through-hole layer and in a second metal layer. 12. A three-dimensional (3D) metal-insulator-metal (MIM) capacitor (MIMCAP), comprising: A base plate, in a first metal layer, the base plate comprising a first surface; A plurality of center bolts extending from a first surface of the base plate through a first through-hole layer and a second metal layer, the plurality of center bolts comprising: The bolt sidewall is orthogonal to the first surface of the base plate; The end of the bottom bolt is on the first surface of the base plate; and The top bolt end is opposite to the bottom bolt end; The top plate comprises a plurality of cavities, each cavity having a cavity wall that surrounds the bolt sidewalls of a plurality of central bolts; A conformal metal layer is disposed between the cavity walls of the plurality of cavities in the top plate and the bolt sidewalls of the plurality of central bolts, and is also disposed on the top bolt ends of the plurality of central bolts; A first dielectric layer is disposed between the conformal metal layer and a plurality of central bolts, on the bolt sidewalls and the top bolt ends; and The second dielectric layer is disposed between the conformal metal layer and the top plate. 13. As per Clause 12 of 3D MIMCAP, further including: A first through-hole is disposed in a second through-hole layer on a second metal layer, and couples a conformal metal layer to a first metal interconnect in a third metal layer; and A second through hole is disposed in the second through hole layer and couples the top plate to the second metal interconnect in the third metal layer. 14. As per Clause 12 or Clause 13 of 3D MIMCAP, further including: The second plurality of center bolts, located in the second through-hole layer and the third metal layer, each of the second plurality of center bolts comprises: The bolt sidewall is orthogonal to the first surface of the base plate; The bottom bolt end is coupled to the conformal metal layer; and The top bolt end is opposite to the bottom bolt end; The second top plate includes a second plurality of cavities, each cavity including a cavity wall that surrounds the bolt sidewalls of the second plurality of central bolts; and The second conformal layer is disposed between the cavity walls of the second plurality of cavities of the second top plate and the bolt sidewalls of the second plurality of central bolts, and is disposed on the top bolt end of the second plurality of central bolts. 15. A method for forming a three-dimensional (3D) metal-insulator-metal (MIM) capacitor (MIMCAP), comprising: A base plate is formed in a first metal layer, the base plate including a first surface; A plurality of center bolts are formed, the plurality of center bolts extending from a first surface of the base plate through a first through-hole layer and a second metal layer, the plurality of center bolts comprising: The bolt sidewall is orthogonal to the first surface of the base plate; The end of the bottom bolt is on the first surface of the base plate; and The top bolt end is opposite to the bottom bolt end; A top plate is formed comprising a plurality of cavities, each cavity having a cavity wall that surrounds the bolt sidewalls of a plurality of central bolts; A conformal metal layer is formed between the cavity walls of the plurality of cavities in the top plate and the bolt sidewalls of the plurality of central bolts, and is disposed on the top bolt ends of the plurality of central bolts; A first dielectric layer is formed between the conformal metal layer and the plurality of central bolts, on the bolt sidewalls and the top bolt ends; and A second dielectric layer is formed between the conformal metal layer and the top plate. 16. The method of Clause 15, wherein forming a plurality of center bolts further comprises: A diffusion barrier layer is formed on the first surface of the base plate; A patterned etch stop layer containing openings is formed on the diffusion barrier layer; An intermetallic dielectric (IMD) is formed in the first through-hole layer and the second metal layer; A trench is formed in the opening of the patterned etch stop layer, the trench passing through the IMD and through the trench of the diffusion barrier layer; and Metal is deposited in the first through-hole layer and in the trenches of the second metal layer. 17. The method of Clause 16, wherein forming the first dielectric layer further comprises: Remove the IMD surrounding a plurality of central bolts to a patterned etch stop layer, the plurality of central bolts being in a first through-hole layer and a second metal layer; A barrier metal layer is formed on the bolt sidewalls of the plurality of central bolts and on the etching stop layer; and A first dielectric layer is deposited on the barrier metal layer. 18. The method of Clause 17, wherein forming the conformal metal layer further comprises: A second barrier metal layer is formed on the first dielectric layer; and A conformal metal layer is formed on the second barrier metal layer. 19. The method of Clause 18, wherein forming the second dielectric layer further comprises: A third blocking metal layer is formed on the conformal metal layer on the bolt sidewalls of a plurality of central bolts; and A second dielectric layer is formed on the third barrier metal layer. 20. The method as described in Clause 19, wherein forming the top plate further comprises: A fourth barrier metal layer is formed on the second dielectric layer on the bolt sidewalls of the plurality of central bolts; A seed layer is formed on the fourth barrier metal layer; and Deposited metal is used to fill the space between the bolt sidewalls of a plurality of central bolts, which are located in a first through-hole layer and a second metal layer.

[0059] 100: Metal-Insulator-Metal (MIM) Capacitor (MIMCAP) 102:Substrate 104: Center Bolt 106: Cavity 108: Top Plate 110: Bolt sidewall 112: First metal layer 114: Cavity wall 116: First end 118: First Surface 120: Second end 122A, 122B: Base plate 124: Metal interconnects 126: Metal Rail 128: First through-hole layer 130: Second metal layer 132: Through-hole bolt 134: Metal Layer Bolt 136: Metal 138: Dielectric layer 140: First electrode 142: Second electrode 200, 400: Integrated circuit (IC) chips 202:Substrate 204, 404: Interconnect layer 206, 402: Metal-Insulator-Metal (MIM) Capacitors (MIMCAP) 207: Transistor 208, 406: Center bolts 210, 454: Cavity 212, 427: Top plate 214, 422: First surface 216, 410: First metal layer 218, 408: Base Plate 219, 414: Intermetallic Dielectric (IMD) Layer 220, 419, 420: Bottom bolt end 221, 424: Through-hole bolts 222, 416: First through-hole layer 224, 418: Second metal layer 226, 426: Metal-layer bolts 228: Diffusion barrier layer 428, 440, 442, 446: Diffuser blocking components 230, 430: Etching stop layer 232, 432: Bolt sidewall 234, 238: Diffusion barrier layer 236: Dielectric layer 237, 452: Cavity wall 240, 456: Second perforation layer 242, 462: Third metal layer 244: Through-hole 246, 460, 466: Metal interconnects 248, 468: First electrode 250, 470: Second electrode 412: Trench 434: First dielectric layer 436: Conformal metal layer 437: Top bolt end 438: Second dielectric layer 444, 448: Seed layer 450: Metal 458: First through hole 464: Second through hole 472: Third electrode 300: Method 302, 304, 306: Square 500: Methods 502, 504, 506, 508, 510, 512: Square 600: Metal-Insulator-Metal (MIM) Capacitor (MIMCAP) 602: The first plurality of capacitor elements 604: Center Bolt 606: Cavity 608, 616: Top Slab 610: First through-hole layer 612: Second metal layer 614: The second plurality of capacitor elements 618: Second through-hole layer 620: Second metal layer 622: Conformal metal layer 700: Metal-Insulator-Metal (MIM) Capacitor (MIMCAP) 700A-700E: Manufacturing Stage 702: Base Plate 704: First metal layer 708: Semiconductor substrate 712: Diffuser Barrier 714: First Surface 716: Etching Stop Layer 718: Opening 720: First through-hole layer 722: Second metal layer 724: Trench 726: Metal 728: Center Bolt 730: Through-hole bolts 732: Metallic Layer Bolt 734: Bottom bolt end 736, 752, 754, 770: Blocking metal 738, 756: Seed layer 740: Top Plate 742: Cavity 744, 772: Metals 746: Dielectric layer 748: Cavity wall 750: Bolt sidewall 760: Diffuse blocking component 762: Second through-hole layer 764: Third metal layer 766: Through-hole 768: Metal interconnects 774: Top diffuser block 800: Method 802, 804, 806, 808, 810: Square 900: Wireless communication device 902: Integrated Circuit (IC) 904: Transceiver 906: Data Processor 908: Launcher 910: Receiver 912(1), 912(2): Digital-to-Analog Converter (DAC) 914(1), 914(2): Low-pass filters 916(1), 916(2): Amplifier (AMP) 918: Up-converter 920(1), 920(2): Mixer 922: Transmit (TX) Local Oscillator (LO) Signal Generator 924: Up-conversion signal 926, 936: Filters 928: Power Amplifier (PA) 930: Duplexer or switch 932: Antenna 934: Low-noise amplifier (LNA) 938(1), 938(2): Down-conversion mixer 940: Receive (RX) Local Oscillator (LO) Signal Generator 942(1), 942(2): Amplifier (AMP) 944(1), 944(2): Low-pass filters 946(1), 946(2): Analog-to-digital converter (ADC) 948: Transmit (TX) Phase-Locked Loop (PLL) Circuit 950: Receiver (RX) Phase-Locked Loop (PLL) Circuit 1000: Processor-based systems 1002: Central Processing Unit (CPU) 1004: Processor 1006: Cache memory 1008: System Bus 1010: Memory controller 1012: Memory System 1014: Memory Array 1016: Input device 1018: Output device 1020: Network Interface Device 1022: Display Controller 1024: Internet 1026: Monitor 1028: Video Processor

Claims

1. A three-dimensional (3D) metal-insulator-metal (MIMCAP) capacitor, comprising: a plurality of central bolts, each of the plurality of central bolts including a bolt sidewall orthogonal to a first surface of a first metal layer and extending through a first through-hole layer and a second metal layer; a top plate including a plurality of cavities, each of the plurality of cavities including a cavity wall continuously surrounding and concentrically surrounding the bolt sidewall of each of the plurality of central bolts; and a dielectric layer disposed between the cavity wall of each of the plurality of cavities of the top plate and the bolt sidewall of the corresponding central bolt of the plurality of central bolts.

2. The 3D MIMCAP of claim 1, wherein each of the plurality of center bolts comprises: a through-hole bolt, containing metal in the first through-hole layer; and a metal bolt, containing metal in the second metal layer, and stacked on the through-hole bolt.

3. As requested in Item 1, the 3D MIMCAP, wherein the top plate comprises metal extending around each of the plurality of center bolts.

4. As claimed in Request 1, the 3D MIMCAP further includes a base plate that includes the first metal layer.

5. As in claim 4, 3D MIMCAP, wherein the first end of each of the plurality of center bolts contacts the surface of the base plate.

6. The 3D MIMCAP of claim 1 further includes: an etch stop layer disposed on the first surface of the first metal layer around the plurality of central bolts, wherein the dielectric layer is further disposed on the etch stop layer.

7. The 3D MIMCAP of claim 1 further includes: a first through hole disposed in a second through hole layer on the second metal layer, and coupling the top plate to a third metal layer disposed on the second through hole layer.

8. The 3D MIMCAP of claim 1 further includes a second plurality of center bolts in the second through-hole layer and the third metal layer; and a second top plate in the second through-hole layer and the third metal layer; wherein: The plurality of central bolts in the first through-hole layer and the second metal layer are coupled to the second plurality of central bolts; and the top plate in the first through-hole layer and the second metal layer is coupled to the second top plate.

9. The 3D MIMCAP of claim 8, wherein the second via layer includes a dielectric layer disposed between the second metal layer and the third metal layer in a direction orthogonal to the first surface of the first metal layer.

10. The 3D MIMCAP of claim 1, wherein the first through-hole layer includes a dielectric layer disposed between the first metal layer and the second metal layer.

11. The 3D MIMCAP of claim 1, wherein the top plate comprises a metal layer having a thickness corresponding to the height of each of the plurality of center bolts.

12. As requested in Item 1 of the 3D MIMCAP, wherein each of the plurality of center bolts is a solid cylindrical bolt.

13. A method of manufacturing a three-dimensional (3D) metal-insulator-metal (MIMCAP) capacitor, comprising: forming a plurality of central bolts, each of the plurality of central bolts including a bolt sidewall orthogonal to a first surface of a first metal layer and extending through a first through-hole layer and a second metal layer; forming a top plate including a plurality of cavities, each of the plurality of cavities including a cavity wall continuously surrounding and concentrically surrounding the bolt sidewall of each of the plurality of central bolts; and forming a dielectric layer between the cavity wall of each of the plurality of cavities in the top plate and the bolt sidewall of the corresponding central bolt of the plurality of central bolts.

14. The method of claim 13, wherein forming the plurality of center bolts further comprises: forming a diffusion barrier layer on the first surface of the first metal layer; forming an etch stop layer on the diffusion barrier layer; forming an intermetallic dielectric (IMD) in the first through-hole layer and in the second metal layer; forming a trench through the IMD; and depositing metal in the trench in the first through-hole layer and in the second metal layer.

15. The method of claim 14, wherein forming the dielectric layer further comprises: removing the IMD of the plurality of central bolts surrounding the first through-hole layer and the second metal layer to the etch stop layer; forming a barrier metal layer on the bolt sidewall of the plurality of central bolts and on the etch stop layer; and depositing the dielectric layer on the barrier metal layer.

16. The method of claim 15, wherein forming the top plate further comprises: forming a second barrier metal layer on the dielectric layer; forming a seed layer on the second barrier metal layer; and depositing metal to fill between the bolt sidewalls of the plurality of central bolts, the plurality of central bolts being in the first through-hole layer and in the second metal layer.

17. A three-dimensional (3D) metal-insulator-metal (MIMCAP) capacitor, comprising: a base plate in a first metal layer, the base plate including a first surface; a plurality of central bolts extending from the first surface of the base plate through a first through-hole layer and a second metal layer, the plurality of central bolts including: bolt sidewalls orthogonal to the first surface of the base plate; bottom bolt ends on the first surface of the base plate; and top bolt ends opposite to the bottom bolt ends; a top plate including a plurality of cavities, the plurality of cavities including cavity walls continuously surrounding and concentric with the bolt sidewalls of the plurality of central bolts; a conformal metal layer between the cavity walls of the plurality of cavities and the bolt sidewalls of the plurality of central bolts, and disposed on the top bolt ends of the plurality of central bolts; A first dielectric layer is disposed between the conformal metal layer and the plurality of central bolts, at the end of the top bolt and on the sidewall of the bolt; and a second dielectric layer is disposed between the conformal metal layer and the top plate.

18. The 3D MIMCAP of claim 17 further comprises: a first through-hole disposed in a second through-hole layer on the second metal layer and a first metal interconnect coupling the conformal metal layer to a third metal layer; and a second through-hole disposed in the second through-hole layer and a second metal interconnect coupling the top plate to the third metal layer.

19. The 3D MIMCAP of claim 17 further comprises: a second plurality of center bolts in a second through-hole layer and a third metal layer, each of the second plurality of center bolts comprising: a bolt sidewall orthogonal to the first surface of the base plate; a bottom bolt end coupled to the conformal metal layer; and a top bolt end opposite to the bottom bolt end; a second top plate comprising a second plurality of cavities, the second plurality of cavities comprising cavity walls surrounding the bolt sidewalls of the second plurality of center bolts; and a second conformal layer disposed between the cavity walls of the second plurality of cavities and the bolt sidewalls of the second plurality of center bolts, and disposed on the top bolt end of the second plurality of center bolts.

20. A method of forming a three-dimensional (3D) metal-insulator-metal (MIMCAP) capacitor, comprising: forming a base plate in a first metal layer, the base plate including a first surface; forming a plurality of central bolts extending from the first surface of the base plate through a first through-hole layer and a second metal layer, the plurality of central bolts including: bolt sidewalls orthogonal to the first surface of the base plate; bottom bolt ends on the first surface of the base plate; and top bolt ends opposite to the bottom bolt ends; forming a top plate including a plurality of cavities, the plurality of cavities including cavity walls continuously surrounding and concentric with the bolt sidewalls of the plurality of central bolts; forming a conformal metal layer between the cavity walls of the plurality of cavities of the top plate and the bolt sidewalls of the plurality of central bolts, and disposed on the top bolt ends of the plurality of central bolts; A first dielectric layer is formed between the conformal metal layer and the plurality of center bolts, at the end of the top bolt and on the sidewall of the bolt; and a second dielectric layer is formed between the conformal metal layer and the top plate.

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