Current mirror circuit and current supply circuit

Abstract

This invention provides a current mirror circuit and a current supply circuit. The current mirror circuit includes: a first transistor configured to supply a data current from a data drive circuit to the first transistor; a second transistor configured to drive a light-emitting diode by mirroring the data current supplied to the first transistor; a capacitor disposed between the first transistor and the second transistor and configured to store the voltage at the gate terminal of the second transistor; and a first switch disposed between the first transistor and the second transistor and configured to adjust the input current at the gate terminal of the second transistor.

Description

[Technical Field]

[0001] This disclosure relates to a current supply circuit and a display device including the current supply circuit. [Previous Technology]

[0002] The display device includes a data driving circuit and a gate driving circuit for driving pixels arranged in the panel, etc.

[0003] The data driving circuit determines the data voltage or data current based on the image data, and supplies the data voltage or data current to the pixels of the panel through the data lines to control the brightness of the pixels.

[0004] Even if the same data voltage is supplied from the data driving circuit, the brightness of each pixel may vary depending on the characteristics of each pixel or the external environment. For example, each pixel includes a driving transistor. If the threshold voltage of the driving transistor changes, the brightness of the pixel may change even if the same data voltage is supplied. If the data driving circuit does not take into account such changes in pixel characteristics, it may lead to problems such as pixels being driven to undesirable brightness and image quality degradation.

[0005] Furthermore, even if the same data voltage is supplied from the data driving circuit, the pixel brightness may vary if current leaks from the pixel's driving transistor or if leakage current from the switching transistor is supplied to the pixel's driving transistor. For example, to prevent image quality degradation, a separate element (e.g., a capacitor) may be included to reduce voltage variations in the driving transistor. However, even in this case, the formation of a current path between the capacitor and the transistor around the pixel to leak current can lead to a problem where the desired pixel brightness cannot be achieved. [Summary of the Invention]

[0006] In this context, various embodiments will provide a current supply circuit that can prevent the voltage of the capacitor from changing due to leakage current between the transistor and the capacitor in the display device, thereby preventing the degradation of the image quality of the display device.

[0007] In addition, various embodiments will provide a current supply circuit that maintains the voltage of the body terminal and the source or drain terminal of the transistor connected to the capacitor at the same level, thereby minimizing leakage of current generated at the body terminal of the transistor.

[0008] In addition, various embodiments will provide a current supply circuit in which a plurality of switches are arranged in a path extending from the data drive circuit to the pixel, and the operation of each switch is correlated so that the components of the current mirror circuit can be disconnected according to time periods.

[0009] In one embodiment, an embodiment may provide a current mirror circuit, comprising: a first transistor configured such that a data current is supplied to the first transistor from a data driving circuit; a second transistor configured to drive a light-emitting diode by mirroring the data current supplied to the first transistor; a capacitor disposed between the first transistor and the second transistor and configured to store the voltage at the gate terminal of the second transistor; and a first switch disposed between the first transistor and the second transistor and configured to adjust the input current at the gate terminal of the second transistor.

[0010] In another embodiment, an embodiment may provide a current supply circuit comprising: a first transistor configured to supply a data drive current to the first transistor via a data line; a second transistor configured to supply a pixel current to a light-emitting diode in response to the data drive current of the first transistor; and a current compensation circuit connected to the first transistor and the second transistor and configured to adjust the current supplied to the second transistor, wherein the current compensation circuit adjusts the current between the first transistor and the second transistor by means of at least one switching transistor.

[0011] In another embodiment, an embodiment may provide a current supply circuit comprising: a first transistor, which is selectively supplied with a data drive current via a data line by means of a data current cut-off switch; a second transistor, which is configured to supply a light-emitting diode with a current having an magnitude corresponding to the magnitude of the data drive current supplied to the first transistor; and a voltage compensation circuit connected to one end of the first transistor and one end of the second transistor, and configured to compensate the voltage at the gate terminals of the second transistor, wherein the operation of the voltage compensation circuit changes in response to the operating timing of the data current cut-off switch.

[0012] It can be clearly seen from the above that, according to the embodiment, the voltage change of the capacitor caused by leakage current between the transistors of the pixels in the display device and the capacitor can be minimized, and because of this fact, the degradation of image quality caused by changes in the characteristics of the pixels can be prevented.

[0013] Furthermore, according to the embodiment, since the voltage change of the driving transistor of the pixel can be prevented by preventing leakage of current generated at the body terminal of the switching transistor of the pixel, the pixel can be controlled to the desired brightness.

[0014] Furthermore, according to the embodiment, since the operation of multiple transistors of a pixel can be electrically disconnected or electrically connected to the internal circuit, unnecessary power consumption can be prevented and power efficiency during panel operation processing can be improved.

Implementation Method

[0027] FIG1 is a diagram showing the configuration of a display device according to an embodiment of the present disclosure.

[0028] Referring to FIG1, the display device 100 may include a panel 110, a data driving circuit 120, a gate driving circuit 130, and a data processing circuit 150, etc.

[0029] In panel 110, multiple data lines DL, multiple gate lines GL and multiple sensing lines SL can be arranged, and multiple pixels P can be arranged.

[0030] Panel 110 may be one or more of a display panel (not shown) and a touch panel (not shown), either formed separately or integrally. Various panels, such as liquid crystal displays (LCDs), organic light-emitting diodes (OLEDs), light-emitting diodes (LEDs), and mini LEDs, can be used without limitation as panel 110.

[0031] Each pixel P arranged in the panel 110 may include at least one light-emitting diode (LED) and at least one transistor. The characteristics of the LED and transistor included in each pixel P may vary over time or according to the surrounding environment. Each pixel P may be controlled using an active matrix (AM) scheme, and may be controlled using a passive matrix (PM) scheme if necessary.

[0032] The data driving circuit 120 can supply data voltage to the pixel P via the data line DL. Based on the scan signal from the gate driving circuit 130, the data voltage supplied to the data line DL can be transmitted to the pixel P connected to the data line DL. If necessary, the data driving circuit 120 can be defined as a source driver.

[0033] The data driving circuit 120 may include a data signal transmission circuit 121 and a pixel sensing circuit 122.

[0034] The data signal transmission circuit 121 can transmit analog signals to the pixel P in the form of voltage or current.

[0035] The data signal transmission circuit 121 may include a voltage / current converter (not shown) and may supply data voltage or data current to the light-emitting diode (LED) of the pixel P.

[0036] The pixel sensing circuit 122 can receive analog signals (e.g., voltage, current, etc.) formed in each pixel P via the sensing line SL, and can determine the characteristics of pixel P. The pixel sensing circuit 122 can sense the changes in the characteristics of each pixel P over time, and can transmit the signals to the data processing circuit 150.

[0037] The pixel sensing circuit 122 may include an analog front end (AFE), a sample and hold (S / H), an amplifier (AMP), and an analog-to-digital converter (ADC).

[0038] An analog front end (not shown) can sense pixel P and can process the current transmitted from pixel P to form a sensing voltage Vi.

[0039] Sample and hold (not shown) can clearly separate the analog front end and the amplifier, and can temporarily store the sensed voltage (Vi) output from the analog front end, and then the sensed voltage (Vi) or the difference (ΔVi) between the sensed voltage (Vi) and the reference voltage can be input to the amplifier.

[0040] An amplifier (not shown) can amplify a sensed voltage (Vi) or the difference (ΔVi) between a sensed voltage (Vi) and a reference voltage transmitted to its input terminal, and can transmit the amplified sensed voltage (Vi) or the amplified difference (ΔVi) to an analog-to-digital converter.

[0041] An analog-to-digital converter (not shown) can convert the output voltage of an amplifier into a digital signal (Ao).

[0042] The gate drive circuit 130 can supply a scan signal of an on-state voltage or an off-state voltage to the gate line GL. When the scan signal of the on-state voltage is supplied to pixel P, the corresponding pixel P is connected to the data line DL, and when the scan signal of the off-state voltage is supplied to pixel P, the connection between the corresponding pixel P and the data line DL is released. If necessary, the gate drive circuit 130 can be defined as a gate driver. The scan signal of the gate drive circuit 130 can define the on-time or off-time of the transistor of pixel P.

[0043] The data processing circuit 150 can supply various control signals to the data driving circuit 120 and the gate driving circuit 130. The data processing circuit 150 can transmit data control signals (DCS) according to various timing sequences or transmit gate control signals (GCS) to the gate driving circuit 130. These data control signals are used to control the data driving circuit 120 to supply data voltage to each pixel P. If necessary, the data processing circuit 150 can be defined as a timing controller (T-Con).

[0044] The data processing circuit 150 can output image data RGB obtained by converting externally input image data according to the data signal format used in the data driving circuit 120, so as to transmit the image data RGB to the data driving circuit 120.

[0045] FIG2 is a diagram showing the signal flow of a current supply circuit according to an embodiment of the present disclosure.

[0046] FIG3 is a diagram showing the signal timing of a current supply circuit according to an embodiment of the present disclosure.

[0047] Referring to Figures 2 and 3, the signal flow of the current supply circuit 111 can be defined by the data voltage V_data transmitted via the data line DL and the scan signal transmitted via the gate line GL.

[0048] The current supply circuit 111 can receive the data voltage V_data from the data drive circuit 120 (see Figure 1), or it can receive the data current I_data converted by the voltage / current converter 123.

[0049] Depending on the type of analog signal transmitted from the data drive circuit 120, the voltage / current converter 123 can be omitted. For example, when the signal transmitted from the data drive circuit 120 is a data current I_data, the voltage / current converter 123 can be omitted, and the data current I_data can be directly transmitted to the current supply circuit 111.

[0050] The current supply circuit 111 can receive the scanning signal from the gate drive circuit 130 (see Figure 1) and can transmit the corresponding output voltage or output current to the light-emitting diode 112 in the corresponding timing sequence.

[0051] The output voltage or output current of the current supply circuit 111 can correspond to the magnitude of the data voltage V_data or the data current I_data. For example, the current supply circuit 111 can be a current mirror circuit (not shown), and in this case, a voltage or current of the same magnitude as the data voltage V_data or the data current I_data can be transmitted to the light-emitting diode 112.

[0052] The magnitude of the current transmitted to the light-emitting diode 112 can be defined based on the voltage at the output terminal OUT of the current supply circuit 111 and the voltage V_LED at one end of the light-emitting diode 112. Furthermore, the magnitude of the current transmitted to the light-emitting diode 112 can be defined based on the state of the transistor connected to the output terminal OUT of the current supply circuit 111.

[0053] Referring to Figure 3, the timing of the input signal and the output signal of the current supply circuit 111 can be compared.

[0054] The data voltage V_data or the data current I_data can be supplied to the current supply circuit 111 via the data line DL, and the scan signal can be supplied via the gate line GL.

[0055] The signal at the output terminal OUT of the current supply circuit 111 can be generated as an output voltage in response to the pulse timing t1, t2 and t3 of the scan signal of the gate line GL.

[0056] The signal at the output terminal OUT of the current supply circuit 111 can be a signal output by mirroring the data voltage V_data or data current I_data transmitted to the data line DL. In this case, the current supply circuit 111 can be a current mirror circuit coupled with multiple transistors, but is not limited thereto. In the current mirror circuit (not shown), the terminals of a transistor can form a common node.

[0057] The magnitudes H4, H5, and H6 of the signals at the output terminal OUT of the current supply circuit 111 can be the same as the magnitudes H1, H2, and H3 of the data voltage V_data or the data current I_data. In other cases, they can be defined as having a preset correlation or having a multiple of the signal magnitude ratio.

[0058] The input and output signals of the current supply circuit 111 illustrate the magnitude and waveform of each signal, and are not limited to Figure 3.

[0059] FIG4 is a first example diagram illustrating a current supply circuit according to an embodiment of the present disclosure.

[0060] Referring to Figure 4, the current supply circuit 200 may include a first transistor 220, a second transistor 230, a first switch 240, a second switch 250, and a capacitor 280, etc.

[0061] Data voltage V_data or data current I_data can be supplied from the data drive circuit (not shown) to the first transistor 220 via the data line DL.

[0062] The voltage / current converter 210 may be arranged between the data drive circuit (not shown) and the first transistor 220 to convert the data voltage V_data into the data current I_data. However, when the type of signal transmitted from the data drive circuit (not shown) is the data current I_data, the voltage / current converter 210 may be omitted.

[0063] The second transistor 230 can receive signals transmitted from the first transistor 220 and supply current to the light-emitting diode 290. The light-emitting diode 290 can be a single element, or it can be multiple elements configured as a channel CH1.

[0064] The second transistor 230 can mirror the data current I_data transmitted to the first transistor 220 and transmit the data current I_data to the light-emitting diode 290. The circuit including the first transistor 220 and the second transistor 230 can be defined as a current mirror circuit (not shown).

[0065] The first switch 240 may be arranged between the first transistor 220 and the second transistor 230, and the input current or input voltage of the gate terminal of the second transistor 230 may be adjusted. The first switch 240 may be a switch that cuts off or transmits current by short-circuiting or opening the signal line, and may be a switching transistor that adjusts the current intensity.

[0066] The overall or partial configuration of the first switch 240 may be defined as a current compensation circuit (not shown) for compensating for leakage current occurring in the second transistor 230, or a voltage compensation circuit (not shown) for compensating for voltage changes occurring in the gate terminals of the second transistor 230.

[0067] The second switch 250 may be arranged between the data drive circuit (not shown) and the first transistor 220, and may adjust the current transmitted through the data line DL. The second switch 250 may be a switch that cuts off or transmits current by short-circuiting or opening the signal line, and may be a switching transistor that adjusts the current intensity.

[0068] The output node of the second switch 250 can form a common node to which the terminals of the first transistor 220 are connected, and can form a current mirror circuit. In this case, the current or voltage of the common node can be controlled in response to the operation of the second switch 250.

[0069] The entire or partial configuration of the second switch 250 can be defined as a data current cutting-off switch (not shown) for cutting off data current.

[0070] The operation of the entire or partial configuration of the first switch 240 and the second switch 250 can be performed by relating them to each other. The operation of the first switch 240 and the second switch 250 can be performed by relating them to each other, such that the second switch 250 is turned off during the off period of the first switch 240, or the second switch 250 is turned on during the on period of the first switch 240.

[0071] A capacitor 280 may be disposed between the first transistor 220 and the second transistor 230 to store the voltage at the gate terminal of the second transistor 230. Since the voltage at the gate terminal of the second transistor 230, which is not connected to the capacitor 280, is sensitive to external changes such as external conditions and pixel states, the capacitor 280 can achieve stable pixel operation by storing the voltage at the gate terminal of the second transistor 230.

[0072] The charging voltage of capacitor 280 can be adjusted according to the operation of the first switch 220 or the second switch 230, and can maintain the same voltage during a preset time period.

[0073] In order to prevent leakage current in capacitor 280, the first switch 240 located adjacent to capacitor 280 may be modified in terms of the terminal connection relationship of transistors or the arrangement of transistors.

[0074] The same voltage (e.g., ground voltage) can be supplied to one of the first transistor 220, the second transistor 230, and the capacitor 280, but is not limited thereto. In this case, since the same voltage is supplied to one end of each of the circuits 220, 230, and 280, a reference point for signal transmission can be set.

[0075] The data voltage V_data can be the power supply voltage Vcc supplied to the current supply circuit 200.

[0076] FIG5 is a second example diagram illustrating a current supply circuit according to an embodiment of the present disclosure.

[0077] Referring to Figure 5, the current supply circuit 300 may include a first transistor 320, a second transistor 330, a current compensation circuit 340, a data current cut-off switch 350, and a capacitor 380, etc., and can achieve the same or similar functions as the current supply circuit 200 in Figure 4 above.

[0078] The second transistor 330 can supply the light-emitting diode 390 with a current of a magnitude corresponding to the data current I_data transmitted to the first transistor 320.

[0079] The current compensation circuit 340 may be a switch or a switching transistor, but may be defined as a circuit group including the switch or switching transistor.

[0080] The operation of the circuit in the current compensation circuit 340 can be controlled by the setting value of the data processing circuit (not shown) or the temporary register (not shown) of the current supply circuit 300.

[0081] The data current cut-off switch 350 can be turned on or off in response to the operation of the current compensation circuit 340. For example, the data current cut-off switch 350 can be turned off during the off-time period of all or some of the circuits in the current compensation circuit 340.

[0082] FIG6 is a third example diagram illustrating a current supply circuit according to an embodiment of the present disclosure.

[0083] Referring to Figure 6, the enlarged view of the current supply circuit 300 in Figure 5 can illustrate the connection relationship of the first transistor 320, the second transistor 330, the current compensation circuit 340, the third transistor 341, the fourth transistor 342, the fifth transistor 343 and the buffer 344.

[0084] The current compensation circuit 340 can be connected to the first transistor 320 and the second transistor 330 to adjust the current supplied to the second transistor 330. One end of the second transistor 330 is connected to a capacitor (not shown), and the current supplied to the second transistor 330 can be changed by leakage current appearing in the capacitor (not shown).

[0085] The current compensation circuit 340 may include one or more transistors to adjust the intensity, timing, etc. of the current flowing between the first transistor 320 and the second transistor 330.

[0086] For example, the current compensation circuit 340 can increase the current to compensate for the decrease in current (e.g., the decrease in current caused by the decrease in voltage due to leakage current in the capacitor), or it can decrease the current to compensate for the increase in current (e.g., the increase in current caused by the increase in voltage due to external parasitic capacitance).

[0087] The current compensation circuit 340 may include a group of transistors connected to one end of the first transistor 320 (e.g., the output node) and one end of the second transistor 330 (e.g., the input node).

[0088] The current compensation circuit 340 may include a third transistor 341, a fourth transistor 342, a fifth transistor 343 and a buffer 344.

[0089] The third transistor 341 and the fourth transistor 342 can be connected in series between the first transistor 320 and the second transistor 330, and each transistor (e.g., a field-effect transistor (MOSFET)) can have a source terminal and a drain terminal connected in series.

[0090] One terminal of the second transistor 330 and one terminal of the third transistor 341 can be connected to form a first node (Node 1). The first node can be a common node of the second transistor 330 and the third transistor 341, and the positive (+) terminal of the input terminal of the buffer 344 can be connected to the first node.

[0091] A terminal of the first transistor 320 and a terminal of the fourth transistor 342 can be connected to form a second node (Node 2). The second node can be a common node of the first transistor 320 and the fourth transistor 342.

[0092] A terminal of the third transistor 341 and a terminal of the fourth transistor 342 can be connected to form a third node (Node 3). The third node can be a common node of the third transistor 341 and the fourth transistor 342, and a terminal of the fifth transistor 343 can be connected to the third node.

[0093] One terminal of the fifth transistor 343 can be connected to one terminal of the third transistor 341 and one terminal of the fourth transistor 342 to form a common third node.

[0094] One terminal of the fifth transistor 343 can be connected to the output terminal of the buffer 344 to form a fourth node (Node 4), and the fourth node can be connected to the negative (-) terminal of the input terminal of the buffer 344. The positive (+) terminal of the input terminal of the buffer 344 can be connected to the first node to transfer the voltage stored in the buffer 344 to the first node. The magnitude, timing, etc. of the voltage transferred to the first node can be determined according to the operation of the first transistor to the fifth transistors 320, 330, 341, 342, and 343 described above.

[0095] Buffer 344 and fifth transistor 343 can be defined as being electrically connected in parallel with the first node and the third node, and can be connected in parallel with the third transistor 341 to be defined as a current compensation circuit for compensating the leakage current of the capacitor.

[0096] The gate terminal of the second transistor 330 can be connected to the source or drain terminal of the third transistor 341 to form a common first node. One terminal of the capacitor and buffer 344 can be connected to the first node and can reduce the voltage change at the gate terminal of the second transistor 330.

[0097] The body terminal of the third transistor 341 may have the same voltage as the source terminal or the drain terminal, and may form a common node if necessary.

[0098] If necessary, the names of the first to fifth transistors 320, 330, 341, 342 and 343 may be defined in different ways, and each transistor may be defined as a switch or a switching transistor.

[0099] The current compensation circuit 340 in Figure 6 can be represented by a block diagram of the configuration of the current compensation circuit 340 in Figure 5 above.

[0100] FIG7 is a diagram illustrating the switching operation of the current supply circuit according to an embodiment of the present disclosure during a first time period.

[0101] FIG8 is a diagram illustrating the switching operation of the current supply circuit according to an embodiment of the present disclosure during a second time period.

[0102] Referring to Figures 7 and 8, each circuit element of the current compensation circuit 340 can be driven independently.

[0103] For example, as shown in Figure 7, when the third transistor 341 and the fourth transistor 342 are in the on state, the fifth transistor 343 can be in the off state, and this can be defined as a switch drive during a first time period. The first time period can be a sampling operation state, but is not limited to this.

[0104] For example, as shown in Figure 8, when the third transistor 341 and the fourth transistor 342 are in the off state, the fifth transistor 343 can be in the on state, and this can be defined as a switch drive during a second time period. The second time period can be a hold operation state, but is not limited to this.

[0105] Figures 7 and 8 may illustrate the operation of the drive current compensation circuit 340 at the timing point where the analog signal is sampled and held in the data drive circuit (not shown), but are not limited thereto.

[0106] FIG9 is a diagram illustrating the switching operation of the current supply circuit according to an embodiment of the present disclosure during a first time period.

[0107] Referring to Figure 9, the current supply circuit 400 may include a first transistor 420, a second transistor 430, a current compensation circuit 440, a data current cut-off switch 450, and a capacitor 480, etc.

[0108] Data drive current I_data can be selectively supplied to the first transistor 420 via the data line.

[0109] The second transistor 430 can supply current or voltage to the light-emitting diode 490 for driving pixels in response to the data driving current I_data of the first transistor 420.

[0110] The current compensation circuit 440 may be a circuit connected to the first transistor 420 and the second transistor 430 to adjust the current.

[0111] The current compensation circuit 440 may include a third transistor 441, a fourth transistor 442, a fifth transistor 443 and a buffer 444.

[0112] The current compensation circuit 440 can adjust the intensity, time interval, etc. of the current transmitted between one end of the first transistor 420 (e.g., the second node (Node 2)) and one end of the second transistor 430 (e.g., the first node (Node 1)) via one or more transistors.

[0113] The third transistor 441 of the current compensation circuit 440 can be arranged between the first transistor 420 and the second transistor 430.

[0114] Buffer 444 can be connected in parallel with third transistor 441 to maintain the voltage of third transistor 441, and the output of buffer 444 can be connected in series with fifth transistor 443. In this case, buffer 444 and fifth transistor 443 can be defined as being connected in parallel to third transistor 441.

[0115] The data current cut-off switch 450 can be arranged on the data line connected to the first transistor 420 and can cut off the data drive current I_data.

[0116] The current cut-off switch 450 can change its operation in response to the operating timing of all or some of the circuits in the current compensation circuit 440.

[0117] The capacitor 480 may be connected to the gate terminal of the second transistor 430 to store the gate voltage of the second transistor 430. For example, the gate terminal of the second transistor 430 may be connected to one terminal of the capacitor 480 without limitation to have the same voltage, and the other terminals of the second transistor 430 (e.g., source terminal or drain terminal) may be supplied with the same voltage (e.g., ground voltage) as the other terminal of the capacitor 480.

[0118] The third transistor 441 may be a field-effect transistor (MOSFET), and its body terminal and source terminal may be coupled to prevent leakage current.

[0119] Referring to FIG9, in the current supply circuit 400, the operation of the current compensation circuit 440 and the data current cut-off switch 450 can be determined during the first time period of the data drive circuit (not shown), but any time period can be defined as the time period for the operation of each circuit.

[0120] During the first time period, the third transistor 441 and the fourth transistor 442 of the current compensation circuit 440 can remain in the on state, and the fifth transistor 443 of the current compensation circuit 440 can remain in the off state. In this case, the third transistor 441 and the fourth transistor 442 can be turned on or off in the same timing sequence.

[0121] During the first time period, the data current cut-off switch 450 can remain in the on state. In this case, the data current I_data can be transmitted to the first transistor 420.

[0122] When current is supplied through a terminal (e.g., the second node) of the first transistor 420, the third transistor 441 and the fourth transistor 442 are in a conducting state. Therefore, current can be supplied to the second transistor 430 through the third transistor 441 and the fourth transistor 442.

[0123] When current is supplied through a terminal (e.g., the second node) of the first transistor 420, the fifth transistor 443 is in the off state. Therefore, current is not supplied to the buffer 444 through the fifth transistor 443.

[0124] Although the third to fifth transistors 441, 442 and 443 can be operated individually, the operation of the third to fifth transistors 441, 442 and 443 can be controlled in the same timing sequence.

[0125] When the operation of the current compensation circuit 440 and the data current cut-off switch 450 is controlled simultaneously, the voltage supplied to the light-emitting diode 490 of the pixel by the second transistor 430 can be stably maintained, and the power consumption of the buffer 444 can be reduced. The operation of the current compensation circuit 440 and the data current cut-off switch 450 can be controlled in the same timing sequence (e.g., any time period such as a first time period or a second time period).

[0126] Based on the arrangement of the third transistor 441, the fourth transistor 442, the fifth transistor 443 and the buffer 444 in the current compensation circuit 440, the voltage change caused by the leakage current occurring at one end of the second transistor 430 or the capacitor 480 can be effectively prevented.

[0127] FIG10 is a diagram illustrating the switching operation of the current supply circuit according to an embodiment of the present disclosure during a second time period.

[0128] Referring to FIG10, the current supply circuit 400 can determine the operation of the current compensation circuit 440 and the data current cut-off switch 450 during the second time period of the data drive circuit (not shown).

[0129] During the second time period, the third transistor 441 and the fourth transistor 442 of the current compensation circuit 440 can remain in the off state during the holding period, and the fifth transistor 443 of the current compensation circuit 440 can remain in the on state. In this case, the third transistor 441 and the fourth transistor 442 can be turned on or off in the same timing.

[0130] During the second time period, the data current cut-off switch 450 can remain in the off state. In this case, the data current I_data transmitted to the first transistor 420 can be cut off.

[0131] When the operation of the current compensation circuit 440 and the data current cut-off switch 450 is controlled simultaneously, the first transistor 420 and the second transistor 430 can be electrically isolated, and the noise caused by leakage current can be reduced at the same time.

[0132] Since the data current cut-off switch 450 cuts off the data current I_data in the off state, the power consumption caused by the continuous supply of data current I_data to the first transistor 420 regardless of the state of the second transistor 430 can be reduced.

[0133] Furthermore, since the third transistor 441 and the fourth transistor 442 of the current compensation circuit 440 cut off the current flow between the first transistor 420 and the second transistor 430 in the off state, the first transistor 420 and the second transistor 430 can be electrically isolated until the next sampling period.

[0134] For example, when the first transistor 420 and the second transistor 430 form a current mirror circuit, the mirror current changes together in response to the change of the input current, but each transistor can be maintained in an electrically independent state by means of the third transistor 441 and the fourth transistor 442.

[0135] The fifth transistor 443 of the current compensation circuit 440 can electrically connect the third node and the fourth node when it is in the on state. In this case, the buffer 444 can maintain the voltage of the fourth node and the voltage of the first node at the same level, and thus, even if the third transistor 441 and the fourth transistor 442 are in the off state, the voltage of the first node can be stably maintained.

[0136] The buffer 444 can be connected in parallel to the terminals of the third transistor 441 to compensate for the leakage current of the capacitor 480 and to compensate for the voltage at the gate terminals of the second transistor 430.

[0137] Therefore, since the current supply circuit 400 according to the embodiment of the present disclosure can prevent voltage changes in the capacitor 480 by compensating for current leakage, a constant current can be supplied to the light-emitting diode 490. Considering this characteristic of the current supply circuit 400, the current compensation circuit 440 can be defined as a voltage compensation circuit, etc.

[0138] The operation of transistors 441, 442 and 443 in Figures 9 and 10 can correspond to the operation sequence of data current cut-off switch 450.

[0139] For example, when the data current cut-off switch 450 is turned on, the third transistor 441 and the fourth transistor 442 can be turned on, and the fifth transistor 443 can be turned off.

[0140] For example, when the data current cut-off switch 450 is turned off, the third transistor 441 and the fourth transistor 442 can be turned off, and the fifth transistor 443 can be turned on.

[0141] The operation of transistors 441, 442, 443 and data current cut-off switch 450 in Figures 9 and 10 is not limited to operation during the sampling and holding period of the data drive circuit (not shown), and the same function can be achieved during any time period.

[0142] Depending on the input / output direction of the current or voltage, the terminals of each transistor can be defined as input terminals or output terminals, and the nodes connected to each terminal can be defined as input nodes or output nodes.

[0143] Figure 11 is a diagram used to illustrate the current leakage treatment of transistors.

[0144] Referring to Figure 11, the switching transistor 1000 may be a field-effect transistor including N-well 1010 and P-well 1020, etc.

[0145] The N-well 1010 may include a body terminal (N+ terminal) 1001, a first terminal 1002, and a second terminal 1003. The first terminal 1002 and the second terminal 1003 may be a source terminal and a drain terminal, and their order may be arbitrarily defined.

[0146] As shown in FIG11, in the conventional technology, since the terminals of the switching transistor 1000 are maintained in an undisturbed state, current may leak from the body terminal 1001 to the first terminal 1002 or the second terminal 1003. In this case, when current leaks from the body terminal 1001 to the second terminal 1003, the brightness of the pixel may change due to the charge transferred to the capacitor.

[0147] For example, the switching transistor 1000 may be the third transistor 441 of FIG9 above, the first terminal 1002 may be a terminal connected to the third node, and the second terminal 1003 may be a terminal connected to the first node.

[0148] If the current supplied to the first terminal 1002 is cut off by a switch (not shown) connected to the first terminal 1002, the current supplied to the second terminal 1003 increases, and therefore the amount of leakage current may increase further.

[0149] In this case, due to the leakage current that occurs in the high-voltage body terminal 1001, the voltage (Vx) of the first terminal 1002 (e.g., the voltage at point X) and the voltage (Vy) of the second terminal 1003 (e.g., the voltage at point Y) become different.

[0150] The parasitic diode formed between the main body terminal 1001 and the second terminal 1003 may not be a physically formed parasitic diode, but rather a conceptually formed parasitic diode.

[0151] The P+ terminal of the P-well 1020 can have a ground voltage.

[0152] FIG12 is a diagram illustrating a method for preventing current leakage of transistors according to an embodiment of the present disclosure.

[0153] As shown in Figure 12, when the main body terminal 1001 and the first terminal 1002 are maintained at the same voltage, current leakage can be prevented.

[0154] The voltage of the main body terminal 1001 can be maintained at the same level as the voltage (Vx) of the first terminal 1002 (e.g., the voltage at point X), and the voltage (Vy) of the second terminal 1003 (e.g., the voltage at point Y) can also be maintained at the same level as the voltage (Vx) of the first terminal 1002.

[0155] The on and off states of the first switching transistor 441 in Figures 9 and 10 can indicate changes in the states of Figures 11 and 12. In this case, the third node of the first switching transistor 441 can be the first terminal 1002, the first node of the first switching transistor 441 can be the second terminal 1003, and the first terminal 1002 and the second terminal 1003 can be maintained at the same voltage by means of the buffer 444.

[0156] The main body terminal 1001 and the first terminal 1002 may be connected by a signal line or form a common node to maintain the same voltage, but are not limited thereto.

[0157] The voltage state of each terminal of the switching transistor 1000 can be changed according to the operation of the internal circuit for different time periods. By combining the operation of one or more switches or switching transistors, leakage current can be prevented and power consumption in the display device can be reduced at the same time.

[0158] The transistor 1000 in Figures 11 and 12 can be the third transistor 441 in Figures 9 and 10, but is not limited thereto.

[0159] Cross-reference to related applications

[0160] This application claims priority to Korean Patent Application 10-2021-0123621, filed on September 16, 2021, the entire contents of which are incorporated herein by reference. [Simplified Explanation of the Diagram]

[0015] FIG1 is a diagram showing the configuration of a display device according to an embodiment of the present disclosure.

[0016] FIG2 is a diagram showing the signal flow of a current supply circuit according to an embodiment of the present disclosure.

[0017] FIG3 is a diagram showing the signal timing of a current supply circuit according to an embodiment of the present disclosure.

[0018] FIG4 is a first example diagram illustrating a current supply circuit according to an embodiment of the present disclosure.

[0019] FIG5 is a second example diagram illustrating a current supply circuit according to an embodiment of the present disclosure.

[0020] FIG6 is a third example diagram illustrating a current supply circuit according to an embodiment of the present disclosure.

[0021] FIG7 is a diagram illustrating the switching operation of the current supply circuit according to an embodiment of the present disclosure during a first time period.

[0022] FIG8 is a diagram illustrating the switching operation of the current supply circuit according to an embodiment of the present disclosure during a second time period.

[0023] FIG9 is a diagram illustrating the switching operation of the current supply circuit according to an embodiment of the present disclosure during a first time period.

[0024] FIG10 is a diagram illustrating the switching operation of the current supply circuit according to an embodiment of the present disclosure during a second time period.

[0025] Figure 11 is a diagram used to illustrate the current leakage treatment of transistors.

[0026] FIG12 is a diagram illustrating a method for preventing current leakage of transistors according to an embodiment of the present disclosure.

Claims

1. A current mirror circuit, comprising: A first transistor is configured such that a data driving circuit supplies data current to the first transistor. A second transistor is configured to drive a light-emitting diode by mirroring the data current transmitted to the first transistor; a capacitor is disposed between the first transistor and the second transistor and is configured to store the voltage at the gate terminal of the second transistor; a first switch is disposed between the first transistor and the second transistor and is configured to adjust the input current at the gate terminal of the second transistor. And a second switch, which is arranged between the data driving circuit and the first transistor, wherein the second switch is turned off during the off period of the first switch, or the second switch is turned on during the on period of the first switch.

2. The current mirror circuit according to claim 1, wherein, The same voltage is supplied to one terminal of the first transistor and one terminal of the second transistor.

3. The current mirror circuit according to claim 1, wherein, The voltage charged in the capacitor is adjusted by operating the first switch and the second switch.

4. The current mirror circuit according to claim 1, wherein, The first switch includes: a third transistor disposed between the first transistor and the second transistor; and a buffer connected in parallel with the terminals of the third transistor and configured to compensate for leakage current of the capacitor.

5. The current mirror circuit according to claim 4, wherein, The body terminal of the third transistor forms a common node with the source terminal or the drain terminal.

6. The current mirror circuit according to claim 4, wherein, The first switch further includes: a fourth transistor connected to a common node connected to the terminals of the first transistor and the output node of the second switch, and the input node of the third transistor; and a fifth transistor connected to a common node formed by the input node of the third transistor and the output node of the fourth transistor, wherein the third transistor and the fourth transistor operate in the same timing sequence.

7. A current supply circuit, comprising: A first transistor is configured such that a data drive current is supplied to the first transistor via a data line. The second transistor is configured to supply pixel current to the light-emitting diode in response to the data drive current of the first transistor. The current compensation circuit is connected to the first transistor and the second transistor and configured to adjust the current delivered to the second transistor. The current compensation circuit adjusts the current between the first transistor and the second transistor by means of at least one switching transistor. The current compensation circuit includes: a third transistor disposed between the first transistor and the second transistor and connected to the gate terminal of the second transistor; and a buffer connected in parallel with each terminal of the third transistor and configured to maintain the voltage of the third transistor.

8. The current supply circuit according to claim 7, wherein, The data line connected to the first transistor includes a data current cut-off switch for cutting off the data drive current.

9. The current supply circuit according to claim 7, wherein, The second transistor forms a common node with the capacitor used to store the voltage of the gate terminals.

10. The current supply circuit according to claim 9, wherein, The third transistor is a field-effect transistor in which the body terminal and the source terminal are connected.

11. The current supply circuit according to claim 9, wherein, The current compensation circuit further includes a fourth transistor, which is arranged between the first transistor and the third transistor, wherein the fourth transistor is turned on or off in the same timing sequence as the third transistor.

12. The current supply circuit according to claim 11, wherein, The current compensation circuit further includes a fifth transistor connected to a common node of the third and fourth transistors, wherein one end of the fifth transistor forms the common node by being connected to the output terminal of the buffer.

13. The current supply circuit according to claim 12, wherein, When the third and fourth transistors are in the ON state, the fifth transistor remains in the OFF state; and when the third and fourth transistors are in the OFF state, the fifth transistor remains in the ON state.

14. The current supply circuit according to claim 13, wherein, The operating timing of the third to fifth transistors corresponds to the operating timing of the data current cut-off switch connected to one end of the first transistor.

15. A current supply circuit, comprising: The first transistor is selectively supplied with data drive current via a data line by using a data current cut-off switch; A second transistor is configured to supply a current to a light-emitting diode having a magnitude corresponding to the magnitude of the data drive current transmitted to the first transistor; and a voltage compensation circuit is connected to one end of the first transistor and one end of the second transistor and configured to compensate the voltage at the gate terminals of the second transistor, wherein the operation of the voltage compensation circuit changes according to the operating timing of the data current cut-off switch.

16. The current supply circuit according to claim 15 further includes: A third and a fourth transistor are connected to the gate terminals of the first and second transistors, wherein when the data current cut-off switch is turned off, the third and the fourth transistors electrically isolate the first and the second transistors by stopping the current supply.

17. The current supply circuit according to claim 16 further includes: The fifth transistor is connected to the common node formed by the third and fourth transistors; And a buffer having an input terminal connected to a common node between the second and third transistors, and an output terminal connected to a node at one end of the fifth transistor, to maintain the gate voltage of the second transistor at a constant.

18. The current supply circuit according to claim 17, wherein, The operating timing sequence of the third to the fifth transistors corresponds to the operating timing sequence of the data current cut-off switch. When the data current cut-off switch is turned on, the third and fourth transistors are turned on and the fifth transistor is turned off; or when the data current cut-off switch is turned off, the third and fourth transistors are turned off and the fifth transistor is turned on.

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