Method for lane synchronization for an interconnection protocol, controller and storage device

Abstract

A method, controller, and storage device for channel synchronization of an interconnection protocol. The method is applicable to a first device capable of linking a second device according to an interconnection protocol, and includes: providing data representing a tolerance interval, indicating the time interval between two consecutive periodic tolerance patterns; and adaptively transmitting periodic tolerance patterns on a channel between the first and second devices according to the tolerance interval, in response to communication status information between the first and second devices, by means of a hardware protocol engine for implementing the interconnection protocol link layer, wherein the hardware protocol engine is configured to periodically transmit tolerance patterns according to the tolerance interval when the communication status information meets a criterion, and to delay transmitting tolerance patterns when the criterion does not meet a criterion.

Description

Technical Field

[0001] The present invention relates to an electronic device, and more particularly to a method, a controller and a storage device for channel synchronization of an interconnection protocol. Prior Art

[0002] The amount of data transmitted and processed in today's mobile devices (such as smartphones, tablets, multimedia devices, wearable devices and other computing devices) continues to increase. The chip-to-chip interconnect interface technology within mobile devices or those affected by mobile devices needs to further evolve to achieve goals such as higher transmission speeds, low-power operation, scalability, support for multi-tasking, and ease of adoption.

[0003] To this end, the Mobile Industry Processor Interface (MIPI) Alliance has developed interconnect interface technologies that meet these goals, such as the MIPI M-PHY specification for the physical layer and the MIPI UniPro specification for the Unified Protocol (UniPro). Separately, the Joint Electron Device Engineering Council (JEDEC) is leveraging the MIPI M-PHY and MIPI UniPro specifications to launch a next-generation, high-performance non-volatile memory standard called Universal Flash Storage (UFS). UFS achieves gigabit-per-second (GB / s) high-speed transmission and low-power operation, while also possessing the functionality and scalability required for high-end mobile systems, facilitating rapid industry adoption.

[0004] When developing products based on these interconnect interface technologies, such as chips, electronic modules, or electronic devices, technicians must ensure that the product's functionality and operation comply with the specifications. For example, a system implemented according to the UFS standard includes a computing device and a non-volatile memory storage device, with the computing device and storage device acting as the local host and remote device, respectively. A bidirectional link is established between the host and device, and the link between the host and device can be configured as multiple lanes in either direction. Accordingly, the processing circuitry in both the host and device, configured according to the UniPro interconnect protocol, must be capable of handling multiple lanes.

[0005] To maintain accurate and efficient data transmission between the host and device, the channels between the two must be synchronized. Any misalignment between the channels will result in transmission errors. Interconnect interface technologies typically provide error recovery mechanisms to ensure continued data transmission between the host and device. However, error recovery mechanisms are time-consuming and can affect or even reduce transmission performance between the host and device. Summary of the Invention

[0006] This disclosure provides a technology for channel synchronization within an interconnect protocol, applicable to a first device capable of connecting to a second device according to the interconnect protocol. During communication between the first device and the second device via the interconnect protocol, this technology adaptively utilizes a periodic anti-skew pattern within the interconnect protocol to promote channel synchronization, thereby helping to reduce errors and improve transmission performance between the host and the device.

[0007] Various implementations are proposed below based on this technology, such as a method, a controller, and a storage device for channel synchronization of an interconnection protocol.

[0008] The present disclosure provides an embodiment of a method for channel synchronization of an interconnect protocol, which is applicable to a first device capable of linking to a second device according to the interconnect protocol. The method for channel synchronization of the interconnect protocol includes: providing data representing an anti-skew interval, the anti-skew interval representing the time interval between two consecutive periodic anti-skew patterns; and, by a hardware protocol engine for implementing a link layer of the interconnect protocol, responsive to communication status information between the first device and the second device and based on the anti-skew interval, adaptively transmitting the periodic anti-skew pattern on a channel from the first device to the second device. The hardware protocol engine is configured to periodically send the anti-skew pattern according to the anti-skew interval when the communication status information meets a criterion for transmitting the periodic anti-skew pattern, and to delay sending the anti-skew pattern when the communication status information does not meet the criterion.

[0009] The present disclosure provides a controller embodiment for use in a first device capable of connecting to a second device according to an interconnect protocol. The controller includes an interface circuit and a hardware protocol engine. The interface circuit is configured to implement a physical layer of the interconnect protocol to connect to the second device. The hardware protocol engine is coupled to the interface circuit and is configured to implement a link layer of the interconnect protocol. The hardware protocol engine is configured to, in response to communication status information between the first and second devices during a burst transmission, adaptively transmit a periodic anti-skew pattern on a channel from the first device to the second device according to an anti-skew interval, wherein the anti-skew interval represents the time interval between two consecutive periodic anti-skew patterns. The hardware protocol engine is configured to periodically transmit an anti-skew pattern according to the anti-skew interval when the communication status information meets a criterion for transmitting the periodic anti-skew pattern, and to delay transmitting the anti-skew pattern when the communication status information does not meet the criterion.

[0010] The present disclosure provides an embodiment of a storage device capable of connecting to a host according to an interconnection protocol. The storage device includes: a storage module and a controller. The controller is coupled to the storage module and configured to implement the interconnection protocol. The controller includes an interface circuit and a hardware protocol engine. The interface circuit implements a physical layer of the interconnection protocol to connect to the host. The hardware protocol engine is coupled to the interface circuit and configured to implement a link layer of the interconnection protocol. The hardware protocol engine is configured to, in response to communication status information between the storage device and the host during a burst transmission, adaptively transmit a periodic anti-skew pattern on a channel from the storage device to the host according to an anti-skew interval, wherein the anti-skew interval represents the time interval between two consecutive periodic anti-skew patterns. The hardware protocol engine is configured to periodically transmit an anti-skew pattern according to the anti-skew interval when the communication status information meets a criterion for transmitting the periodic anti-skew pattern, and to delay transmitting the anti-skew pattern when the communication status information does not meet the criterion.

[0011] In some embodiments of the above-mentioned method, controller or storage device for channel synchronization of an interconnection protocol, the communication status information includes a burst transmission indication signal and frame busy information.

[0012] In some embodiments of the method, controller, or storage device for channel synchronization of an interconnect protocol, the determination criteria include: the burst transmission indication signal indicates that the burst transmission is in progress, when a period according to the anti-skew interval is reached, and when the frame busy information indicates that no frame is being transmitted.

[0013] In some embodiments of the method, controller, or storage device for channel synchronization of an interconnect protocol, the hardware protocol engine is configured to send the anti-skew pattern when it is determined that the burst transmission indication signal indicates that the burst transmission is in progress, a period based on the anti-skew interval has been reached, and the frame busy information indicates that no frame is being transmitted.

[0014] In some embodiments of the method, controller, or storage device for channel synchronization of an interconnect protocol, the hardware protocol engine is configured to delay sending the anti-skew pattern when determining that the burst transmission indication signal indicates that the burst transmission is in progress, a period based on the anti-skew interval has been reached, and the frame busy information indicates that a frame is being transmitted.

[0015] In some embodiments of the aforementioned method, controller, or storage device for channel synchronization of an interconnect protocol, the hardware protocol engine is configured to, when determining that the burst transmission indication signal indicates that the burst transmission is in progress, a period according to the anti-skew interval has expired, and the frame busy information indicates that no frame transmission has occurred, further check whether the time interval between the current time and the time point at which the next period according to the anti-skew interval is reached is greater than or equal to a minimum value to determine whether to send the anti-skew pattern.

[0016] In some embodiments of the method, controller, or storage device for channel synchronization of an interconnect protocol, the hardware protocol engine is configured to send the anti-skew pattern if the time interval is greater than or equal to the minimum value.

[0017] In some embodiments of the controller or storage device described above, the controller further includes an anti-skew request circuit. The anti-skew request circuit is disposed within the hardware protocol engine and is configured to respond to communication status information between the first device and the second device during a burst transmission and adaptively transmit periodic anti-skew requests based on the anti-skew interval. When the anti-skew request circuit determines that the communication status information meets the judgment criteria, the anti-skew request circuit periodically transmits an anti-skew request based on the anti-skew interval. When the anti-skew request circuit determines that the communication status information does not meet the judgment criteria, the anti-skew request circuit delays transmitting the anti-skew request. The hardware protocol engine is configured to transmit the anti-skew pattern on the channel from the first device to the second device in response to the anti-skew request.

[0018] In some embodiments of the controller or storage device, the controller or storage device is further configured to dynamically adjust the value of the anti-skew interval according to an indication signal of the link layer regarding the quality of service when the anti-skew interval is greater than a minimum allowed value.

[0019] In some embodiments of the above-mentioned controller or storage device, the controller or storage device is configured to perform multiple operations to dynamically adjust the anti-deviation interval, and the operations include: determining whether the value of the anti-deviation interval is greater than the minimum value allowed in response to the indication signal to notify that the threshold value of the error event has been reached; and when the anti-deviation interval is greater than the minimum value allowed, changing the value of the anti-deviation interval from a first value to a second value, wherein the second value is less than the first value and greater than or equal to the minimum value allowed.

[0020] In some embodiments of the method, controller, or storage device for channel synchronization of an interconnect protocol, the interconnect protocol is a Universal Flash Storage (UFS) standard. Simple diagram description

[0021] FIG. 1A is a schematic circuit diagram of an embodiment of a storage system. FIG. 1B is a block diagram of one embodiment of a controller for interconnection protocols applicable to FIG. 1A . FIG. 1C is a block diagram of another embodiment of a controller for interconnection protocols applicable to FIG. 1A . FIG. 2 is a schematic diagram of a layered architecture of the storage system of FIG. 1A according to the UFS standard. FIG. 3A is a schematic flow chart of an embodiment of a method for channel synchronization of an interconnect protocol. FIG. 3B is a schematic circuit architecture diagram of an embodiment for implementing the method based on FIG. 3A . FIG. 3C is a schematic circuit diagram illustrating an embodiment of a circuit for implementing a physical adapter layer. FIG. 4A is a timing diagram illustrating an embodiment of adaptively utilizing a periodic anti-skew pattern. FIG. 4B is a timing diagram illustrating an embodiment of adaptively utilizing a periodic anti-skew pattern. FIG. 4C is a timing diagram illustrating an embodiment of adaptively utilizing a periodic anti-skew pattern. FIG. 4D is a timing diagram illustrating an embodiment of adaptively utilizing a periodic anti-skew pattern. FIG. 5 is a block diagram of an embodiment of the anti-skew request generation circuit in FIG. 3C . FIG. 6 is a schematic timing diagram illustrating an embodiment of adaptively sending a periodic anti-skew pattern using the circuit of FIG. 5 . FIG. 7 is a schematic timing diagram illustrating another embodiment of adaptively sending a periodic anti-skew pattern using the circuit of FIG. 5 . FIG8 is a schematic flow chart of another embodiment of adaptively utilizing anti-bias patterns. FIG9 is a schematic flow chart of yet another embodiment of adaptively utilizing anti-bias patterns. Implementation Method

[0022] In order to fully understand the purpose, features and effects of the present invention, the present invention is described in detail through the following specific embodiments and the accompanying drawings.

[0023] Several embodiments of a technology for channel synchronization for an interconnect protocol are provided below. These technologies are applicable to a first device capable of connecting to a second device according to the interconnect protocol. During communication between the first device and the second device via the interconnect protocol, this technology adaptively utilizes a periodic de-skew pattern within the interconnect protocol to facilitate channel synchronization, thereby reducing errors and improving transmission performance between the host and the device.

[0024] To facilitate understanding and illustration of various implementations of this technology, the following first provides a circuit architecture for a communication system based on an interconnect protocol. Please refer to Figure 1A, which is a schematic circuit architecture diagram according to one embodiment. As shown in Figure 1A, a storage system 1 includes a host 10 and a storage device 20. Host 10 and storage device 20 communicate via an interconnect protocol, allowing host 10 to access data from storage device 20. This interconnect protocol, for example, is the Universal Flash Storage (UFS) standard or other suitable chip-to-chip communication protocol. Based on the circuit architecture of Figure 1A, the aforementioned technology can be applied to a first device (such as storage device 20 in Figure 1A) that can connect to a second device (such as host 10 in Figure 1A) based on the interconnect protocol. It is also applicable to scenarios where the first device is host 10 and the second device is storage device 20. In the circuit architecture of Figure 1A, the controller in host 10 or storage device 20 that implements the interconnect protocol can be implemented in various ways. As shown in FIG1A , the controller for implementing the interconnection protocol in host 10 (e.g., host controller 12) or the controller for implementing the interconnection protocol in storage device 20 (e.g., device controller 22) can each be implemented as a circuit architecture including a hardware protocol engine and a processing unit, wherein the processing unit of each controller is optional. In another example, as shown in FIG1B , the controller for implementing the interconnection protocol in host 10, such as protocol controller PC1, can be configured to include host interface 11 and hardware protocol engine 13 and implemented as a single chip, wherein processing unit 14 can be considered an external circuit of protocol controller PC1. Similarly, the controller for implementing the interconnection protocol in storage device 20 (or storage device 20 protocol controller) can be configured to include device interface 21 and hardware protocol engine 23 and implemented as a single chip, wherein processing unit 24 can be considered an external circuit of the protocol controller. For example, as shown in FIG1C , the controller for implementing the interconnection protocol in host 10, such as protocol controller PC2, can be configured to include host interface 11, hardware protocol engine 13, and processing unit 14, and implemented as a single chip. Similarly, the controller for implementing the interconnection protocol in storage device 20 (or the protocol controller of storage device 20) can be configured to include device interface 21, hardware protocol engine 23, and processing unit 24, and implemented as a single chip. Thus, based on the circuit architecture of FIG1A , the controller for implementing the interconnection protocol in host 10 or storage device 20 can be considered to encompass or represent the aforementioned embodiments based on FIG1A , FIG1B , or FIG1C . The following further examples regarding FIG1A are also applicable to the embodiments based on FIG1A , FIG1B , or FIG1C .

[0025] The circuit architecture shown in FIG1A is sufficiently flexible and can be efficiently configured to meet the needs of different products, adapting to the designs of various manufacturers and facilitating product development. For example, host 10 is a computing device such as a smartphone, tablet computer, or multimedia device. Storage device 20 is, for example, an internal or external storage device of the computing device, such as a non-volatile memory-based storage device. Storage device 20 can write data under the control of host 10 or provide written data to host 10. Storage device 20 can be implemented as a solid-state storage device (SSD), a multimedia card (MMC), an embedded MMC (eMMC), a secure digital (SD) card, or a universal flash storage (UFS) device, however, implementation of the present disclosure is not limited to these examples.

[0026] The host 10 includes a host interface 11 , a host controller 12 , and an application processor 16 .

[0027] The host interface 11 is used to implement a physical layer of the interconnection protocol to connect to the storage device 20. For example, the host interface 11 is used to implement the physical (M-PHY) layer of the UFS standard.

[0028] The host controller 12 is coupled between the host interface 11 and the application processor 16. When the application processor 16 needs to access data from the storage device 20, it issues a corresponding access instruction or writes data to the host controller 12. The host controller 12 then communicates with the storage device 20 via the interconnect protocol, thereby enabling data access to the storage device 20.

[0029] The host controller 12 includes, for example, a hardware protocol engine 13 and a processing unit 14, wherein the processing unit 14 is optional.

[0030] The hardware protocol engine 13 implements a link layer of the interconnect protocol. For example, if the interconnect protocol is the UFS standard, the link layer is the Unified Protocol (UniPro) layer. The hardware protocol engine 13 communicates with the host interface 11 and the processing unit 14 and converts information based on the link layer specifications.

[0031] The processing unit 14 is coupled to the hardware protocol engine 13 for communicating with the application processor 16. The processing unit 14 can execute one or more firmware programs. For example, access commands or write data issued by the operating system, driver, or application program executed by the application processor 16 are converted by the firmware executed by the processing unit 14 into a command format that complies with the link layer of the interconnect protocol and is then sent to the hardware protocol engine 13 for processing according to the link layer specifications. Alternatively, read data returned by the storage device 20 in response to a read command from the host 10 is returned to the hardware protocol engine 13 according to the link layer specifications of the interconnect protocol and converted by the corresponding firmware executed by the processing unit 14 into a format that can be read by the operating system, driver, or application program executed by the application processor 16. The firmware can be stored, for example, in the internal memory of the processing unit 14 or in the internal memory of the host controller 12, where the internal memory may include volatile memory and non-volatile memory. The processing unit 14 is optional, that is, the above-mentioned firmware work can also be implemented in the hardware protocol engine 13 using hardware.

[0032] The storage device 20 includes a device interface 21 , a device controller 22 , and a storage module 26 .

[0033] The device interface 21 is used to implement a physical layer of the interconnection protocol to connect to the host 10. For example, the device interface 21 is used to implement the physical (M-PHY) layer of the UFS standard.

[0034] The device controller 22 is coupled between the device interface 21 and the storage module 26. The device controller 22 essentially performs the same functions as the host controller 12 described above. When access commands or write data issued by the host 10 are transmitted to the storage device 20 via the interconnect protocol, the device controller 22 converts the data received via the interconnect protocol into corresponding access commands or write data for the storage module 26, enabling the storage module 26 to access the data. Alternatively, the device controller 22 transmits read data returned by the storage device 20 in response to read commands from the host 10 back to the host 10 according to the link layer specifications of the interconnect protocol. For example, the storage module 26 includes one or more non-volatile memory chips, such as flash memory chips. To this end, in one example, the storage device 20 may further include a flash memory controller. The flash memory controller is coupled between the device controller 22 and the storage module 26 and can be configured to control write operations, read operations, or erase operations of the storage module 26 and can exchange data with the storage module 26 via an address bus or a data bus. In another example, the flash memory controller can also be further provided in the device controller 22.

[0035] The device controller 22 includes a hardware protocol engine 23 and a processing unit 24, wherein the processing unit 24 is optional.

[0036] The hardware protocol engine 23 is used to implement a link layer of the interconnection protocol. For example, if the interconnection protocol is the UFS standard, the link layer is the UniPro layer. The hardware protocol engine 23 communicates with the device interface 21 and the processing unit 24 and converts information according to the specifications of the link layer.

[0037] The processing unit 24 is coupled to the hardware protocol engine 23 and is configured to communicate with the host 10 via the device interface 21. The processing unit 24 may execute one or more firmware programs. For example, the processing unit 24 executes one or more firmware programs to communicate with the aforementioned flash memory controller to facilitate the exchange of information between the interconnect protocol and the flash memory controller, such as access operation commands, data writing, and data reading. The firmware programs may be stored in the internal memory of the processing unit 24, the internal memory of the device controller 22, or a specific storage area of ​​the storage module 26. The internal memory may include both volatile and non-volatile memory.

[0038] As shown in Figure 1A, the host interface 11 can be coupled to the device interface 21 via data lines Din and Dout for sending / receiving data, a reset line RST for sending a hardware reset signal, and a clock line CLK for sending data. The data lines Din and Dout can be implemented as multiple pairs, with a pair of data lines Din or a pair of data lines Dout being referred to as a lane. The host interface 11 can communicate with the device interface 21 using at least one interface protocol, such as the Mobile Industry Processor Interface (MIPI), Universal Flash Storage (UFS), Small Computer System Interface (SCSI), or Serial Attached SCSI (SAS), although the implementation of the present disclosure is not limited to these examples. Under the UFS standard, the connection between the host 10 and the storage device 20 can be configured to support multiple lanes to improve transmission efficiency. Currently, a maximum of two lanes are supported in either direction, either between the host 10 and the storage device 20 or between the storage device 20 and the host 10. Multiple lanes can be enabled or disabled.

[0039] The following uses the Universal Flash Storage (UFS) standard as an example to explain this interconnect protocol in detail. The UFS standard comprises the UFS Command Set Layer (USC), the UFS Transport Protocol (UTP), and the UFS Interconnect Layer (UIC). The UIC further comprises a link layer and a physical layer. The UIC link layer is defined according to the UniPro specification, while the UIC physical layer is defined according to the M-PHY specification.

[0040] Please refer to FIG2 , which is a schematic diagram of the layered architecture of the storage system shown in FIG1A , based on the UFS standard. Since the UFS standard is based on the MIPI unified protocol (UniPro) layer and the MIPI physical (M-PHY) layer, the host interface 11 and hardware protocol engine 13 of the host 10 shown in FIG1A are used to implement the physical layer 110 and UniPro layer 130 , respectively, in FIG2 . The device interface 21 and hardware protocol engine 23 of the storage device 20 shown in FIG1A are used to implement the physical layer 210 and UniPro layer 230 , respectively, in FIG2 .

[0041] As shown in FIG2 , the UniPro layer 130 (or 230) may include a physical adapter layer (PHY adapter layer, PA) 131 (or 231), a data link layer (DL) 132 (or 232), a network layer 133 (or 233), and a transport layer 134 (or 234). The various layers in the UniPro layer 230 of the storage device 20 may also operate and be implemented similarly.

[0042] The physical adapter layer (131 or 231) couples the physical layer (110 or 210) to the data link layer (132 or 232). The physical adapter layer (131 or 231) can perform bandwidth control, power management, and other functions between the physical layer (110 or 210) and the data link layer (132 or 232). In implementation, the physical layer 110 of the host 10 includes a transmitter 111 and a receiver 112, and the physical layer 210 of the storage device 20 includes a transmitter 211 and a receiver 212, thereby establishing data channels SL1 and SL2 for full-duplex communication. The UniPro specification supports multiple data channels in each transmission direction (e.g., forward or reverse) of the link.

[0043] The data link layer (132 or 232) can perform flow control for data transmission between the host 10 and the storage device 20. Specifically, the data link layer (132 or 232) can monitor data transmission or control the data transmission rate. Furthermore, the data link layer (132 or 232) can perform error control based on a cyclic redundancy check (CRC). The data link layer (132 or 232) can generate frames using packets received from the network layer (133 or 233) or can generate packets using frames received from the physical adapter layer (131 or 231).

[0044] The network layer (133 or 233) is used for a routing function of selecting a transmission path for a packet received from the transport layer (134 or 234).

[0045] The transport layer (134 or 234) can use the command received from the UFS application layer to configure a data segment suitable for the protocol and send the data segment to the network layer (133 or 233), or can extract the command from the packet received from the network layer (133 or 233) and send the command to the UFS application layer. The transport layer (134 or 234) can use a sequence-based error control scheme to ensure the validity of data transmission.

[0046] Furthermore, the UniPro layer (130 or 230) further defines a device management entity (DME) (135 or 235), which can communicate with the physical layer (110 or 210) and various layers in the UniPro layer (130 or 230), such as the physical adapter layer (131 or 231), the data link layer (132 or 232), the network layer (133 or 233), the transport layer (134 or 234), and even the UFS application layer, thereby realizing the overall functions of the unified protocol (UniPro), such as power on, power off, reset, power mode change, and other control or configuration functions.

[0047] The following uses the power consumption mode and burst transmission operation defined by UniPro in the physical adapter layer of the UniPro specification as an example to illustrate the technical issues regarding channel synchronization observed by the inventors of this case in interconnect protocols supporting multiple channels.

[0048] Table 1 below shows the mapping between the UniPro power consumption modes and UniPro power consumption states defined in the UniPro specification and the M-PHY states defined in the M-PHY specification. Table 1 UniPro Power Mode UniPro Power Consumption Status M-PHY Status Fast Mode Fast State (FAST_STATE) High-Speed ​​Burst (HS-BURST) Fast Auto Mode (FastAuto_Mode) Slow Mode (Slow_Mode) SLOW_STATE Pulse Width Modulation Burst (PWM-BURST) Slow Auto Mode (SlowAuto_Mode) Fast Auto Mode (FastAuto_Mode) Sleep state (SLEEP_STATE) Stagnation Slow Auto Mode (SlowAuto_Mode) Sleep Hibernate Mode (Hibernate_Mode) Hibernation state (HIBERNATE_STATE) Hibernation (HIBERN8) Off Mode (Off_Mode) Shutdown state (OFF_STATE) Unpowered

[0049] In the UFS system, the physical adapter layer supports UniPro power modes for burst transmission. These include "Fast Auto Mode" (referred to as "FastAuto_Mode") and "Slow Auto Mode" (referred to as "SlowAuto_Mode"), which can be referred to as "auto modes," and "Fast Mode" (referred to as "Fast_Mode") and "Slow Mode" (referred to as "Slow_Mode"), which can be referred to as "non-auto modes."

[0050] According to the UniPro specification, an M-PHY burst (or burst transmission) is initiated by sending a de-skew pattern, wherein the de-skew pattern is, for example, a control symbol defined in the M-PHY specification, such as "<MK0, MK1> The control symbol MK0 serves as a marker for the start of an M-PHY burst. The skew-resistance pattern is also used for channel resynchronization. It must be sent simultaneously on all enabled channels. Although the skew-resistance pattern can be sent at any time, the physical adapter layer transmitter (PA transmitter, or PA TX) must maintain at least a certain distance between consecutive skew-resistance patterns sent on each channel while complying with proximity rules. This distance, for example, is 32 physical adapter layer protocol data units (PA_PDUs), which is equivalent to 64 symbol intervals (SIs). The physical adapter layer receiver (PA receiver, or PA RX) must be able to receive the skew-resistance pattern at any time.

[0051] In FastAuto_Mode, the link behaves in part like in Fast_Mode, but sometimes data arrives a little late because of the skew-proofing pattern transmitted at the start of data transmission during the transition from SLEEP_STATE to FAST_STATE.<MK0, MK1> The latency caused by starting a new burst is: SlowAuto_Mode is the equivalent mechanism of SLOW_STATE.

[0052] As mentioned above, the latency to start the next burst transmission in non-auto mode is shorter because the burst transmission is already started without the need to switch from SLEEP_STATE to FAST_STATE.<MK0, MK1> ) is only sent at the beginning of a burst transmission. During burst transmission, no skew patterns are used except in error conditions. In the event of an error, the UniPro specification mandates error recovery. During this error recovery process, the physical adapter layer is required to perform lane synchronization, which involves sending skew patterns.

[0053] During burst transmission in non-auto mode, after a period of time when the skew-resistance pattern is sent, clock phase shift or offset may cause skew between channels, leading to transmission errors. Consequently, the host and storage device may need to perform error recovery multiple times. Consequently, the more error recovery is performed, the lower the transmission performance between the host and storage device.

[0054] As described above, the inventors of this application observed technical issues regarding channel synchronization in interconnect protocols supporting multiple channels (such as the UFS standard). To address these technical issues, they proposed a technology for channel synchronization in interconnect protocols. This technology further proposes a mechanism that adaptively utilizes a periodic anti-skew pattern within the interconnect protocol to facilitate channel synchronization. This technology is applicable to a first device capable of connecting to a second device in accordance with the interconnect protocol. The first and second devices can be a host and a storage device, respectively, or vice versa.

[0055] To implement this mechanism, please refer to FIG3A , which is a schematic flow chart of an embodiment of a method for channel synchronization for an interconnection protocol. The method is applicable to a first device capable of connecting to a second device according to the interconnection protocol, and includes the following steps S10 and S20.

[0056] In step S10 , data representing an anti-skew interval is provided. The anti-skew interval represents a time interval between two consecutive periodic anti-skew patterns.

[0057] In step S20, a hardware protocol engine for implementing a link layer of the interconnect protocol, in response to communication status information between the first device and the second device during a burst transmission, adaptively transmits a periodic anti-skew pattern on a channel from the first device to the second device based on the anti-skew interval. The hardware protocol engine is configured to periodically transmit an anti-skew pattern based on the anti-skew interval when the communication status information meets a criterion for transmitting the periodic anti-skew pattern, and to delay transmitting the anti-skew pattern when the communication status information does not meet the criterion.

[0058] In a host or storage device, this mechanism can be implemented in circuitry that implements the interconnect protocol. For example, if the interconnect protocol is the UFS standard, this mechanism is applicable to circuitry that implements the physical adapter layer (e.g., 131 or 231), such as the controller of the host 10 (e.g., host controller 12 or protocol controller (PC1 or PC2)) or the controller of the storage device 20 (e.g., device controller 22 or protocol controller) in FIG1A .

[0059] Please refer to Figure 3B, which is a schematic circuit architecture diagram for implementing an embodiment of the method according to Figure 3A. This circuit architecture is used to implement the aforementioned mechanism and can be implemented in a hardware protocol engine (such as hardware protocol engine 13 of host 10 or hardware protocol engine 23 of storage device 20). The hardware protocol engine is used to implement a link layer of the interconnection protocol (such as the UniPro specification adopted by UFS; such as 130 or 230 in Figure 2), and is used to communicate with an interface circuit (such as 11 or 21 in Figure 1A) that implements a physical layer of the interconnection protocol (such as 110 or 210 in Figure 2). In addition to being implemented according to the UniPro specification, the hardware protocol engine can further include corresponding anti-skew request generation circuits 311 to facilitate the aforementioned mechanism. Optionally, the management information base 312 can be implemented within or outside the hardware protocol engine.

[0060] The anti-skew request generation circuit 311 is configured to respond to communication status information between the first and second devices during a burst transmission and adaptively transmit periodic anti-skew requests based on an anti-skew interval. When the anti-skew request generation circuit 311 determines that the communication status information meets a criterion, it periodically transmits an anti-skew request based on the anti-skew interval. When the anti-skew request generation circuit 311 determines that the communication status information does not meet the criterion, it delays transmitting the anti-skew request.

[0061] The management information base 312 is used to store the value of the anti-skew interval, where the anti-skew interval represents the time interval between two consecutive periodic anti-skew patterns.

[0062] The hardware protocol engine is further configured to transmit skew patterns on multiple lanes from the first device to the second device in response to a skew request sent by the skew request generation circuit 311, in accordance with the interconnect protocol. For example, in an interconnect protocol such as the UFS standard, circuitry implementing the link layer in accordance with the UniPro specification must be able to respond to skew requests and transmit corresponding skew patterns. For example, in the UniPro specification, a skew request must be generated at the beginning of a burst transmission to transmit a skew pattern. Another example is the PA_LANE_ALIGN.req primitive, which can be considered a skew request. The data link layer can generate this request to cause the physical adapter layer to perform lane synchronization, thereby transmitting a skew pattern within the physical adapter layer. Compared to the skew request required to be generated in accordance with the UniPro specification, the skew request sent by the skew request generation circuit 311 is generated during a burst transmission in response to communication status information and adaptively transmits periodic skew requests based on the skew interval.

[0063] In some embodiments, the communication status information detected by the anti-skew request generating circuit 311 includes, for example, a burst transmission indication signal and frame busy information.

[0064] In some embodiments, the determination criteria used by the anti-skew request generation circuit 311 include, for example: the burst transmission indication signal indicates that burst transmission is in progress, when the period according to the anti-skew interval is reached, and when the frame busy information indicates that no frame is being transmitted.

[0065] In some embodiments, the anti-skew request generating circuit 311 is configured to send the anti-skew request when it is determined that the burst transmission indication signal indicates that burst transmission is in progress, the period according to the anti-skew interval is reached, and the frame busy information indicates that no frame is being transmitted.

[0066] In some embodiments, the anti-skew request generating circuit 311 is configured to delay sending the anti-skew request when it is determined that the burst transmission indication signal indicates that burst transmission is in progress, a period of the anti-skew interval has been reached, and the frame busy information indicates that there is frame transmission.

[0067] In some embodiments, the anti-skew request generation circuit 311 is configured to determine, when the burst transmission indication signal indicates that burst transmission is in progress, the period according to the anti-skew interval has expired, and the frame busy information indicates that no frame transmission has occurred, further check whether the time interval between the current time and the time point at which the next period according to the anti-skew interval expires is greater than or equal to a minimum value to determine whether to send the anti-skew request. In some embodiments, the anti-skew request generation circuit 311 is configured to send the anti-skew request if the time interval is greater than or equal to the minimum value.

[0068] In some embodiments, the circuitry implementing the physical adapter layer may be configured to further adaptively utilize a periodic anti-skew pattern under an interconnect protocol to facilitate channel synchronization, thereby helping to reduce errors and improve transmission performance between the host and the device.

[0069] The following uses the UFS standard as an example to propose various implementation methods for this mechanism.

[0070] Please refer to Figure 3C , which is a schematic circuit architecture diagram of one embodiment of a circuit for implementing a physical adapter layer. Various examples can be derived based on Figure 3C . The circuit architecture shown in Figure 3C can be applied to a host's hardware protocol engine (such as 13 in Figures 1A, 1B, or 1C) or a storage device's hardware protocol engine (such as 23 in Figure 1A ), for example, to implement a physical adapter layer (such as 131 or 231 in Figure 2 ) in the hardware protocol engines of a host or storage device.

[0071] As shown in FIG3C , the physical adapter layer circuit 300 includes a physical adapter layer transmitter (PA TX) circuit 310 and a physical adapter layer receiver (PA RX) circuit 320. To provide a mechanism for adaptively utilizing periodic de-skew patterns to promote channel synchronization, the physical adapter layer transmitter (PA TX) circuit 310 of this embodiment includes a de-skew request generation circuit 311, which triggers a request to transmit the de-skew pattern. Furthermore, a specific management information base (MIB) 312 within the physical adapter layer transmitter (PA TX) circuit 310 can be used to store data (e.g., values) related to the de-skew interval, allowing the de-skew request generation circuit 311 to read and utilize the data.

[0072] Management Information Base (MIB) 312 is implemented using, for example, various suitable memory devices, such as volatile or non-volatile memory or registers. Alternatively, in one example, a controller (such as 12 or 22 in FIG. 1A ) or a protocol controller or other circuitry of host 10 (or storage device 20 ) can be configured to set the value of the anti-skew interval in MIB 312 , or firmware can set the value. Alternatively, the storage of the anti-skew interval value can be implemented outside of physical adapter layer circuitry 300 .

[0073] The physical adapter layer transmitter (PA TX) circuit 310 distributes symbol data from the data link layer (such as 132 or 232 in FIG. 2 ) to multiple enabled channels, processes the symbols according to the UniPro specification, and then transmits the processed symbols to the physical layer (such as 110 or 210 in FIG. 2 ). As shown in FIG. 3C , the physical adapter layer transmitter (PA TX) circuit 310 includes PA TX-related circuits implemented based on the UniPro specification, such as a PA layer protocol data unit (PA_PDU) processing unit 313, a PA layer control protocol (PACP) frame processing unit 314, a DL frame processing unit 315, a frame allocation unit 316, an idle frame insertion unit 317, a frame scrambling unit 318, and a frame remapping unit 319. The aforementioned units are implemented according to the operation of the physical adapter layer transmitter corresponding to the UniPro specification. In addition to generating the PA layer protocol data unit according to the operation of the PA layer corresponding to the UniPro specification, the PA_PDU processing unit 313 is further configured to respond to the anti-skew request generated by the anti-skew request generating circuit 311 according to the control symbol "<MK0, MK1> " to generate the PA layer protocol data unit, thereby generating the anti-skew pattern.

[0074] The physical adapter layer receiver (PA RX) circuit 320 combines symbol data from multiple enabled channels of the physical layer (e.g., 110 or 210 in FIG. 2 ), processes the symbols according to the UniPro specification, and then transmits the processed symbols to the data link layer (e.g., 132 or 232 in FIG. 2 ). As shown in FIG. 3C , the physical adapter layer receiver (PA RX) circuit 320 includes PA RX-related circuits implemented according to the UniPro specification, such as a frame anti-skew processing unit 321, a frame descrambling unit 322, an idle frame removal unit 323, a frame assembly unit 324, a DL frame processing unit 325, and a PACP frame processing unit 326. These units are implemented to operate in accordance with the UniPro specification for the physical adapter layer receiver.

[0075] Based on the embodiment of the physical adapter layer circuit architecture of FIG3C , the interconnect protocol can further implement adaptive utilization of a periodic de-skew pattern mechanism to promote channel synchronization. To this end, the following further defines the range of values ​​for the "de-skew interval" and the meaning of the values ​​under the UniPro specification. Please refer to Table 2, which defines a time interval parameter called the de-skew interval. Table 2 Attribute PA_Vendor_DeSkew_Interval (This refers to the PA vendor-specific "deskew interval") Attribute ID Vendor MIB (vendor-specific MIB, which can appropriately set the actual value of the ID according to the UniPro specification) describe In non-automatic mode, the time interval between two consecutive periodic anti-skew patterns; Time interval to send anti-bias patterns<MK0, MK1> Definition: 0: Default value, which means that the function of sending periodic anti-skew patterns is disabled; 1 to 65535: Send periodic anti-skew patterns based on this value Note: In fast mode, the minimum value of PA_Vendor_DeSkew_Interval is 1; In slow mode, the minimum value of PA_Vendor_DeSkew_Interval is 256. Type 16-bit word unit Microseconds (μs) Valid attribute values 0 to 65535 Reset value 0

[0076] As shown in Table 2, in this example based on the UniPro specification, a new management information base (MIB) attribute can be added to represent the "anti-skew interval." Specifically, the aforementioned "anti-skew interval" can be further defined and categorized as an attribute within the vendor-specific management information base (MIB) of the physical adapter layer in the UniPro specification. Therefore, as shown in Table 2, based on the UniPro specification's description of attributes, this example further defines the "anti-skew interval" attribute's name, attribute identifier, description, type, unit, valid attribute values, and reset value.

[0077] In the example in Table 2, the value of "Deskew Interval" is an integer. When the value of "Deskew Interval" (PA_Vendor_DeSkew_Interval) is zero, the mechanism for adaptively utilizing periodic deskew patterns is disabled. When the value of "Deskew Interval" is a non-zero value, the circuit architecture based on the physical adapter layer of Figure 3C can adaptively send periodic deskew patterns based on the value of the deskew interval to promote channel synchronization. For example, when the value of "Deskew Interval" is set to the minimum non-zero value of 1 (μs), the mechanism for adaptively utilizing periodic deskew patterns is enabled. This 1 μs interval complies with the aforementioned proximity rule, which requires that the distance between two consecutive deskew patterns sent on each channel be at least 32 PA_PDUs.

[0078] In the UniPro specification's DL_CreditUnit32 mode, the transport layer's maximum transfer unit (MTU) is 274 bytes. For example, 16 outstanding frames take up 16 * 274 * 8 * (10 / 8) * 0.801 ns (HSG1-A) = 35.115 μs. In the UniPro specification (UniPro 2.0)'s DL_CreditUnit128 mode, the transport layer's MTU is 1144 bytes. For example, 16 outstanding frames take up 16 * 1144 * 8 * (10 / 8) * 0.801 ns (HSG1-A) = 146.615 μs. Based on the above calculations, the range of the "anti-skew interval" value (1 μs to 65535 μs) should be effective. The appropriate anti-skew interval value can be set to perform periodic anti-skew pattern transmission without frequently interfering with the data link layer frame.

[0079] In addition, to ensure that the distance between two adjacent deskew patterns in the same channel meets the proximity rule, as shown in Table 2, the minimum value of PA_Vendor_DeSkew_Interval is 1 in fast mode and 256 in slow mode. This minimum value can be considered the period threshold of the deskew interval.

[0080] Of course, when implementing the aforementioned techniques and mechanisms, the "anti-skew interval" can be appropriately defined and implemented based on the interconnection protocol used (such as UFS or other similar protocols). Therefore, the implementation of the present disclosure is not limited to the above examples.

[0081] As previously described, with regard to adaptively transmitting periodic anti-skew requests, for example, the physical adapter layer transmitter (PA TX) circuit 310 or the anti-skew request generation circuit 311 can be configured to detect information indicating the communication status between the first device and the second device (e.g., including one or more related signals (or parameters)). When the physical adapter layer transmitter (PA TX) circuit 310 or the anti-skew request generation circuit 311 determines that the information meets the criteria for allowing the transmission of an anti-skew request, the anti-skew request is transmitted. When the physical adapter layer transmitter (PA TX) circuit 310 or the anti-skew request generation circuit 311 determines that the communication status information does not meet the criteria, the anti-skew request is transmitted at a later time or a specific anti-skew request is canceled. To this end, the following further illustrates how to adaptively transmit periodic anti-skew patterns and their timing, based on the UniPro specification. Furthermore, the following further illustrates the "communication status" information and the "determination criteria" that the anti-skew request generation circuit 311 needs to detect.

[0082] For example, according to the UniPro specification, a deskew pattern must be sent in the following situations: in non-automatic mode, at the beginning of a burst transmission, and during error recovery. According to some embodiments of the present invention, periodic deskew transmission is further performed based on the aforementioned "deskew interval" (PA_Vendor_DeSkew_Interval) to compensate for the absence of a deskew pattern during a burst transmission and prevent errors. Therefore, during the aforementioned burst transmission, periodic deskew transmission based on the aforementioned "deskew interval" can be performed, as shown in the timing diagrams of Figures 4A through 4D.

[0083] The embodiment shown in FIG4A is Scenario 1, which is a general case of sending a periodic deskewing pattern. The physical adapter layer can be implemented by setting the TX_Burst signal to the active state (e.g., at time point T1) to indicate that the TX_Symbol signal is about to start burst transmission, and sending a periodic deskewing pattern (e.g., at time points T1, T2 to T5) every deskewing interval (PA_Vendor_DeSkew_Interval) after the burst transmission starts.<MK0,MK1> ) (as represented by DW in the figure) until the TX_Burst signal is set to the inactive state (de-asserted) due to the MK2 control symbol (as represented by DWE) defined in the M-PHY specification, thereby turning off the burst transmission. Scenario 1 uses a periodic anti-skew pattern as a pilot signal to synchronize the channel between the local device (such as a host) and the counterpart device (such as a storage device). Since no frame is transmitted at each time the period according to the anti-skew interval is reached, such as at time points T1, T2 to T5, such as the case where a PACP frame (as represented by FP) or a DL frame (as represented by FD) is transmitted, when the TX_Burst signal is in the active state, the anti-skew pattern (as represented by<MK0,MK1> ) (as represented by DW in the figure) is sent periodically.

[0084] The embodiment shown in FIG4B is Scenario 2, which illustrates the periodic anti-skew pattern and the PACP frame or DL ​​frame. When the time to send the periodic anti-skew pattern arrives, such as when a PACP frame is being transmitted at time T2 or a DL frame is being transmitted at time T4, the physical adapter layer can be implemented to delay sending the anti-skew pattern until after the PACP frame (e.g., at time T2) or the DL frame (e.g., at time T4) has been transmitted. At time T3, since there are no frames to be transmitted, the anti-skew pattern is sent. Furthermore, the time interval between two consecutive periodic anti-skew patterns should be greater than 64 symbol intervals (SIs), for example, the time interval between the anti-skew pattern at time T3 (or T5) and its immediately preceding anti-skew pattern (e.g., TL1 and TL2 shown in FIG4B ).

[0085] The embodiment shown in Figure 4C is Scenario 3, which illustrates an example of back-to-back PACP and DL frames at time points T2 and T3 (following the UniPro pause / resume scheme). At time point T2, the PACP and DL frames are already being transmitted. The physical adapter layer can be implemented to delay sending the anti-skew pattern until after the PACP and DL frames have completed transmission. At time point T3, since no other frames are being transmitted, the anti-skew pattern is sent. Furthermore, the time interval between two consecutive anti-skew patterns should be greater than 64 symbol intervals (SIs), for example, the time interval between the anti-skew pattern at time point T3 and the previous anti-skew pattern (TL3 shown in Figure 4C).

[0086] The embodiment shown in Figure 4D is Scenario 4, another example in which PACP frames and DL frames are sent back-to-back at time points T2 and T3 (following the UniPro pause / resume scheme). Compared to Figure 4C , where there is still sufficient time interval between the PACP frame at time point T2 and the subsequent DL frame and time point T3 to transmit the anti-skew pattern, the PACP frame at time point T2 and the subsequent DL frame in Figure 4D take up more time, resulting in a remaining time interval (TL4 in Figure 4D) of less than 64 SIs until time point T3. Therefore, there is insufficient time to transmit the anti-skew pattern originally scheduled for time point T2. Therefore, the physical adapter layer can be implemented to send the anti-skew pattern at time point T3 instead, without sending (or canceling) the anti-skew pattern originally scheduled for time point T2.

[0087] Furthermore, during error recovery (e.g., link reinitialization via the UniPro specification's PA_INIT primitive, power mode change request via the PACP_PWR_req frame, or power mode change confirmation via the PACP_PWR_cnf frame), the Reference M-PHY Module Interface (RMMI) burst is disabled, and a new burst is issued at the next transmission. When bursting is disabled, periodic anti-skew patterns are disabled or delayed until the PACP frame transmission is complete. Furthermore, the time interval between two consecutive anti-skew patterns must be greater than 64 symbol intervals (SIs).

[0088] In some embodiments, the physical adapter layer transmitter (PA TX) circuit 310 or the anti-skew request generation circuit 311 of FIG. 3C may be configured to adaptively utilize a periodic anti-skew pattern, thereby implementing the scenarios of various embodiments shown in the timing diagrams of FIG. 4A to FIG. 4D .

[0089] Please refer to Figure 5, which is a block diagram of one embodiment of the anti-skew request generation circuit in Figure 3C. As shown in Figure 5, anti-skew request generation circuit 500 includes a first anti-skew request circuit 501 and a second anti-skew request circuit 502. The first anti-skew request circuit 501 is configured to send an anti-skew request (referred to as the first anti-skew request in Figure 5) at the beginning of a burst transmission or when an error recovery occurs, in accordance with an interconnect protocol (such as the link layer of the UFS standard, i.e., the UniPro specification), thereby triggering the transmission of an anti-skew pattern. The second anti-skew request circuit 502 is configured to adaptively send an anti-skew request in a periodic anti-skew pattern (referred to as the second anti-skew request in Figure 5), thereby triggering the transmission of the anti-skew pattern. In implementation, the signal output by anti-skew request generation circuit 500 is, for example, implemented as an anti-skew request signal, and the anti-skew request is indicated by the anti-skew request signal being asserted or having a pulse.

[0090] As shown in FIG5 , the PA_PDU processing unit 313 receives the anti-skew request sent by the anti-skew request generation circuit 500. For the PA_PDU processing unit 313, the first anti-skew request or the second anti-skew request sent by the anti-skew request generation circuit 500 is the pulse in the anti-skew request signal output by the anti-skew request generation circuit 500. The PA_PDU processing unit 313 is used to respond to the anti-skew request by inserting an anti-skew pattern, for example, inserting the anti-skew pattern (<MK0, MK1> ) is inserted into the PA layer protocol data unit (PA_PDU) and output to the frame allocation unit 316 for further processing according to the UniPro specification.

[0091] In FIG5 , an anti-deviation request generation circuit 500 detects information representing the communication status between a first device and a second device (e.g., including one or more related signals (or parameters)) and determines whether the communication status information meets a criterion for sending an anti-deviation request, thereby adaptively sending the anti-deviation request.

[0092] For example, the first anti-skew request circuit 501 detects the TX_Burst signal and information about the error recovery condition to determine whether to send the first anti-skew request at the beginning of a burst transmission or when an error recovery condition occurs.

[0093] For example, the second de-skew request circuit 502 detects the TX_Burst signal, frame busy information, and error recovery status information, and adaptively sends periodic de-skew requests during burst transmission based on the aforementioned "de-skew interval" and the reference clock signal. The frame busy information, for example, includes a DL frame or PACP frame request signal (e.g., a frame or corresponding signal transmitted via a primitive in the UniPro specification) or corresponding information. The presence of such a frame request signal indicates a frame busy condition. The error recovery status information, for example, includes the aforementioned signals or information related to error recovery, such as the request for channel synchronization at the PA layer via the UniPro specification PA_LANE_ALIGN.req primitive, link reinitialization via the PA_INIT primitive, power mode change request via the PACP_PWR_req frame, or power mode change confirmation via the PACP_PWR_cnf frame. In one embodiment, the second anti-skew request circuit 502 may include an anti-skew interval check unit 521, a frame busy check unit 523, a minimum distance check unit 525, and a logic unit 527. Each of the above units (e.g., 521, 523, 525) determines whether the corresponding communication status information (e.g., including one or more related signals (or parameters) or corresponding primitives or corresponding signals in the UniPro specification) meets corresponding criteria based on the corresponding communication status information, and outputs a corresponding check result signal.

[0094] The skew-checking unit 521 is configured to output a first check result signal based on judgment criterion 1. Judgment criterion 1 can be described as follows: the burst transmission indication signal is asserted (e.g., the TX_Burst signal = 1'b1 in the RMMI of the UniPro specification (expressed in Verilog)) and the period of the periodic skew-checking pattern, which corresponds to the "skew-checking interval," has been reached. If judgment criterion 1 is met, the first check result signal is asserted; otherwise, the first check result signal is de-asserted. Furthermore, the skew-checking unit 521 needs to obtain the "skew-checking interval," which can be achieved in a variety of ways. For example, an anti-skew interval timer 530 may be provided that reads the anti-skew interval value or data from the management information base (MIB) 312 and outputs an anti-skew interval count signal accordingly. The anti-skew interval check unit 521 receives the anti-skew interval count signal and a reference clock signal and determines when the period of the periodic anti-skew pattern based on the anti-skew interval has reached. The anti-skew interval count signal, for example, represents a signal that counts down from the value based on the anti-skew interval to zero (e.g., if the anti-skew interval value is A, the countdown starts from A-1, A-2, ..., 1, 0). The reference clock signal may be a pulse wave with a period of each unit time (e.g., 1 μs). In another example, the de-skew interval check unit 521 can also be implemented to, when the burst transmission indication signal is active, set the first check result signal to an active state, such as by sending a pulse, when the de-skew interval count signal indicates that the de-skew interval count signal has finished counting down to 0 and is about to restart from A-1, thereby indicating that the de-skew interval period has expired. Otherwise, the first check result signal is set to an inactive state. For ease of explanation, the first check result signal can be referred to as a de-skew interval request signal (e.g., denoted as De-Skew_Interval_Request), as shown in FIG6 or FIG7 .

[0095] The frame busy check unit 523 is configured to output a second check result signal based on judgment criterion 2. Judgment criterion 2 can be described as follows: if no other frames, such as PACP frames or DL ​​frames, are being transmitted, the second check result signal is set to an active state; when a PACP frame or DL ​​frame is being transmitted, the transmission of the anti-skew pattern is postponed. The PACP frame or DL ​​frame may be sent under normal circumstances or due to error recovery. If judgment criterion 2 is met, the second check result signal is set to an active state; otherwise, the second check result signal is set to an inactive state, indicating a frame busy state. In another example, the frame busy check unit 523 can also be implemented to set the second check result signal to an active state when a PACP frame or DL ​​frame is being transmitted; otherwise, the second check result signal is set to an inactive state. For convenience of explanation, the second check result signal can be referred to as a frame busy signal, which indicates whether a PACP frame or DL ​​frame is being transmitted, as shown in Figures 6 or 7.

[0096] Minimum distance check unit 525 is configured to output a third check result signal based on judgment criterion 3. Judgment criterion 3 can be described as a minimum distance requirement of at least 32 PA_PDUs (64 symbol intervals (SIs)) between consecutive de-skew patterns transmitted on each channel. If judgment criterion 3 is met, the third check result signal is set to an active state; otherwise, the third check result signal is set to an inactive state. In another example, minimum distance check unit 525 can also be implemented to set the third check result signal to an active state during the last minimum distance (e.g., 32 PA_PDUs) interval in each period based on the de-skew interval; otherwise, the third check result signal is set to an inactive state. For this purpose, the third check result signal can also be referred to as a minimum distance mask signal (also referred to as Minimum_Distance_Mask), as shown in FIG6 or FIG7.

[0097] In this embodiment, the minimum distance time for Fast Mode (or corresponding to M-PHY's High-Speed ​​Mode (HS Mode)) is designed to be 1 μs. For the lowest M-PHY HS-G1A, each bit period is 801 ps (corresponding to 1 / 1248 Mbps). The time per symbol in the sequencer / deserializer (SERDES) channel is 10 bits * 0.801 ns = 8.01 ns. The time for 64 symbol intervals (SIs) is 64 * 8.01 ns = 512 ns. Therefore, in this embodiment, the minimum distance time is set to 1 μs to meet the proximity rule (maintaining a distance of 32 PA_PDUs (64 SIs)). This minimum distance time is sufficient for higher data rates. The above calculations are for High-Speed ​​Mode (HS) rates. For M-PHY's low-speed (LS) rate (corresponding to pulse-width modulation (PWM) mode), the minimum distance to be checked in LS is 256 μs (64 * 10 bits * (1 / 3 Mbps) = 213.12 μs), rather than the 1 μs value in HS. Therefore, the deskew interval (PA_Vendor_DeSkew_Interval) can be determined and programmed by the application layer, for example, through a procedure, to meet proximity rules. Furthermore, the minimum deskew interval value can be implemented by defining additional attributes in the Management Information Base (MIB). For example, in addition to setting the "deskew interval" value in MIB 312, the minimum values ​​for high-speed mode and low-speed mode can also be set.

[0098] Logic unit 527 adaptively sends a periodic de-skew request based on the first, second, and third check result signals. For example, logic unit 527 utilizes logic circuits such as an AND gate, an OR gate, a NOT gate, or a combination of other gates, or any other suitable circuitry to implement the determination operation. In one embodiment, logic unit 527 can be configured to send a de-skew request when the first, second, and third check result signals indicate that all of the above determination criteria 1, 2, and 3 are satisfied. In another embodiment, logic unit 527 can be configured to send a de-skew request when the de-skew interval request signal (De-Skew_Interval_Request) is active, the frame busy signal is inactive, and the minimum distance mask signal (Minimum_Distance_Mask) is inactive. Furthermore, if the de-skew interval request signal is active, but either the frame busy signal or the minimum distance mask signal, or both, are active, then no de-skew request is sent. The logic unit 527 indicates the anti-skew request by, for example, sending a pulse or setting an output signal to an active state.

[0099] Furthermore, when the TX_Burst signal is turned off by the MK2 control symbol and the anti-skew pattern is being transmitted simultaneously, the anti-skew pattern is terminated. Specifically, when the TX_Burst signal changes to a deasserted state, burst transmission ceases, and the transmission of the periodic anti-skew pattern is also terminated. For example, the anti-skew interval check unit 521 may output a deasserted first check result signal to indicate this.

[0100] Based on the "deskew interval" and "determination criteria" described in the aforementioned embodiments, the second skew reduction request circuit 502 can transmit a periodic skew reduction pattern in non-automatic mode to prevent loss of channel synchronization, particularly in multi-channel scenarios. By adaptively sending skew reduction requests for periodic skew reduction patterns, the chance of error recovery caused by channel synchronization issues in non-automatic mode is reduced, thereby improving burst transmission efficiency.

[0101] Please refer to Figure 6, which is a schematic timing diagram of one embodiment of the anti-skew request generation circuit in Figure 5. Figure 6 illustrates the general situation of transmitting a periodic anti-skew pattern, as described in Scenario 1 above. In Figure 6, the top waveform represents the symbol clock (e.g., the symbol clock of the TX RMMI). At time T1, the TX sends an anti-skew request because the TX_Burst signal is asserted, indicating the start of burst transmission. Subsequently, when each period corresponding to the anti-skew interval is reached, an anti-skew request is sent, such as at times T5 and T8. In Figure 6, the frame busy signal indicates whether a PACP frame or DL ​​frame is busy. Since the frame busy signal is inactive from times T1 to T8, indicating that no PACP frame or DL ​​frame is busy, anti-skew requests can be sent at times T5 and T8.

[0102] In one embodiment, two counters can be implemented to facilitate the implementation of the deskew interval check unit 521 and the minimum distance check unit 525. Each time the TX_Burst signal is asserted, both counters are reloaded with the value of the deskew interval (PA_Vendor_DeSkew_Interval). The two counters continue to operate until the TX_Burst signal is deasserted.

[0103] For example, the two counters are called the de-skew interval check counter and the minimum distance check counter. The de-skew interval check counter decrements from PA_Vendor_DeSkew_Interval - 1 to 0 every 1 μs, and then repeats this decrementing operation until the TX_Burst signal is turned off. The count signal output by the de-skew interval check counter can be recorded as "De-Skew_Interval_Counter."

[0104] The minimum distance counter decrements from the value of PA_Vendor_DeSkew_Interval – 1 to a minimum value (e.g., 1 for fast mode, or 256 for slow mode) every 1 μs. It maintains this value until the next pulse of the de-skew interval request signal (e.g., De-Skew_Interval_Request) is issued, and the decrementing operation repeats. The minimum distance counter outputs a count signal denoted as "Minimum_Distance_Counter." When the minimum distance counter reaches the minimum value (denoted by MIN in Figures 6 and 7), the minimum distance mask signal (Minimum_Distance_Mask) is asserted (e.g., between time T4 and T5) to disable the transmission of the de-skew pattern until the next pulse of the De-Skew_Interval_Request signal is issued.

[0105] For example, the anti-deviation interval check counter may be implemented in the anti-deviation interval check unit 521. For another example, the minimum distance counter may be implemented in the minimum distance check unit 525.

[0106] Please refer to Figure 7, which is a schematic timing diagram of another embodiment of the anti-skew request generation circuit in Figure 5. Figure 7 illustrates the case of a busy frame when transmitting periodic anti-skew patterns, as described in Scenarios 2-4 above. In Figure 7, at time T1, a anti-skew request is issued because the TX_Burst signal is asserted, indicating the start of burst transmission. From time T3 to T7, the frame busy signal is asserted, indicating a busy frame, such as a PACP frame or DL ​​frame being transmitted. The anti-skew request is configured to be issued at each period based on the anti-skew interval, but its issuance is delayed due to a busy frame at time T5. At time T7, the frame busy signal becomes de-asserted. However, because the time interval between time T7 and the next scheduled anti-skew request time T8 is less than the minimum distance (e.g., less than 1 μs), the minimum distance check is not met and the request is masked (or cancelled). Then, at time point T8, a de-skew request is issued according to the de-skew interval, wherein no PACP frame or DL ​​frame is busy.

[0107] Furthermore, in some embodiments, interconnect protocol applications (such as the UniPro application layer) can combine periodic deskew patterns with Quality of Service (QoS) monitoring. The application can dynamically adjust the deskew interval (PA_Vendor_Deskew_Interval). When channel quality deteriorates, such as when the error rate increases, the deskew interval can be reduced. This allows both the host and device to synchronize faster in non-automatic mode. If channel quality cannot be improved or the deskew interval cannot be reduced, the application may report a critical error.

[0108] In some embodiments of the controller or storage device, the controller or storage device is further configured to dynamically adjust the value of the anti-skew interval according to an indication signal of the link layer regarding the quality of service when the anti-skew interval is greater than a minimum allowed value.

[0109] Figures 8 and 9 are schematic flow charts illustrating some embodiments of adaptively utilizing skew-resistant patterns. For example, UniPro version 1.8 and later specifications provide for link Quality of Service (QoS) functionality. The UniPro link layer communicates with the M-PHY via the RMMI, independently monitoring both the forward and reverse links. When QoS functionality is enabled, circuits implemented in accordance with the UniPro specification can provide QoS records, such as the symbol count within a desired time window during transmission and the number of error events. QoS parameters, such as the corresponding error event threshold, can be programmed by the application. When the number of error events reaches the threshold, the UniPro circuitry notifies the application layer, for example by sending a DME_QOS.ind primitive, to notify the application layer that the threshold has been reached.

[0110] As shown in FIG8 , one embodiment of adaptively utilizing a de-skew pattern includes multiple operations for dynamically adjusting the de-skew interval. These operations include: in step S50 , in response to the indication signal (e.g., via the aforementioned DME_QOS.ind) indicating that the error event threshold has been reached, determining whether the value of the de-skew interval is greater than the minimum allowable value. In step S60 , if the de-skew interval is greater than the minimum allowable value, changing the value of the de-skew interval from a first value to a second value, wherein the second value is less than the first value and greater than or equal to the minimum allowable value.

[0111] In some examples, the host 10 or storage device 20 can be configured to perform the operations shown in FIG. 8 and to cooperate with the method of FIG. 3A to dynamically facilitate channel synchronization. The operations of FIG. 8 can be implemented by configuring logic circuitry corresponding to the operations of FIG. 8 in a hardware protocol engine of the host 10 or storage device 20. The logic circuitry can be coupled to a device management entity (DME) (135 or 235) to obtain the indication signal. The logic circuitry can utilize primitives or service access points (SAPs) provided by a DME implemented in accordance with the UniPro specification to obtain parameters or information related to the Quality of Service (QoS) function, such as the indication signal.

[0112] Furthermore, the operation of Figure 8 can also be implemented in the host 10 or storage device 20 using firmware or software. In the embodiment of Figure 9, an application can be used to dynamically adjust the value of the deskew interval (PA_Vendor_DeSkew_Interval). Figure 9 is described from the perspective of an application. This application can be implemented in firmware in the host or storage device, for example, executed by the processing unit 14 of the host 10 or the processing unit 24 of the storage device 20. The circuitry implemented according to the UniPro specification provides Quality of Service (QoS) functionality, for example, by the hardware protocol engine 13 of the host 10 or the hardware protocol engine 23 of the storage device 20. This allows the hardware circuitry and firmware (e.g., the application) to work together and coordinate with each other, providing a more flexible implementation for dynamically adjusting the deskew interval, thereby enhancing channel synchronization and improving transmission performance.

[0113] In step S100, an application is executed to process the quality of service (QoS) application.

[0114] In step S110, it is checked whether the Quality of Service (QoS) function is enabled. If the function is enabled, step S120 is further executed. Otherwise, the system waits in the original state to determine whether the function is enabled.

[0115] In step S120, if the Quality of Service (QoS) function is enabled, a determination is made as to whether a DME_QoS.ind primitive indicating that the number of error events has reached an error threshold has been received. If such a primitive is received, step S130 is executed. Otherwise, the determination as to whether such a primitive has been received is awaited in the current state.

[0116] In step S130, it is determined whether the deskewing interval (PA_Vendor_DeSkew_Interval) is greater than the minimum allowed value (as described in Table 2). If so, step S140 is further executed; if not, the process returns to step S100, where the deskewing interval value is no longer adjustable.

[0117] In step S140, if the deskewing interval (PA_Vendor_DeSkew_Interval) is greater than the minimum value, the deskewing interval is adjusted, such as by decreasing its value. After adjusting the deskewing interval, as shown in FIG9 , the process returns to step S100 . Alternatively, other appropriate operations may be performed based on actual needs.

[0118] Thus, when the Quality of Service (QoS) monitoring function is enabled (which can correspond to inbound, outbound, or PA_INIT), the application waits for DME_QoS.ind. If DME_QoS.ind is set as asserted, the application can reduce the value of the PA_Vendor_DeSkew_Interval until the value of the PA_Vendor_DeSkew_Interval is reduced to the minimum value (a minimum of 1 in fast mode and a minimum of 256 in slow mode).

[0119] In one example of step S140 (or step S60), in fast mode, at the start of a burst transmission, the deskew interval (PA_Vendor_DeSkew_Interval) is set to 1000. After the application receives DME_QoS.ind, it notifies the PA layer (131 or 231 in FIG. 2; 300 in FIG. 3C) via the DME primitive (e.g., 135 or 235 in FIG. 2). The PA layer (e.g., 300 or 310 in FIG. 3C) changes the deskew interval value stored in the management information base (MIB) 312 to 500. If the application receives DME_QoS.ind again, the PA layer (e.g., 300 or 310 in FIG. 3C) can further reduce the deskew interval value (e.g., to 450, 400, 350, 300, and so on). The application can repeat this process until the deskew interval value reaches a minimum value (e.g., 1). In another example, in slow mode, similar operations can be performed, but the minimum value is 256.

[0120] Furthermore, in one example, after QoS is enabled and the value of PA_Vendor_DeSkew_Interval is dynamically reduced, the application calculates the error rate using the symbol count and the number of error events within a desired time window to determine whether the error rate has decreased.

[0121] In some embodiments of step S140 (or step S60), the anti-skew interval adjustment method can be determined based on the change in the error rate. For example, the adjustment method can be configured such that the reduction in the anti-skew interval is positively correlated with the reduction in the error rate. For example, when the error rate increases, the anti-skew interval is reduced (or shortened), thereby reducing the error rate.

[0122] In some embodiments of step S140 (or step S60), after adjusting the anti-skew interval, a determination may be made as to whether to adjust the anti-skew interval again based on the change in the error rate. For example, if the application monitors a decrease in the error rate after reducing the anti-skew interval, the adjustment is effective. If the error rate has not yet reached the desired value, the anti-skew interval may be further reduced. For another example, if the error rate does not decrease or decreases only slightly after reducing the anti-skew interval (e.g., once or multiple times), this indicates that the error rate is not a factor in the anti-skew issue, and the anti-skew interval may be determined to be unnecessary.

[0123] Thus, the above-mentioned embodiments based on Figures 8, 9 or related embodiments illustrate that, on the basis of adaptively sending a periodic anti-deviation pattern (such as based on Figure 3A or its embodiments), further dynamically adjusting the value of the anti-deviation interval can avoid the loss of channel synchronization, and this technology that helps to improve transmission quality is feasible.

[0124] Additionally, in this disclosure, "asserting" (or alternatives such as "asserted" or "assertion") a signal means that the signal is set to its active state (or active voltage level), which can be high or low. "De-asserting" (or alternatives such as "de-asserted" or "de-assertion") a signal means that the signal is set to its inactive state (or inactive voltage level), which can be high or low. If a signal has an active-low state (active-low), then "asserting" the signal means setting the signal to a low level, while "de-asserting" the signal means setting the signal to a high level. If a signal has an active-high state (active-high), then "asserting" the signal means setting the signal to a high level, while "de-asserting" the signal means setting the signal to a low level.

[0125] Furthermore, in the aforementioned embodiments regarding a host and a storage device, the hardware protocol engine in the host controller or device controller can be designed using a hardware description language (HDL) such as Verilog or any other digital circuit design method familiar to those skilled in the art. The design can be implemented using one or more circuits such as a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a complex programmable logic device (CPLD), or using a dedicated circuit or module. The host controller or device controller (or the processing unit or hardware protocol engine therein) can also be implemented using a microcontroller, a processor, or a digital signal processor.

[0126] As described above, various embodiments of the technology for channel synchronization of interconnection protocols are provided, such as a method, a controller, and a storage device for channel synchronization of interconnection protocols.

[0127] The present invention has been disclosed above through various embodiments. However, those skilled in the art should understand that these embodiments are merely illustrative of the present invention and should not be construed as limiting its scope. It should be noted that all equivalent variations and substitutions to these embodiments are intended to fall within the scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the patent applications.

[0128] 1: Storage system 10: Host 11: Host interface 12: Host Controller 13: Hardware Protocol Engine 14: Processing unit 16: Application Processor 20: Storage device 21: Device Interface 22: Device controller 23: Hardware Protocol Engine 24: Processing unit 26: Storage Module 110: Physical layer 111: Transmitter 112: Receiver 130:MIPI Unified Protocol (UniPro) layer 131: Physical Adapter Layer 132: Data Link Layer 133: Network Layer 134: Transport layer 135: Device Management Entity 210: Physical layer 211: Transmitter 212: Receiver 230:MIPI Unified Protocol (UniPro) layer 231: Physical Adapter Layer 232: Data Link Layer 233: Network Layer 234: Transport layer 235: Device Management Entity 300: Physical adapter layer circuit 310: Physical adapter layer transmitter circuit 311: Anti-deviation request generation circuit 312: Management Information Database 313:PA_PDU processing unit 314:PACP frame processing unit 315: DL frame processing unit 316: Frame Allocation Unit 317: Frame idle insertion unit 318: Frame mixing unit 319: Frame remapping unit 320: Physical adapter layer receiver circuit 321: Frame anti-deviation processing unit 322: Frame Decoding Unit 323: Frame Idle Removal Unit 324: Frame assembly unit 325:DL frame processing unit 326:PACP frame processing unit 500: Anti-deviation request generation circuit 501: First anti-deviation request circuit 502: Second anti-deviation request circuit 521: Anti-deviation interval inspection unit 523: Frame busy check unit 525: Minimum distance check unit 527:Logical Unit 530: Anti-deviation interval timer S10~S20: Steps S50~S60: Steps S100~S140: Steps PC1, PC2: protocol controller CLK: clock line Din, Dout: data line RST: Reset line SL1: Data Channel SL2: Data Channel DW: Anti-deviation type DWE:MK2 control symbols FP:PACP frame FD:DL frame TL1, TL2, TL3, TL4: time interval De-Skew_Interval_Request: De-Skew interval request signal De-Skew_Interval_Counter: De-Skew interval check counter output count signal Minimum_Distance_Counter: The counting signal output by the minimum distance counter Minimum_Distance_Mask: Minimum distance mask signal MIN: minimum value

Claims

1. A method for channel synchronization for an interconnection protocol, applicable to a first device capable of linking a second device according to the interconnection protocol, the method comprising the steps of: providing data representing a misalignment interval, the misalignment interval representing a time interval between two consecutive periodic misalignment patterns; and, by means of a hardware protocol engine for implementing the interconnection protocol, responding to communication status information between the first device and the second device during a transmission process and according to the misalignment interval, adaptively transmitting a periodic misalignment pattern on the channel from the first device to the second device, wherein the hardware protocol engine is configured to periodically transmit a misalignment pattern according to the misalignment interval when the communication status information meets a criterion for transmitting a periodic misalignment pattern, and to delay transmitting the misalignment pattern when the communication status information does not meet the criterion; The communication status information includes a burst transmission indication signal and frame busy information; the determination criteria include: the burst transmission indication signal indicating that burst transmission is in progress, the period of the anti-misalignment interval being reached, and the frame busy information indicating that no frame is being transmitted; wherein the hardware protocol engine is configured to send the anti-misalignment pattern when the burst transmission indication signal indicates that burst transmission is in progress, the period of the anti-misalignment interval being reached, and the frame busy information indicating that no frame is being transmitted.

2. The method for channel synchronization of an interconnection protocol as described in claim 1, wherein the hardware protocol engine is configured to delay sending the anti-misalignment pattern when the cluster transmission indication signal indicates that the cluster transmission is in progress, the period of the anti-misalignment interval is reached, and the frame busy information indicates that there is frame transmission.

3. The method for channel synchronization of an interconnection protocol as described in claim 1, wherein the hardware protocol engine is configured to, when determining that the cluster transmission indication signal indicates that the cluster transmission is in progress, the period according to the anti-misalignment interval has been reached, and the frame busy information indicates that there is no frame transmission, further check whether the time interval between the current time point and the time point at which the next period according to the anti-misalignment interval is reached is greater than or equal to a minimum value to determine whether to send the anti-misalignment pattern.

4. The method for channel synchronization of an interconnection protocol as described in claim 3, wherein the hardware protocol engine is configured to send the anti-bias pattern if the time interval is greater than or equal to the minimum value.

5. The method for channel synchronization for an interconnection protocol as described in claim 1, wherein the interconnection protocol is the Universal Flash Storage (UFS) standard.

6. A controller adapted in a first device capable of linking a second device according to an interconnection protocol, the controller comprising: An interface circuit is used to implement a physical layer of the interconnection protocol to link the second device; The system also includes a hardware protocol engine coupled to the interface circuit and serving as a link layer for implementing the interconnection protocol. The hardware protocol engine is configured to respond to communication status information between the first device and the second device during a burst transmission and adaptively transmit periodic anti-misalignment patterns on the channel from the first device to the second device according to an anti-misalignment interval, wherein the anti-misalignment interval represents the time interval between two consecutive periodic anti-misalignment patterns. The hardware protocol engine is configured to periodically transmit an anti-misalignment pattern according to the anti-misalignment interval when the communication status information meets a criterion for transmitting the periodic anti-misalignment pattern, and to delay transmitting the anti-misalignment pattern when the communication status information does not meet the criterion. The communication status information includes a burst transmission indication signal and frame busy information. The criterion includes: the burst transmission indication signal indicating that burst transmission is in progress; the period according to the anti-misalignment interval being reached; and the frame busy information indicating that no frame is being transmitted. The hardware protocol engine is configured to send the anti-misalignment pattern when the burst transmission indication signal indicates that the burst transmission is in progress, when the anti-misalignment interval period is reached, and when the information of the busy frame indicates that no frame is being transmitted.

7. The controller as claimed in claim 6, wherein the hardware protocol engine is configured to delay sending the anti-misalignment pattern when the burst transmission indication signal indicates that the burst transmission is in progress, the period of the anti-misalignment interval is reached, and the frame busy information indicates that there is frame transmission.

8. The controller as described in claim 6, wherein the hardware protocol engine is configured to, when the cluster transmission indication signal indicates that the cluster transmission is in progress, the period according to the anti-misalignment interval is reached, and the frame busy information indicates that there is no frame transmission, further check whether the time interval between the current time point and the time point at which the next period according to the anti-misalignment interval is reached is greater than or equal to a minimum value to determine whether to send the anti-misalignment pattern.

9. The controller as described in claim 8, wherein the hardware protocol engine is configured to send the anti-bias pattern if the time interval is greater than or equal to the minimum value.

10. The controller as described in claim 6, wherein the controller further comprises: An anti-misalignment request circuit, disposed in the hardware protocol engine, is used to respond to communication status information between the first device and the second device during a transmission process and adaptively transmit periodic anti-misalignment requests according to the anti-misalignment interval. When the anti-misalignment request circuit determines that the communication status information meets the judgment criterion, the anti-misalignment request circuit periodically sends an anti-misalignment request according to the anti-misalignment interval; when the anti-misalignment request circuit determines that the communication status information does not meet the judgment criterion, the anti-misalignment request circuit delays the transmission of the anti-misalignment request. The hardware protocol engine is configured to transmit the anti-misalignment pattern on the channel from the first device to the second device in response to the anti-misalignment request.

11. The controller as described in claim 6, wherein the controller further comprises: A processing unit coupled to the hardware protocol engine is configured to dynamically adjust the value of the anti-misalignment interval based on an indication signal regarding quality of service from the link layer when the anti-misalignment interval exceeds a minimum permissible value.

12. The controller as claimed in claim 11, wherein the processing unit is configured to perform a plurality of operations to dynamically adjust the anti-deviation interval, the operations including: When the threshold value for notifying an error event has been reached in response to the indication signal, determine whether the value of the anti-deviation interval is greater than the minimum allowable value; And when the anti-deviation interval is greater than the allowable minimum value, the value of the anti-deviation interval is changed from a first value to a second value, wherein the second value is less than the first value and greater than or equal to the allowable minimum value.

13. The controller as described in claim 6, wherein the controller is further configured to dynamically adjust the value of the anti-deviation interval based on an indication signal regarding service quality from the link layer when the anti-deviation interval is greater than a minimum permissible value.

14. The controller as claimed in claim 13, wherein the controller is configured to perform a plurality of operations to dynamically adjust the anti-deviation interval, the operations including: When the threshold value for notifying an error event has been reached in response to the indication signal, determine whether the value of the anti-deviation interval is greater than the minimum allowable value; And when the anti-deviation interval is greater than the allowable minimum value, the value of the anti-deviation interval is changed from a first value to a second value, wherein the second value is less than the first value and greater than or equal to the allowable minimum value.

15. The controller as described in claim 6, wherein the interconnection protocol is the Universal Flash Storage (UFS) standard.

16. A storage device capable of being linked to a host according to an interconnection protocol, the storage device comprising: One storage module; and a controller coupled to the storage module and used to implement the interconnection protocol, the controller including: an interface circuit for implementing a physical layer of the interconnection protocol to link the host; The system also includes a hardware protocol engine coupled to the interface circuitry and serving as a link layer for implementing the interconnect protocol. The hardware protocol engine is configured to respond to communication status information between the storage device and the host during a burst transmission and adaptively transmit periodic anti-misaligned patterns on the channel from the storage device to the host according to an anti-misalignment interval, wherein the anti-misalignment interval represents the time interval between two consecutive periodic anti-misaligned patterns. The hardware protocol engine is configured to periodically transmit an anti-misaligned pattern according to the anti-misalignment interval when the communication status information meets a criterion for transmitting the periodic anti-misaligned pattern, and to delay transmitting the anti-misaligned pattern when the communication status information does not meet the criterion. The communication status information includes a burst transmission indication signal and frame busy information. The criterion includes: the burst transmission indication signal indicating that burst transmission is in progress; the period according to the anti-misalignment interval being reached; and the frame busy information indicating that no frame is being transmitted. The hardware protocol engine is configured to send the anti-misalignment pattern when the burst transmission indication signal indicates that the burst transmission is in progress, when the anti-misalignment interval period is reached, and when the information of the busy frame indicates that no frame is being transmitted.

17. The storage device as claimed in claim 16, wherein the controller is further configured to dynamically adjust the value of the anti-deviation interval based on an indication signal of the link layer regarding quality of service when the anti-deviation interval is greater than a permissible minimum value.

18. The storage device as claimed in claim 16, wherein the storage device further comprises: A processing unit coupled to the hardware protocol engine is configured to dynamically adjust the value of the anti-misalignment interval based on an indication signal regarding quality of service from the link layer when the anti-misalignment interval exceeds a minimum permissible value.

19. The storage device as described in claim 16, wherein the interconnection protocol is the Universal Flash Storage (UFS) standard.

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