Semiconductor device

Abstract

A semiconductor device may include: a substrate including a first active region and a second active region adjacent to each other; a first active pattern and a second active pattern respectively disposed on the first active region and the second active region; and a gate electrode extending to intersect with the first active pattern and the second active pattern. The gate electrode may include a first electrode portion and a second electrode portion respectively disposed on the first active region and the second active region. The second electrode portion may include a first metal pattern, an etched barrier pattern, a second metal pattern, and a third metal pattern sequentially covering the second active pattern. The first electrode portion may include a second metal pattern covering the first active pattern. The etched barrier pattern may contact the first metal pattern and the second metal pattern, and may be thinner than both the first and second metal patterns.

Description

Technical Field

[0001] [Cross - Reference to Related Applications]

[0002] This U.S. non - provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10 - 2022 - 0012711, filed with the Korean Intellectual Property Office on January 27, 2022, the entire contents of which are incorporated herein by reference.

[0003] This disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including a field - effect transistor. Prior Art

[0004] Semiconductor devices include integrated circuits composed of metal - oxide - semiconductor field - effect transistors (MOS - FETs). To meet the growing demand for semiconductor devices with small pattern sizes and reduced design rules, MOS - FETs are being aggressively scaled down. The scaling down of MOS - FETs may lead to deterioration of the operational properties of semiconductor devices. Various studies are underway to overcome the technical limitations associated with the scaling down of semiconductor devices and to achieve high - performance semiconductor devices. Summary of the Invention

[0005] One aspect is to provide a semiconductor device having improved electrical characteristics.

[0006] According to one aspect of one or more embodiments, a semiconductor device may include: a substrate including a first active region and a second active region adjacent to each other; a first active pattern and a second active pattern disposed on the first active region and the second active region, respectively; and a gate electrode extending to cross the first active pattern and the second active pattern. The gate electrode may include a first electrode portion located on the first active region and a second electrode portion located on the second active region. The second electrode portion may include a first metal pattern, an etching barrier pattern, a second metal pattern, and a third metal pattern that sequentially cover the second active pattern. The first electrode portion may include a second metal pattern covering the first active pattern. The etching barrier pattern may be in contact with the first metal pattern and the second metal pattern, and the etching barrier pattern may be thinner than the first metal pattern and thinner than the second metal pattern.

[0007] According to another aspect of one or more embodiments, a semiconductor device may include: a substrate including a first active region and a second active region adjacent to each other; a first active pattern and a second active pattern disposed on the first active region and the second active region, respectively; a gate electrode extending to cross the first active pattern and the second active pattern; and a gate insulating layer disposed between the gate electrode and the first active region and between the gate electrode and the second active region. The gate electrode may include a first electrode portion on the first active region and a second electrode portion on the second active region. The second electrode portion may include a first metal pattern, an etching barrier pattern, and a second metal pattern sequentially covering the second active pattern. The first electrode portion may include a second metal pattern covering the first active pattern. The etching barrier pattern may be in contact with the first metal pattern and the second metal pattern. The etching barrier pattern may be in contact with the gate insulating layer.

[0008] According to another aspect of one or more embodiments, a semiconductor device may include: a substrate including a first active region and a second active region adjacent to each other in a first direction; a device isolation layer filling trenches formed to define the first active region and the second active region; a first active pattern and a second active pattern disposed on the first active region and the second active region, respectively; a first source / drain pattern and a second source / drain pattern disposed on the first active pattern and the second active pattern, respectively; a first channel pattern and a second channel pattern connected to the first source / drain pattern and the second source / drain pattern, respectively, each of the first channel pattern and the second channel pattern including a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern stacked to be spaced apart from each other; a gate electrode extending in the first direction to cross the first channel pattern and the second channel pattern; a gate insulating layer interposed between the gate electrode and the first channel pattern and between the gate electrode and the second channel pattern; a gate spacer disposed on a side surface of the gate electrode; a gate cap pattern disposed on a top surface of the gate electrode; a first interlayer insulating layer on the gate cap pattern; an active contact penetrating the first interlayer insulating layer and coupled to the first source / drain pattern and the second source / drain pattern, respectively; a gate contact penetrating the first interlayer insulating layer and coupled to the gate electrode; a second interlayer insulating layer on the first interlayer insulating layer; a first metal layer disposed in the second interlayer insulating layer, the first metal layer including lower interconnects electrically connected to the active contact and the gate contact, respectively; a third interlayer insulating layer on the second interlayer insulating layer; and a second metal layer disposed in the third interlayer insulating layer. The second metal layer may include upper interconnects electrically connected to the lower interconnects, respectively. The gate electrode may include a first electrode portion on the first active region and a second electrode portion on the second active region. The second electrode portion may include a first metal pattern, an etch barrier pattern, and a second metal pattern sequentially covering the second active pattern. The first electrode portion may include a second metal pattern covering the first active pattern. The etch barrier pattern may contact the first metal pattern and the second metal pattern of the second electrode portion. The etch barrier pattern may be thinner than the first metal pattern and thinner than the second metal pattern of the second electrode portion. Brief Description of the Drawings

[0009] FIG. 1 is a plan view showing a semiconductor device according to an embodiment. FIGS. 2A to 2D are cross-sectional views taken along lines A-A', B-B', C-C', and D-D' shown in FIG. 1, respectively. FIG. 2E is an enlarged cross-sectional view of portion Q shown in FIG. 2D. FIG. 2F is an enlarged cross-sectional view of portion R shown in FIG. 2E. FIGS. 3A to 14C are cross-sectional views showing a method of fabricating a semiconductor device according to an embodiment. FIGS. 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, and 14A are cross-sectional views taken along line A-A' shown in FIG. 1. FIGS. 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, and 14B are cross-sectional views taken along line B-B' shown in FIG. 1. FIGS. 5C, 6C, 7C, and 8C are cross-sectional views taken along line C-C' shown in FIG. 1. FIGS. 3B, 4B, 5D, 6D, 7D, 8D, 9C, 10C, 11C, 12C, 13C, and 14C are cross-sectional views taken along line D-D' shown in FIG. 1. FIGS. 15A to 15C are cross-sectional views taken along lines A-A', B-B', and D-D' shown in FIG. 1, respectively. FIG. 15D is an enlarged cross-sectional view of portion Q' shown in FIG. 15C. FIG. 15E is an enlarged cross-sectional view of portion R' shown in FIG. 15D. FIGS. 16A to 21C are cross-sectional views showing a method of fabricating a semiconductor device according to an embodiment. FIGS. 16A, 17A, 18A, 19A, 20A, and 21A are cross-sectional views taken along line A-A' shown in FIG. 1. FIGS. 16B, 17B, 18B, 19B, 20B, and 21B are cross-sectional views taken along line B-B' shown in FIG. 1. FIGS. 16C, 17C, 18C, 19C, 20C, and 21C are cross-sectional views taken along line D-D' shown in FIG. 1. FIGS. 22A to 29C are cross-sectional views showing a method of fabricating a semiconductor device according to an embodiment. FIGS. 22A, 23A, 24A, 25A, 26A, 27A, 28A, and 29A are cross-sectional views taken along line A-A' shown in FIG. 1. FIGS. 22B, 23B, 24B, 25B, 26B, 27B, 28B, and 29B are cross-sectional views taken along line B-B' shown in FIG. 1. FIG. 22C, FIG. 23C, FIG. 24C, FIG. 25C, FIG. 26C, FIG. 27C, FIG. 28C, and FIG. 29C are cross-sectional views taken along line D-D' shown in FIG. 1. FIG. 30 is an enlarged cross-sectional view of a part shown in FIG. 2D. Embodiments

[0010] Various exemplary embodiments will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments are shown.

[0011] FIG. 1 is a plan view showing a semiconductor device according to an embodiment. FIGS. 2A to 2D are cross-sectional views taken along lines A-A', B-B', C-C', and D-D' shown in FIG. 1, respectively. FIG. 2E is an enlarged cross-sectional view of a part Q shown in FIG. 2D. FIG. 2F is an enlarged cross-sectional view of a part R shown in FIG. 2E.

[0012] Referring to FIGS. 1 and 2A to 2F, logic cells may be provided on a substrate 100. In this specification, a logic cell may mean a logic device (e.g., an inverter, a flip-flop, etc.) configured to perform a specific function. For example, a logic cell may include transistors constituting a logic device and interconnects connecting the transistors to each other.

[0013] The substrate 100 may include a first active region PR and a second active region NR. In an embodiment, the first active region PR may be a P-type metal oxide semiconductor field effect transistor (PMOSFET) region, and the second active region NR may be an N-type metal oxide semiconductor field effect transistor (NMOSFET) region. The substrate 100 may be a semiconductor substrate formed of silicon, germanium, silicon germanium, a compound semiconductor material, or a similar material or include silicon, germanium, silicon germanium, a compound semiconductor material, or a similar material. In an embodiment, the substrate 100 may be a silicon wafer.

[0014] The first active region PR and the second active region NR may be defined by a second trench TR2 formed in an upper portion of the substrate 100 (best shown in FIG. 2C). The second trench TR2 may be located between the first active region PR and the second active region NR. The first active region PR and the second active region NR may be spaced apart from each other in a first direction D1, and the second trench TR2 is sandwiched between the first active region PR and the second active region NR. Each of the first active region PR and the second active region NR may extend in a second direction D2 different from the first direction D1 (best shown in FIG. 1).

[0015] The first active pattern AP1 and the second active pattern AP2 may be defined by a first trench TR1 formed in an upper portion of the substrate 100 (best shown in FIG. 2C). The first active pattern AP1 and the second active pattern AP2 may be disposed on the first active region PR and the second active region NR, respectively. In some embodiments, the first trench TR1 may be shallower than the second trench TR2. The first active pattern AP1 and the second active pattern AP2 may extend in the second direction D2. The first active pattern AP1 and the second active pattern AP2 may be portions of the substrate 100 that protrude in a vertical direction.

[0016] The device isolation layer ST may be provided to fill the first trench TR1 and the second trench TR2. The device isolation layer ST may include a silicon oxide layer. Upper portions of the first active pattern AP1 and the second active pattern AP2 may protrude in a vertical direction above the device isolation layer ST (e.g., see FIG. 2D). The device isolation layer ST may not cover the upper portions of the first active pattern AP1 and the second active pattern AP2. The device isolation layer ST may cover lower side surfaces of the first active pattern AP1 and the second active pattern AP2.

[0017] The first active pattern AP1 may include an upper portion that serves as a first channel pattern CH1 (best shown in FIG. 2A). The second active pattern AP2 may include an upper portion that serves as a second channel pattern CH2 (best shown in FIG. 2B). Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 stacked in sequence. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be spaced apart from each other in a vertical direction (i.e., a third direction D3).

[0018] Each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be formed of or include silicon (Si), germanium (Ge), or silicon germanium (SiGe). In an embodiment, each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be formed of crystalline silicon or include crystalline silicon.

[0019] A plurality of first grooves RS1 (best shown in FIG. 2A) may be formed in an upper portion of the first active pattern AP1. First source / drain patterns SD1 may be respectively disposed in the first grooves RS1. The first source / drain patterns SD1 may be impurity regions of a first conductivity type (e.g., p-type). The first channel pattern CH1 may be sandwiched between each pair of the first source / drain patterns SD1. In other words, each pair of the first source / drain patterns SD1 may be connected to each other by the stacked first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3.

[0020] A plurality of second grooves RS2 (best shown in FIG. 2B) may be formed in an upper portion of the second active pattern AP2. Second source / drain patterns SD2 may be respectively disposed in the second grooves RS2. The second source / drain patterns SD2 may be impurity regions of a second conductivity type (e.g., n-type). The second channel pattern CH2 may be sandwiched between each pair of the second source / drain patterns SD2. In other words, each pair of the second source / drain patterns SD2 may be connected to each other by the stacked first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3.

[0021] The first source / drain patterns SD1 and the second source / drain patterns SD2 may be epitaxial patterns formed by a selective epitaxial growth (SEG) process. As an example, each of the first source / drain patterns SD1 and the second source / drain patterns SD2 may have a top surface located substantially at the same level as the top surface of the third semiconductor pattern SP3. However, in an embodiment, the top surface of each of the first source / drain patterns SD1 and the second source / drain patterns SD2 may be higher than the top surface of the third semiconductor pattern SP3.

[0022] The first source / drain pattern SD1 may include a semiconductor material (e.g., SiGe) having a lattice constant greater than that of the semiconductor material of the substrate 100. In such a case, the pair of first source / drain patterns SD1 may apply compressive stress to the first channel pattern CH1 located therebetween.

[0023] In an embodiment, the second source / drain pattern SD2 may be formed of or include the same semiconductor material as the substrate 100 (e.g., Si). In another embodiment, the second source / drain pattern SD2 may be formed of or include a material containing both silicon (Si) and carbon (C). For example, the second source / drain pattern SD2 may be formed of or include silicon carbide (SiC). In the case where the second source / drain pattern SD2 is formed of silicon carbide (SiC), the carbon content in the second source / drain pattern SD2 may range from 10 atomic % to 30 atomic %. The pair of second source / drain patterns SD2 containing silicon carbide (SiC) may apply tensile stress to the second channel pattern CH2 located therebetween.

[0024] Each of the first source / drain patterns SD1 may include a first semiconductor layer SEL1 and a second semiconductor layer SEL2 stacked in sequence. The cross-sectional shape of the first source / drain pattern SD1 taken parallel to the second direction D2 will be described with reference to FIG. 2A. The first semiconductor layer SEL1 may have a "U"-shaped cross-section. The first semiconductor layer SEL1 may have a decreasing thickness in the upward direction. In other words, the thickness of the first semiconductor layer SEL1 may decrease as the distance from the substrate 100 increases. The second semiconductor layer SEL2 may be disposed on the first semiconductor layer SEL1. The volume of the second semiconductor layer SEL2 may be greater than the volume of the first semiconductor layer SEL1. In other words, the ratio of the volume of the second semiconductor layer SEL2 to the total volume of the first source / drain pattern SD1 may be greater than the ratio of the volume of the first semiconductor layer SEL1 to the total volume of the first source / drain pattern SD1.

[0025] Each of the first semiconductor layer SEL1 and the second semiconductor layer SEL2 may be formed of or include silicon germanium (SiGe). In some embodiments, the first semiconductor layer SEL1 may be configured to have a relatively low germanium concentration. In another embodiment, the first semiconductor layer SEL1 may be configured to include only silicon (Si) and not germanium (Ge). The germanium concentration of the first semiconductor layer SEL1 may range from 0 atomic % to 10 atomic %.

[0026] The second semiconductor layer SEL2 can be configured to have a relatively high germanium concentration. As an example, the germanium concentration of the second semiconductor layer SEL2 can range from 30 atomic % to 70 atomic %. In some embodiments, the germanium concentration of the second semiconductor layer SEL2 can increase in the third direction D3. For example, the germanium concentration of the second semiconductor layer SEL2 can be about 40 atomic % near the first semiconductor layer SEL1, but can be about 60 atomic % at its top level (i.e., farthest from the substrate 100).

[0027] The first semiconductor layer SEL1 and the second semiconductor layer SEL2 can contain impurities (e.g., boron), such that the first source / drain pattern SD1 can have p-type conductivity. In an embodiment, the impurity concentration (in atomic %) in the second semiconductor layer SEL2 can be greater than the impurity concentration in the first semiconductor layer SEL1.

[0028] The first semiconductor layer SEL1 can prevent stacking faults from occurring between the substrate 100 and the second semiconductor layer SEL2, and between the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 and the second semiconductor layer SEL2. Stacking faults may cause an increase in channel resistance, but the stacking faults can be prevented by the first semiconductor layer SEL1 and thereby improve the electrical characteristics of the semiconductor device.

[0029] In a process of replacing the sacrificial layer SAL with the gate electrode GE (which will be described below), the first semiconductor layer SEL1 can protect the second semiconductor layer SEL2. For example, the first semiconductor layer SEL1 can prevent the second semiconductor layer SEL2 from being damaged by an etching material used to remove the sacrificial layer SAL in an undesired manner.

[0030] The gate electrode GE can be configured to cross the first active pattern AP1 and the second active pattern AP2 and extend in the first direction D1. The gate electrodes GE can be arranged in the second direction D2 with a first pitch P1. When observed in a plan view, each of the gate electrodes GE can overlap the first channel pattern CH1 and the second channel pattern CH2.

[0031] The gate electrode GE may include a first electrode portion GE1 located on the first active region PR and a second electrode portion GE2 located on the second active region NR. Each of the first electrode portion GE1 and the second electrode portion GE2 of the gate electrode GE may include a first portion sandwiched between the substrate 100 and the first semiconductor pattern SP1, a second portion sandwiched between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third portion sandwiched between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and a fourth portion located on the third semiconductor pattern SP3.

[0032] Referring back to FIGS. 2A, the first to third portions of the first electrode portion GE1 may have different widths from each other (e.g., in the second direction D2). Referring back to FIG. 2D, the gate electrode GE may be disposed on the top surface, bottom surface, and opposite side surfaces of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. In other words, the logic transistor according to the present embodiment may be a three-dimensional field-effect transistor in which the gate electrode GE is disposed to surround the channel pattern three-dimensionally (e.g., a multi-bridge channel field-effect transistor (MBCFET)).

[0033] Referring back to FIGS. 1 and 2A to 2D, a pair of gate spacers GS may be respectively disposed on the opposite side surfaces of the fourth portion of the gate electrode GE. That is, the gate spacers GS may be disposed on each of the opposite side surfaces of the fourth portion of the gate electrode GE. The gate spacers GS may extend along the gate electrode GE in the third direction D3 and the first direction D1. The top surface of the gate spacers GS may be higher than the top surface of the gate electrode GE. The top surface of the gate spacers GS may be coplanar with the top surface of the first interlayer insulating layer 110 to be described below. The gate spacers GS may be formed of or include at least one of SiCN, SiCON, or SiN. In an embodiment, the gate spacers GS may have a multi-layered structure including at least two layers, each of the at least two layers being made of SiCN, SiCON, or SiN.

[0034] A gate cap pattern GP may be disposed on the gate electrode GE. The gate cap pattern GP may extend along the gate electrode GE and in a first direction D1. The gate cap pattern GP may be formed of or include a material having an etching selectivity with respect to a first interlayer insulating layer 110 and a second interlayer insulating layer 120 to be described below. For example, the gate cap pattern GP may be formed of or include at least one of SiON, SiCN, SiCON, or SiN.

[0035] A gate insulating layer GI may be sandwiched between the gate electrode GE and the first channel pattern CH1 and between the gate electrode GE and the second channel pattern CH2. The gate insulating layer GI may cover the top surface, bottom surface, and opposite side surfaces of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The gate insulating layer GI may cover the top surface of the device isolation layer ST located under the gate electrode GE (see, for example, FIG. 2D).

[0036] In an embodiment, the gate insulating layer GI may include a silicon oxide layer, a silicon oxynitride layer, and / or a high-k dielectric layer. The high-k dielectric layer may be formed of or include at least one of high-k dielectric materials having a dielectric constant higher than that of silicon oxide. As an example, the high-k dielectric material may be formed of or include at least one of the following: hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and / or lead zinc niobate.

[0037] In another embodiment, the semiconductor device may include a negative capacitance (NC) FET using a negative capacitor. For example, the gate insulating layer GI may include a ferroelectric layer exhibiting ferroelectric material properties and a paraelectric layer exhibiting paraelectric material properties.

[0038] The ferroelectric layer may have a negative capacitance. The paraelectric layer may have a positive capacitance. In a case where two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance may be smaller than the capacitance of each capacitor. In contrast, in a case where at least one of the capacitors connected in series has a negative capacitance, the total capacitance of the capacitors connected in series may have a positive value and may be greater than the absolute value of each capacitance.

[0039] In a case where a ferroelectric layer having a negative capacitance is connected in series with a paraelectric layer having a positive capacitance, the total capacitance of the series-connected ferroelectric layer and paraelectric layer can be increased. Due to this increase in the total capacitance, a transistor including the ferroelectric layer can have a subthreshold swing (SS) of less than 60 millivolts per decade of drain current change at room temperature.

[0040] The ferroelectric layer can have ferroelectric material properties. The ferroelectric layer can be formed of or include at least one of, for example, the following materials: hafnium oxide, hafnium zirconium oxide, barium strontium titanate, barium titanate, and / or lead zirconium titanate. Here, hafnium zirconium oxide can be hafnium oxide doped with zirconium (Zr). As an alternative, hafnium zirconium oxide can be a compound composed of hafnium (Hf), zirconium (Zr), and / or oxygen (O).

[0041] The ferroelectric layer can further include a dopant. For example, the dopant can include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and / or tin (Sn). The type of dopant in the ferroelectric layer can vary depending on the ferroelectric material contained in the ferroelectric layer.

[0042] In a case where the ferroelectric layer contains hafnium oxide, the dopant in the ferroelectric layer can include at least one of, for example, gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and / or yttrium (Y).

[0043] In a case where the dopant is aluminum (Al), the content of aluminum in the ferroelectric layer can range from 3 atomic % to 8 atomic % (atomic percentage). Here, the content of aluminum as the dopant can be the ratio of the number of aluminum atoms to the number of hafnium atoms and aluminum atoms.

[0044] In a case where the dopant is silicon (Si), the content of silicon in the ferroelectric layer can range from 2 atomic % to 10 atomic %. In a case where the dopant is yttrium (Y), the content of yttrium in the ferroelectric layer can range from 2 atomic % to 10 atomic %. In a case where the dopant is gadolinium (Gd), the content of gadolinium in the ferroelectric layer can range from 1 atomic % to 7 atomic %. In a case where the dopant is zirconium (Zr), the content of zirconium in the ferroelectric layer can range from 50 atomic % to 80 atomic %.

[0045] The paraelectric layer may have the properties of a paraelectric material. The paraelectric layer may be formed of or include at least one of, for example, silicon oxide and / or a high-k metal oxide. The metal oxides that can be used as the paraelectric layer may include at least one of, for example, hafnium oxide, zirconium oxide, and / or aluminum oxide, but the inventive concept is not limited to these examples.

[0046] The ferroelectric layer and the paraelectric layer may be formed of or include the same material. The ferroelectric layer may have the properties of a ferroelectric material, but the paraelectric layer may not have the properties of a ferroelectric material. For example, in the case where the ferroelectric layer and the paraelectric layer include hafnium oxide, the crystal structure of hafnium oxide in the ferroelectric layer may be different from the crystal structure of hafnium oxide in the paraelectric layer.

[0047] The ferroelectric layer can exhibit the properties of a ferroelectric material only when its thickness is within a specific range. In an embodiment, the ferroelectric layer may have a thickness in the range from 0.5 nm to 10 nm, but the embodiment is not limited to this example. Since the critical thickness associated with the emergence of the ferroelectric material properties varies depending on the type of ferroelectric material, the thickness of the ferroelectric layer may vary depending on the type of ferroelectric material.

[0048] As an example, the gate insulating layer GI may include a single ferroelectric layer. As another example, the gate insulating layer GI may include a plurality of ferroelectric layers spaced apart from each other. The gate insulating layer GI may have a multilayer structure in which a plurality of ferroelectric layers and a plurality of paraelectric layers are alternately stacked.

[0049] The second electrode portion GE2 of the gate electrode GE may include a first metal pattern MP1b, an etching barrier pattern BP, a second metal pattern MP2b, and a third metal pattern MP3b. The first electrode portion GE1 of the gate electrode GE may include a second metal pattern MP2a and a third metal pattern MP3a.

[0050] The first metal pattern MP1b may cover the second active pattern AP2. For example, the first metal pattern MP1b may be disposed adjacent to the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 on the gate insulating layer GI. The first metal pattern MP1b may include a work-function metal, which can be used to adjust the threshold voltage of the transistor. By adjusting the thickness and composition of the first metal pattern MP1b, a transistor with a desired threshold voltage can be achieved. The first metal pattern MP1b may be disposed to fill the space between the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 of the second channel pattern CH2. In an embodiment, the first metal pattern MP1b may extend to face the side surfaces of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 and the top surface of the third semiconductor pattern SP3. The first metal pattern MP1b may include an end portion EG1 disposed on the device isolation layer ST between the first active region PR and the second active region NR (best shown in FIGS. 2E and 2F).

[0051] The second metal pattern MP2a of the first electrode portion GE1 and the second metal pattern MP2b of the second electrode portion GE2 may be part of the second metal layer ML2. The second metal pattern MP2a of the first electrode portion GE1 and the second metal pattern MP2b of the second electrode portion GE2 may be part of layers formed of the same material using the same process. The second metal pattern MP2a of the first electrode portion GE1 and the second metal pattern MP2b of the second electrode portion GE2 may be connected to each other on the device isolation layer ST between the first active region PR and the second active region NR, but in some embodiments, the second metal pattern MP2a of the first electrode portion GE1 and the second metal pattern MP2b of the second electrode portion GE2 may be cut by an insulating layer on the device isolation layer ST between the first active region PR and the second active region NR.

[0052] The first metal pattern MP1b may include a metal nitride layer. For example, the first metal pattern MP1b may include a layer composed of at least one metal material selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo) and nitrogen (N). In an embodiment, the first metal pattern MP1b may further include carbon (C). The first metal pattern MP1b may include a plurality of work-function metal layers stacked in sequence.

[0053] The second metal layer ML2 may include a metal nitride layer. For example, the first metal pattern MP1b may include at least one of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo) and nitrogen (N). In an embodiment, the second metal layer ML2 may further include carbon (C). The second metal layer ML2 may include a plurality of work function metal layers stacked in sequence.

[0054] An etch barrier pattern BP disposed between the first metal pattern MP1b and the second metal pattern MP2b of the second electrode portion GE2 may separate the first metal pattern MP1b and the second metal pattern MP2b. In an embodiment, the etch barrier pattern BP may not extend into the space between the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 of the second channel pattern CH2. The first electrode portion GE1 may not include the etch barrier pattern BP. In an embodiment, an end portion EG2 of the etch barrier pattern BP may be disposed on a device isolation layer ST between the first active region PR and the second active region NR.

[0055] The etch barrier pattern BP may be formed of or include a material different from that of the first metal pattern MP1b. The etch barrier pattern BP may be formed of or include a material having an etch selectivity with respect to the first metal pattern MP1b selected in a fabrication process to be described below. In an embodiment, the etch barrier pattern BP may be formed of or include a material including at least one of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), or molybdenum (Mo) and nitrogen (N) but different from the material of the first metal pattern MP1b. In an embodiment, the etch barrier pattern BP may be formed of or include a material including at least one of TiAlN, TaAlC, TiN, or TaN but different from the material of the first metal pattern MP1b. In a case where the etch barrier pattern BP includes TiAlN, its aluminum concentration may be in the range of from about 10 atomic % to 19 atomic %.

[0056] Referring to FIGS. 2E and 2F, an end portion EG2 of the etch barrier pattern BP may cover an end portion EG1 of the first metal pattern MP1b. Specifically, the end portion EG1 of the first metal pattern MP1b may include a side surface SF, and the end portion EG2 of the etch barrier pattern BP may include a first portion Y1 covering the top surface of the first metal pattern MP1b, a second portion Y2 covering the side surface SF of the first metal pattern MP1b, and a third portion Y3 in contact with the gate insulating layer GI. Therefore, the end portion EG2 of the etch barrier pattern BP may have a stepped structure. The second metal layer ML2 may have a stepped structure STP near the end portion EG1 of the first metal pattern MP1b and the end portion EG2 of the etch barrier pattern BP. That is, the second metal layer ML2 may have a stepped structure STP starting from a portion of the second metal layer ML2 located above the first portion Y1 to a portion of the second metal layer ML2 in contact with the gate insulating layer GI.

[0057] The etch barrier pattern BP may be thinner than the first metal pattern MP1b and thinner than the second metal pattern MP2b (e.g., in a first direction D1). The thickness of the etch barrier pattern BP may be about 20% to about 70% of the thickness of the first metal pattern MP1b. The thickness of the etch barrier pattern BP may be about 20% to about 70% of the thickness of the second metal pattern MP2b. In an embodiment, the thickness of the etch barrier pattern BP may range from about 10 angstroms to about 20 angstroms.

[0058] The third metal pattern MP3b of the second electrode portion GE2 and the third metal pattern MP3a of the first electrode portion GE1 may be parts of the third metal layer ML3. The third metal patterns MP3a and MP3b may be formed of or include a metal material having a lower resistance than the resistance of the first metal pattern MP1b. For example, the third metal patterns MP3a and MP3b may be formed of or include at least one of tungsten (W), aluminum (Al), titanium (Ti), or tantalum (Ta). The third metal pattern MP3b of the second electrode portion GE2 and the third metal pattern MP3a of the first electrode portion GE1 may be formed of the same material or include the same material, but in an embodiment, the third metal pattern MP3b of the second electrode portion GE2 and the third metal pattern MP3a of the first electrode portion GE1 may be formed of different materials or include different materials. For example, in the case of different materials, the boundary between the third metal pattern MP3b of the second electrode portion GE2 and the third metal pattern MP3a of the first electrode portion GE1 may be located at the boundary between the first active region PR and the second active region NR.

[0059] A first interlayer insulating layer 110 (best shown in FIG. 2C) may be disposed on the substrate 100. The first interlayer insulating layer 110 may cover the gate spacer GS and the first source / drain pattern SD1 and the second source / drain pattern SD2. The first interlayer insulating layer 110 may have a top surface substantially coplanar with the top surface of the gate cap pattern GP and the top surface of the gate spacer GS. A second interlayer insulating layer 120 may be disposed on the first interlayer insulating layer 110 to cover the gate cap pattern GP. In an embodiment, at least one of the first interlayer insulating layer 110 and the second interlayer insulating layer 120 may include a silicon oxide layer.

[0060] A pair of split structures DB opposite to each other in the second direction D2 may be disposed on both sides of the logic cell. The split structures DB may extend parallel to the gate electrode GE in the first direction D1. The pitch between the adjacent split structures DB and the gate electrode GE may be equal to the first pitch P1 between the adjacent gate electrodes GE described previously.

[0061] The split structures DB may be disposed to penetrate the first interlayer insulating layer 110 and the second interlayer insulating layer 120 and may extend into the first active pattern AP1 and the second active pattern AP2. The split structures DB may be disposed to penetrate the upper portions of each of the first active pattern AP1 and the second active pattern AP2. The split structures DB may separate the first active region PR and the second active region NR of the logic cell from the active regions of adjacent logic cells.

[0062] The upper portion of each of the first active pattern AP1 and the second active pattern AP2 may further include a sacrificial layer SAL disposed adjacent to the split structure DB (see, for example, FIG. 2A). The sacrificial layers SAL may be stacked to be spaced apart from each other. Each of the sacrificial layers SAL may be at the same level as the corresponding one of the first part, the second part, and the third part of the gate electrode GE. The split structures DB may be disposed to penetrate the sacrificial layers SAL. An internal spacer IP (see, for example, FIG. 2B) may be sandwiched between the sacrificial layer SAL and the second source / drain pattern SD2. As an example, the internal spacer IP may be formed of or include silicon nitride.

[0063] The active contact AC can be configured to penetrate the first interlayer insulating layer 110 and the second interlayer insulating layer 120 and can be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. A pair of active contacts AC can be respectively disposed on both sides of the gate electrode GE. That is, an active contact can be disposed on each side of the gate electrode GE. When observed in a plan view, the active contact AC can be a strip-shaped pattern extending in the first direction D1. The active contact AC can be a self-aligned contact. For example, the active contact AC can be formed by using a self-alignment process of the gate cap pattern GP and the gate spacer GS. In an embodiment, the active contact AC can cover at least a part of the side surface of the gate spacer GS. Although not shown, the active contact AC can be configured to cover a part of the top surface of the gate cap pattern GP.

[0064] A silicide pattern SC can be respectively interposed between the active contact AC and the first source / drain pattern SD1 and between the active contact AC and the second source / drain pattern SD2. The active contact AC can be electrically connected to the source / drain pattern SD1 or SD2 via the silicide pattern SC. The silicide pattern SC can be formed of at least one of metal silicide materials (e.g., titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, or cobalt silicide) or can contain at least one of metal silicide materials (e.g., titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, or cobalt silicide).

[0065] The gate contact GC can be configured to penetrate the second interlayer insulating layer 120 and the gate cap pattern GP and can be electrically connected to the gate electrode GE. Referring to FIG. 2B, the upper regions of each of the active contacts AC adjacent to the gate contact GC can be filled with the upper insulating pattern UIP. Thus, process failures (e.g., short circuits) that may occur when the gate contact GC contacts the adjacent active contact AC can be prevented.

[0066] Each of the active contact AC and the gate contact GC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM (best shown in FIGS. 2C and 2D). For example, the conductive pattern FM may be formed of or include at least one of metallic materials such as aluminum, copper, tungsten, molybdenum, or cobalt. The barrier pattern BM may be disposed to cover side and bottom surfaces of the conductive pattern FM. In an embodiment, the barrier pattern BM may include a metal layer and a metal nitride layer. The metal layer may be formed of or include at least one of titanium, tantalum, tungsten, nickel, cobalt, or platinum. The metal nitride layer may be formed of or include at least one of the following materials: titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), or platinum nitride (PtN).

[0067] A first metal layer M1 may be disposed in the third interlayer insulating layer 130. The first metal layer M1 may include a first lower interconnect M1_R, a second lower interconnect M1_I, and a lower via VI1. The lower via VI1 may be disposed below the first lower interconnect M1_R and the second lower interconnect M1_I.

[0068] Each of the first lower interconnects M1_R may extend in a second direction D2 to cross the logic cells. Each of the first lower interconnects M1_R may be a power line. For example, a drain voltage VDD or a source voltage VSS may be applied to the first lower interconnects M1_R.

[0069] Referring to FIG. 1, a first cell boundary CB1 extending in the second direction D2 may be defined in a region of the logic cells. A second cell boundary CB2 extending in the second direction D2 may be defined in a region of the logic cells opposite to the first cell boundary CB1. The first lower interconnects M1_R to which the drain voltage VDD (i.e., the power supply voltage) is applied may be disposed on the first cell boundary CB1. The first lower interconnects M1_R to which the drain voltage VDD is applied may extend along the first cell boundary CB1 and in the second direction D2. The first lower interconnects M1_R to which the source voltage VSS (i.e., the ground voltage) is applied may be disposed on the second cell boundary CB2. The first lower interconnects M1_R to which the source voltage VSS is applied may extend along the second cell boundary CB2 and in the second direction D2.

[0070] The second lower internal connection M1_I can be disposed between the first lower internal connections M1_R to which a drain voltage VDD and a source voltage VSS are respectively applied in a first direction D1. Each of the second lower internal connections M1_I can be a linear pattern or a strip-shaped pattern extending in a second direction D2. The second lower internal connections M1_I can be arranged in the first direction D1 with a second pitch P2. The second pitch P2 can be smaller than the first pitch P1.

[0071] The lower vias VI1 can be disposed below the first lower internal connections M1_R and the second lower internal connections M1_I of the first metal layer M1. The lower vias VI1 can be respectively sandwiched between the active contacts AC and the first lower internal connections M1_R and the second lower internal connections M1_I. The lower vias VI1 can be respectively sandwiched between the gate contacts GC and the second lower internal connections M1_I.

[0072] The lower internal connections M1_R or M1_I of the first metal layer M1 and the lower vias VI1 located below the lower internal connections M1_R or M1_I can be formed by a separate process. For example, each of the lower internal connections M1_R or M1_I and the lower vias VI1 can be formed by a single damascene process. A semiconductor device according to this embodiment can be fabricated using a sub-20 nm process.

[0073] A second metal layer M2 can be disposed in the fourth interlayer insulating layer 140. The second metal layer M2 can include upper internal connections M2_I. Each of the upper internal connections M2_I can be a linear pattern or a strip-shaped pattern extending in the first direction D1. In other words, the upper internal connections M2_I can extend parallel to each other in the first direction D1. When observed in a plan view, the upper internal connections M2_I can be parallel to the gate electrodes GE. The upper internal connections M2_I can be arranged in the second direction D2 with a third pitch P3. The third pitch P3 can be smaller than the first pitch P1. The third pitch P3 can be larger than the second pitch P2.

[0074] The second metal layer M2 can further include upper vias VI2. The upper vias VI2 can be disposed below the upper internal connections M2_I. The upper vias VI2 can be respectively sandwiched between the lower internal connections M1_R and M1_I and the upper internal connections M2_I.

[0075] The upper internal connections M2_I of the second metal layer M2 and the upper vias VI disposed below the upper internal connections M2_I can be formed by the same process and can form a single object. In other words, the upper internal connections M2_I of the second metal layer M2 and the upper vias VI2 can be formed together by a dual damascene process.

[0076] The lower interconnects M1_R and M1_I of the first metal layer M1 and the upper interconnect M2_I of the second metal layer M2 may be formed of the same material or different conductive materials or may include the same material or different conductive materials. For example, the lower interconnects M1_R and M1_I and the upper interconnect M2_I may be formed of at least one of metal materials (e.g., aluminum, copper, tungsten, molybdenum, or cobalt) or may include at least one of metal materials (e.g., aluminum, copper, tungsten, molybdenum, or cobalt).

[0077] In an embodiment, although not shown, additional metal layers (e.g., M3, M4, M5, etc.) may be further stacked on the fourth interlayer insulating layer 140. Each of the stacked metal layers may include wiring traces.

[0078] In a semiconductor device according to an embodiment, a gate electrode GE disposed to cross two regions (e.g., PR and NR) having different properties may include a metal pattern formed of a material and structure suitable for each region (e.g., PR or NR), and thus the performance of the semiconductor device may be optimized. Accordingly, the electrical characteristics of the semiconductor device may be improved.

[0079] FIGS. 3A to 14C are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment. FIGS. 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, and 14A are cross-sectional views taken along line A-A' of FIG. 1. FIGS. 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, and 14B are cross-sectional views taken along line B-B' of FIG. 1. FIGS. 5C, 6C, 7C, and 8C are cross-sectional views taken along line C-C' of FIG. 1. FIGS. 3B, 4B, 5D, 6D, 7D, 8D, 9C, 10C, 11C, 12C, 13C, and 14C are cross-sectional views taken along line D-D' of FIG. 1.

[0080] Referring to FIGS. 3A and 3B, a substrate 100 including a first active region PR and a second active region NR may be provided. A sacrificial layer SAL and an active layer ACL may be alternately stacked on the substrate 100. The sacrificial layer SAL and the active layer ACL may be formed of at least one of silicon (Si), germanium (Ge), or silicon germanium (SiGe) or may include at least one of silicon (Si), germanium (Ge), or silicon germanium (SiGe), but the material of the active layer ACL may be different from the material of the sacrificial layer SAL.

[0081] For example, the sacrificial layer SAL can be formed of or include silicon germanium (SiGe), and the active layer ACL can be formed of or include silicon (Si).

[0082] A mask pattern can be formed on the first active region PR and the second active region NR of the substrate 100, respectively. The mask pattern can be a linear pattern or a strip pattern extending in the second direction D2.

[0083] A first patterning process can be performed in which the mask pattern is used as an etching mask to form a first trench TR1 that defines the first active pattern AP1 and the second active pattern AP2. The first active pattern AP1 and the second active pattern AP2 can be formed on the first active region PR and the second active region NR, respectively. Each of the first active pattern AP1 and the second active pattern AP2 can include a sacrificial layer SAL and an active layer ACL, and the sacrificial layer SAL and the active layer ACL are alternately stacked in the upper portion of the first active pattern AP1 and the second active pattern AP2.

[0084] A second patterning process can be performed on the substrate 100 to form a second trench TR2 that defines the first active region PR and the second active region NR. The second trench TR2 can be formed to have a depth greater than the depth of the first trench TR1.

[0085] A device isolation layer ST can be formed on the substrate 100 to fill the first trench TR1 and the second trench TR2. For example, an insulating layer can be formed on the substrate 100 to cover the first active pattern AP1 and the second active pattern AP2. The device isolation layer ST can be formed by recessing the insulating layer until the sacrificial layer SAL is exposed.

[0086] The device isolation layer ST can be formed of or include at least one of insulating materials (e.g., silicon oxide). Each of the first active pattern AP1 and the second active pattern AP2 can include an upper portion protruding above the device isolation layer ST. In other words, the upper portion of each of the first active pattern AP1 and the second active pattern AP2 can be a protruding pattern extending vertically above the device isolation layer ST.

[0087] Referring to FIGS. 4A and 4B, a sacrificial pattern PP can be formed on the substrate 100 to intersect with the first active pattern AP1 and the second active pattern AP2. Each of the sacrificial patterns PP can be a linear pattern or a strip-shaped pattern extending in the first direction D1. The sacrificial patterns PP can be arranged at a specific pitch in the second direction D2.

[0088] Specifically, forming the sacrificial pattern PP can include: forming a sacrificial layer on the substrate 100; forming a hard mask pattern MK on the sacrificial layer; and patterning the sacrificial layer using the hard mask pattern MK as an etching mask. The sacrificial layer can be formed of polysilicon or contain polysilicon.

[0089] A pair of gate spacers GS can be formed on opposite side surfaces of each of the sacrificial patterns PP. That is, gate spacers GS can be formed on each side surface of each of the sacrificial patterns PP. Forming the gate spacers GS can include conformally forming a gate spacer layer on the substrate 100 and anisotropically etching the gate spacer layer. The gate spacer layer can be formed of at least one of SiCN, SiCON, or SiN or contain at least one of SiCN, SiCON, or SiN. As an alternative, the gate spacer layer can include at least two layers, each of the at least two layers being formed of at least one of SiCN, SiCON, or SiN; that is, the gate spacer layer can have a multi-layer structure.

[0090] Referring to FIGS. 5A to 5D, a first groove RS1 can be formed in an upper portion of the first active pattern AP1. A second groove RS2 can be formed in an upper portion of the second active pattern AP2. During the formation of the first groove RS1 and the second groove RS2, the device isolation layer ST can be recessed at both sides of each of the first active pattern AP1 and the second active pattern AP2 (e.g., see FIG. 5C).

[0091] Specifically, the first groove RS1 can be formed by etching an upper portion of the first active pattern AP1 using the hard mask pattern MK and the gate spacer GS as an etching mask. Each of the first grooves RS1 can be formed between each pair of sacrificial patterns PP. The second groove RS2 in the upper portion of the second active pattern AP2 can be formed by the same method as the method for forming the first groove RS1, and thus will not be described in detail for the sake of brevity. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 can be formed by the first groove RS1 and the second groove RS2.

[0092] Referring to FIGS. 6A to 6D, a first SEG process using the inner surface of the first groove RS1 as a seed layer can be performed to form a first semiconductor layer SEL1. The first semiconductor layer SEL1 can be grown using the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the substrate 100 exposed by the first groove RS1 as seeds. As an example, the first SEG process can include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0093] The first semiconductor layer SEL1 can be formed of a semiconductor material (e.g., SiGe) having a lattice constant greater than that of the substrate 100 or include a semiconductor material (e.g., SiGe) having a lattice constant greater than that of the substrate 100. In some embodiments, the first semiconductor layer SEL1 can be formed to have a relatively low germanium concentration. In another embodiment, the first semiconductor layer SEL1 can only contain silicon (Si) and not contain germanium (Ge). The germanium concentration of the first semiconductor layer SEL1 can range from 0 atomic % to 10 atomic %.

[0094] The second semiconductor layer SEL2 can be formed by performing a second SEG process on the first semiconductor layer SEL1. The second semiconductor layer SEL2 can be formed to completely fill the first groove RS1. The second semiconductor layer SEL2 can be formed to have a relatively high germanium concentration. As an example, the germanium concentration of the second semiconductor layer SEL2 can range from 30 atomic % to 70 atomic %.

[0095] The first semiconductor layer SEL1 and the second semiconductor layer SEL2 can constitute a first source / drain pattern SD1. During the first SEG process and the second SEG process, the first semiconductor layer SEL1 and the second semiconductor layer SEL2 can be in-situ doped with impurities. As an alternative, the first source / drain pattern SD1 can be doped with impurities after the first source / drain pattern SD1 is formed. The first source / drain pattern SD1 can be doped to have a first conductivity type (e.g., p-type).

[0096] A second source / drain pattern SD2 may be formed in an upper portion of the second active pattern AP2. Specifically, a selective epitaxial growth process may be performed in which the inner surface of the second recess RS2 is used as a seed layer to form the second source / drain pattern SD2. The second source / drain pattern SD2 may be formed of the same semiconductor material (e.g., Si) as the substrate 100 or may include the same semiconductor material (e.g., Si) as the substrate 100. The second source / drain pattern SD2 may be doped to have a second conductivity type (e.g., n-type).

[0097] Before forming the second source / drain pattern SD2, the sacrificial layer SAL exposed by the second recess RS2 may be locally removed. An internal spacer IP may be formed by filling the region formed by locally removing the sacrificial layer SAL with an insulating material.

[0098] Referring to FIGS. 7A to 7D, a first interlayer insulating layer 110 may be formed to cover the first source / drain pattern SD1, the second source / drain pattern SD2, the hard mask pattern MK, and the gate spacer GS. As an example, the first interlayer insulating layer 110 may include a silicon oxide layer.

[0099] The first interlayer insulating layer 110 may be planarized to expose the top surface of the sacrificial pattern PP. The planarization of the first interlayer insulating layer 110 may be performed using an etch-back or chemical mechanical polishing (CMP) process. All of the hard mask pattern MK may be removed during the planarization process. Accordingly, the first interlayer insulating layer 110 may have a top surface coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

[0100] In an embodiment, the exposed sacrificial pattern PP may be selectively removed. As a result of removing the sacrificial pattern PP, a first empty space ET1 may be formed to expose the first active pattern AP1 and the second active pattern AP2 (e.g., see FIG. 7D).

[0101] In an embodiment, some of the sacrificial patterns PP in the sacrificial pattern PP may not be removed. For example, the sacrificial patterns PP located on the cell boundaries may not be removed. Specifically, by forming a mask layer on the sacrificial patterns PP that should not be removed, the sacrificial patterns PP that are not intended to be removed in the sacrificial pattern PP can be prevented from being removed. As a result of removing the sacrificial pattern PP, the first active pattern AP1 and the second active pattern AP2 can be exposed through the first empty space ET1. The sacrificial layer SAL of each of the first active pattern AP1 and the second active pattern AP2 can be exposed through the first empty space ET1.

[0102] Referring to FIGS. 8A to 8D, the sacrificial layer SAL exposed through the first empty space ET1 can be selectively removed. Specifically, an etching process that selectively etches only the sacrificial layer SAL can be performed to remove only the sacrificial layer SAL and leave the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. Due to the internal spacer IP, defects can be prevented from occurring in the second source / drain pattern SD2 during this process.

[0103] As a result of removing the sacrificial layer SAL, a second empty space ET2 can be formed. The second empty space ET2 can be defined between the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3.

[0104] Referring to FIGS. 9A to 9C, a gate insulating layer GI can be conformally formed in the first empty space ET1 and the second empty space ET2. The gate insulating layer GI can cover the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The gate insulating layer GI can extend to cover the inner surface of the gate spacer GS.

[0105] A first metal layer ML1 can be formed on the gate insulating layer GI. The first metal layer ML1 can be conformally formed on the gate insulating layer GI. The first metal layer ML1 can completely fill the second empty space ET2. The first metal layer ML1 can partially fill the first empty space ET1. The first metal layer ML1 can include a metal nitride layer. For example, the first metal layer ML1 can contain at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo) and nitrogen (N). In an embodiment, the first metal layer ML1 can further contain carbon (C). The first metal layer ML1 can include a plurality of work function metal layers stacked in sequence.

[0106] Referring to FIGS. 10A to 10C, the first metal layer ML1 can be locally removed by an etching process. As a result of the etching process, a first metal pattern MP1a and a first metal pattern MP1b can be formed on the first active region PR and the second active region NR, respectively. The etching process can be performed using a first mask pattern MS1 covering the second active region NR. In an embodiment, the first mask pattern MS1 can include a silicon oxide layer and / or a photoresist layer. The first metal pattern MP1a on the first active region PR can be partially left in the second empty space ET2 and removed from the first empty space ET1. The first metal layer ML1 on the second active region NR can be protected by the first mask pattern MS1. The etching process can be a wet etching process.

[0107] Referring to FIGS. 11A to 11C, the first mask pattern MS1 can be removed, and then an etch barrier pattern BP can be formed on the second active region NR. Forming the etch barrier pattern BP can include conformally forming an etch barrier layer and forming a second mask pattern MS2 on the second active region NR. The etch barrier pattern BP can be formed by etching the etch barrier layer using the second mask pattern MS2. The etch barrier pattern BP can cover an end portion EG1 of the first metal pattern MP1b on the second active region NR.

[0108] Specifically, as illustrated with reference to FIG. 2F, the etch barrier pattern BP can cover a side surface SF of the end portion EG1 of the first metal pattern MP1b. Thus, the end portion EG1 of the first metal pattern MP1b can be not exposed to an etchant solution used in the process of forming the etch barrier pattern BP. In an embodiment, the etch barrier pattern BP can be formed of or include a material different from that of the first metal patterns MP1a and MP1b and including at least one of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), or molybdenum (Mo) and nitrogen (N). Thus, at least a portion of the first metal pattern MP1b on the second active region NR can be not removed during the formation of the etch barrier pattern BP.

[0109] Referring to FIGS. 12A to 12C, the first metal pattern MP1a on the first active region PR can be selectively removed. This step can be performed using a fabrication method selected to minimize the removal of the etch barrier pattern BP. As a result of removing the first metal pattern MP1a, the second empty space ET2 on the first active region PR can be reopened.

[0110] Referring to FIGS. 13A to 13C, the second mask pattern MS2 can be removed, and then the second metal layer ML2 can be formed. The second metal pattern MP2a of the second metal layer ML2 formed on the first active region PR can be formed to fill the second empty space ET2 and partially fill the first empty space ET1. The second metal pattern MP2b of the second metal layer ML2 formed on the second active region NR can be formed to cover the etching barrier pattern BP in the first empty space ET1.

[0111] The second metal layer ML2 can include a metal nitride layer. For example, the first metal pattern MP1b can include at least one of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo) and nitrogen (N). In an embodiment, the second metal layer ML2 can further include carbon (C). The second metal layer ML2 can include a plurality of work function metal layers stacked in sequence.

[0112] Referring to FIGS. 14A to 14C, a third metal layer ML3 can be formed on the second metal layer ML2. The third metal layer ML3 can be formed of a metal material having a resistance lower than that of the first metal pattern MP1b or include a metal material having a resistance lower than that of the first metal pattern MP1b. For example, the third metal layer ML3 can be formed of at least one of tungsten (W), aluminum (Al), titanium (Ti), or tantalum (Ta) or include at least one of tungsten (W), aluminum (Al), titanium (Ti), or tantalum (Ta). The formation of the third metal layer ML3 can include a planarization process.

[0113] Referring back to FIGS. 1 and 2A to 2F, a gate cap pattern GP can be formed on the gate electrode GE. Specifically, forming the gate cap pattern GP can include etching an upper portion of the gate electrode GE and forming the gate cap pattern GP on the etched gate electrode GE.

[0114] A second interlayer insulating layer 120 can be formed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 can include a silicon oxide layer. The active contact AC can be formed to penetrate the second interlayer insulating layer 120 and the first interlayer insulating layer 110 and be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. The gate contact GC can be formed to penetrate the second interlayer insulating layer 120 and the gate cap pattern GP and be electrically connected to the gate electrode GE.

[0115] A pair of split structures DB can be formed on both sides of the logic cell. That is, the split structures DB can be formed on each side of the logic cell. The split structures DB can be formed to penetrate the second interlayer insulating layer 120, the remaining part of the sacrificial pattern PP, and the upper part of the active pattern AP1 or AP2 under the sacrificial pattern PP. The split structures DB can be formed of at least one of insulating materials (e.g., silicon oxide or silicon nitride) or include at least one of insulating materials (e.g., silicon oxide or silicon nitride).

[0116] A third interlayer insulating layer 130 can be formed on the active contact AC and the gate contact GC. A first metal layer M1 can be formed in the third interlayer insulating layer 130. A fourth interlayer insulating layer 140 can be formed on the third interlayer insulating layer 130. A second metal layer M2 can be formed in the fourth interlayer insulating layer 140.

[0117] When a work function metal is formed on each of the first active region PR and the second active region NR, a wet etching process can be performed to etch a part of the work function metal. In the case where there is penetration of the etching solution or patterning failure of the etching mask in this step, the work function metal may be over-etched or under-etched. Therefore, the boundary between the work function metals on the first active region PR and the second active region NR may not be formed at the desired position, and in such a case, it may be difficult to achieve the desired threshold voltage of the transistor. That is, the electrical characteristics of the semiconductor device may deteriorate.

[0118] According to an embodiment, an etching barrier pattern BP having an etching selectivity with respect to the work function metal can be used to prevent the work function metal from being damaged or misaligned, and thus the threshold voltage of the transistor can be prevented from being changed. Therefore, the electrical characteristics of the semiconductor device can be improved.

[0119] FIGS. 15A to 15C are cross-sectional views taken along lines A-A', B-B', and D-D' shown in FIG. 1, respectively. FIG. 15D is an enlarged cross-sectional view of a portion Q' shown in FIG. 15C. FIG. 15E is an enlarged cross-sectional view of a portion R' shown in FIG. 15D. For the sake of brevity of description, the previously described elements can be identified by the same reference numerals and will not be described again.

[0120] Referring to FIGS. 15A to 15E, the second electrode portion GE2 according to the embodiment shown in FIGS. 15A to 15E may include a first metal pattern MP1b, a second metal pattern MP2b, an etching barrier pattern BP, and a third metal pattern MP3b. The first metal pattern MP1b may be partially disposed in the second empty space ET2 and may not be disposed in the first empty space ET1. Different from the embodiment shown in FIGS. 2A to 2F, the first metal pattern MP1b may not extend to the region on the device isolation layer ST. For example, the first metal pattern MP1b of the second electrode portion GE2 may include a plurality of patterns spaced apart from each other in the third direction D3.

[0121] The etching barrier pattern BP may be in contact with the gate insulating layer GI. In an embodiment, the etching barrier pattern BP may be in contact with the top surface and the side surface of the gate insulating layer GI, as shown in FIGS. 15D and 15F. The second metal layer ML2 may have a stepped structure STP near the end portion EG2 of the etching barrier pattern BP.

[0122] FIGS. 16A to 21C are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment. FIGS. 16A, 17A, 18A, 19A, 20A, and 21A are cross-sectional views taken along line A-A' shown in FIG. 1. FIGS. 16B, 17B, 18B, 19B, 20B, and 21B are cross-sectional views taken along line B-B' shown in FIG. 1. FIGS. 16C, 17C, 18C, 19C, 20C, and 21C are cross-sectional views taken along line D-D' shown in FIG. 1. For simplicity of explanation, the previously described elements may be identified by the same reference numerals and will not be described again.

[0123] The method according to FIGS. 3A to 9C may be performed, and then referring to FIGS. 16A to 16C, an etching process may be performed on the structure shown in FIGS. 9A to 9C, and thus a first metal pattern MP1a located on the first active region PR and a first metal pattern MP1b located on the second active region NR may be formed from the first metal layer ML1. The first metal pattern MP1a on the first active region PR may be partially left in the second empty space ET2 and may be removed from the first empty space ET1. Different from the embodiment shown in FIG. 10C, since the first metal pattern MP1b on the second active region NR is formed without a mask pattern, the first metal pattern MP1b may be removed from the first empty space ET1 and may be partially left in the second empty space ET2.

[0124] Referring to FIGS. 17A to 17C, an etch barrier layer BL can be conformally formed. The etch barrier layer BL can be formed in the first empty space ET1 and can be in contact with the gate insulating layer GI. The etch barrier layer BL can be in contact with the side surfaces of the first metal patterns MP1a and MP1b covering the second empty space ET2.

[0125] Referring to FIGS. 18A to 18C, a first mask pattern MS1 can be formed to cover the second active region NR, and an etch barrier pattern BP can be formed on the second active region NR by removing the etch barrier layer BL on the first active region PR. The end portions of the etch barrier pattern BP are shown aligned with the side surfaces of the first mask pattern MS1, but in embodiments, the exposed portions of the etch barrier pattern BP can be partially removed to form a groove region.

[0126] Referring to FIGS. 19A to 19C, the first metal pattern MP1a on the first active region PR can be selectively removed. This step can be performed using a process selected to minimize the removal of the etch barrier pattern BP. As a result of removing the first metal pattern MP1a, the second empty space ET2 on the first active region PR can be reopened.

[0127] Referring to FIGS. 20A to 20C, the second mask pattern MS2 can be removed, and then a second metal layer ML2 can be formed. The second metal pattern MP2a of the second metal layer ML2 formed on the first active region PR can be formed to fill the second empty space ET2 and partially fill the first empty space ET1. The second metal pattern MP2b of the second metal layer ML2 formed on the second active region NR can be formed to cover the etch barrier pattern BP in the first empty space ET1.

[0128] Referring to FIGS. 21A to 21C, a third metal layer ML3 can be formed on the second metal layer ML2. Thereafter, the process described with reference to FIGS. 2A to 2D can be performed to form a semiconductor device according to the embodiments shown in FIGS. 15A to 15E.

[0129] FIGS. 22A to 29C are cross-sectional views showing a method of fabricating a semiconductor device according to an embodiment. FIGS. 22A, 23A, 24A, 25A, 26A, 27A, 28A, and 29A are cross-sectional views taken along line A-A' shown in FIG. 1. FIGS. 22B, 23B, 24B, 25B, 26B, 27B, 28B, and 29B are cross-sectional views taken along line B-B' shown in FIG. 1. FIGS. 22C, 23C, 24C, 25C, 26C, 27C, 28C, and 29C are cross-sectional views taken along line D-D' shown in FIG. 1. For simplicity of explanation, the previously described elements may be identified by the same reference numerals and will not be described again.

[0130] The method according to FIGS. 3A to 8C may be performed, and then referring to FIGS. 22A to 22C, an adjustment layer DL may be formed on the structure shown in FIGS. 8A to 8C. The adjustment layer DL may be formed to contact the gate insulating layer GI and cover the first empty space ET1 and the second empty space ET2. In an embodiment, the adjustment layer DL may include a lanthanum oxide layer or an aluminum oxide layer. In an embodiment, the adjustment layer DL may be used to precisely adjust the threshold voltage of the transistor.

[0131] Referring to FIGS. 23A to 23C, an etching assist pattern PB may be formed. The etching assist pattern PB may be formed by forming a metal nitride layer and patterning the metal nitride layer. In an embodiment, the etching assist pattern PB may be formed of at least one of metal nitride materials (e.g., TiN or TaN) or include at least one of metal nitride materials (e.g., TiN or TaN). The etching assist pattern PB may be formed in the second empty space ET2 and may not remain in the first empty space ET1.

[0132] Referring to FIGS. 24A to 24C, an etching barrier layer CL may be formed to cover the side surfaces of the adjustment layer DL and the etching assist pattern PB. The etching barrier layer CL may be formed of the same material as the etching barrier pattern BP described with reference to FIGS. 2A to 2F or include the same material as the etching barrier pattern BP. In an embodiment, the etching barrier layer CL may be formed of at least one of TiAlN, TaAlC, TiN, or TaN or include at least one of TiAlN, TaAlC, TiN, or TaN. The etching barrier layer CL may be thicker than the adjustment layer DL. Thereafter, a third mask pattern MS3 may be formed to cover the second active region NR.

[0133] Referring to FIGS. 25A to 25C, an etch barrier pattern CP can be formed on the second active region NR by patterning the etch barrier layer CL by using the third mask pattern MS3 as an etch mask. The adjustment layer DL and the etch assist pattern PB on the first active region PR can be exposed to the outside.

[0134] Referring to FIGS. 26A to 26C, the etch assist pattern PB on the first active region PR can be selectively removed to expose the adjustment layer DL. The adjustment layer DL can remain on the first active region PR.

[0135] Referring to FIGS. 27A to 27C, a process of patterning the adjustment layer DL by using the third mask pattern MS3 as an etch mask can be performed to expose the second empty space ET2 of the first active region PR. Accordingly, an adjustment pattern DP can be formed on the second active region NR. The etch barrier pattern CP on the second active region NR can not be removed.

[0136] Referring to FIGS. 28A to 28C, the third mask pattern MS3 can be removed, and then the etch barrier pattern CP can be selectively removed. Accordingly, the side surface of the etch assist pattern PB on the second active region NR can be exposed.

[0137] Referring to FIGS. 29A to 29C, the etch assist pattern PB on the second active region NR can be selectively removed. Accordingly, the adjustment pattern DP on the second active region NR can be exposed.

[0138] Thereafter, a heat treatment process can be performed. As a result of the heat treatment process, elements of the adjustment pattern DP can diffuse into the gate insulating layer GI or toward the surfaces of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. Next, the process described with reference to FIGS. 9A to 21C can be performed.

[0139] FIG. 30 is an enlarged cross-sectional view showing a part of the structure shown in FIG. 2D and particularly showing a part of the structure formed by performing the process shown in FIGS. 9A to 21C after the heat treatment process. As shown in FIG. 30, the adjustment pattern DP can be completely removed, but the elements diffused from the adjustment pattern DP can remain in the gate insulating layer GI or on the surfaces of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3.

[0140] The concentration of the adjustment element for self-adjusting pattern DP diffusion can vary depending on the position. Such a variation may cause a difference in the etching method between the etching processes performed to form the adjustment pattern DP. In an embodiment, etching agent materials different from each other may be used to perform the process of removing the etching barrier pattern CP (e.g., in FIGS. 28A to 28C) and the process of removing the etching assist pattern PB (e.g., in FIGS. 29A to 29C), and thus the concentration of the adjustment element in the internal region IR covered by the etching assist pattern PB may be different from the concentration of the adjustment element in the external region OR not covered by the etching assist pattern PB. In an embodiment, the internal region IR may have a higher aluminum concentration than the external region OR. In another embodiment, the external region OR may have a higher lanthanum concentration than the internal region IR.

[0141] According to various embodiments described herein, a semiconductor device having improved electrical characteristics may be provided.

[0142] Although the exemplary embodiments have been specifically shown and described, those of ordinary skill in the art should understand that changes in form and detail may be made thereto without departing from the spirit and scope of the appended claims.

[0143] 100: Substrate 110: First interlayer insulating layer 120: Second interlayer insulating layer 130: Third interlayer insulating layer 140: Fourth interlayer insulating layer A - A’, B - B’, C - C’, D - D’: Lines AC: Active contact ACL: Active layer AP1: First active pattern / Active pattern AP2: Second active pattern / Active pattern BL, CL: Etching barrier layer BM: Barrier pattern BP, CP: Etching barrier pattern CB1: First cell boundary CB2: Second cell boundary CH1: First channel pattern CH2: Second channel pattern D1: First direction D2: Second direction D3: Third direction DB: Division structure DL: Adjustment layer DP: Adjustment pattern EG1, EG2: End portions ET1: First empty space ET2: Second empty space FM: Conductive pattern GC: Gate contact GE: Gate electrode GE1: First electrode portion GE2: Second electrode portion GI: Gate insulating layer GP: Gate cap pattern GS: Gate spacer IP: Internal spacer IR: Internal region M1, ML1: First metal layer M1_I: Second lower interconnect / lower interconnect M1_R: First lower interconnect / lower interconnect M2, ML2: Second metal layer M2_I: Upper interconnect MK: Hard mask pattern ML3: Third metal layer MP1a, MP1b: First metal pattern MP2a, MP2b: Second metal pattern MP3a, MP3b: Third metal pattern MS1: First mask pattern MS2: Second mask pattern MS3: Third mask pattern NR: Second active region / region OR: External region P1: First pitch P2: Second pitch P3: Third pitch PB: Etching assist pattern PP: Sacrificial pattern PR: First active region / region Q, Q’, R, R’: Portions RS1: First groove RS2: Second groove SAL: Sacrificial layer SC: Silicide pattern SD1: First source / drain pattern / source / drain pattern SD2: Second Source / Drain Pattern / Source / Drain Pattern SEL1: First Semiconductor Layer SEL2: Second Semiconductor Layer SF: Side Surface SP1: First Semiconductor Pattern SP2: Second Semiconductor Pattern SP3: Third Semiconductor Pattern ST: Device Isolation Layer STP: Step Structure TR1: First Trench TR2: Second Trench UIP: Upper Insulation Pattern VDD: Drain Voltage VI1: Lower Via VI2: Upper Via VSS: Source Voltage Y1: First Portion Y2: Second Portion Y3: Third Portion

Claims

1. A semiconductor device, comprising: The substrate includes a first active region and a second active region that are adjacent to each other; A first active pattern and a second active pattern are respectively disposed on the first active region and the second active region; and a gate electrode extends to intersect with the first active pattern and the second active pattern, wherein the gate electrode includes a first electrode portion located on the first active region and a second electrode portion located on the second active region, the second electrode portion includes a first metal pattern, an etched barrier pattern, a second metal pattern and a third metal pattern sequentially covering the second active pattern, the first electrode portion includes a second metal pattern covering the first active pattern, the etched barrier pattern is in contact with the first metal pattern and the second metal pattern of the second electrode portion, the etched barrier pattern is thinner than the first metal pattern and thinner than the second metal pattern of the second electrode portion, the substrate further includes a device isolation layer located between the first active region and the second active region, the end portion of the first metal pattern is disposed on the device isolation layer, the end portion of the etched barrier pattern is disposed on the device isolation layer and covers the end portion of the first metal pattern, and the end portion of the etched barrier pattern includes a first portion covering the top surface of the first metal pattern and a second portion covering the side surface of the first metal pattern.

2. The semiconductor device of claim 1, wherein the second metal pattern of the first electrode portion has the same thickness and comprises the same material as the second metal pattern of the second electrode portion.

3. The semiconductor device of claim 2, wherein the second metal pattern of the first electrode portion and the second metal pattern of the second electrode portion are connected to each other on the device isolation layer.

4. The semiconductor device of claim 1, wherein the etched barrier pattern comprises a material having etch selectivity relative to the first metal pattern of the second electrode portion.

5. The semiconductor device of claim 4, wherein the etched barrier pattern comprises at least one of TiAlN, TiAlC, TiN, and TaN.

6. The semiconductor device of claim 1, wherein the etched barrier pattern extends from the end portion to a region on the device isolation layer.

7. The semiconductor device of claim 1, wherein the second active pattern comprises sequentially stacked semiconductor patterns, and the first metal pattern of the second electrode portion extends into the region between the semiconductor patterns.

8. The semiconductor device of claim 1, further comprising a gate insulating layer located between the second active pattern and the second electrode portion, wherein the second active pattern comprises sequentially stacked semiconductor patterns, the first metal pattern of the second electrode portion is disposed between the semiconductor patterns, and the etched barrier pattern is in contact with the gate insulating layer.

9. The semiconductor device of claim 8, wherein the first metal pattern of the second electrode portion comprises a plurality of electrode portions spaced apart from each other, the semiconductor pattern being sandwiched between the plurality of electrode portions.

10. The semiconductor device of claim 1, wherein the first electrode portion further includes a third metal pattern covering the second metal pattern of the first electrode portion, and the third metal pattern of the second electrode portion covers the second metal pattern of the second electrode portion.

11. The semiconductor device of claim 10, wherein the third metal pattern of the first electrode portion is connected to the third metal pattern of the second electrode portion.

12. A semiconductor device, comprising: The substrate includes a first active region and a second active region that are adjacent to each other; A first active pattern and a second active pattern are respectively disposed on the first active region and the second active region; a gate electrode extends to intersect with the first active pattern and the second active pattern; and a gate insulating layer is disposed between the gate electrode and the first active region and between the gate electrode and the second active region, wherein the gate electrode includes a first electrode portion located on the first active region and a second electrode portion located on the second active region, the second electrode portion includes a first metal pattern, an etched barrier pattern and a second metal pattern sequentially covering the second active pattern, the first electrode portion includes a second metal pattern covering the first active pattern, the etched barrier pattern contacts the first metal pattern and the second metal pattern of the second electrode portion, and the etched barrier pattern contacts the gate insulating layer.

13. The semiconductor device of claim 12, wherein the second active pattern comprises sequentially stacked semiconductor patterns, and the first metal pattern of the second active pattern comprises a plurality of electrode portions spaced apart from each other, the semiconductor pattern being sandwiched between the plurality of electrode portions.

14. The semiconductor device of claim 13, wherein the first metal pattern extends to a side surface of the semiconductor pattern and the first metal pattern contacts the gate insulating layer.

15. The semiconductor device of claim 12, wherein the substrate further includes a device isolation layer located between the first active region and the second active region, and the second metal pattern of the first electrode portion and the second metal pattern of the second electrode portion are connected to each other on the device isolation layer.

16. The semiconductor device of claim 12, wherein the etched barrier pattern comprises a material having etch selectivity relative to the first metal pattern of the second electrode portion.

17. The semiconductor device of claim 16, wherein the etched barrier pattern comprises at least one of TiAlN, TiAlC, TiN, and TaN.

18. A semiconductor device, comprising: The substrate includes a first active region and a second active region that are adjacent to each other in a first direction; A device isolation layer fills a trench, the trench being formed to define the first active region and the second active region; a first active pattern and a second active pattern are respectively disposed on the first active region and the second active region; a first source / drain pattern and a second source / drain pattern are respectively disposed on the first active pattern and the second active pattern; a first channel pattern and a second channel pattern are respectively connected to the first source / drain pattern and the second source / drain pattern, each of the first channel pattern and the second channel pattern including a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern stacked and spaced apart from each other; a gate electrode extends in the first direction to intersect the first channel pattern and the second channel pattern; a gate insulating layer is sandwiched between the gate electrode and the first channel pattern and between the gate electrode and the second channel pattern; a gate spacer is disposed on the side surface of the gate electrode; a gate top cover pattern is disposed on the top surface of the gate electrode; a first interlayer insulating layer is located on the gate top cover pattern; An active contact penetrates the first interlayer insulating layer and is coupled to the first source / drain pattern and the second source / drain pattern, respectively; a gate contact penetrates the first interlayer insulating layer and is coupled to the gate electrode; a second interlayer insulating layer is located on the first interlayer insulating layer; a first metal layer is disposed in the second interlayer insulating layer, the first metal layer including lower internal interconnects electrically connected to the active contact and the gate contact, respectively; a third interlayer insulating layer is located on the second interlayer insulating layer; and a second metal layer is disposed in the third interlayer insulating layer, wherein the second metal layer includes upper internal interconnects electrically connected to the lower internal interconnects, the gate electrode includes a first electrode portion located on the first active region and a second electrode portion located on the second active region, the second electrode portion including a first metal pattern, an etched barrier pattern, and a second metal pattern sequentially covering the second active pattern, and the first electrode portion including a second metal pattern covering the first active pattern. The etched barrier pattern is in contact with the first metal pattern and the second metal pattern of the second electrode portion, and the etched barrier pattern is thinner than the first metal pattern and thinner than the second metal pattern of the second electrode portion.

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