Semiconductor-superconductor hybrid devices with a horizontally-confined channel and methods of forming the same

Abstract

A semiconductor-superconductor hybrid device with horizontally confined channels and a method for forming the same. An exemplary semiconductor-superconductor hybrid device includes a semiconductor heterostructure formed over a substrate. The semiconductor-superconductor hybrid device may further include a superconducting layer formed over the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a first gate having a first top surface and formed adjacent to a first side of the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a second gate having a second top surface and formed adjacent to a second side of the semiconductor heterostructure relative to the first side, wherein each of the first top surface of the first gate and the second top surface of the second gate is vertically offset from a selected surface of the semiconductor heterostructure by a predetermined offset.

Description

[Technical Field]

[0001] This disclosure relates to a semiconducting superconducting hybrid device with a horizontally confined channel and a method for forming the same. [Previous Technology]

[0002] Currently, devices such as topological nanowires are fabricated by patterning a superconductor formed in a wafer, electrostatically defining lines from top to bottom. The patterning of the superconductor defines the electrostatic potential of the channels associated with the nanowires. However, the patterning of the superconductor causes the electrostatic potential of the channels to be affected by the line edge roughness (LER) of the superconductor, which in turn reduces the size of the topological gaps. Furthermore, since the electrostatic channels are formed close to the wafer surface, they are affected by charge scattering effects.

[0003] Therefore, there is a need for improved devices that are not easily affected by charge scattering effects and are not affected by the LER of patterned superconductors. [Summary of the Invention]

[0004] In one example, this disclosure relates to a semiconductor-superconductor hybrid device including a semiconductor heterostructure formed over a substrate. The semiconductor-superconductor hybrid device may further include a superconducting layer formed over the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a first gate having a first top surface and formed adjacent to a first side of the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a second gate having a second top surface and formed adjacent to a second side of the semiconductor heterostructure relative to the first side, wherein each of the first top surface of the first gate and the second top surface of the second gate is vertically offset from a selected surface of the semiconductor heterostructure by a predetermined offset.

[0005] In another embodiment, this disclosure relates to a semiconductor-superconductor hybrid device including a semiconductor heterostructure formed over a substrate. The semiconductor-superconductor hybrid device may further include a superconducting layer formed over the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a first gate having a first top surface and formed adjacent to a first side of the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a second gate having a second top surface and formed adjacent to a second side of the semiconductor heterostructure relative to the first side, wherein each of the first top surface of the first gate and the second top surface of the second gate is vertically offset from a selected surface of the semiconductor heterostructure by a predetermined offset, the predetermined offset being selected to ensure the formation of a horizontally confined electrostatic channel at a selected distance from the selected surface of the semiconductor heterostructure to reduce the effects of any line edge roughness (LER) associated with the superconducting layer.

[0006] In yet another embodiment, this disclosure relates to a semiconductor-superconductor hybrid device, including a first and a second isolating semiconductor heterostructure formed on a substrate. The semiconductor-superconductor hybrid device may further include a left gate, which is formed adjacent to a first side of each of the first and second isolating semiconductor heterostructures. The semiconductor-superconductor hybrid device may further include a right gate, which is formed adjacent to a second side of each of the first and second isolating semiconductor heterostructures opposite to the first side, wherein the top surfaces of each of the left and right gates are vertically offset from selected surfaces of each of the first and second isolating semiconductor heterostructures by a predetermined offset. The semiconductor-superconductor hybrid device may further include a superconducting layer formed on each of the first and second isolating semiconductor heterostructures.

[0007] This summary is provided to introduce some conceptual choices in a simplified form, which are further illustrated in the embodiments below. This summary is not intended to identify key or essential features of the claimed technical subject matter, nor is it intended to limit the scope of the claimed technical subject matter.

Implementation Method

[0029] The examples described in this disclosure relate to semiconductor-superconductor hybrid devices having horizontally confined channels and methods for forming the same. Some examples relate to semiconductor-superconductor hybrid devices in which electrostatic channels (e.g., two-dimensional electron gas (2-DEG) channels) can be horizontally confined within a semiconductor heterostructure. Some examples also relate to topological nanowires that can be realized using confined horizontally confined electrostatic channels. Such semiconductor heterostructures can be formed using materials from Group III and Group V of the periodic table. Furthermore, such semiconductor heterostructures can also be formed using materials from Group II, Group IV, or Group VI of the periodic table. Topological nanowires can be formed using chemical beam epitaxy or molecular beam epitaxy and then transferred to a substrate to form the source, drain, and gate aspects of the device. Furthermore, these materials can be used to form topological nanowires using selective region growth (SAG) techniques.

[0030] Various materials can be grown in situ on a semiconductor wafer to form the example device. The example semiconductor wafer includes a wafer formed using indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), mercury cadmium telluride (HgCdTe), or any suitable combination of materials selected from Groups III, III, IV, V, and VI of the periodic table, or a wafer formed using any ternary compound of three different atoms selected from Groups II, III, IV, V, and VI of the periodic table. For example, the wafer can be formed by epitaxially growing any of these material combinations on a substrate. Topological nanowires can be formed on such a wafer by forming a superconductor-semiconductor interface.

[0031] During the formation of such a device, a mask (or multiple masks) can be used to define the topological active region of the device. The topological active region may include quantum wells, such as InAs quantum wells or GaAs quantum wells. For such devices, the interface between the topological active region (including a superconducting metal layer (e.g., an aluminum layer)) and the topological inactive region (excluding a metal layer (e.g., an aluminum layer)) is important. Direct in-situ deposition of superconductors (such as epitaxial growth of aluminum) after semiconductor growth improves the quality of the superconducting gap. However, this technique introduces additional fabrication challenges. For example, aluminum must be removed to define the topological region of the device. Selective wet etching solutions for aluminum are highly exothermic and can damage the semiconductor. This damage to the semiconductor leads to an increase in the line edge roughness (LER) of the superconductor, which in turn reduces the size of the topological gap.

[0032] Furthermore, the etching step disrupts the interface between the topological active and non-active regions. Some of this damage corresponds to charged surface states that may interfere with device operation. This is because the quantum well is formed at a relatively shallow depth (e.g., within approximately 10 nm of the surface). Charged surface states can interfere with the quality of the 2-DEG. Similarly, other structures, such as nanowires grown using the VLS method, may also be damaged.

[0033] Figure 1 shows a view 100 of an example semiconductor-superconductor hybrid device 10 in a stage of processing. In this example, as part of this step, a semiconductor heterostructure 110 can be formed on a substrate 102. The substrate 102 can be any type of suitable substrate, including an indium phosphide (InP) substrate. The semiconductor heterostructure 110 can include a buffer layer 112 and a quantum well layer 114. The semiconductor heterostructure 110 can also include another buffer layer 116 formed on top of the quantum well layer 114 to complete the formation of a heterostructure corresponding to one or more superconducting quantum wells. Each of these layers can be formed using molecular beam epitaxy (MBE). As an example, MBE-related processes can be performed in an MBE system that allows the deposition of suitable materials (e.g., III-V semiconductor materials) in a vacuum. The buffer layer 116 may not be necessary to complete the formation of certain types of quantum wells.

[0034] In this example, substrate 102 may be an indium phosphide (InP) substrate. Buffer layer 112 may be an indium gallium arsenide (InGaAs) layer. Quantum well layer 114 may be an indium arsenide (InAs) layer. Buffer layer 116 may be an indium aluminum arsenide (InAlAs) layer. Although FIG. 1 shows a certain number of layers of the semiconductor-superconductor hybrid device 10 arranged in a certain way, there may be more or fewer layers with different arrangements. As an example, substrate 102 may include indium arsenide, indium antimonide, indium antimonide arsenide, or similar substrate materials. In addition, each buffer layer may include other materials, including aluminum, lead, niobium, tin, tantalum, or vanadium. Moreover, each buffer layer does not need to include the same group of materials and may include different materials. In one example, the semiconductor heterostructure may include a first layer of indium arsenide or aluminum arsenide, a second layer of indium arsenide, and a third layer of indium arsenide or gallium arsenide. In addition, although FIG. 1 does not show a capping layer, a capping layer may be formed on the semiconductor heterostructure 110 to protect the top surface of the semiconductor heterostructure from oxidation or other process-induced changes. This capping layer can be a gallium arsenide layer or an aluminum arsenide layer. Other materials that can help protect the semiconductor heterostructure may include materials such as alumina, niobium, or other suitable materials. Furthermore, the semiconductor-superconductor hybrid device 10 may include additional or fewer intermediate layers besides those shown in FIG. 1. As an example, the semiconductor-superconductor hybrid device 10 may be formed as a one-dimensional nanowire.

[0035] Figure 2 shows a view 200 of the exemplary semiconductor-superconductor hybrid device 10 of Figure 1 in a subsequent stage of processing. In this stage of processing, a superconducting metal layer 120 may be formed on top of the semiconductor heterostructure 110. In this example, the superconducting metal layer 120 may be deposited using an MBE (Metal-Based Electron Equivalent). Any superconductor exhibiting an electron pairing periodicity associated with the presence of Cooper pairs can be used to form the superconducting metal layer 120. Example materials that can be used to form the superconducting metal layer 120 include, but are not limited to, lead, indium, tin, and aluminum. Although Figure 2 shows a certain number of layers of the semiconductor-superconductor hybrid device 10 arranged in a certain way, there may be more or fewer layers with different arrangements.

[0036] Figure 3 shows a view 300 of the exemplary semiconductor-superconductor hybrid device 10 of Figure 2 in a subsequent stage of processing. As part of this step, a portion 302 of the superconducting metal layer 120 may be selectively removed. This step may be performed using wet etching or dry etching. A mask may be used to define the topological active region of the topological quantum computing device. The topological active region may include quantum wells, such as InAs quantum wells or GaAs quantum wells. For the purposes of topological quantum computing, the interface between the topological active region (including the metal layer (e.g., aluminum layer)) and the topological non-active region (excluding the metal layer (e.g., aluminum layer)) is important. The etching step may damage the surface (e.g., 304) of the portion 302 of the superconducting metal layer 120 exposed as a result of the etching step, including the interface between the topological active region and the topological non-active region. Some of this damage corresponds to charged surface states that may interfere with the operation of the semiconductor-superconductor hybrid device 10. This is because the quantum well (or similar structure) is formed at a relatively shallow depth (e.g., within approximately 10 nm of the surface). Charged surface states can interfere with the quality of electrostatic channels (e.g., 2-DEG channels). Similarly, other structures, such as nanowires grown using VLS or SAG methods, can also be damaged.

[0037] Figure 4 shows a view 400 of the exemplary semiconductor-superconductor hybrid device 10 of Figure 3 in a subsequent stage of processing. In this stage of processing, each side of the semiconductor heterostructure 110 can be selectively etched away to expose these sides. Additionally, as part of this step, each side of the superconducting metal layer 120 can also be removed. These selective removals of materials can be performed using wet etching or dry etching. In this example, the selective removal of these materials results in the formation of a semiconductor-superconductor hybrid structure with a specific aspect ratio defined by the ratio of its width (B) to its depth (A). In one example, assuming a width B of 100 nm and a depth A of 100 nm, this would result in an aspect ratio of 1. However, the aspect ratio does not have to be 1; it can be less than or greater than 1. Process node size and associated technical limitations can determine the aspect ratio and the corresponding values ​​for depth A and width B. In this example, the purpose of exposing the sides is to allow the formation of gates on each side of the semiconductor heterostructure 110.

[0038] Figure 5 shows a view 500 of the exemplary semiconductor-superconductor hybrid device 10 of Figure 4 in a subsequent stage of processing. In this stage of processing, two steps can be performed. First, as shown in Figure 5, a dielectric layer 130 can be formed. Second, gates 142 and 144 can be formed, as shown in Figure 5. The dielectric layer 130 can be conformally deposited (or otherwise formed) on the top surface of the semiconductor-superconductor hybrid device 10 of Figure 4 using techniques such as atomic layer deposition. The material used to form the dielectric layer 130 can include oxides (e.g., alumina or hafnium oxide) or nitrides. Additionally, spin-coated dielectrics such as polyimide can also be used to form the dielectric layer 130. Example organic-based dielectric materials can include silsesquioxane (HSQ), benzocyclobutene (BCB), etc. Such materials may require curing and additional processing. Each of gates 142 and 144 can be formed using materials such as gold or titanium. Other materials can also be used. The gates can be configured such that each of the left gate (e.g., gate 142) and the right gate (e.g., gate 144) is vertically offset by a predetermined amount from a selected surface (e.g., the top surface) of the semiconductor heterostructure. Additional details regarding the arrangement and offset of the gates are provided with reference to Figure 6 and the associated description. Although Figure 5 shows a certain number of layers of the semiconductor-superconductor hybrid device 10 arranged in a certain way, there can be more or fewer layers with different arrangements.

[0039] Figure 6 illustrates the operation of the exemplary semiconductor-superconductor hybrid device described herein, which includes the semiconductor-superconductor hybrid device 10 of Figure 5 and includes a horizontally confined channel. This operation is explained in terms of the horizontal confinement of the electrostatic channel and the tunability aspects associated with the semiconductor-superconductor hybrid device 10, particularly when used as a nanowire. View 610 shows a side view of the semiconductor-superconductor hybrid device 10, and View 620 shows a top view of the semiconductor-superconductor hybrid device 10. Each of these views is only used to illustrate the operation of the semiconductor-superconductor hybrid device 10 with a horizontally confined electrostatic channel and is not intended to limit the various ways in which such a device can be formed. As previously stated, the patterning of the superconductor (e.g., the superconducting metal layer 120) causes the electrostatic potential of the channel to be affected by the line edge roughness (LER) of the superconductor (e.g., the LER associated with the superconductor formed on the top surface of the semiconductor heterostructure as shown in Figure 6), which in turn reduces the size of the topological gap. Furthermore, since in conventional devices, the electrostatic channel is formed near the wafer surface, the channel is subject to charge scattering effects. However, the gates (e.g., GATE1 and GATE2) formed on each side of the semiconductor heterostructure create a horizontally confined electrostatic channel (e.g., the horizontally confined channel (dashed line) shown in Figure 6), located further away from the top surface of the semiconductor heterostructure. This, in turn, causes electrons in the electrostatic channel to move away from the structural disorder (e.g., roughness and / or thickness variations of the top barrier layer) caused by the etching steps described above. The improvement in electrostatic channel quality due to the offset (e.g., the distance between the top surfaces of GATE1 and GATE2 and the top surface of the semiconductor heterostructure) can be determined by testing device samples. Improvements in mobility and electron density within the horizontally confined electrostatic channel can be tested. Mobility may relate to how far electrons travel within the channel before being scattered or otherwise affected. The offset, as represented by distance D in this example, can be optimized by testing several batches of samples with different offsets. Alternatively or additionally, device behavior including channel characteristics can be simulated to determine the appropriate offset.

[0040] Continuing to refer to Figure 6, applying different amounts of voltage to the gates (e.g., GATE1 and GATE2) located on each side of the horizontally confined channel allows for variation in the size of the stop gap defined by the geometry of the nanowire. In this example, GATE1 may correspond to gate 142 of Figure 5, and GATE2 may correspond to gate 144 of Figure 5. The voltage applied to the gates (e.g., via terminals T1 and T2) generates an electric field that can move electrons within the horizontally confined channel. In one example, assuming the voltage applied to the gates produces a voltage difference of 2 volts, then the nanowire (shown as a dashed line in view 620) could be a 100 nm wide nanowire. In another example, assuming the voltage applied to the gates produces a voltage difference of 4 volts, then the same nanowire could be a 50 nm wide nanowire. In summary, applying appropriate voltages through the gates (e.g., GATE1 and GATE2) allows for modulation of the width of the nanowires formed as part of the semiconductor-superconductor hybrid device 10 of Figure 5. Furthermore, as mentioned earlier, damage to the semiconductor during the formation of such a device leads to an increase in the line edge roughness (LER) of the superconductor, which in turn reduces the size of the topological gap. In the fabrication of the semiconductor-superconductor hybrid device described herein, tunability allows for more relaxed process constraints.

[0041] Still referring to Figure 6, the tunability provided by the gates on each side of the horizontally confined electrostatic channels of the semiconductor-superconductor hybrid device 10 can offer additional advantages. For example, the size of the topological gap associated with the semiconductor-superconductor hybrid device 10 is a function of many process and material-related aspects. Therefore, a single subband scheme may vary from device to device depending on the materials and processes used to fabricate the device. However, the tunability of the horizontally confined electrostatic channels allows for fine-tuning of the channels, even in a single subband scheme, to achieve the desired topological gap. Another potential advantage may relate to the ability to use the same set of materials and processes for multi-window stacks and other more complex nanowire arrangements. This is because the corresponding nanowires can be tuned to the desired subband scheme by applying an appropriate voltage to the gates associated with the corresponding horizontally confined electrostatic channels. Furthermore, this tunability can be particularly useful when the energy separation between subbands is very low in a multi-subband scheme.

[0042] A suitable voltage for the gate can be coupled to the gate through a power grid formed as part of an integrated circuit identical to the semiconductor-superconductor hybrid device 10. The power grid can be coupled through vias or other interconnect structures formed as part of the integrated circuit. The voltage itself can be generated using a voltage regulator that includes a controller associated with the integrated circuit. This controller can be separate from or integrated with the integrated circuit, which includes multiple instances of semiconductor-superconductor hybrid devices used as nanowires or other types of topological quantum computing devices.

[0043] Figure 7 shows a view 700 of another exemplary semiconductor-superconductor hybrid device 20 during the processing stage. The semiconductor-superconductor hybrid device 20 may include a semiconductor heterostructure wafer 210 covered with a capping layer 212. The semiconductor heterostructure wafer 210 may be formed using materials previously discussed in a manner similar to that described earlier with respect to Figure 1. The capping layer 212 may be formed on the semiconductor heterostructure wafer 210 to protect the top surface of the semiconductor heterostructure from oxidation or other process-induced changes. This capping layer may be a gallium arsenide layer or an aluminum arsenide layer. Other materials that may help protect the 2-DEG may include materials such as alumina, niobium, or other suitable materials. Furthermore, the semiconductor-superconductor hybrid device 20 may include additional or fewer intermediate layers besides those shown in Figure 7.

[0044] Figure 8 shows a view 800 of the exemplary semiconductor-superconductor hybrid device 20 of Figure 7 in a subsequent stage of processing. This processing state corresponds to the patterning of the semiconductor heterostructure wafer 210. Photolithography can be used to form a mask with the desired pattern, which can then be transferred to the semiconductor heterostructure wafer 210 using isotropic etching (or other types of techniques for removing material to form a structure). In this example, the isotropic etching step can result in the formation of isolated semiconductor heterostructures 214, 216, and 218, where the capping layer 212 is now retained only on the isolated semiconductor heterostructures formed as part of this step. Each isolated semiconductor heterostructure can have a specific aspect ratio similar to that described earlier with respect to Figure 4. In one example, the aspect ratio can be less than 1 or greater than 1. Process node size and associated technology limitations can determine the aspect ratio. In this example, the purpose of exposing the sides is to allow the formation of gates on each side of the isolated semiconductor heterostructures 214, 216, and 218. Furthermore, the spacing between each of the isolated semiconductor heterostructures 214, 216, and 218 can be selected to ensure functional and electrical isolation for the operation of these structures. Although Figure 8 shows a certain number of layers of the semiconductor-superconductor hybrid device 20 arranged in a certain way, there can be more or fewer layers with different arrangements.

[0045] Figure 9 shows a view 900 of the exemplary semiconductor-superconductor hybrid device 20 of Figure 8 in a subsequent stage of processing. In this stage of processing, a dielectric layer 220 may be conformally deposited on top of isolated semiconductor heterostructures 214, 216, and 218. Subsequently, a metal layer 222 may be formed on top of the dielectric layer 220. The dielectric layer 220 may be conformally deposited (or otherwise formed) using techniques such as atomic layer deposition. Materials used to form the dielectric layer 220 may include oxides (e.g., alumina or hafnium oxide) or nitrides. Additionally, spin-coated dielectrics such as polyimide may also be used to form the dielectric layer 220. Example organic-based dielectric materials may include silsesquioxane (HSQ), benzocyclobutene (BCB), etc. Such materials may require curing and additional processing. In one example, the dielectric layer 220 may have a thickness in the range of 5 nm to 10 nm.

[0046] Referring again to FIG9, a metal layer 222 may be formed using atomic layer deposition. The metal layer 222 may include aluminum, cobalt, or another metal suitable for use as a gate electrode. Although FIG9 shows a certain number of layers of the semiconductor-superconductor hybrid device 20 arranged in a certain way, there may be more or fewer layers with different arrangements.

[0047] Figure 10 shows a view 1000 of the exemplary semiconductor-superconductor hybrid device 20 of Figure 9 in a subsequent stage of processing. As part of this step, a dielectric material can be used to complete the filler 224. Any dielectric material that allows conformal deposition (e.g., a suitable oxide or nitride) can be used to produce the filler 224. Alternatively, a dielectric such as polyimide can also be used. Although Figure 10 shows a certain number of layers of the semiconductor-superconductor hybrid device 20 arranged in a certain way, there can be more or fewer layers with different arrangements.

[0048] Figure 11 shows a view 1100 of the exemplary semiconductor-superconductor hybrid device 20 of Figure 10 in a subsequent stage of processing. In this stage of processing, the filler 224 associated with the semiconductor-superconductor hybrid device 20 can be planarized. Any of chemical polishing, mechanical polishing, or chemical mechanical polishing (CMP) can be used as part of this step. The polishing step can be used to remove sufficient material to expose the previously described capping layer 212.

[0049] Figure 12 shows a view 1200 of the exemplary semiconductor-superconductor hybrid device 20 of Figure 11 in a subsequent stage of processing. In this processing stage, a portion of the metal layer 222 may be selectively etched to remove a portion of the metal layer 222 along the sidewalls of each of the isolated semiconductor heterostructures 214, 216, and 218. Any etching chemical that is selective to the metal used to form the metal layer 222 may be used as part of this step. As an example, assuming the metal layer 222 is formed using aluminum, a Transene Etchant Type D etching chemical may be used. As another example, assuming the metal layer 222 is formed using cobalt, citric acid or a similar etching chemical may be used. Additional details about this step are provided by showing a portion 1210 of view 1200 as an extended view 1300 in Figure 13. As shown in Figure 13, the removal of a portion of the metal layer 222 results in the top surface of each gate being identical to the surface of the top layer labeled as the gate metal layer after selective etching. In Figure 13, the letter D indicates the offset between the top surface of the semiconductor heterostructure and the top surfaces of each of the left and right gates. Although Figure 12 shows a certain number of layers of the semiconductor-superconductor hybrid device 20 arranged in a certain way, there can be more or fewer layers with different arrangements.

[0050] Figure 14 shows a view 1400 of the exemplary semiconductor-superconductor hybrid device 20 of Figure 12 in a subsequent stage of processing. As part of this step, a dielectric material can be used to complete the fill 230. The purpose of this step is to ensure that the grooves created by the selective etching of the metal layer 222 are properly filled without keyholes or other types of cavitation. Any dielectric material that allows conformal deposition (e.g., a suitable oxide or nitride) can be used to produce the fill 230. Alternatively, a dielectric such as polyimide can also be used. Although Figure 14 shows a certain number of layers of the semiconductor-superconductor hybrid device 20 arranged in a certain way, there can be more or fewer layers with different arrangements.

[0051] Figure 15 shows a view 1500 of the exemplary semiconductor-superconductor hybrid device 20 of Figure 14 in a subsequent stage of processing. In this stage of processing, the filler 230 associated with the semiconductor-superconductor hybrid device 20 can be planarized. Any of chemical polishing, mechanical polishing, or chemical mechanical polishing (CMP) can be used as part of this step. The polishing step can be used to remove sufficient material to expose the previously described capping layer 212.

[0052] Figure 16 shows a view 1600 of the exemplary semiconductor-superconductor hybrid device 20 of Figure 15 in a subsequent stage of processing. In this stage, the capping layer 212 can be selectively removed without causing the removal of other materials at or near the top surface of the semiconductor-superconductor hybrid device 20. Assuming the capping layer 212 is an arsenide capping layer, thermal desorption (e.g., in a temperature range between 300°C and 375°C) can be used to achieve arsenic desorption from the capping layer 212. In practice, if a material other than arsenic is used for the capping layer 212, appropriate heat or other techniques can be used to selectively remove the capping layer 212. Figure 17 shows an enlarged view of a portion 1610 of the exemplary semiconductor-superconductor hybrid device of Figure 16.

[0053] Figure 18 shows a view 1800 of the exemplary semiconductor-superconductor hybrid device 20 of Figure 16 in a subsequent stage of processing. In this stage of processing, a superconducting metal layer 240 may be formed on the top surface of the semiconductor-superconductor hybrid device 20 of Figure 16. Any superconductor exhibiting an electron pairing periodicity associated with the presence of Cooper pairs can be used to form the superconducting metal layer 240. Example materials that can be used to form the superconducting metal layer 240 include, but are not limited to, lead, indium, tin, and aluminum. Although Figure 18 shows a certain number of layers of the semiconductor-superconductor hybrid device 20 arranged in a certain way, there may be more or fewer layers with different arrangements.

[0054] In terms of operation of the semiconductor-superconductor hybrid device 20, similar to what was previously explained with respect to FIG. 6, applying different amounts of voltage to the gates located on each side of the horizontal confinement channel allows for variation in the size of the expedient gap defined by the geometry of the nanowires. The voltage applied to the gates (e.g., to gates GATE1 and GATE2 shown in FIG. 18) generates an electric field that can move electrons in the horizontal confinement channel (e.g., the horizontal confinement channel identified as the dashed line in FIG. 18). As mentioned earlier, applying appropriate voltage through the gates (e.g., GATE1 and GATE2) allows for modulation of the width of the nanowires formed as part of the semiconductor-superconductor hybrid device 20 of FIG. 18. Furthermore, as mentioned earlier, damage to the semiconductor during the formation of such a device results in an increase in the line edge roughness (LER) of the superconductor, which in turn reduces the size of the topological gap. For similar reasons as previously discussed, the tunability of the topological gap size allows for more relaxed process constraints during the fabrication of the semiconductor-superconductor hybrid device described herein.

[0055] Furthermore, as previously described with respect to FIG. 6, the tunability provided by the gates (e.g., GATE1 and GATE2) located on each side of the horizontally confined electrostatic channels of the semiconductor-superconductor hybrid device 10 can provide additional advantages. For example, the size of the topological gap associated with the semiconductor-superconductor hybrid device 20 is a function of many process and material-related aspects. Therefore, a single subband scheme may vary from device to device depending on the materials and processes used to fabricate the device. However, the tunability of the horizontally confined electrostatic channels allows for fine-tuning of the channels, even in a single subband scheme, to achieve the desired topological gap. Another potential advantage may relate to the ability to use the same set of materials and processes for multi-window stacks and other more complex nanowire arrangements. This is because the corresponding nanowires can be tuned to the desired subband scheme by applying an appropriate voltage to the gate associated with the corresponding horizontally confined electrostatic channel. Moreover, this tunability can be particularly useful when the energy separation between subbands is very low in a multi-subband scheme.

[0056] As previously stated, a suitable voltage for the gate can be coupled to the gate via a power grid formed as part of an integrated circuit identical to the semiconductor-superconductor hybrid device 20. The power grid can be coupled via vias or other interconnect structures formed as part of the integrated circuit. The voltage itself can be generated using a voltage regulator that includes a controller associated with the integrated circuit. This controller can be separate from or integrated with the integrated circuit, which includes multiple instances of semiconductor-superconductor hybrid devices used as nanowires or other types of topological quantum computing devices. Furthermore, as previously stated, these techniques are applicable not only to InAs 2-DEGs but also to VLS lines, SAG materials, or any other device made of any semiconductor material selected from groups III-V of the periodic table. Although semiconductor-superconductor hybrid devices are described as being formed using materials with conduction and valence band offsets to collect electrons, such devices can be formed using different sets of materials and arranged in different ways to collect holes. As an example, a semiconductor-superconductor hybrid device may include a two-dimensional hole gas (2-DHG) structure instead of a 2-DEG structure.

[0057] Figure 19 shows a flowchart 1900 of a method for forming a semiconductor-superconductor hybrid device according to an example. Step 1910 may include forming a semiconductor heterostructure over a substrate. In one example, this step may include forming the layers described in Figure 1. Furthermore, the semiconductor heterostructure may also include a capping layer. As mentioned above, the semiconductor heterostructure may include a first layer of indium arsenide or aluminum arsenide, a second layer of indium arsenide, and a third layer of indium arsenide or gallium arsenide. Other material combinations may also be used. The substrate may include one of indium phosphide, indium arsenide, indium antimonide, or indium antimony arsenide.

[0058] Step 1920 may include forming a superconducting layer over the semiconductor heterostructure. In one example, this step may include the process previously described with respect to FIG2. As previously mentioned, the superconducting layer may include one of lead, indium, tin, or aluminum.

[0059] Step 1930 may include exposing a first side of the semiconductor heterostructure and a second side of the semiconductor heterostructure opposite to the first side to allow the formation of a first gate adjacent to the first side of the semiconductor heterostructure and for forming a second gate adjacent to the second side of the semiconductor heterostructure. As described above with respect to FIG4, this step may be performed by selectively removing (e.g., by etching) certain materials to expose the sides. In this example, the selective removal of these materials results in the formation of a semiconductor-superconductor hybrid structure having a specific aspect ratio defined by the ratio of its width (B) to its depth (A).

[0060] Step 1940 may include removing a first portion of the first gate and a second portion of the second gate, such that each of the first top surface of the first gate and the second top surface of the second gate is vertically offset from a selected surface of the semiconductor heterostructure by a predetermined offset. As explained with respect to Figures 5 and 6, the formation of the gate may include selectively removing the gate metal layer (or other gate-related material) to ensure that any horizontally confined channels are formed at a distance from any structural disorder located at or near the top surface of the semiconductor heterostructure. In one example, the selected surface may be the top surface of the semiconductor heterostructure.

[0061] FIG20 illustrates another flowchart 2000 of a method for forming a semiconductor-superconductor hybrid device according to an example. Step 2010 may include forming a first isolated semiconductor heterostructure and a second isolated semiconductor heterostructure over a substrate. As described above with respect to FIG7 and 8, photolithography can be used to form a mask with a desired pattern, which can then be transferred to the semiconductor heterostructure wafer 210 of FIG8 using isotropic etching (or other types of techniques for removing material to form a structure). As previously described, the isotropic etching step can result in the formation of isolated semiconductor heterostructures (e.g., isolated semiconductor heterostructures 214, 216, and 218 with a capping layer 212).

[0062] Step 2020 may include forming a left gate, the left gate being adjacent to a first side of each of the first isolation semiconductor heterostructure and the second isolation semiconductor heterostructure. Additional details regarding one manner of forming the left gate are described with reference to FIG9.

[0063] Step 2030 may include forming a right gate, which is adjacent to a second side opposite to the first side of each of the first and second isolation semiconductor heterostructures, wherein the top surface of each of the left and right gates is perpendicularly offset from selected surfaces of each of the first and second isolation semiconductor heterostructures by a predetermined offset. Additional details regarding one manner of forming the left gate are described with reference to FIG9. In practice, the left and right gates can be formed using process steps performed simultaneously. As previously described with reference to FIGS. 12 and 13, a portion of the metal layer 222 (related to each of the left and right gates) may be selectively etched to remove a portion of the metal layer 222 along the side surface of each of the aforementioned isolation semiconductor heterostructures 214, 216, and 218.

[0064] Step 2040 may include forming a superconducting layer over each of the first and second isolation semiconductor heterostructures. In one example, this step may be performed as described with respect to FIG18.

[0065] In summary, this disclosure relates to a semiconductor-superconductor hybrid device including a semiconductor heterostructure formed over a substrate. The semiconductor-superconductor hybrid device may further include a superconducting layer formed over the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a first gate having a first top surface and formed adjacent to a first side of the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a second gate having a second top surface and formed adjacent to a second side of the semiconductor heterostructure relative to the first side, wherein each of the first top surface of the first gate and the second top surface of the second gate is vertically offset from a selected surface of the semiconductor heterostructure by a predetermined offset.

[0066] The semiconductor-superconductor hybrid device can be configured to form a horizontally confined electrostatic channel in the semiconductor heterostructure in response to an electric field applied to the semiconductor heterostructure through a first gate and a second gate. A predetermined offset can be selected to ensure that the horizontally confined electrostatic channel is formed at a selected distance from the top surface of the semiconductor heterostructure, thereby reducing the effects of any structural disorder associated with the interface between the superconducting layer and the semiconductor heterostructure. Interface-related structural disorder may include line edge roughness (LER) associated with the superconducting layer. The horizontally confined electrostatic channel may include one of a two-dimensional electron gas (2-DEG) channel or a two-dimensional hole gas (2-DHG) channel.

[0067] The semiconductor-superconductor hybrid device may further include a first terminal coupled to a first gate and a second terminal coupled to a second gate, wherein an electric field is generated by applying a first voltage to the first terminal and a second voltage to the second terminal. The amounts of the first and second voltages can be selected to tune the width associated with a horizontally limited electrostatic channel. The semiconductor-superconductor hybrid device can be used as a nanowire with an adjustable width.

[0068] In another embodiment, this disclosure relates to a semiconductor-superconductor hybrid device including a semiconductor heterostructure formed over a substrate. The semiconductor-superconductor hybrid device may further include a superconducting layer formed over the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a first gate having a first top surface and formed adjacent to a first side of the semiconductor heterostructure. The semiconductor-superconductor hybrid device may further include a second gate having a second top surface and formed adjacent to a second side of the semiconductor heterostructure relative to the first side, wherein each of the first top surface of the first gate and the second top surface of the second gate is vertically offset from a selected surface of the semiconductor heterostructure by a predetermined offset, the predetermined offset being selected to ensure the formation of a horizontally confined electrostatic channel at a selected distance from the selected surface of the semiconductor heterostructure to reduce the effects of any line edge roughness (LER) associated with the superconducting layer.

[0069] A horizontally confined electrostatic channel can be formed in the semiconductor heterostructure in response to the application of an electric field through the first gate and the second gate. The horizontally confined electrostatic channel may include one of a two-dimensional electron gas (2-DEG) channel or a two-dimensional hole gas (2-DHG) channel.

[0070] The semiconductor-superconductor hybrid device may further include a first terminal coupled to a first gate and a second terminal coupled to a second gate, wherein an electric field is generated by applying a first voltage to the first terminal and a second voltage to the second terminal. The amounts of the first and second voltages can be selected to tune the width associated with a horizontally limited electrostatic channel. The semiconductor-superconductor hybrid device can be used as a nanowire with an adjustable width.

[0071] In yet another embodiment, this disclosure relates to a semiconductor-superconductor hybrid device, including a first isolation semiconductor heterostructure and a second isolation semiconductor heterostructure formed on a substrate. The semiconductor-superconductor hybrid device may further include a left gate, which is formed adjacent to a first side of each of the first and second isolation semiconductor heterostructures. The semiconductor-superconductor hybrid device may further include a right gate, which is formed adjacent to a second side of each of the first and second isolation semiconductor heterostructures opposite to the first side, wherein the top surfaces of each of the left and right gates are vertically offset from selected surfaces of each of the first and second isolation semiconductor heterostructures by a predetermined offset. The semiconductor-superconductor hybrid device may further include a superconducting layer, which is formed on each of the first and second isolation semiconductor heterostructures.

[0072] The semiconductor-superconductor hybrid device can be configured to form a horizontally confined electrostatic channel in the respective isolated semiconductor heterostructure in response to the application of an electric field through the respective left gate and the respective right gate. A predetermined offset can be selected to ensure that the horizontally confined electrostatic channel is formed at a selected distance from a selected top surface of the respective semiconductor heterostructure, thereby reducing the influence of any structural disorder related to the interface between the superconducting layer and the respective isolated semiconductor heterostructure.

[0073] Interface-related structural disorder may include line edge roughness (LER) associated with the superconducting layer. Horizontally confined electrostatic channels may include either two-dimensional electron gas (2-DEG) channels or two-dimensional hole gas (2-DHG) channels. Semiconductor-superconductor hybrid devices can be used as nanowires with tunable widths.

[0074] It should be understood that the methods, modules, and components described herein are merely exemplary. For example, but not limited to, illustrative devices may include semiconductor-superconductor hybrid devices, topological nanowires, and other topological quantum computing devices. Although the formation of the device has been described with respect to a specific type of conductivity or potential polarity, those skilled in the art will understand that the type of conductivity and polarity of the potential can be reversed. Furthermore, the terms "before," "after," "top," "bottom," "above," "below," etc., that may appear in the specification and claims are for illustrative purposes and are not necessarily used to describe permanent relative positions. It should be understood that the terms used are interchangeable where appropriate so that specific embodiments of the disclosure described herein (e.g.) can operate in orientations other than those illustrated or described.

[0075] Furthermore, in an abstract but still explicit sense, any arrangement of components that achieves the same function is effectively “related” to achieve the desired functionality. Therefore, any two components combined in this document to achieve a specific function can be considered as “related” to each other to achieve the desired function, regardless of the architecture or intermediate components. Similarly, any two such related parts can also be considered as “operably connected” or “operably coupled” to each other to achieve the desired function.

[0076] Furthermore, those skilled in the art will recognize that the boundaries between the functions of the aforementioned layers or the components included in the device are merely illustrative. The functions of multiple layers may be combined into a single layer, and / or the functions of a single layer may be distributed across additional layers. Additionally, alternative embodiments may include multiple instances of a particular layer, and the order of the layers (e.g., from top to bottom or from bottom to top) may be varied in various other embodiments.

[0077] Although specific examples are provided in this disclosure, various modifications and changes may be made without departing from the scope of this disclosure as set forth in the following claims. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive, and all such modifications are intended to be included within the scope of this disclosure. Any benefits, advantages, or solutions to problems described herein with reference to specific examples are not intended to be construed as key, essential, or fundamental features or elements of any or all claims.

[0078] Furthermore, the terms "a(a)" or "an(an)" as used herein are defined as one or more. Additionally, quotations such as "at least one" and "one or more" used in the claims should not be interpreted as implying that the introduction of another claim element through the indefinite article "a(a)" or "an(an)" would limit any particular claim containing such an introduced claim element to an invention containing only one such element, even if the same claim contains the quotations "one or more" or "at least one" with indefinite articles (such as "a(a)" or "an(an)"). The same applies to the use of definite articles.

[0079] Unless otherwise stated, terms such as “first” and “second” are used to arbitrarily distinguish the elements described by such terms. Therefore, these terms are not necessarily intended to indicate the timing or other priority of such elements. [Simplified Explanation of the Diagram]

[0008] The present disclosure is shown by way of example and not limitation in the accompanying drawings, in which similar reference numerals indicate similar elements. The elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale.

[0009] Figure 1 shows a view of an example semiconductor-superconductor hybrid device in a stage of processing;

[0010] Figure 2 shows a view of the exemplary semiconductor-superconductor hybrid device of Figure 1 in a subsequent stage of the process;

[0011] Figure 3 shows a view of the exemplary semiconductor-superconductor hybrid device of Figure 2 in a subsequent stage of the process;

[0012] Figure 4 shows a view of the exemplary semiconductor-superconductor hybrid device of Figure 3 in a subsequent stage of the process;

[0013] Figure 5 shows a view of the exemplary semiconductor-superconductor hybrid device of Figure 4 in a subsequent stage of the process;

[0014] Figure 6 illustrates the operation of the exemplary semiconductor-superconductor hybrid device described herein, the device including the semiconductor-superconductor hybrid device of Figure 5 and including a horizontally confined channel;

[0015] Figure 7 shows a view of another example semiconductor-superconductor hybrid device in a stage of processing;

[0016] Figure 8 shows a view of the exemplary semiconductor-superconductor hybrid device of Figure 7 in a subsequent stage of the process;

[0017] Figure 9 shows a view of the exemplary semiconductor-superconductor hybrid device of Figure 8 in a subsequent stage of the process;

[0018] Figure 10 shows a view of the exemplary semiconductor-superconductor hybrid device of Figure 9 in a subsequent stage of the process;

[0019] Figure 11 shows a view of the exemplary semiconductor-superconductor hybrid device of Figure 10 in a subsequent stage of the process;

[0020] Figure 12 shows a view of the exemplary semiconductor-superconductor hybrid device of Figure 11 in a subsequent stage of the process;

[0021] Figure 13 shows an enlarged view of a portion of the exemplary semiconductor-superconductor hybrid device of Figure 12;

[0022] Figure 14 shows a view of the exemplary semiconductor-superconductor hybrid device of Figure 12 in a subsequent stage of the process;

[0023] Figure 15 shows a view of the exemplary semiconductor-superconductor hybrid device of Figure 14 in a subsequent stage of the process;

[0024] Figure 16 shows a view of the exemplary semiconductor-superconductor hybrid device of Figure 15 in a subsequent stage of the process;

[0025] Figure 17 shows an enlarged view of a portion of the exemplary semiconductor-superconductor hybrid device of Figure 16;

[0026] Figure 18 shows a view of the exemplary semiconductor-superconductor hybrid device of Figure 16 in a subsequent stage of the process;

[0027] Figure 19 shows a flowchart of a method for forming a semiconductor-superconductor hybrid device according to an example; and

[0028] Figure 20 shows another flowchart of a method for forming a semiconductor-superconductor hybrid device according to an example. [Biomaterial Storage]

[0081] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A semiconductor-superconductor hybrid device, the semiconductor-superconductor hybrid device comprising: A semiconductor heterostructure is formed on a substrate; A superconducting layer is formed on the semiconductor heterostructure; a first gate has a first top surface and is formed adjacent to a first side of the semiconductor heterostructure; And a second gate having a second top surface and formed adjacent to a second side of the semiconductor heterostructure relative to the first side, wherein each of the first top surface of the first gate and the second top surface of the second gate is vertically offset from a top surface of the semiconductor heterostructure by a predetermined offset, wherein the semiconductor-superconductor hybrid device is configured to form a horizontally confined electrostatic channel in the semiconductor heterostructure in response to applying an electric field to the semiconductor heterostructure through the first gate and the second gate, wherein the predetermined offset is selected to ensure that the horizontally confined electrostatic channel is formed at a selected distance from the top surface of the semiconductor heterostructure to reduce the effects of any structural disorder associated with an interface between the superconducting layer and the semiconductor heterostructure, and wherein the structural disorder associated with the interface includes line edge roughness (LER) associated with the superconducting layer.

2. The semiconductor-superconductor hybrid device as claimed in claim 1, wherein the horizontally confined electrostatic channel comprises either a two-dimensional electron gas (2-DEG) channel or a two-dimensional hole gas (2-DHG) channel.

3. The semiconductor-superconductor hybrid device as claimed in claim 1, the semiconductor-superconductor hybrid device further comprising a first terminal coupled to the first gate and a second terminal coupled to the second gate, wherein the electric field is generated by applying a first voltage to the first terminal and a second voltage to the second terminal.

4. The semiconductor-superconductor hybrid device as claimed in claim 3, wherein an amount of the first voltage and an amount of the second voltage are selected to tune a width associated with the electrostatic channel limited by the level.

5. The semiconductor-superconductor hybrid device as claimed in claim 1, wherein the semiconductor-superconductor hybrid device can be used as a nanowire having an adjustable width.

6. The semiconductor-superconductor hybrid device as claimed in claim 1, wherein the predetermined offset is determined by testing samples of multiple devices to increase the mobility of electrons within the electrostatic channel limited by the level.

7. The semiconductor-superconductor hybrid device as claimed in claim 1, wherein the predetermined offset is determined by testing samples of multiple devices to increase the density of electrons within the electrostatic channel confined by the level.

8. An integrated circuit comprising a semiconductor-superconductor hybrid device, comprising: A semiconductor heterostructure is formed on a substrate; A superconducting layer is formed on the semiconductor heterostructure; a first gate has a first top surface and is formed adjacent to a first side of the semiconductor heterostructure; And a second gate, the second gate having a second top surface and formed adjacent to a second side of the semiconductor heterostructure relative to the first side, wherein each of the first top surface of the first gate and the second top surface of the second gate is vertically offset from a top surface of the semiconductor heterostructure by a predetermined offset, wherein the predetermined offset is selected to ensure the formation of a horizontally confined electrostatic channel at a selected distance from the top surface of the semiconductor heterostructure to reduce the effects of any structural disorder associated with an interface between the superconducting layer and the semiconductor heterostructure, and wherein the junction associated with the interface The disorder includes line edge roughness (LER) associated with the superconducting layer; and the integrated circuit further includes a controller coupled to the semiconductor-superconductor hybrid device, wherein the horizontally confined electrostatic channel is formed in response to an electric field generated by applying a first voltage to a first terminal associated with the first gate and a second voltage to a second terminal associated with the second gate, and wherein the first voltage and the second voltage are generated using at least one voltage regulator included in the controller coupled to the semiconductor-superconductor hybrid device.

9. The integrated circuit as claimed in claim 8, wherein the horizontally confined electrostatic channel is formed in the semiconductor heterostructure in response to the application of an electric field through the first gate and the second gate to the semiconductor heterostructure.

10. The integrated circuit as claimed in claim 8, wherein the horizontally limited electrostatic channel comprises one of a two-dimensional electron gas (2-DEG) channel or a two-dimensional hole gas (2-DHG) channel.

11. The integrated circuit as claimed in claim 8, wherein an amount of the first voltage and an amount of the second voltage are selected to tune a width associated with the electrostatic channel of the horizontal limitation.

12. The integrated circuit as claimed in claim 8, wherein the semiconductor-superconductor hybrid device can be used as a nanowire with an adjustable width.

13. A semiconductor-superconductor hybrid device, the semiconductor-superconductor hybrid device comprising: A first isolation semiconductor heterostructure and a second isolation semiconductor heterostructure are formed on a substrate; a left gate is formed adjacent to a first side of each of the first isolation semiconductor heterostructure and the second isolation semiconductor heterostructure; a right gate is formed adjacent to a second side of each of the first isolation semiconductor heterostructure and the second isolation semiconductor heterostructure opposite to the first side, wherein a top surface of each of the left gate and the right gate is vertically offset from a top surface of each of the first isolation semiconductor heterostructure and the second isolation semiconductor heterostructure by a predetermined offset, wherein the semiconductor-superconductor hybrid device is configured to, in response to applying an electric field through a corresponding left gate and a corresponding right gate to a corresponding isolation semiconductor heterostructure, [the following is unclear and likely incomplete: "in the corresponding isolation semiconductor heterostructure"] A horizontally confined electrostatic channel is formed in the conductor heterostructure, wherein the predetermined offset is selected to ensure that the horizontally confined electrostatic channel is formed at a selected distance from the top surface of the corresponding isolation semiconductor heterostructure to reduce the effects of any structural disorder associated with an interface between the superconducting layer and the corresponding isolation semiconductor heterostructure, wherein the structural disorder associated with the interface includes line edge roughness (LER) associated with the superconducting layer; and a superconducting layer is formed above each of the first isolation semiconductor heterostructure and the second isolation semiconductor heterostructure.

14. The semiconductor-superconductor hybrid device as claimed in claim 13, further comprising a first terminal coupled to the first gate and a second terminal coupled to the second gate, wherein the electric field is generated by applying a first voltage to the first terminal and a second voltage to the second terminal.

15. The semiconductor-superconductor hybrid device as claimed in claim 14, wherein an amount of the first voltage and an amount of the second voltage are selected to tune a width associated with the electrostatic channel limited by the level.

16. The semiconductor-superconductor hybrid device as claimed in claim 13, wherein the horizontally confined electrostatic channel comprises either a two-dimensional electron gas (2-DEG) channel or a two-dimensional hole gas (2-DHG) channel.

17. The semiconductor-superconductor hybrid device as claimed in claim 13, wherein the semiconductor-superconductor hybrid device can be used as a nanowire having an adjustable width.

18. The semiconductor-superconductor hybrid device as claimed in claim 13, wherein the predetermined offset is determined by testing samples of multiple devices to increase the mobility of electrons within the electrostatic channel limited by the level.

19. The semiconductor-superconductor hybrid device as claimed in claim 13, wherein the predetermined offset is determined by testing samples of multiple devices to increase the density of electrons within the electrostatic channel confined by the level.

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