Device with package, apparatus with package,and method for fabricating package

Abstract

An apparatus comprising a first package and a second package coupled to the first package via a first plurality of solder interconnects. The first package includes: a first substrate including at least one first dielectric layer and a first plurality of interconnects; and a first integrated means coupled to the first substrate. The second package includes: a second substrate including at least one second dielectric layer and a second plurality of interconnects; a second integrated means coupled to a first surface of the second substrate; a third integrated means coupled to the first surface of the second substrate via a second plurality of solder interconnects; and a first plurality of channel interconnects coupled to the first surface of the second substrate, wherein the first plurality of channel interconnects are located between solder interconnects from the second plurality of solder interconnects.

Description

Technical Field

[0001] This patent application claims priority to non-provisional application No. 17 / 532,754, filed on November 22, 2021, with the United States Patent and Trademark Office, the entire contents of which are incorporated herein by reference as fully set forth in their entirety below and for all applicable purposes.

[0002] Various features relate to the packaging of integrated devices. Prior Technology

[0003] A package may include a substrate and an integrated device. These components are coupled together to provide a package capable of performing various electrical functions. There has always been a need to provide high-performance packages while reducing the overall size of the package. Summary of the Invention

[0004] Various features involve packaging with integrated devices.

[0005] One example provides an apparatus including a first package and a second package coupled to the first package via a first plurality of solder interconnects. The first package includes: a first substrate including at least one first dielectric layer and a first plurality of interconnects; and a first integrated means coupled to the first substrate. The second package includes: a second substrate including at least one second dielectric layer and a second plurality of interconnects; a second integrated means coupled to a first surface of the second substrate; a third integrated means coupled to the first surface of the second substrate via a second plurality of solder interconnects; and a first plurality of channel interconnects coupled to the first surface of the second substrate, wherein the first plurality of channel interconnects are located between solder interconnects from the second plurality of solder interconnects.

[0006] Another example provides an apparatus comprising a first package and a second package coupled to the first package via a first plurality of solder interconnects. The first package includes: a first substrate including at least one first dielectric layer and a first plurality of interconnects; and a first integrated means coupled to the first substrate. The second package includes: a second substrate including at least one second dielectric layer and a second plurality of interconnects; a second integrated means coupled to a first surface of the second substrate; a third integrated means coupled to the first surface of the second substrate via a second plurality of solder interconnects; and means for channel interconnects coupled to the first surface of the second substrate, wherein the means for channel interconnects are located between solder interconnects from the second plurality of solder interconnects.

[0007] Another instance provides a method for fabricating packages. The method provides a first package comprising: a first substrate comprising at least one first dielectric layer and a first complex number of interconnects; The method couples a second substrate to a first substrate via a first complex number of solder interconnects, wherein the second substrate includes at least one second dielectric layer and a second complex number of interconnects. The method provides a first complex number of channel interconnections on top of the first surface of the second substrate. The method couples the second integration device to the first surface of the second substrate. The method couples the third integral device to the first surface of the second substrate via a second complex of solder interconnects, wherein the first complex channel interconnects are located between the solder interconnects of the second complex solder interconnects. Brief explanation of the schema

[0008] In understanding the detailed description elaborated below in conjunction with the drawings, the various features, essences and advantages will become apparent, in the drawings, similar component symbols are always marked accordingly.

[0009] 1 illustrates an exemplary cross-sectional cross-sectional view of a package including a channel interconnect.

[0010] 2 illustrates an exemplary cross-sectional plan view of a package including a channel interconnect.

[0011] 3 illustrates an exemplary circuit in a package including a channel interconnect.

[0012] 4 illustrates an exemplary cross-sectional cross-sectional view of a package including a channel interconnect.

[0013] 5 illustrates an exemplary cross-sectional plan view of a package including channel interconnects.

[0014] 6 illustrates an exemplary cross-sectional cross-sectional view of a package including a channel substrate with channel interconnects.

[0015] 7 illustrates an exemplary cross-sectional plan view of a package including a channel substrate with channel interconnects.

[0016] 8 illustrates an exemplary cross-sectional cross-sectional view of a package including a flexible cable with channel interconnects.

[0017] 9 illustrates an exemplary cross-sectional plan view of a package including a flexible cable having a channel interconnect.

[0018] Figure 10 illustrates an exemplary cross-sectional view of a package including several interconnected channels.

[0019] Figures 11A to 11C illustrate exemplary steps for manufacturing a package that includes a plurality of channel interconnects.

[0020] Figures 12A to 12C illustrate exemplary processes for manufacturing a package including a channel substrate containing a plurality of channel interconnects.

[0021] Figure 13 illustrates an exemplary flowchart of a method for manufacturing a package including channel interconnects.

[0022] Figures 14A-14B illustrate exemplary processes for manufacturing a substrate.

[0023] Figure 15 illustrates an exemplary flowchart of a method for manufacturing a substrate.

[0024] Figure 16 illustrates various electronic devices that can integrate the chips, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. Implementation

[0025] In the following description, specific details are provided to provide a thorough understanding of the various forms of this invention. However, those skilled in the art will understand that these forms can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring these forms in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid obscuring these forms of this invention.

[0026] This application describes an apparatus comprising a first package and a second package coupled to the first package via a first plurality of solder interconnects. The first package includes: a first substrate including at least one first dielectric layer and a first plurality of interconnects, and a first integrated device coupled to the first substrate. The second package includes: a second substrate including at least one second dielectric layer and a second plurality of interconnects; a second integrated device coupled to a first surface of the second substrate; a third integrated device coupled to the first surface of the second substrate via a second plurality of solder interconnects; and a first plurality of channel interconnects coupled to the first surface of the second substrate, wherein the first plurality of channel interconnects are located between solder interconnects from the second plurality of solder interconnects. As will be further described below, using a first plurality of channel interconnects between solder interconnects helps to: (i) improve signal isolation in the package, (ii) streamline signal paths, (iii) reduce package thickness, (iv) improve heat dissipation, and / or (v) improve manufacturing lead time. Exemplary package including channel interconnects

[0027] Figure 1 illustrates a cross-sectional view of a package 100 including channel interconnects. Package 100 may be a stacked package (PoP). Package 100 may include a first package 101 and a second package 103. Package 100 is coupled to a board 106 via a plurality of solder interconnects 110. Board 106 includes at least one board dielectric layer 160 and a plurality of board interconnects 162. Board 106 may include a printed circuit board (PCB).

[0028] The first package 101 includes a first substrate 102 and a first integrated device 105. The first integrated device 105 is coupled to a first surface (e.g., the top surface) of the substrate 102 via a plurality of solder interconnects 150. The first substrate 102 includes at least one first dielectric layer 120 and a first plurality of interconnects 122. The first integrated device 105 is coupled to the first plurality of interconnects 122 of the first substrate 102 via the plurality of solder interconnects 150.

[0029] The second package 103 includes a second substrate 104, a second integration device 107, a third integration device 109, and a plurality of channel interconnects 108. The second integration device 107 is coupled to a first surface (e.g., the top surface) of the second substrate 104 via a plurality of solder interconnects 170. The third integration device 109 is coupled to the first surface (e.g., the top surface) of the second substrate 104 via a plurality of solder interconnects 190. The second integration device 107 is located between the second substrate 104 and the third integration device 109. The second integration device 107 is located below the third integration device 109. The plurality of solder interconnects 190 may laterally surround the second integration device 107.

[0030] The plurality of channel interconnects 108 are located on a first surface (e.g., top surface) of the second substrate 104. Note that the plurality of channel interconnects 108 shown in FIG. 1 represents a conceptual representation of possible channel interconnects. As will be further described below at least in FIG. 4 to 9, the plurality of channel interconnects 108 may be implemented as and / or include a plurality of channel interconnects, channel substrates (e.g., a fourth substrate, a patch substrate), and / or flexible cables (e.g., a flexible substrate, a flexible board). The plurality of channel interconnects 108 may be means for channel interconnection. At least one channel interconnect from the plurality of channel interconnects 108 is located between adjacent solder interconnects from the plurality of solder interconnects 190. The plurality of channel interconnects 108 may extend below the third integration device 109.

[0031] The first plurality of channel interconnects 108 between solder interconnects contribute to: (i) improved signal isolation in the package, (ii) clearer signal paths, (iii) reduced package thickness, (iv) improved heat dissipation, and / or (v) improved manufacturing lead time. For example, some signals may be configured to travel via electrical paths including the plurality of channel interconnects 108 so that these signals do not interfere with other signals. In some implementations, signals to and / or from integrated device 107 may be configured to travel via electrical paths including the plurality of channel interconnects 108 so that these signals do not interfere with and / or are isolated from signals traveling between integrated device 105 and integrated device 109. This can result in improved performance of integrated device 105, integrated device 107, integrated device 109, and / or package 100. Some electrical paths may include the plurality of channel interconnects 108 to reduce congestion and clear paths in the second substrate 104. Using multiple interconnect channels 108 can reduce the number of metal layers in the second substrate 104, which can reduce the total thickness of the second substrate 104 and / or the package 100. Using a substrate with fewer metal layers helps improve heat dissipation in the package 100, which in turn helps improve the overall performance of the package 100.

[0032] In some implementations, the total thickness of the second substrate 104, the plurality of solder interconnects 112, the first substrate 102, and the plurality of solder interconnects 110 can be about 510 micrometers or less. The second substrate 104 includes at least one second dielectric layer 140 and a plurality of interconnects 142. The second substrate 104 can be an interposer. In some implementations, the second substrate 104 may have two or fewer metal layers. A third integration device 109 is coupled to the second plurality of interconnects 142 of the second substrate 104 via a plurality of solder interconnects 190. A second integration device 107 is coupled to the second plurality of interconnects 142 of the second substrate 104 via a plurality of solder interconnects 170. A second package 103 is coupled to the first package 101 via the plurality of solder interconnects 112. For example, the second substrate 104 is coupled to the first substrate 102 via the plurality of solder interconnects 112. The plurality of solder interconnects 112 can be considered part of the first package 101 and / or the second package 103.

[0033] Figure 2 illustrates a plan view of a cross-section AA across substrate 100. Figure 2 illustrates a second substrate 104, a second integration device 107, a plurality of solder interconnects 190, and a plurality of channel interconnects 108. As shown in Figure 2, at least one channel interconnect from the plurality of channel interconnects 108 is located between adjacent solder interconnects from the plurality of solder interconnects 190. The plurality of channel interconnects 108 is located above the second substrate 104. The plurality of channel interconnects 108 can conceptually represent the area in which the channel interconnects can be implemented in package 100 and / or located. Figure 2 conceptually illustrates the plurality of channel interconnects 108 as a single component. However, the plurality of channel interconnects 108 can be provided as one or more components. The plurality of channel interconnects 108 can laterally surround the second integration device 107. The plurality of channel interconnects 108 can include one or more metal layers (e.g., one metal layer, two metal layers) to accommodate various interconnection needs and / or designs. The plurality of solder interconnects 190 may laterally surround the second integration device 107.

[0034] Figure 3 illustrates possible electrical paths within package 100. Figure 3 illustrates electrical paths 305, 306, and 307. Electrical path 305 may represent one or more possible electrical paths for a signal to and / or from the second integrated device 107. Electrical path 306 may represent one or more possible electrical paths for a signal to and / or from the second integrated device 107. Electrical path 307 may represent one or more possible electrical paths for a signal to and / or from the first integrated device 105.

[0035] Electrical path 305 (e.g., a first electrical path, a second electrical path, a third electrical path) may be an example of one or more signal electrical paths between the second integrated device 107 and the first substrate 102. Electrical path 305 may include: (i) at least one solder interconnect (e.g., 170) coupling the second integrated device 107 to the second substrate 104, (ii) at least one first interconnect from a second plurality of interconnects 142 of the second substrate 104, (iii) at least one channel interconnect (e.g., a plurality of channel interconnects) from a plurality of channel interconnects 108, (iv) at least one second interconnect from the second plurality of interconnects 142 of the second substrate 104, (v) at least one second solder interconnect from a first plurality of solder interconnects 112 coupling the second substrate 104 and the first substrate 102, and (vi) at least one interconnect from a first plurality of interconnects 122 of the first substrate 102. The at least one second solder interconnect, which is part of the electrical path 305, originating from the first plurality of solder interconnects 112, may be a solder interconnect 112 positioned along the periphery of the substrate 102, substrate 104, and / or package 100. In some implementations, the solder interconnects 112 positioned along the periphery of the substrate 102 and / or substrate 104 include solder interconnects closest to one or more edges of the substrate 102 and / or substrate 104. In some implementations, the solder interconnects 112 positioned along the periphery of the substrate 102 and / or substrate 104 include rows of solder interconnects closest to one or more edges of the substrate 102 and / or substrate 104. In some implementations, the solder interconnects 112 positioned along the periphery of the substrate 102 and / or substrate 104 may include two rows of solder interconnects closest to one or more edges of the substrate 102 and / or substrate 104. A row of solder interconnects may include rows along the X direction and / or along the Y direction of the substrate.

[0036] Electrical path 305 may extend to be coupled to board 106. For example, electrical path 305 may also include at least one solder interconnect from a plurality of solder interconnects 110 and at least one board interconnect from a plurality of board interconnects 162. Thus, one or more signals between board 106 and second integrated device 107 may travel via electrical path 305 as described above.

[0037] Electrical path 306 (e.g., a first electrical path, a second electrical path, a third electrical path) may be an example of one or more signal electrical paths between the second integrated device 107 and the first integrated device 105. Electrical path 306 may include: (i) at least one solder interconnect (e.g., 170) coupling the second integrated device 107 to the second substrate 104, (ii) at least one first interconnect from a second plurality of interconnects 142 of the second substrate 104, (iii) at least one channel interconnect (e.g., a plurality of channel interconnects) from a plurality of channel interconnects 108, (iv) at least one second interconnect from the second plurality of interconnects 142 of the second substrate 104, (v) at least one solder interconnect from a plurality of solder interconnects 112, at least one interconnect from a first plurality of interconnects 122, and (vi) at least one solder interconnect from a plurality of solder interconnects 150.

[0038] Electrical path 307 (e.g., a first electrical path, a second electrical path, a third electrical path) may be an example of one or more signal electrical paths between the first integrated device 105 and the third integrated device 109. Electrical path 307 may include: (i) at least one solder interconnect (e.g., 150) coupling the first integrated device 105 to the first substrate 102, (ii) at least one first interconnect from a first plurality of interconnects 122 of the first substrate 102, (iii) at least one solder interconnect from a plurality of solder interconnects 112 coupling the second substrate 104 and the first substrate 102, (iv) at least one interconnect from a second plurality of interconnects 142 of the second substrate 104, and (v) at least one solder interconnect from a plurality of solder interconnects 190 coupling the third integrated device 109 and the second substrate 104.

[0039] Figure 3 illustrates how electrical paths are implemented and configured within a package to enter and exit channel interconnects to help reduce routing congestion, improve signal isolation, and streamline routing to demonstrate improvements in package performance. In one example, integrated device 105 may include an application processor, integrated device 107 may include a modem, and integrated device 109 may include memory. In some implementations, substrate 104 may include two metal layers (e.g., M1, M2). In some implementations, integrated device 107 may include one or more cores and / or one or more functions. In some implementations, different channel interconnects may be configured to be coupled to different cores and / or different functions of integrated device 107. In some implementations, the plurality of channel interconnects 108 are configured to be used for transmitting signals, currents, and / or ground to and from and / or via integrated device 107.

[0040] Figure 4 illustrates a cross-sectional view of a package 400 including channel interconnects. Package 400 may be a stacked package (PoP). Package 400 may be similar to package 100 and include components similar to those in package 100. Package 400 may include a first package 101 and a second package 103. Package 400 is coupled to board 110 via a plurality of solder interconnects 107. Package 400 includes a plurality of channel interconnects 408. The plurality of channel interconnects 408 may be examples of a plurality of channel interconnects 108. The plurality of channel interconnects 408 may be formed and / or located on a second substrate 104. The plurality of channel interconnects 408 may be coupled to a second plurality of interconnects 142. The plurality of channel interconnects 408 may be examples of means for channel interconnects. The plurality of channel interconnects 408 may be printed (e.g., inkjet printed) on the second substrate 104. The plurality of channel interconnects 408 includes a metal layer. However, in some implementations, the plurality of channel interconnects 408 may include two or more metal layers. When more than one metal layer exists for the plurality of channel interconnects 408, a dielectric layer may be formed or located on a first metal layer of the plurality of channel interconnects 408, and a second metal layer may be formed on the dielectric layer and the first metal layer. The plurality of channel interconnects 408 may be defined by channel interconnects on the first metal layer and the second metal layer. In this example, the plurality of channel interconnects 408 on the first metal layer and the second metal layer on the substrate 104 may be located (e.g., laterally) between adjacent solder interconnects from the plurality of solder interconnects 190. In some implementations, at least one dielectric layer (not shown) may be located on the plurality of interconnects 408. The at least one dielectric layer may include a polymer (e.g., a pure polymer). In some implementations, the dielectric layer located on the plurality of interconnects 408 is different from at least one dielectric layer 140 of the second substrate 104.

[0041] Electrical paths 305, 306, and / or 307 as described in FIG3 can be implemented in package 400. For example, electrical path 305 implemented in package 400 may include: (i) at least one solder interconnect (e.g., 170) coupling the second integrated device 107 to the second substrate 104, (ii) at least one first interconnect from a second plurality of interconnects 142 of the second substrate 104, (iii) at least one channel interconnect from the plurality of channel interconnects 408, (iv) at least one second interconnect from the second plurality of interconnects 142 of the second substrate 104, (v) at least one second solder interconnect from a first plurality of solder interconnects 112 coupling the second substrate 104 and the first substrate 102, and (vi) at least one interconnect from a first plurality of interconnects 122 of the first substrate 102. Electrical path 305 may extend to be coupled to board 106. For example, electrical path 305 may also include at least one solder interconnect from a plurality of solder interconnects 110 and at least one board interconnect from a plurality of board interconnects 162. Therefore, one or more signals between board 106 and the second integrated device 107 may travel via electrical path 305 as described above. Electrical path 305 may extend vertically through the peripheral portions of substrate 102 and / or substrate 104. For example, electrical path 305 may include interconnects (e.g., via interconnects) located in the peripheral portions of substrate 102 and / or substrate 104.

[0042] The electrical path 306 implemented in package 400 may include: (i) at least one solder interconnect (e.g., 170) coupling the second integrated device 107 to the second substrate 104, (ii) at least one first interconnect from a second plurality of interconnects 142 of the second substrate 104, (iii) at least one channel interconnect from a plurality of channel interconnects 408, (iv) at least one second interconnect from the second plurality of interconnects 142 of the second substrate 104, (v) at least one solder interconnect from a plurality of solder interconnects 112, at least one interconnect from a first plurality of interconnects 122, and (vi) at least one solder interconnect from a plurality of solder interconnects 150.

[0043] Electrical paths 307 implemented in package 400 may include: (i) at least one solder interconnect (e.g., 150) coupling the first integrated device 105 to the first substrate 102, (ii) at least one first interconnect from a first plurality of interconnects 122 of the first substrate 102, (iii) at least one solder interconnect from a plurality of solder interconnects 112 coupling the second substrate 104 and the first substrate 102, (iv) at least one interconnect from a second plurality of interconnects 142 of the second substrate 104, and (v) at least one solder interconnect from a plurality of solder interconnects 190 coupling the third integrated device 109 and the second substrate 104. Electrical paths 307 may extend vertically through the peripheral portions of substrates 102 and / or 104. For example, electrical paths 307 may include interconnects (e.g., via interconnects) located in the peripheral portions of substrates 102 and / or 104. The periphery of the substrates (e.g., 102, 104) may be defined differently. In some implementations, the peripheral portion of the substrate may include one or more substrate portions (e.g., including interconnects) between the edges of the substrate (e.g., first edge, second edge, third edge, fourth edge) and an inner portion of the substrate located above or below the outermost rows of solder interconnects relative to the center of the substrate. The solder interconnect rows may be positioned along the X direction and / or along the Y direction. For example, the periphery of substrate 102 may include the edges of substrate 102 and one or more portions of substrate 102 between the edges of substrate 102 and an inner portion located above or below the outermost rows of solder interconnects 112 (e.g., the rows of solder interconnects closest to the edges of the substrate, the row closest to the first edge, the row closest to the second edge, the row closest to the third edge, the row closest to the fourth edge). The periphery of substrate 104 may include an edge of substrate 104 and one or more portions of substrate 104 located above or below the outermost rows of solder interconnects 112 (e.g., rows of solder interconnects closest to the edges of the substrate, rows closest to the first edge, rows closest to the second edge, rows closest to the third edge, rows closest to the fourth edge). In some implementations, the peripheral portion of the substrate may include an edge of the substrate and one or more portions of substrate located above or below the inner portions of the two outermost rows of solder interconnects 112 (e.g., two rows of solder interconnects closest to the edges of the substrate).

[0044] Figure 5 illustrates a plan view of a cross-section AA across substrate 400. Figure 5 illustrates a second substrate 104, a second integration device 107, a plurality of solder interconnects 190, and a plurality of channel interconnects 408. As shown in Figure 5, at least one channel interconnect from the plurality of channel interconnects 408 is located between adjacent solder interconnects from the plurality of solder interconnects 190. The plurality of channel interconnects 408 are located above the second substrate 104. The plurality of channel interconnects 408 may extend below the third integration device 109. The plurality of channel interconnects 408 may include channel traces and / or channel pads. The plurality of channel interconnects 408 face each of the four sides of the integration device 107. For example, a first plurality of channel interconnects face a first side of the integration device 107, a second plurality of channel interconnects face a second side of the integration device 107, a third plurality of channel interconnects face a third side of the integration device 107, and a fourth plurality of channel interconnects face a fourth side of the integration device 107. However, note that the plurality of channel interconnects may face fewer than all four sides of the integrated device 107 (e.g., facing one or more sides of the integrated device). The plurality of channel interconnects 408 may laterally surround the second integrated device 107. The plurality of channel interconnects 408 may include one or more metal layers (e.g., one metal layer, two metal layers) to accommodate various interconnection needs and / or designs. The plurality of solder interconnects 190 may laterally surround the second integrated device 107.

[0045] Figure 6 illustrates a cross-sectional view of a package 600 including channel interconnects. Package 600 may be a PoP (PoP) package. Package 600 may be similar to package 100 and include components similar to those in package 100. Package 600 may include a first package 101 and a second package 103. Package 600 is coupled to a board 106 via a plurality of solder interconnects 110. Package 600 includes a plurality of channel substrates 608 (e.g., a fourth substrate, a surface mount substrate). The plurality of channel substrates 608 may include at least one channel dielectric layer 602 and a plurality of channel interconnects 408. The plurality of channel substrates 608 may include different numbers of metal layers. The plurality of channel substrates 608 may be an example of the plurality of channel interconnects 108. The plurality of channel substrates 608 may be provided on a second substrate 104. The plurality of channel substrates 608 may be coupled to a second plurality of interconnects 142 via a plurality of solder interconnects 610. For example, the plurality of channel interconnects 408 can be coupled to a second plurality of interconnects 142 via a plurality of solder interconnects 610. The plurality of channel substrates 608 can be an example of a device for channel interconnects. FIG6 illustrates a plurality of channel substrates 608 coupled to a second substrate 104 via a plurality of solder interconnects 610 (e.g., ball grid array (BGA)). However, in some implementations, the plurality of channel substrates 608 can be coupled to the second substrate 104 via a plane grid array (LGA). In some implementations, the plurality of channel interconnects 408 of the plurality of channel substrates 608 can be coupled to the second plurality of interconnects 142 without solder interconnects. FIG6 illustrates a plurality of channel substrates 608 including a single metal layer. However, in some implementations, the plurality of channel substrates 608 can include a plurality of channel interconnects 408 on two or more metal layers.

[0046] Electrical paths 305, 306, and / or 307 as described in FIG3 can be implemented in package 600. For example, electrical path 305 implemented in package 600 may include: (i) at least one solder interconnect (e.g., 170) coupling the second integrated device 107 to the second substrate 104, (ii) at least one first interconnect from a second plurality of interconnects 142 of the second substrate 104, (iii) at least one channel interconnect from a plurality of channel interconnects 408 of a plurality of channel substrates 608 (which may also include solder interconnects from a plurality of solder interconnects 610 (among and from the plurality of solder interconnects 610), (iv) at least one second interconnect from the second plurality of interconnects 142 of the second substrate 104, (v) at least one second solder interconnect from a first plurality of solder interconnects 112 coupling the second substrate 104 and the first substrate 102, and (vi) at least one interconnect from a first plurality of interconnects 122 of the first substrate 102. Electrical path 305 may extend to be coupled to board 106. For example, electrical path 305 may also include at least one solder interconnect from a plurality of solder interconnects 110 and at least one board interconnect from a plurality of board interconnects 162. Thus, one or more signals between board 106 and second integrated device 107 may travel via electrical path 305 as described above.

[0047] The electrical path 306 implemented in package 600 may include: (i) at least one solder interconnect (e.g., 170) coupling the second integrated device 107 to the second substrate 104, (ii) at least one first interconnect from a second plurality of interconnects 142 of the second substrate 104, (iii) at least one channel interconnect from a plurality of channel interconnects 408 of a plurality of channel substrates 608 (which may also include solder interconnects from a plurality of solder interconnects 610 (among and from the plurality of solder interconnects), (iv) at least one second interconnect from the second plurality of interconnects 142 of the second substrate 104, (v) at least one solder interconnect from a plurality of solder interconnects 112, at least one interconnect from a first plurality of interconnects 122, and (vi) at least one solder interconnect from a plurality of solder interconnects 150.

[0048] The electrical path 307 implemented in package 600 may include: (i) at least one solder interconnect (e.g., 150) coupling the first integrated device 105 to the first substrate 102, (ii) at least one first interconnect from the first plurality of interconnects 122 of the first substrate 102, (iii) at least one solder interconnect from the plurality of solder interconnects 112 coupling the second substrate 104 and the first substrate 102, (iv) at least one interconnect from the second plurality of interconnects 142 of the second substrate 104, and (v) at least one solder interconnect from the plurality of solder interconnects 190 coupling the third integrated device 109 and the second substrate 104.

[0049] Figure 7 illustrates a plan view of a cross-section AA across substrate 600. Figure 7 illustrates a second substrate 104, a second integration device 107, a plurality of solder interconnects 190, and a plurality of channel substrates 608. As shown in Figure 7, at least some of the plurality of channel interconnects 408 from the plurality of channel substrates 608 are located between adjacent solder interconnects from the plurality of solder interconnects 190. The plurality of channel interconnects 408 from the plurality of channel substrates 608 and the plurality of channel substrates 608 are located above the second substrate 104. The plurality of channel interconnects 408 may extend below the third integration device 109. The plurality of channel interconnects 408 may include channel traces and / or channel pads. The plurality of channel substrates 608 face each of the four sides of the integration device 107. For example, a first plurality of channel substrates face a first side of the integrated device 107, a second plurality of channel substrates face a second side of the integrated device 107, a third plurality of channel substrates face a third side of the integrated device 107, and a fourth plurality of channel substrates face a fourth side of the integrated device 107. However, note that the plurality of channel substrates may face fewer than all four sides of the integrated device 107 (e.g., facing one or more sides of the integrated device). The plurality of channel interconnects 408 face each of the four sides of the integrated device 107. For example, a first plurality of channel interconnects face a first side of the integrated device 107, a second plurality of channel interconnects face a second side of the integrated device 107, a third plurality of channel interconnects face a third side of the integrated device 107, and a fourth plurality of channel interconnects face a fourth side of the integrated device 107. However, note that the plurality of channel interconnects may face fewer than all four sides of the integrated device 107 (e.g., facing one or more sides of the integrated device). The plurality of channel substrates 608 may laterally surround the second integrated device 107. The plurality of channel substrates 608 may include one or more metal layers (e.g., one metal layer, two metal layers) to accommodate various interconnection needs and / or designs. The plurality of solder interconnects 190 may laterally surround the second integration device 107.

[0050] Figure 8 illustrates a cross-sectional view of a package 800 including channel interconnects. Package 800 may be a PoP (PoP) package. Package 800 may be similar to package 100 and include components similar to those in package 100. Package 800 may include a first package 101 and a second package 103. Package 800 is coupled to board 106 via a plurality of solder interconnects 110. Package 800 includes a plurality of flexible cables 808 (e.g., flexible substrate, flexible board, flexible printed circuit board). The plurality of flexible cables 808 may include at least one flexible dielectric layer 802 and a plurality of channel interconnects 408. The at least one flexible dielectric layer 802 may include polyimide. The plurality of flexible cables 808 may include different numbers of metal layers. The plurality of flexible cables 808 may be examples of the plurality of channel interconnects 108. The plurality of flexible cables 808 may be provided on a second substrate 104. The plurality of flexible cables 808 can be coupled to a second plurality of interconnects 142 via a plurality of solder interconnects 810. For example, the plurality of channel interconnects 408 can be coupled to a second plurality of interconnects 142 via the plurality of solder interconnects 810. The plurality of flexible cables 808 can be an example of a device for channel interconnects. Figure 8 illustrates a plurality of flexible cables 808 comprising a single metal layer. However, in some implementations, the plurality of flexible cables 808 may comprise a plurality of channel interconnects 408 on two or more metal layers.

[0051] Electrical paths 305, 306, and / or 307 as described in FIG3 can be implemented in package 800. For example, electrical path 305 implemented in package 800 may include: (i) at least one solder interconnect (e.g., 170) coupling the second integrated device 107 to the second substrate 104, (ii) at least one first interconnect from the second plurality of interconnects 142 of the second substrate 104, (iii) at least one channel interconnect from the plurality of channel interconnects 408 of the plurality of flexible cables 808 (which may also include solder interconnects from the plurality of solder interconnects 810 (among and from the plurality of solder interconnects 610), (iv) at least one second interconnect from the second plurality of interconnects 142 of the second substrate 104, (v) at least one second solder interconnect from the first plurality of solder interconnects 112 coupling the second substrate 104 and the first substrate 102, and (vi) at least one interconnect from the first plurality of interconnects 122 of the first substrate 102. Electrical path 305 may extend to be coupled to board 106. For example, electrical path 305 may also include at least one solder interconnect from a plurality of solder interconnects 110 and at least one board interconnect from a plurality of board interconnects 162. Thus, one or more signals between board 106 and second integrated device 107 may travel via electrical path 305 as described above.

[0052] The electrical path 306 implemented in package 800 may include: (i) at least one solder interconnect (e.g., 170) coupling the second integrated device 107 to the second substrate 104, (ii) at least one first interconnect from a second plurality of interconnects 142 of the second substrate 104, (iii) at least one channel interconnect from a plurality of flexible cables 408 of a plurality of channel substrates 808 (which may also include solder interconnects from a plurality of solder interconnects 810 (among or from the plurality of solder interconnects 610), (iv) at least one second interconnect from the second plurality of interconnects 142 of the second substrate 104, (v) at least one solder interconnect from a plurality of solder interconnects 112, at least one interconnect from a first plurality of interconnects 122, and (vi) at least one solder interconnect from a plurality of solder interconnects 150.

[0053] The electrical path 307 implemented in package 800 may include: (i) at least one solder interconnect (e.g., 150) coupling the first integrated device 105 to the first substrate 102, (ii) at least one first interconnect from the first plurality of interconnects 122 of the first substrate 102, (iii) at least one solder interconnect from the plurality of solder interconnects 112 coupling the second substrate 104 and the first substrate 102, (iv) at least one interconnect from the second plurality of interconnects 142 of the second substrate 104, and (v) at least one solder interconnect from the plurality of solder interconnects 190 coupling the third integrated device 109 and the second substrate 104.

[0054] Figure 9 illustrates a plan view of a cross-section AA across substrate 800. Figure 9 illustrates a second substrate 104, a second integration device 107, a plurality of solder interconnects 190, and a plurality of flexible cables 808. As shown in Figure 9, at least some of the plurality of channel interconnects 408 from the plurality of flexible cables 808 are located between adjacent solder interconnects from the plurality of solder interconnects 190. The plurality of channel interconnects 408 from the plurality of flexible cables 808 and the plurality of flexible cables 808 are located above the second substrate 104. The plurality of channel interconnects 408 may extend below the third integration device 109. The plurality of channel interconnects 408 may include channel traces and / or channel pads. The plurality of flexible cables 808 face each of the four sides of the integration device 107. For example, a first plurality of flexible cables face a first side of the integrated device 107, a second plurality of flexible cables face a second side of the integrated device 107, a third plurality of flexible cables face a third side of the integrated device 107, and a fourth plurality of flexible cables face a fourth side of the integrated device 107. However, note that the plurality of flexible cables may face fewer than all four sides of the integrated device 107 (e.g., facing one or more sides of the integrated device). The plurality of channel interconnects 408 face each of the four sides of the integrated device 107. For example, a first plurality of channel interconnects face a first side of the integrated device 107, a second plurality of channel interconnects face a second side of the integrated device 107, a third plurality of channel interconnects face a third side of the integrated device 107, and a fourth plurality of channel interconnects face a fourth side of the integrated device 107. However, note that the plurality of channel interconnects may face fewer than all four sides of the integrated device 107 (e.g., facing one or more sides of the integrated device). The plurality of flexible cables 808 may laterally surround the second integrated device 107. The plurality of flexible cables 808 may include one or more metal layers (e.g., one metal layer, two metal layers) to accommodate various interconnection needs and / or designs. The plurality of solder interconnects 190 may laterally surround the second integration device 107.

[0055] Figure 10 illustrates a cross-sectional view of package 1000 including channel interconnects. Package 1000 may be a stacked package (PoP). Package 1000 may be similar to package 100 and include components similar to those in package 100. Package 1000 may include a first package 101 and a second package 103. Package 1000 is coupled to board 106 via a plurality of solder interconnects 110.

[0056] Package 1000 includes a plurality of channel interconnects 108, a plurality of channel interconnects 1008, and a plurality of channel interconnects 1009. The plurality of channel interconnects 1008 may be implemented as a plurality of channel interconnects 408, a plurality of channel substrates 608, and / or a plurality of flexible cables 808, as described in Figures 4 to 9. Similarly, the plurality of channel interconnects 1009 may be implemented as a plurality of channel interconnects 408, a plurality of channel substrates 608, and / or a plurality of flexible cables 808, as described in Figures 4 to 9. The plurality of channel interconnects 1008 are coupled to a first surface (e.g., top surface) of a first substrate 102. The plurality of channel interconnects 1009 are coupled to a second surface (e.g., bottom surface) of a second substrate 104.

[0057] Electrical path 1005 (e.g., a first electrical path, a second electrical path) may include a plurality of channel interconnects 1008 (e.g., a plurality of channel interconnects 408). For example, at least one signal traveling via electrical path 1005 may enter and exit the plurality of channel interconnects 1008 (e.g., a plurality of channel interconnects 408) via a first plurality of interconnects 122 of the first substrate 102 (e.g., via a first surface of the first substrate 102). In some implementations, electrical path 1005 may be implemented using electrical path 305, electrical path 306, and / or electrical path 307. Electrical path 1005 may be part of an electrical path (e.g., 305, 306, 307) coupled to a first integrated device 105, a second integrated device 107, and / or a third integrated device 109.

[0058] Electrical path 1006 (e.g., a first electrical path, a second electrical path) may include a plurality of channel interconnects 1009 (e.g., a plurality of channel interconnects 408). For example, at least one signal traveling via electrical path 1006 may enter and exit the plurality of channel interconnects 1009 (e.g., the plurality of channel interconnects 408) via a second plurality of interconnects 142 of the second substrate 104 (e.g., via a second surface of the second substrate 104). In some implementations, electrical path 1005 may be implemented using electrical path 305, electrical path 306, and / or electrical path 307. Electrical path 1006 may be part of an electrical path (e.g., 305, 306, 307) coupled to a first integrated device 105, a second integrated device 107, and / or a third integrated device 109.

[0059] As described in this case, the plurality of channel interconnects (e.g., 108, 1006, 1008) can be implemented as part of a package comprising one substrate, two substrates, or more than two substrates. The substrate may include one or more channel interconnects on one surface (e.g., top surface, bottom surface) or both surfaces. In some implementations, the package may include different designs and / or variations of the plurality of channel interconnects. For example, a combination of a substrate and a flexible cable may be used with the substrate. The plurality of channel interconnects may have different sizes and / or shapes. The plurality of channel interconnects may have different numbers of channel interconnects.

[0060] The integrated device (e.g., 105, 107, 109) may include a die (e.g., a semiconductor bare die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, gallium arsenide (GaAs)-based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si)-based integrated devices, silicon carbide (SiC)-based integrated devices, memory, power management processors, and / or combinations thereof. The integrated device (e.g., 105, 107, 109) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated device may include a transistor. The integrated device may be an example of electronic components and / or electrical devices.

[0061] Packages (e.g., 100, 400, 600, 800) can be implemented in radio frequency (RF) packages. RF packages can be radio frequency front-end (RFFE) packages. Packages (e.g., 100, 400, 600, 800) can be configured to provide Wi-Fi and / or cellular communication (e.g., 2G, 3G, 4G, 5G). Packages (e.g., 100, 400, 600, 800) can be configured to support Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), and / or Long Term Evolution (LTE). Packages (e.g., 100, 400) can be configured to transmit and receive signals with different frequencies and / or communication protocols.

[0062] Various packages have been described; the processes used to manufacture these packages will now be described below. Exemplary process for manufacturing a package including channel interconnects

[0063] In some implementations, manufacturing a package includes several processes. Figures 11A to 11C illustrate exemplary processes for providing or manufacturing a package including channel interconnects. In some implementations, the processes of Figures 11A-11C may be used to provide or manufacture package 400. However, the processes of Figures 11A-11C may be used to manufacture any package described in this case (e.g., 100, 1000).

[0064] It should be noted that the processes in Figures 11A-11C can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the package. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more processes can be substituted or replaced without departing from the scope of this application.

[0065] As shown in Figure 11A, stage 1 illustrates the state after substrate 102 has been provided. Substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. Substrate 102 may include a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). Substrate 102 can be manufactured using the methods described in Figures 14A-14B. In some implementations, a cored substrate (e.g., a substrate including a core layer) is provided.

[0066] Phase 2 illustrates the state after the first integrated device 105 has been coupled to a first surface (e.g., the top surface) of the substrate 102. The first integrated device 105 may be coupled to the substrate 102 via a plurality of solder interconnects 150. A solder reflow process may be used to couple the first integrated device 105 to the substrate 102.

[0067] Phase 3 illustrates the state after substrate 102 is coupled to substrate 104 via a plurality of solder interconnects 112. A solder reflow process can be used to couple substrate 104 to substrate 102. Substrate 104 is coupled to substrate 102 such that a first integrated device 105 is located between substrate 102 and substrate 104. Substrate 104 includes at least one dielectric layer 140 and a plurality of interconnects 142. Substrate 104 can be manufactured using the methods described in Figures 14A-14B. Substrate 104 can be an interposer.

[0068] As shown in Figure 11B, stage 4 illustrates the state after a plurality of channel interconnects 408 have been formed on the first surface of the second substrate 104. The plurality of channel interconnects 408 can be coupled to a second plurality of interconnects 142. The plurality of channel interconnects 408 can be printed (e.g., inkjet printed) on the second substrate 104. An additional metal layer can be formed on the substrate 104 for the plurality of channel interconnects 408. One or more dielectric layers can be formed on the plurality of channel interconnects 408.

[0069] Phase 5 illustrates the state after the second integrated device 107 has been coupled to a first surface (e.g., the top surface) of the substrate 104. The second integrated device 107 may be coupled to the substrate 104 via a plurality of solder interconnects 170. A solder reflow process may be used to couple the second integrated device 107 to the substrate 104.

[0070] As shown in Figure 11C, stage 6 illustrates the state after the third integration device 109 is coupled to a first surface (e.g., the top surface) of the substrate 104. The third integration device 109 may be coupled to the substrate 104 via a plurality of solder interconnects 190. A solder reflow process may be used to couple the third integration device 109 to the substrate 104. The third integration device 109 may be located above the second integration device 107. The second integration device 107 may be located between the third integration device 109 and the substrate 104. At least one channel interconnect from a plurality of channel interconnects 408 may be located between solder interconnects from a plurality of solder interconnects 190. The plurality of solder interconnects 190 may laterally surround the second integration device 107.

[0071] Phase 7 illustrates the state after a plurality of solder interconnects 110 have been coupled to the second surface of substrate 102. A solder reflow process can be used to couple the plurality of solder interconnects 110 to substrate 102. Phase 7 may illustrate a package 400 including a plurality of channel interconnects 408, as described at least in Figure 4. Package 400 may be manufactured one at a time, or may be manufactured together (partially or integrally as part of one or more strips or panels) and subsequently assembled or cut into individual packages. Exemplary process for manufacturing a package including channel interconnects

[0072] In some implementations, manufacturing a package includes several processes. Figures 12A to 12C illustrate exemplary processes for providing or manufacturing a package including channel interconnects. In some implementations, the processes of Figures 12A-12C may be used to provide or manufacture package 600. However, the processes of Figures 12A-12C may be used to manufacture any package described in this case (e.g., 800, 1000).

[0073] It should be noted that the processes in Figures 12A-12C can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the package. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more procedures can be substituted or replaced without departing from the scope of this application.

[0074] As shown in Figure 12A, stage 1 illustrates the state after substrate 102 has been provided. Substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. Substrate 102 may include a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). Substrate 102 can be manufactured using the methods described in Figures 14A-14B. In some implementations, a cored substrate (e.g., a substrate including a core layer) is provided.

[0075] Phase 2 illustrates the state after the first integrated device 105 has been coupled to a first surface (e.g., the top surface) of the substrate 102. The first integrated device 105 may be coupled to the substrate 102 via a plurality of solder interconnects 150. A solder reflow process may be used to couple the first integrated device 105 to the substrate 102.

[0076] Phase 3 illustrates the state after substrate 104 is coupled to substrate 102 via a plurality of solder interconnects 112. A solder reflow process can be used to couple substrate 104 to substrate 102. Substrate 104 is coupled to substrate 102 such that a first integrated device 105 is located between substrate 102 and substrate 104. Substrate 104 includes at least one dielectric layer 140 and a plurality of interconnects 142. Substrate 104 can be manufactured using the methods described in Figures 14A-14B. Substrate 104 can be an interposer.

[0077] As shown in Figure 12B, stage 4 illustrates the state after a plurality of channel substrates 608 have been coupled to a first surface of the second substrate 104. The plurality of channel substrates 608 may include a plurality of channel interconnects 408. The plurality of channel interconnects 408 may be coupled to a second plurality of interconnects 142 via a plurality of solder interconnects 610. In some implementations, the plurality of channel interconnects 408 from the plurality of channel substrates 608 may be coupled to the substrate 104 via a plane grid array (LGA).

[0078] In some implementations, as a supplement to or alternative to the plurality of channel substrates 608, a plurality of flexible cables 808 may be coupled to a first surface of the second substrate 104. In some implementations, the plurality of channel substrates 608 and / or the plurality of flexible cables 808 may be coupled to a second surface of the second substrate 104 and / or a first surface of the substrate 102. Before the substrate 104 is coupled to the substrate 102, the plurality of channel substrates 608 and / or the plurality of flexible cables 808 may be coupled to the second surface of the second substrate 104 and / or the first surface of the substrate 102.

[0079] Phase 5 illustrates the state after the second integrated device 107 has been coupled to a first surface (e.g., the top surface) of the substrate 104. The second integrated device 107 may be coupled to the substrate 104 via a plurality of solder interconnects 170. A solder reflow process may be used to couple the second integrated device 107 to the substrate 104.

[0080] As shown in Figure 12C, stage 6 illustrates the state after the third integration device 109 is coupled to a first surface (e.g., the top surface) of the substrate 104. The third integration device 109 may be coupled to the substrate 104 via a plurality of solder interconnects 190. A solder reflow process may be used to couple the third integration device 109 to the substrate 104. The third integration device 109 may be located above the second integration device 107. The second integration device 107 may be located between the third integration device 109 and the substrate 104. A plurality of channel interconnects 408 from a plurality of channel substrates 608 may be located between solder interconnects from the plurality of solder interconnects 190. The plurality of solder interconnects 190 may laterally surround the second integration device 107.

[0081] Phase 7 illustrates the state after a plurality of solder interconnects 110 have been coupled to the second surface of substrate 102. A solder reflow process can be used to couple the plurality of solder interconnects 110 to substrate 102. Phase 7 may illustrate a package 600 including a plurality of channel substrates 608, each including a plurality of channel interconnects 408, as described at least in Figure 6. Package 600 may be manufactured one at a time, or may be manufactured together as part of or integral to one or more strips or panels and subsequently assembled or cut into individual packages. Exemplary flowchart of a method for manufacturing a package including channel interconnects

[0082] In some implementations, manufacturing a package includes several processes. Figure 13 illustrates an exemplary flowchart of method 1300 for providing or manufacturing a package including channel interconnects. In some implementations, method 1300 of Figure 13 can be used to provide or manufacture packages 100, 400, 600, 800, and / or 1000 described herein. Method 1300 can be used to provide or manufacture any package described herein.

[0083] It should be noted that the method in Figure 13 can combine one or more processes to simplify and / or clarify the method used to provide or manufacture the package. In some implementations, the order of the processes can be changed or modified.

[0084] The method (at 1305) provides a first substrate (e.g., 102) and a first integrated means (e.g., 105) coupled to a first surface of the first substrate (e.g., 102). The first substrate 102 and the first integrated means 105 may be part of a first package 101. The first substrate 102 includes at least one first dielectric layer 120 and a first plurality of interconnects 122. Phase 2 of FIG11A illustrates and describes an example of a first substrate having the first integrated means. Phase 2 of FIG12A illustrates and describes an example of a first substrate having the first integrated means.

[0085] The method (at 1310) couples a second substrate (e.g., 104) to a first substrate (e.g., 102) via a plurality of solder interconnects (e.g., 112). The second substrate may include an interposer. The second substrate 104 includes at least one second dielectric layer 140 and a second plurality of interconnects 142. A solder reflow process may be used to couple the second substrate to the first substrate. Stage 3 of FIG11A illustrates and describes an example of a second substrate coupled to a first substrate. Stage 3 of FIG12A illustrates and describes an example of a second substrate coupled to a first substrate.

[0086] This method (at 1315) provides a plurality of channel interconnects on a first surface (e.g., top surface) of the second substrate 104. Different implementations may provide the plurality of channel interconnects differently. In some implementations, the plurality of channel interconnects 408 are formed on the second substrate 104 via a printing process (e.g., inkjet printing process), as described in stage 4 of FIG11B. In some implementations, the plurality of channel interconnects 408 are part of a plurality of channel substrates 608 coupled to the second substrate 104, as described in stage 4 of FIG12B. In some implementations, the plurality of channel interconnects 408 are part of a plurality of flexible cables 808 coupled to the second substrate 104, as described in stage 4 of FIG12B. Note that this method may provide the plurality of channel interconnects on and / or under different surfaces of the first substrate 102 and / or the second substrate 104.

[0087] This method (at 1320) couples a second integrated device (e.g., 107) to a first surface of a second substrate (e.g., 104) via a plurality of solder interconnects (e.g., 170). A solder reflow process can be used to couple the second integrated device to the first surface of the second substrate 104. Phase 5 of Figure 11B illustrates and describes an example of a second integrated device coupled to a second substrate. Phase 5 of Figure 12B illustrates and describes an example of a second integrated device coupled to a second substrate.

[0088] The method (at 1325) couples a third integrated device (e.g., 109) to a first surface of a second substrate (e.g., 104) via a plurality of solder interconnects (e.g., 190). A solder reflow process can be used to couple the third integrated device to the first surface of the second substrate 104. The third integrated device 109 may be located above the second integrated device 107. The second integrated device 107 may be located between the third integrated device 109 and the substrate 104. A plurality of channel interconnects 408 may be located between the solder interconnects from the plurality of solder interconnects 190. A plurality of channel interconnects 408 from a plurality of channel substrates 608 may be located between the solder interconnects from the plurality of solder interconnects 190. A plurality of channel interconnects 408 from a plurality of flexible cables 808 may be located between the solder interconnects from the plurality of solder interconnects 190. The plurality of solder interconnects 190 may laterally surround the second integrated device 107.

[0089] In some implementations, several packages are manufactured simultaneously. In such cases, the method can (at 1330) cut the package into individual units (e.g., 100, 400, 600, 800, 1000). In other cases, the cutting occurs before the substrates are coupled to each other. Exemplary process for manufacturing a substrate

[0090] In some implementations, manufacturing the substrate includes several processes. Figures 14A-14B illustrate exemplary processes for providing or manufacturing the substrate. In some implementations, the processes of Figures 14A-14B may be used to provide or manufacture substrate 102. However, the processes of Figures 14A-14B may be used to manufacture any substrate described in this case, such as substrate 104 and / or channel substrate 608.

[0091] It should be noted that the processes in Figures 14A-14B can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the substrate. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more processes can be substituted or replaced without departing from the scope of this application.

[0092] As shown in Figure 14A, Stage 1 illustrates the state after the carrier 1400 is provided. A seed layer 1401 and interconnects 1402 may be located on the carrier 1400. Interconnects 1402 may be located on the seed layer 1401. Interconnects 1402 can be formed using plating and etching processes. In some implementations, the carrier 1400 may be provided with a seed layer 1401 and a metal layer patterned to form interconnects 1402. Interconnects 1402 may represent at least some of the plurality of interconnects 122.

[0093] Phase 2 illustrates the state after the dielectric layer 1420 is formed over the carrier 1400, seed layer 1401, and interconnect 1402. The dielectric layer 1420 can be formed using deposition and / or lamination processes. The dielectric layer 1420 may include prepreg and / or polyimide. The dielectric layer 1420 may include photoimageable dielectrics. However, different implementations may use different materials for the dielectric layer.

[0094] Stage 3 illustrates the state after the plurality of cavities 1410 are formed in the dielectric layer 1420. The plurality of cavities 1410 can be formed using an etching process (e.g., a photolithography process) or a laser process.

[0095] Stage 4 illustrates the state after interconnects 1412 are formed in and on the dielectric layer 1420 (including in and on the plurality of cavities 1410). For example, vias, pads, and / or traces may be formed. Plating processes may be used to form the interconnects.

[0096] Phase 5 illustrates the state after dielectric layer 1422 is formed over dielectric layer 1420 and interconnect 1412. Dielectric layer 1422 can be formed using deposition and / or lamination processes. Dielectric layer 1422 may include prepreg and / or polyimide. Dielectric layer 1422 may include photoimageable dielectric. However, different implementations may use different materials for the dielectric layer.

[0097] As shown in Figure 14B, stage 6 illustrates the state after the plurality of cavities 1430 have been formed in the dielectric layer 1422. The plurality of cavities 1430 can be formed using an etching process (e.g., a photolithography process) or a laser process.

[0098] Stage 7 illustrates the state after interconnects 1414 are formed in and over dielectric layer 1422 (including in and over the plurality of cavities 1430). For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects. The plurality of interconnects 1402, the plurality of interconnects 1412, and / or the plurality of interconnects 1414 may be represented by the plurality of interconnects 122. Dielectric layer 1420 and / or dielectric layer 1422 may be represented by the at least one dielectric layer 120. The at least one dielectric layer 120 may include a photoimageable dielectric. The at least one dielectric layer 120 may include a prepreg and / or polyimide.

[0099] Phase 8 illustrates the state after the carrier 1400 is decoupled (e.g., separated, removed, ground away) from the at least one dielectric layer 120 and the seed layer 1401, and portions of the seed layer 1401 are removed (e.g., etched away), leaving the substrate 102 including the at least one dielectric layer 120 and the plurality of interconnects 122.

[0100] In some implementations, the substrate may include a solder resist layer. Stage 9 illustrates the state after solder resist layers 124 and 126 have been formed on substrate 102. Solder resist layers 124 and 126 can be formed using a deposition process. In some implementations, a solder resist layer may not be formed or may be formed over at least one dielectric layer 120.

[0101] Different implementations may use different processes to form the metal layers and / or interconnects. In some implementations, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form the metal layers. Exemplary flowchart of a method for manufacturing a substrate

[0102] In some implementations, manufacturing the substrate includes several processes. Figure 15 illustrates an exemplary flowchart of a method 1500 for providing or manufacturing a substrate. In some implementations, method 1500 of Figure 15 can be used to provide or manufacture the substrate(s) of this invention. For example, method 1500 of Figure 15 can be used to manufacture substrate 102.

[0103] It should be noted that method 1500 of Figure 15 can combine one or more processes to simplify and / or clarify the method for providing or manufacturing a substrate. In some implementations, the order of the processes can be changed or modified.

[0104] The method (at 1505) provides a carrier (e.g., 1400). Different implementations may use different materials for the carrier 1400. The carrier 1400 may include a seed layer (e.g., 1401). The seed layer 1401 may include a metal (e.g., copper). The carrier may include a substrate, glass, quartz, and / or a carrier strip. Phase 1 of Figure 14A illustrates and describes an example of providing a carrier with a seed layer.

[0105] This method (at 1510) forms and patterns interconnects over a carrier 1400 and a seed layer 1401. A metal layer may be patterned to form the interconnects. A plating process may be used to form the metal layer and the interconnects. In some implementations, the carrier and seed layer may include a metal layer. The metal layer is located over the seed layer and may be patterned to form interconnects (e.g., 402). Stage 1 of Figure 14A illustrates and describes an example of forming and patterning interconnects over a seed layer and a carrier.

[0106] This method (at 1515) forms a dielectric layer 1420 over a seed layer 1401, a carrier 1400, and an interconnect 1402. The dielectric layer 1420 can be formed using deposition and / or lamination processes. The dielectric layer 1420 may include a prepreg and / or polyimide. The dielectric layer 1420 may include a photoimageable dielectric. Forming the dielectric layer 1420 may also include forming a plurality of cavities (e.g., 1410) within the dielectric layer 1420. These cavities can be formed using etching processes (e.g., photolithography) or laser processes. Stages 2-3 of Figure 14A illustrate and depict examples of forming a dielectric layer and forming cavities within it.

[0107] This method (at 1520) forms interconnects within and over the dielectric layer. For example, interconnect 1420 may be formed within and over dielectric layer 1412. A plating process may be used to form the interconnects. Forming interconnects may include providing a patterned metal layer over and / or within the dielectric layer. Forming interconnects may also include forming interconnects within cavities of the dielectric layer. Stage 4 of Figure 14A illustrates and describes an example of forming interconnects within and over the dielectric layer.

[0108] The method (at 1525) forms a dielectric layer 1422 over a dielectric layer 1420 and an interconnect 1412. The dielectric layer 1422 can be formed using deposition and / or lamination processes. The dielectric layer 1422 may include a prepreg and / or polyimide. The dielectric layer 1422 may include a photoimageable dielectric. Forming the dielectric layer 1422 may also include forming a plurality of cavities (e.g., 1430) within the dielectric layer 1422. These cavities can be formed using etching processes (e.g., photolithography) or laser processes. Stages 5–6 of Figures 14A–14B illustrate and describe examples of forming a dielectric layer and forming cavities within it.

[0109] This method (at 1530) forms interconnects within and over the dielectric layer. For example, interconnect 1422 may be formed within and over dielectric layer 1414. A plating process may be used to form the interconnects. Forming interconnects may include providing a patterned metal layer over and / or within the dielectric layer. Forming interconnects may also include forming interconnects within cavities of the dielectric layer. Stage 7 of Figure 14B illustrates and describes an example of forming interconnects within and over the dielectric layer.

[0110] This method (at 1535) decouples the carrier (e.g., 1400) from the seed layer (e.g., 1401). The carrier 1400 can be separated and / or ground away. This method can also (at 1535) remove portions of the seed layer (e.g., 1401). An etching process can be used to remove portions of the seed layer 1401. Stage 8 of Figure 14B illustrates and describes an example of carrier decoupling and seed layer removal.

[0111] In some implementations, the method may form a solder resist layer over a first surface and / or a second surface of the substrate. Stage 9 of Figure 14B illustrates and describes an example of forming a solder resist layer.

[0112] Different implementations may use different processes to form the metal layers. In some implementations, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form the metal layers. Exemplary electronic devices

[0113] Figure 16 illustrates various electronic devices that can integrate any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, stacked packages (PoP), system-in-package (SiP), or system-on-a-chip (SoC). For example, mobile phone device 1602, laptop device 1604, fixed-location terminal device 1606, wearable device 1608, or motor vehicle 1610 may include the device 1600 as described herein. Device 1600 may be any of the devices and / or integrated circuit (IC) packages described herein, for example. Devices 1602, 1604, 1606, and 1608, and vehicle 1610 illustrated in Figure 16 are merely exemplary. Other electronic devices may also be characterized by device 1600, including but not limited to a group of devices (e.g., electronic devices) comprising: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablets, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0114] One or more of the components, programs, features, and / or functions illustrated in Figures 1-10, 11A-11C, 12A-12C, 13, 14A-14B, and 15-16 may be rearranged and / or combined into a single component, program, feature, or function, or may be implemented in several components, programs, or functions. Additional components, programs, and / or functions may also be added without departing from this invention. It should also be noted that Figures 1-10, 11A-11C, 12A-12C, 13, 14A-14B, and 15-16 and their corresponding descriptions in this invention are not limited to dies and / or ICs. In some implementations, Figures 1-10, 11A-11C, 12A-12C, 13, 14A-14B, and 15-16 and their corresponding descriptions may be used to manufacture, establish, provide, and / or produce apparatus and / or integrate apparatus. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a stacked package (PoP) device, a heat dissipation device, and / or an intermediary.

[0115] Note that the accompanying drawings in this application may represent actual and / or conceptual representations of various components, parts, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all components and / or parts are illustrated for clarity. In some instances, the positioning, location, size, and / or shape of the various components and / or parts in the drawings may be exemplary. In some implementations, the various components and / or parts in the drawings may be optional.

[0116] The term "exemplary" is used herein to mean "serving as an example, illustration, or diagram." Any implementation or manner described herein as "exemplary" need not be construed as superior to or better than other manners in this case. Similarly, the term "manner" does not require that all manners in this case include the features, advantages, or modes of operation discussed. The term "coupling" is used herein to refer to direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, then objects A and C can still be considered coupled to each other—even if they are not in direct physical contact. Object A coupled to object B may be coupled to at least a portion of object B. The term "electrical coupling" may mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can be transferred between the two objects. Electrically coupled objects may or may not have current transferred between them. The use of the terms "first," "second," "third," and "fourth" (and / or anything above fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as the second component can be a first component, a second component, a third component, or a fourth component. The terms "enclosing," "enclosing," and / or any derivative meaning that an object can partially or completely enclose another object. As used in this case, a first object surrounding a second object can mean that the first object partially surrounds or completely surrounds the second object. The terms "top" and "bottom" are arbitrary. A component located at the top can be situated on top of a component located at the bottom. A top component can be considered a bottom component, and vice versa. As described in this case, a first component situated "above" a second component can mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined. In another instance, a first component can be situated above (e.g., above) a first surface of a second component, while a third component can be situated above (e.g., below) a second surface of a second component, wherein the second surface is opposite the first surface. It should be further noted that the term "above," as used in the context of one component being above another in this case, can be used to mean that the component is on and / or in another component (e.g., on the surface of the component or embedded in the component). Thus, for example, "above a second component" can mean: (1) the first component is above the second component but does not directly contact the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component located "in" the second component can be partially or completely located in the second component. Values ​​of approximately X–XX can mean values ​​between X and XX (inclusive). Values(s) between X and XX can be discrete or continuous.The terms "approximately 'value X'" or "approximately 'value X'" as used in this case mean within ten percent of 'value X'. For example, a value of approximately 1 or approximately 1 would mean a value in the range of 0.9–1.1.

[0117] In some implementations, an interconnect is an element or component in a device or package that allows or facilitates an electrical connection between two points, elements, and / or parts. In some implementations, an interconnect may include traces (e.g., trace interconnects), vias (e.g., via interconnects), pads (e.g., pad interconnects), solder pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some implementations, an interconnect may include conductive material that can be configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or steps to form interconnects. In some implementations, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or electroplating processes may be used to form interconnects.

[0118] It should also be noted that the various disclosures contained herein can be described as programs illustrated as flowcharts, diagrams, block diagrams, or block diagrams. Although flowcharts can describe operations as a sequential procedure, many operations can be executed in parallel or concurrently. Furthermore, the order of operations can be rearranged. The program terminates when its operations are completed.

[0119] Further examples are described below to facilitate understanding of the invention.

[0120] Version 1: An apparatus comprising a first package and a second package coupled to the first package via a first plurality of solder interconnects. The first package includes: a first substrate including at least one first dielectric layer and a first plurality of interconnects, and a first integrated device coupled to the first substrate. The second package includes: a second substrate including at least one second dielectric layer and a second plurality of interconnects; a second integrated device coupled to a first surface of the second substrate; a third integrated device coupled to the first surface of the second substrate via a second plurality of solder interconnects; and a first plurality of channel interconnects coupled to the first surface of the second substrate, wherein the first plurality of channel interconnects are located between solder interconnects from the second plurality of solder interconnects.

[0121] State 2: The device as in State 1, wherein the second integrated device is located between the third integrated device and the second substrate.

[0122] State 3: The apparatus of states 1 to 2 further includes: a fourth substrate coupled to a first surface of a second substrate, wherein the first plurality of channel interconnects are part of the fourth substrate.

[0123] State 4: The apparatus of states 1 to 3 further includes: a flexible cable coupled to a first surface of a second substrate, wherein the first plurality of channel interconnects are part of the flexible cable.

[0124] State 5: A device as in states 1 to 4, wherein a first plurality of interconnected channels extend below a third integrated device.

[0125] State 6: A device as in States 1 to 5, wherein a first electrical path between the second integrated device and the first substrate includes a first plurality of channel interconnects.

[0126] Type 7: The apparatus of types 1 to 6, wherein the first electrical path between the second integrated device and the first substrate includes: at least one first solder interconnect coupling the second integrated device to the second substrate; at least one first interconnect from a second plurality of interconnects of the second substrate; at least one channel interconnect from a first plurality of channel interconnects; at least one second interconnect from a second plurality of interconnects of the second substrate; at least one second solder interconnect from a first plurality of solder interconnects coupling the second substrate and the first substrate; and at least one interconnect from a first plurality of interconnects of the first substrate.

[0127] State 8: The apparatus as in states 1 to 7, further comprising: a second plurality of channel interconnects coupled to a second surface of a second substrate.

[0128] State 9: The apparatus as in states 1 to 8, further comprising: a second plurality of channel interconnects coupled to a first surface of a first substrate.

[0129] Type 10: A device as in Types 8 to 9, wherein the second plurality of channel interconnects is part of a fourth substrate and / or a flexible cable.

[0130] Version 11: An apparatus comprising a first package and a second package coupled to the first package via a first plurality of solder interconnects. The first package includes: a first substrate including at least one first dielectric layer and a first plurality of interconnects; and a first integrated means coupled to the first substrate. The second package includes: a second substrate including at least one second dielectric layer and a second plurality of interconnects; a second integrated means coupled to a first surface of the second substrate; a third integrated means coupled to the first surface of the second substrate via a second plurality of solder interconnects; and means for channel interconnects coupled to the first surface of the second substrate, wherein the means for channel interconnects are located between solder interconnects from the second plurality of solder interconnects.

[0131] State 12: The equipment as in State 11, wherein: the second integration device is located between the third integration device and the second substrate.

[0132] State 13: The apparatus of states 11 to 12, wherein the means for channel interconnection includes a fourth substrate.

[0133] Version 14: Equipment as in versions 11 to 13, wherein the means for channel interconnection includes flexible cables.

[0134] Version 15: The equipment as in versions 11 to 14, wherein the means for channel interconnection extends below the third integration unit.

[0135] Version 16: An apparatus as in versions 11 to 15, wherein a first electrical path between the second integrated device and the first substrate includes means for channel interconnection.

[0136] Version 17: The apparatus of versions 11 to 16, wherein the first electrical path between the second integrated device and the first substrate includes: at least one first solder interconnect coupling the second integrated device to the second substrate; at least one first interconnect from a second plurality of interconnects of the second substrate; means for channel interconnection; at least one second interconnect from the second plurality of interconnects of the second substrate; at least one second solder interconnect from the first plurality of solder interconnects coupling the second substrate and the first substrate; and at least one interconnect from the first plurality of interconnects of the first substrate.

[0137] State 18: The apparatus of states 11 to 17 further includes: a second means for channel interconnection coupled to a second surface of a second substrate.

[0138] Version 19: The apparatus of versions 11 to 18 further includes: a second means for channel interconnection coupled to a first surface of the first substrate.

[0139] Type 20: Equipment as described in Types 11 to 19, wherein the equipment includes devices selected from the group comprising: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptops, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

[0140] Version 21: A method of providing a first package, the first package comprising: a first substrate including at least one first dielectric layer and a first plurality of interconnects; and a first integrated device coupled to the first substrate. The method couples a second substrate to the first substrate via a first plurality of solder interconnects, wherein the second substrate includes at least one second dielectric layer and a second plurality of interconnects. The method provides a first plurality of channel interconnects over a first surface of the second substrate. The method couples a second integrated device to the first surface of the second substrate. The method couples a third integrated device to the first surface of the second substrate via a second plurality of solder interconnects, wherein the first plurality of channel interconnects are located between solder interconnects from the second plurality of solder interconnects.

[0141] State 22: The method of State 21, wherein the second integration device is located between the third integration device and the second substrate.

[0142] Version 23: The method of versions 21 to 22, wherein providing the first plurality of channel interconnects includes coupling a fourth substrate including the first plurality of channel interconnects to a first surface of a second substrate.

[0143] Version 24: The method of versions 21 to 23, wherein providing the first plurality of channel interconnects includes coupling a flexible cable including the first plurality of channel interconnects to a first surface of a second substrate.

[0144] State 25: The method of states 21 to 24, wherein the first plurality of interconnected channels extend below the third integration device.

[0145] Version 26: A device including a package, the package comprising: a substrate including at least one dielectric layer and a plurality of interconnects; and an integrated means coupled to the substrate. The device includes a first plurality of channel interconnects coupled to a first surface of the substrate.

[0146] State 27: The device as in State 26 further includes: another substrate coupled to a first surface of the substrate, wherein the first plurality of channel interconnects are part of the other substrate.

[0147] Version 28: The apparatus of versions 26 to 27 further includes: a flexible cable coupled to a first surface of the substrate, wherein the first plurality of channel interconnects are part of the flexible cable.

[0148] State 29: A device as in States 26 to 28, wherein the first electrical path to / from the integrated device includes a first plurality of interconnected channels.

[0149] State 30: The apparatus as described in states 26 to 29, wherein

[0150] The first electrical path to / from the integrated device includes: at least one first solder interconnect coupling the integrated device to the substrate; at least one first interconnect from a plurality of interconnects of the substrate; at least one channel interconnect from a first plurality of channel interconnects; and at least one second interconnect from a plurality of interconnects of the substrate.

[0151] State 31: The apparatus of states 26 to 30 further includes: a second plurality of channel interconnects coupled to a second surface of the substrate.

[0152] State 32: A device as in State 31, wherein the second plurality of channel interconnects are part of a fourth substrate and / or a flexible cable.

[0153] State 33: The apparatus of states 1 to 32 further includes: another integrated device coupled to a first surface of the substrate via a second plurality of solder interconnects, wherein the first plurality of channel interconnects are located between solder interconnects from the second plurality of solder interconnects, wherein the other integrated device is located on the integrated device.

[0154] The various features of this invention described herein can be implemented in different systems without departing from this invention. It should be noted that the above-described embodiments are merely examples and should not be construed as limiting the scope of this invention. The descriptions of the embodiments are intended to be illustrative and not to limit the scope of the appended claims. Therefore, the teachings of this invention can be readily applied to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art to which this invention pertains.

[0155] 100: Package 101: First Package 102: First substrate 103: Second Package 104: Second substrate 105: Integrated Device 106: Board 107: Second Integration Device 108: Channel Interconnection 109: Third Integration Unit 110: Solder interconnect 112: Solder interconnect 120: Dielectric layer 122: Interconnection 140: Dielectric layer 142: Interconnection 150: Solder interconnect 160: Dielectric layer of the board 162: Board interconnection 170: Solder interconnect 190: Solder interconnect 305: Electrical Path 306: Electrical Path 307: Electrical Path 400: Package 408: Channel Interconnection 600: Package 602: Channel Dielectric Layer 608: Channel substrate 610: Solder interconnect 800: Package 802: Flexible dielectric layer 808: Flexible Cable 810: Solder interconnect 1000: Package 1005: Electrical Path 1006: Electrical Path 1008: Channel Interconnection 1009: Channel Interconnection 1300: Method 1305: Square 1310: Square 1315: Square 1320: Square 1325: Square 1330: Square 1400: Carrier 1401: Seed layer 1402: Interconnection 1410: cavity 1412: Interconnection 1414: Interconnection 1420: Dielectric layer 1422: Dielectric layer 1430: cavity 1500: Method 1505: Square 1510: Square 1515: Square 1520: Square 1525: Square 1530: Square 1535: Square 1600: Device 1602: Equipment 1604: Equipment 1606: Equipment 1608: Equipment 1610: Equipment A: Object X: Direction Y: direction Z: Direction

[0156] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A device with encapsulation, comprising: A first package includes: a first substrate including at least one first dielectric layer and a first plurality of interconnects; and a first integrated device coupled to the first substrate; and a second package includes: a second substrate including at least one second dielectric layer and a second plurality of interconnects, wherein the second substrate is coupled to the first substrate via a first plurality of solder interconnects; a second integrated device coupled to a first surface of the second substrate; a third integrated device coupled to the first surface of the second substrate via a second plurality of solder interconnects; and a first plurality of channel interconnects coupled to the first surface of the second substrate, wherein the first plurality of channel interconnects are laterally located between solder interconnects from the second plurality of solder interconnects.

2. The apparatus of claim 1, wherein the second integrated device is located between the third integrated device and the second substrate.

3. The apparatus of claim 1, further comprising a fourth substrate coupled to the first surface of the second substrate, wherein the first plurality of channel interconnects are part of the fourth substrate.

4. The apparatus of claim 1, further comprising a flexible cable coupled to the first surface of the second substrate, wherein the first plurality of interconnected channels are part of the flexible cable.

5. The apparatus of claim 1, wherein the first plurality of channel interconnects extends below the third integrated apparatus, and wherein the first plurality of channel interconnects are vertically located between the first substrate and the second substrate.

6. The apparatus of claim 1, wherein a first electrical path between the second integrated device and the first substrate includes the first plurality of channel interconnects.

7. The apparatus of claim 1, wherein a first electrical path between the second integrated device and the first substrate comprises: The second integrated device is coupled to at least one first solder interconnect on the second substrate; At least one first interconnect from the second plurality of interconnects originating from the second substrate; At least one channel interconnect from the first plurality of channel interconnects; At least one second interconnect from the second plurality of interconnects of the second substrate; at least one second solder interconnect from the first plurality of solder interconnects coupling the second substrate and the first substrate; and at least one interconnect from the first plurality of interconnects of the first substrate.

8. The apparatus of claim 1, further comprising a second plurality of channel interconnects coupled to a second surface of the second substrate.

9. The apparatus of claim 1, further comprising a second plurality of channel interconnects coupled to a first surface of the first substrate.

10. The apparatus of claim 9, wherein the second plurality of channel interconnects is part of a fourth substrate and / or a flexible cable.

11. An encapsulated device, comprising: A first package includes: a first substrate including at least one first dielectric layer and a first plurality of interconnects; and a first integrated device coupled to the first substrate; and a second package includes: a second substrate including at least one second dielectric layer and a second plurality of interconnects, wherein the second substrate is coupled to the first substrate via a first plurality of solder interconnects; a second integrated device coupled to a first surface of the second substrate; a third integrated device coupled to the first surface of the second substrate via a second plurality of solder interconnects; and a first device for channel interconnects coupled to the first surface of the second substrate, wherein the first device for channel interconnects is laterally located between the solder interconnects from the second plurality of solder interconnects.

12. The equipment as claimed in claim 11, wherein the second integrated device is located between the third integrated device and the second substrate.

13. The apparatus of claim 11, wherein the first device for channel interconnection includes a fourth substrate.

14. The equipment as claimed in claim 11, wherein the first device for channel interconnection includes a flexible cable.

15. The apparatus of claim 11, wherein the first means for channel interconnection extends below the third integrated means, and wherein the first means for channel interconnection is vertically located between the first substrate and the second substrate.

16. The apparatus of claim 11, wherein a first electrical path between the second integrated device and the first substrate includes the first device for channel interconnection.

17. The apparatus of claim 11, wherein a first electrical path between the second integrated device and the first substrate comprises: The second integrated device is coupled to at least one first solder interconnect on the second substrate; At least one first interconnect from the second plurality of interconnects originating from the second substrate; The first device for channel interconnection; At least one second interconnect from the second plurality of interconnects of the second substrate; at least one second solder interconnect from the first plurality of solder interconnects coupling the second substrate and the first substrate; and at least one interconnect from the first plurality of interconnects of the first substrate.

18. The apparatus of claim 11 further includes a second means for channel interconnection coupled to a second surface of the second substrate.

19. The apparatus of claim 11 further includes a second means for channel interconnection coupled to a first surface of the first substrate.

20. The equipment as claimed in claim 11, wherein the equipment includes a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a digital assistant, a fixed-location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

21. A method for manufacturing a package, comprising the following steps: A first package is provided, the first package comprising: a first substrate including at least one first dielectric layer and a first plurality of interconnects; and a first integrated device coupled to the first substrate; a second substrate coupled to the first substrate via a first plurality of solder interconnects, wherein the second substrate includes at least one second dielectric layer and a second plurality of interconnects; a first plurality of channel interconnects provided on a first surface of the second substrate; a second integrated device coupled to the first surface of the second substrate; and a third integrated device coupled to the first surface of the second substrate via a second plurality of solder interconnects, wherein the first plurality of channel interconnects are laterally located between solder interconnects from the second plurality of solder interconnects.

22. The method of claim 21, wherein the second integration device is located between the third integration device and the second substrate.

23. The method of claim 21, wherein the step of providing the first plurality of channel interconnects includes the step of coupling a fourth substrate including the first plurality of channel interconnects to the first surface of the second substrate.

24. The method of claim 21, wherein the step of providing the first plurality of channel interconnects includes the step of coupling a flexible cable including the first plurality of channel interconnects to the first surface of the second substrate.

25. The method of claim 21, wherein the first plurality of channel interconnects extends below the third integrated device, and wherein the first plurality of channel interconnects are located vertically between the first substrate and the second substrate.

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