Capacitor-wire-embedded wiring board

Abstract

A terminal block includes: an insulating layer having a first surface and a second surface opposite to each other; an upper wiring pattern located on the first surface of the insulating layer; a lower wiring pattern located on the second surface of the insulating layer; a middle wiring pattern disposed in the insulating layer and electrically connected to the upper wiring pattern and the lower wiring pattern; and capacitor lines connected to corresponding wiring patterns in the upper wiring pattern, the lower wiring pattern, and the middle wiring pattern. The capacitor lines include: a core electrode line having a linear shape; an outer electrode line covering at least a portion of the core electrode line; and a dielectric line sandwiched between the core electrode line and the outer electrode line.

Description

Capacitor wire-embedded wiring board [Cross-reference to related applications] This patent application claims the priority of Korean Patent Application No. 10-2022-0033342, filed with the Korean Intellectual Property Office on March 17, 2022, the entire contents of which are incorporated herein by reference. This disclosure relates to a capacitor wire-embedded wiring board. To achieve a high-performance electronic device with various functions, a plurality of active components and passive components are mounted on the surface of a wiring board. Passive components are used for effective signal exchange between active components and may include resistors, inductors, capacitors, and the like. To mount passive components at high density, many studies are underway to develop an embedded wiring board in which passive components are embedded. An embodiment of the inventive concept provides an embedded wiring board whose size and thickness can be easily reduced. An embodiment of the inventive concept provides an embedded wiring board with high performance and improved reliability. According to an embodiment of the inventive concept, a wiring board may include: an insulating layer having a first surface and a second surface opposite to each other; an upper wiring pattern located on the first surface of the insulating layer; a lower wiring pattern located on the second surface of the insulating layer; an intermediate wiring pattern disposed in the insulating layer and electrically connected to the upper wiring pattern and the lower wiring pattern; and a capacitor wire connected to a corresponding wiring pattern among the upper wiring pattern, the lower wiring pattern, and the intermediate wiring pattern. The capacitor wire may include: a core electrode line having a linear shape; an external electrode line covering at least a portion of the core electrode line; and a dielectric line sandwiched between the core electrode line and the external electrode line. According to an embodiment of the inventive concept, a wiring board may include: an insulating layer having a first surface and a second surface opposite to each other; an upper wiring pattern located on the first surface of the insulating layer; a lower wiring pattern located on the second surface of the insulating layer; an intermediate wiring pattern disposed in the insulating layer and electrically connected to the upper wiring pattern and the lower wiring pattern; and a capacitor chip disposed in the insulating layer and electrically connected to a corresponding intermediate wiring pattern among the intermediate wiring patterns. The capacitor chip may include: a substrate having a top surface and a bottom surface opposite to each other; and a plurality of capacitor wires mounted on the top surface of the substrate. The capacitor chip may be electrically connected to the corresponding intermediate wiring pattern via the substrate. Each of the capacitor wires may include: a core electrode line having a linear shape; an external electrode line covering at least a portion of the core electrode line; and a dielectric line sandwiched between the core electrode line and the external electrode line. According to an embodiment of the inventive concept, a wiring board may include: an insulating layer having a first surface and a second surface opposite to each other; an upper wiring pattern located on the first surface of the insulating layer; a lower wiring pattern located on the second surface of the insulating layer; an intermediate wiring pattern disposed in the insulating layer and electrically connected to the upper wiring pattern and the lower wiring pattern; and a capacitor line connected to a corresponding wiring pattern among the upper wiring pattern, the lower wiring pattern, and the intermediate wiring pattern. The capacitor line may include: a core electrode line having a linear shape and extending in a longitudinal direction; a dielectric line disposed to surround an outer circumferential surface of the core electrode line and extending in the longitudinal direction; and an outer electrode line disposed to surround an outer circumferential surface of the dielectric line and extending in the longitudinal direction. The capacitor line may be connected to the corresponding wiring pattern by a wire bonding method. Exemplary embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments are shown. FIG. 1 is a cross-sectional view showing a wiring board according to an embodiment of the inventive concept. FIG. 2 is a schematic perspective view showing the capacitor line of FIG. 1, FIG. 3A is a cross-sectional view taken along line A-A' of FIG. 2, and FIG. 3B is a cross-sectional view taken along line B-B' of FIG. 2. FIG. 4 is a conceptual view showing an exemplary method of bonding the capacitor line of FIG. 2. Referring to FIG. 1, the wiring board 500 may include: an insulating layer IL having a first surface S1 and a second surface S2 opposite to each other; an upper wiring pattern 122 located on the first surface S1 of the insulating layer IL; a lower wiring pattern 132 located on the second surface S2 of the insulating layer IL; and intermediate wiring patterns 112 and 114 disposed in the insulating layer IL and electrically connected to the upper wiring pattern 122 and the lower wiring pattern 132. The insulating layer IL may include an upper insulating layer 120 adjacent to the first surface S1, a lower insulating layer 130 adjacent to the second surface S2, and an intermediate layer 100 located between the upper insulating layer 120 and the lower insulating layer 130. Each of the upper insulating layer 120 and the lower insulating layer 130 may be formed of or include an insulating polymer material, and may further include glass fibers. In an embodiment, the intermediate layer 100 may include a core substrate. The core substrate may be formed of or include an insulating polymer material, and may further include glass fibers. Alternatively, the core substrate may be formed of or include a metal material (e.g., copper and aluminum). In an embodiment, the intermediate layer 100 may include: a plurality of intermediate insulating layers disposed between the upper insulating layer 120 and the lower insulating layer 130 and stacked in a vertical direction VD perpendicular to the first surface S1; and a core substrate sandwiched between the intermediate insulating layers. In such a case, each of the intermediate insulating layers may be formed of or include an insulating polymer material, and may further include glass fibers. The upper wiring pattern 122 may be disposed on the first surface S1 of the insulating layer IL and on the upper insulating layer 120. The upper wiring pattern 122 may be formed of or include at least one of metal materials (e.g., copper). The lower wiring pattern 132 may be disposed on the second surface S2 of the insulating layer IL and on the lower insulating layer 130. The lower wiring pattern 132 may be formed of or include at least one of metal materials (e.g., copper). The intermediate wiring patterns 112 and 114 may include a first intermediate wiring pattern 112 disposed between the intermediate layer 100 and the upper insulating layer 120, and a second intermediate wiring pattern 114 disposed between the intermediate layer 100 and the lower insulating layer 130. The intermediate wiring patterns 112 and 114 may be formed of or include at least one of metal materials (e.g., copper). The wiring board 500 may further include: an upper through hole 126 disposed in the upper insulating layer 120 to electrically connect the upper wiring pattern 122 to the first intermediate wiring pattern 112; a lower through hole 136 disposed in the lower insulating layer 130 to electrically connect the lower wiring pattern 132 to the second intermediate wiring pattern 114; and an intermediate through hole 116 disposed in the intermediate layer 100 to electrically connect the first intermediate wiring pattern 112 to the second intermediate wiring pattern 114. The wiring board 500 may further include: additional intermediate wiring patterns disposed in the intermediate layer 100; and additional intermediate through holes configured to electrically connect the additional intermediate wiring patterns to each other. The upper through hole 126, the lower through hole 136, and the intermediate through hole 116 may be formed of at least one of metallic materials (e.g., copper) or include at least one of metallic materials (e.g., copper). The wiring board 500 may include a capacitor line WCAP electrically connected to corresponding ones of the upper wiring pattern 122, the lower wiring pattern 132, and the intermediate wiring patterns 112 and 114. The capacitor line WCAP may be connected to the corresponding wiring patterns 122, 132, 112, and 114 by a wire bonding method. Referring to FIGS. 2, 3A, and 3B, the capacitor line WCAP may include a core electrode line 10, an external electrode line 30 covering at least a portion of the core electrode line 10, a dielectric line 20 sandwiched between the core electrode line 10 and the external electrode line 30, and a passivation line 40 covering at least a portion of the external electrode line 30. The core electrode line 10 may have a linear shape and may extend in a specific direction. The specific direction may be referred to as the longitudinal direction LD of the core electrode line 10, and a direction perpendicular to the longitudinal direction LD may be referred to as the width direction WD. In an embodiment, as shown in FIG. 3B, when observed in a cross-sectional view taken in the width direction WD, the core electrode line 10 may have a circular shape or a cylindrical shape (e.g., the shape of a circle). In another embodiment, different from that shown in the drawings, when observed in a cross-sectional view taken in the width direction WD, the core electrode line 10 may have a polygonal shape (e.g., a rectangular shape). The core electrode line 10 may include a first metal, and the first metal may include at least one of, for example, Au, Ag, Pd, Cu, and Al. The dielectric line 20 may cover at least a portion of the core electrode line 10 and may extend in the longitudinal direction LD between the core electrode line 10 and the external electrode line 30. The dielectric line 20 may surround the outer peripheral surface 10os of the core electrode line 10 and may extend along the outer peripheral surface 10os of the core electrode line 10 or in the longitudinal direction LD. The dielectric line 20 may be formed of at least one of ceramic materials (e.g., Al 2 O 3 ) forming or including at least one of ceramic materials (e.g., Al 2 O 3 ). The inner surface of the dielectric line 20 can contact the outer peripheral surface 10os of the core electrode line 10, the inner surface of the outer electrode line 30 can contact the outer peripheral surface 20os of the dielectric line 20, and the inner surface of the passivation line 40 can contact the outer peripheral surface 30os of the outer electrode line 30. It should be understood that when an element is referred to as "connected" or "coupled" to another element or "located on another element", the one element can be directly connected or coupled to the other element or located on the other element, or there may be intermediate elements. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, or is referred to as "contacting" another element or "in contact with another element", there are no intermediate elements at the contact point. The outer electrode line 30 can cover at least a part of the dielectric line 20 and can extend in the longitudinal direction LD between the dielectric line 20 and the passivation line 40. The outer electrode line 30 can surround the outer peripheral surface 20os of the dielectric line 20 and can extend along the outer peripheral surface 20os of the dielectric line 20 or in the longitudinal direction LD. The outer electrode line 30 can be electrically disconnected or electrically isolated from the core electrode line 10 by the dielectric line 20. In the longitudinal direction LD, the length of the outer electrode line 30 can be less than the lengths of the core electrode line 10 and the dielectric line 20. The length of the dielectric line 20 can be substantially the same as the length of the core electrode line 10. The external electrode line 30 may be formed of at least one of metal materials including metal or metal alloy (i.e., "first metal") having a melting point lower than that of the core electrode line 10. In addition, the first metal may have a mechanical strength smaller than that of the core electrode line 10. For example, the external electrode line 30 may include a second metal different from the first metal, or an alloy of the second metal. In an embodiment, the external electrode line 30 may be formed of or include at least one of an arsenic-copper alloy, an aluminum-cerium alloy, an aluminum-scandium alloy, a silver-germanium alloy, a silver-palladium alloy, an aluminum-indium alloy, Field's metal, an arsenic-antimony alloy, an aluminum-magnesium alloy, a magnesium-praseodymium alloy, an arsenic-tin alloy, an aluminum-silicon alloy, a gold-magnesium alloy, an aluminum-gold alloy, a silver-aluminum alloy, a gold-lanthanum alloy, an aluminum-copper alloy, a silver-calcium alloy, an aluminum-calcium alloy, a silver-arsenic alloy, a silver-cerium alloy, a gold-cerium alloy, a silver-lanthanum alloy, a magnesium-nickel alloy, a gold-cadmium alloy, a silver-antimony alloy, a silver-magnesium alloy, a silver-strontium alloy, Babbitt metal, an aluminum-germanium alloy, a magnesium-strontium alloy, a gold-tellurium alloy, an aluminum-zinc alloy, a gold-silicon alloy, a gold-antimony alloy, a gold-germanium alloy, a silver-tellurium alloy, a magnesium-zinc alloy, or a silver-lead alloy. The passivation line 40 may cover at least a part of the external electrode line 30 and may extend on the external electrode line 30 in the longitudinal direction LD. The passivation line 40 may surround the outer peripheral surface 30os of the external electrode line 30 and may extend along the outer peripheral surface 30os of the external electrode line 30 and in the longitudinal direction LD. The external electrode line 30 may be sandwiched between the dielectric line 20 and the passivation line 40. The passivation line 40 may be formed of or include at least one of an insulating or ceramic material (e.g., Al 2 O 3 ), or a metal material (e.g., Au, Ni, and Pd). The length of the passivation line 40 may be smaller than the lengths of the core electrode line 10 and the dielectric line 20 in the longitudinal direction LD. The length of the passivation line 40 may be substantially the same as the length of the external electrode line 30. The end portion 10E of the core electrode line 10 may be surrounded by the end portion 20E of the dielectric line 20. The end portion 20E of the dielectric line 20 may not be covered by the external electrode line 30 and the passivation line 40 and may be exposed. The end portion 30E of the external electrode line 30 may be adjacent to the end portion 20E of the dielectric line 20 and may be covered by the passivation line 40. The first voltage V1 can be applied to the core electrode line 10 via the end portion 10E of the core electrode line 10, and the second voltage V2 can be applied to the external electrode line 30. The first voltage V1 and the second voltage V2 can be different from each other. For example, one of the first voltage V1 and the second voltage V2 can be a power supply voltage, and the other of the first voltage V1 and the second voltage V2 can be a ground voltage. Since different voltages are applied to the core electrode line 10 and the external electrode line 30, charges may accumulate in the dielectric line 20. Therefore, the linearly shaped capacitance line WCAP can be used as a capacitor. Referring to FIGS. 1 and 4, the capacitance line WCAP can be connected to the corresponding wiring patterns 122, 132, 112, and 114 by a wire bonding method. The capacitance line WCAP can have a first end portion E1 and a second end portion E2 that are opposite to each other in the longitudinal direction LD. At the first end portion E1 of the capacitance line WCAP, the end portion 10E of the core electrode line 10 can be connected to one of the corresponding wiring patterns 122, 132, 112, and 114 by a ball bonding method or a wedge bonding method. The first end portion E1 of the capacitance line WCAP can include the end portion 30E of the external electrode line 30, and the second end portion E2 of the capacitance line WCAP can include the opposite end portion of the external electrode line 30. At the second end portion E2 of the capacitance line WCAP, the opposite end portion of the external electrode line 30 can be connected to the other of the corresponding wiring patterns 122, 132, 112, and 114 by a wedge bonding method. For example, the capacitance line WCAP can be disposed on the first surface S1 of the insulating layer IL and can be connected to the corresponding upper wiring pattern 122 in the upper wiring pattern 122. At the first end portion E1 of the capacitance line WCAP, the core electrode line 10 can be connected to one of the corresponding upper wiring patterns 122 by a ball bonding method or a wedge bonding method, and at the second end portion E2 of the capacitance line WCAP, the external electrode line 30 can be connected to the other of the corresponding upper wiring patterns 122 by a wedge bonding method. As another example, the capacitance line WCAP can be disposed on the second surface S2 of the insulating layer IL and can be connected to the corresponding lower wiring pattern 132 in the lower wiring pattern 132. At the first end portion E1 of the capacitance line WCAP, the core electrode line 10 can be connected to one of the corresponding lower wiring patterns 132 by a ball bonding method or a wedge bonding method, and at the second end portion E2 of the capacitance line WCAP, the external electrode line 30 can be connected to the other of the corresponding lower wiring patterns 132 by a wedge bonding method. Referring back to FIG. 1, the wiring board 500 may further include an upper mask layer 150A and a lower mask layer 150B. The upper mask layer 150A is disposed on the first surface S1 of the insulating layer IL to cover the upper wiring pattern 122, and the lower mask layer 150B is disposed on the second surface S2 of the insulating layer IL to cover the lower wiring pattern 132. Each of the upper mask layer 150A and the lower mask layer 150B may be a solder mask or a solder resist, and may be formed of or include an insulating material. The capacitor wire WCAP connected to the corresponding upper wiring pattern 122 may be disposed in the upper mask layer 150A, and the capacitor wire WCAP connected to the corresponding lower wiring pattern 132 may be disposed in the lower mask layer 150B. The wiring board 500 may further include a protective layer 160 covering the surfaces of the upper wiring pattern 122, the lower wiring pattern 132, and the intermediate wiring patterns 112 and 114. The protective layer 160 may be formed of at least one of metal oxide materials (e.g., aluminum oxide) or include at least one of metal oxide materials (e.g., aluminum oxide), and may prevent the surfaces of the upper wiring pattern 122, the lower wiring pattern 132, and the intermediate wiring patterns 112 and 114 from being oxidized. The protective layer 160 covering the surface of the first intermediate wiring pattern 112 may be sandwiched between the first intermediate wiring pattern 112 and the upper insulating layer 120, and may extend into the region between the intermediate layer 100 and the upper insulating layer 120. The protective layer 160 covering the surface of the second intermediate wiring pattern 114 may be sandwiched between the second intermediate wiring pattern 114 and the lower insulating layer 130, and may extend into the region between the intermediate layer 100 and the lower insulating layer 130. The protective layer 160 covering the surface of the upper wiring pattern 122 may be sandwiched between the upper wiring pattern 122 and the upper mask layer 150A, and may extend into the region between the upper insulating layer 120 and the upper mask layer 150A. The capacitor wire WCAP may be disposed to penetrate the protective layer 160 and may be connected to the corresponding upper wiring pattern 122. The protective layer 160 covering the surface of the lower wiring pattern 132 may be sandwiched between the lower wiring pattern 132 and the lower mask layer 150B, and may extend into the region between the lower insulating layer 130 and the lower mask layer 150B. The capacitor wire WCAP may be disposed to penetrate the protective layer 160 and may be connected to the corresponding lower wiring pattern 132. In an embodiment, the protective layer 160 may be omitted. The upper mask layer 150A may include an upper opening OP_A. The upper opening OP_A may vertically overlap (e.g., in the vertical direction VD) a corresponding upper wiring pattern 122 in the upper wiring patterns 122, and may expose the protective layer 160 on the corresponding upper wiring pattern 122. The lower mask layer 150B may include a lower opening OP_B. The lower opening OP_B may vertically overlap (e.g., in the vertical direction VD) a corresponding lower wiring pattern 132 in the lower wiring patterns 132, and may expose the protective layer 160 on the corresponding lower wiring pattern 132. In an embodiment, the protective layer 160 may be omitted, and in such a case, the upper opening OP_A and the lower opening OP_B may expose the corresponding upper wiring pattern 122 and the corresponding lower wiring pattern 132, respectively. According to an embodiment of the inventive concept, the wiring board 500 may be an embedded wiring board in which a capacitive wire WCAP is embedded, and may be an embedded printed circuit board. The capacitive wire WCAP may have a wire shape, and may be connected to corresponding ones of the upper wiring pattern 122, the lower wiring pattern 132, and the intermediate wiring patterns 112 and 114 in the wiring board 500 by a wire bonding method. Since the capacitive wire WCAP has a wire shape, the size of the capacitive wire WCAP may be easily reduced. In addition, since the capacitive wire WCAP is connected to the corresponding wiring patterns 122, 132, 112, and 114 by a wire bonding method, the capacitive wire WCAP may be easily mounted in the wiring board 500. Accordingly, the integration density of the capacitive wire WCAP embedded in the wiring board 500 may be easily increased. Therefore, not only the size and thickness of the wiring board 500 may be easily reduced, but also the performance characteristics and reliability characteristics of the wiring board 500 may be improved. FIGS. 5 to 12 are conceptual diagrams exemplarily showing some methods of mounting the capacitive wire WCAP of FIG. 1 on the wiring board 500 of FIG. 1. Referring to FIGS. 5 to 8, the capacitive wire WCAP may be connected to the corresponding wiring patterns 122, 132, 112, and 114 by a wire bonding method. The capacitive wire WCAP may have a first end portion E1 and a second end portion E2 that face each other in the longitudinal or extending direction of the capacitive wire WCAP. As described with reference to FIG. 4, the first end portion E1 and the second end portion E2 of the capacitive wire WCAP may be connected to the corresponding wiring patterns 122, 132, 112, and 114 by a ball bonding method or a wedge bonding method. The capacitive wire WCAP connected to the corresponding wiring patterns 122, 132, 112, and 114 may have an arcuate shape. In an embodiment, as shown in FIG. 5, the first end portion E1 and the second end portion E2 of the capacitor line WCAP may be in contact with corresponding wiring patterns 122, 132, 112, and 114. In another embodiment, as shown in FIG. 6, solder balls 200 may be sandwiched between each of the first end portion E1 and the second end portion E2 of the capacitor line WCAP and the corresponding wiring patterns 122, 132, 112, or 114. The solder balls 200 may be formed of at least one of conductive materials (e.g., metal materials) or include at least one of conductive materials (e.g., metal materials). A portion of each of the first end portion E1 and the second end portion E2 of the capacitor line WCAP may be inserted into the solder balls 200. In yet another embodiment, as shown in FIG. 7, conductive bumps 210 may be sandwiched between each of the first end portion E1 and the second end portion E2 of the capacitor line WCAP and the corresponding wiring patterns 122, 132, 112, or 114. The conductive bumps 210 may be formed of at least one of conductive materials (e.g., metal materials) or include at least one of conductive materials (e.g., metal materials). In still another embodiment, as shown in FIG. 8, the first end portion E1 and the second end portion E2 of the capacitor line WCAP may be in contact with corresponding wiring patterns 122, 132, 112, and 114, and reinforcement patterns 220 may be respectively disposed on the corresponding wiring patterns 122, 132, 112, and 114. The reinforcement patterns 220 may be configured to respectively cover the first end portion E1 and the second end portion E2 of the capacitor line WCAP. The reinforcement patterns 220 may be formed of at least one of conductive materials (e.g., metal materials) or include at least one of conductive materials (e.g., metal materials). Referring to FIGS. 9 to 11, a plurality of capacitor lines WCAP may be connected to corresponding wiring patterns 122, 132, 112, and 114 by a wire bonding method. Each of the capacitor lines WCAP connected to the corresponding wiring patterns 122, 132, 112, and 114 may have an arcuate shape. In an embodiment, as shown in FIG. 9, the first end portions E1 of the plurality of capacitor lines WCAP may be commonly connected to one of the corresponding wiring patterns 122, 132, 112, and 114, and the second end portions E2 of the plurality of capacitor lines WCAP may be commonly connected to another one of the corresponding wiring patterns 122, 132, 112, and 114. The capacitor lines WCAP may have different lengths from each other and may be stacked in the vertical direction VD for installation on the corresponding wiring patterns 122, 132, 112, and 114. In another embodiment, as shown in FIG. 10, the first end portions E1 of the plurality of capacitor lines WCAP may be commonly connected to one of the corresponding wiring patterns 122, 132, 112, and 114, and the second end portions E2 of the plurality of capacitor lines WCAP may be commonly connected to another one of the corresponding wiring patterns 122, 132, 112, and 114. The capacitor lines WCAP may have substantially the same length and may be mounted on the corresponding wiring patterns 122, 132, 112, and 114 to be spaced apart from each other in a horizontal direction HD parallel to the first surface S1 of the insulating layer IL of FIG. 1. Terms such as "same", "equal", "planar", or "coplanar" as described herein encompass the same or approximately the same (including possible variations such as those occurring due to manufacturing processes). Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning. In yet another embodiment, as shown in FIG. 11, the first end portions E1 of the plurality of capacitor lines WCAP may be commonly connected to one of the corresponding wiring patterns 122, 132, 112, and 114, and the second end portions E2 of the plurality of capacitor lines WCAP may be respectively connected to different wiring patterns among the corresponding wiring patterns 122, 132, 112, and 114. In such a case, a ground voltage may be commonly applied to the plurality of capacitor lines WCAP, and different power supply voltages may be respectively applied to the plurality of capacitor lines WCAP. Referring to FIG. 12, the capacitor lines WCAP may be connected to the corresponding wiring patterns 122, 132, 112, and 114 by a stitch bonding method. In such a case, the capacitor lines WCAP may include external electrode segments spaced apart from each other in the extending direction (or longitudinal direction LD) of the capacitor lines WCAP. The external electrode segments of the capacitor lines WCAP may be respectively connected to the corresponding wiring patterns 122, 132, 112, and 114 by the stitch bonding method. The capacitor lines WCAP connected to the corresponding wiring patterns 122, 132, 112, and 114 may include a plurality of arc-shaped portions. FIG. 13 is a cross-sectional view of a wiring board showing an embodiment according to the inventive concept. For simplicity, the following will mainly describe features different from the wiring board described with reference to FIGS. 1 to 4. Referring to FIG. 13, the wiring board 500 may not include the upper mask layer 150A. Accordingly, the capacitor lines WCAP connected to the corresponding upper wiring pattern 122 and the protective layer 160 disposed on the upper wiring pattern 122 may be exposed. In an embodiment, the protective layer 160 may be omitted, and in such a case, the upper wiring pattern 122 may be exposed. FIG. 14 is a cross-sectional view showing a wiring board according to an embodiment of the concept of the present invention. For simplicity, the following will mainly describe features different from those of the wiring board described with reference to FIGS. 1 to 4. In some embodiments, as shown in FIG. 14, the capacitor line WCAP may be disposed in the insulating layer IL and may be connected to the corresponding intermediate wiring patterns 112 and 114 in the intermediate wiring patterns 112 and 114. For example, the capacitor line WCAP may be disposed in the upper insulating layer 120 and may be connected to the corresponding first intermediate wiring pattern 112 in the first intermediate wiring pattern 112. As shown in FIG. 4, at the first end portion E1 of the capacitor line WCAP, the core electrode line 10 may be connected to one of the corresponding intermediate wiring patterns 112 and 114 by a ball bonding method or a wedge bonding method, and at the second end portion E2 of the capacitor line WCAP, the external electrode line 30 may be connected to the other of the corresponding intermediate wiring patterns 112 and 114 by a wedge bonding method. In an embodiment, the insulating layer IL may include a cavity CV formed to penetrate the insulating layer IL, and the capacitor line WCAP may be disposed in the cavity CV. For example, the upper insulating layer 120 may include a cavity CV formed to penetrate the upper insulating layer 120, and the capacitor line WCAP may be disposed in the cavity CV. The capacitor line WCAP may be connected to one of the upper wiring patterns 122 and one of the first intermediate wiring patterns 112 by a wire bonding method. FIG. 15 is a cross-sectional view showing a wiring board according to an embodiment of the concept of the present invention. For simplicity, the following will mainly describe features different from those of the wiring board described with reference to FIGS. 1 to 4. Referring to FIG. 15, the insulating layer IL may include a cavity CV formed to penetrate the insulating layer IL, and the capacitor line WCAP may be disposed in the cavity CV. For example, the upper insulating layer 120 may include a first upper insulating layer 120a and a second upper insulating layer 120b sequentially stacked on the intermediate layer 100, and the first upper insulating layer 120a may include a cavity CV formed to penetrate the first upper insulating layer 120a. The capacitor line WCAP may be disposed in the cavity CV of the first upper insulating layer 120a and may be connected to the corresponding first intermediate wiring pattern 112 in the first intermediate wiring pattern 112. The wiring board 500 may further include a molding layer 170, and the molding layer 170 is disposed to fill the cavity CV and cover the capacitor line WCAP. The second upper insulating layer 120b may be disposed on the first upper insulating layer 120a and may extend to an area located on the molding layer 170. The molding layer 170 may be formed of or include an insulating polymer material and may further include glass fibers. Except for the foregoing features, the wiring board 500 according to the present embodiment may be substantially the same as the wiring board 500 described with reference to FIG. 14. FIG. 16 is a cross-sectional view showing a wiring board according to an embodiment of the concept of the present invention. For simplicity, the following will mainly describe the features different from the wiring board described with reference to FIGS. 1 to 4. Referring to FIG. 16, the wiring board 500 may include: an insulating layer IL having a first surface S1 and a second surface S2 opposite to each other; an upper wiring pattern 122 located on the first surface S1 of the insulating layer IL; a lower wiring pattern 132 located on the second surface S2 of the insulating layer IL; and an intermediate wiring pattern 134 disposed in the insulating layer IL and electrically connected to the upper wiring pattern 122 and the lower wiring pattern 132. The insulating layer IL may include an upper insulating layer 120 adjacent to the first surface S1 and a lower insulating layer 130 adjacent to the second surface S2. In an embodiment, the insulating layer IL may not include the intermediate layer 100 of FIG. 1. The wiring board 500 may be a coreless wiring board (e.g., a coreless printed circuit board) that does not include any core substrate. The upper wiring pattern 122 may be disposed on the first surface S1 of the insulating layer IL and in the upper insulating layer 120. The upper wiring pattern 122 may be embedded in the upper insulating layer 120. The intermediate wiring pattern 134 may be disposed between the upper insulating layer 120 and the lower insulating layer 130 and may be embedded in the lower insulating layer 130. The lower wiring pattern 132 may be disposed on the second surface S2 of the insulating layer IL and on the lower insulating layer 130. The wiring board 500 may further include an upper via hole 126 disposed in the upper insulating layer 120 to electrically connect the upper wiring pattern 122 to the intermediate wiring pattern 134, and a lower via hole 136 disposed in the lower insulating layer 130 to electrically connect the lower wiring pattern 132 to the intermediate wiring pattern 134. The wiring board 500 may include a capacitor wire WCAP that is electrically connected to a corresponding upper wiring pattern 122 in the upper wiring pattern 122, a corresponding lower wiring pattern 132 in the lower wiring pattern 132, and a corresponding intermediate wiring pattern 134 in the intermediate wiring pattern 134. The capacitor wire WCAP may be connected to the corresponding wiring patterns 122, 132, and 134 by a wire bonding method. The capacitor wire WCAP may be substantially the same as the capacitor wire WCAP described with reference to FIGS. 2, 3A, and 3B. As described with reference to FIG. 4, the capacitor wire WCAP may be connected to the corresponding wiring patterns 122, 132, and 134 by a ball bonding method or a wedge bonding method. For example, the capacitor wire WCAP may be disposed on the first surface S1 of the insulating layer IL and may be connected to a corresponding upper wiring pattern 122 in the upper wiring pattern 122. As another example, the capacitor wire WCAP may be disposed on the second surface S2 of the insulating layer IL and may be connected to a corresponding lower wiring pattern 132 in the lower wiring pattern 132. The wiring board 500 may further include: an upper mask layer 150A disposed on the first surface S1 of the insulating layer IL; and a lower mask layer 150B disposed on the second surface S2 of the insulating layer IL to cover the lower wiring pattern 132. The capacitor line WCAP connected to the corresponding upper wiring pattern 122 may be disposed in the upper mask layer 150A, and the capacitor line WCAP connected to the corresponding lower wiring pattern 132 may be disposed in the lower mask layer 150B. The wiring board 500 may further include a protective layer 160, and the protective layer 160 is disposed to cover the surfaces of the upper wiring pattern 122, the lower wiring pattern 132, and the intermediate wiring pattern 134. The protective layer 160 may be disposed in the upper insulating layer 120 and may be sandwiched between the upper wiring pattern 122 and the upper insulating layer 120. The protective layer 160 may be disposed on the first surface S1 of the insulating layer IL to cover the upper wiring pattern 122 and the upper insulating layer 120. The protective layer 160 may be sandwiched between the upper wiring pattern 122 and the upper mask layer 150A and may extend into the region between the upper insulating layer 120 and the upper mask layer 150A. The capacitor line WCAP may be disposed to penetrate the protective layer 160 and may be connected to the corresponding upper wiring pattern 122. The protective layer 160 may be disposed on the second surface S2 of the insulating layer IL to cover the surface of the lower wiring pattern 132. The protective layer 160 may be sandwiched between the lower wiring pattern 132 and the lower mask layer 150B and may extend into the region between the lower insulating layer 130 and the lower mask layer 150B. The capacitor line WCAP may be disposed to penetrate the protective layer 160 and may be connected to the corresponding lower wiring pattern 132. The protective layer 160 may be disposed in the lower insulating layer 130 and may be sandwiched between the intermediate wiring pattern 134 and the lower insulating layer 130. In an embodiment, the protective layer 160 may be omitted. In addition to the foregoing features, the wiring board 500 according to the present embodiment may be substantially the same as the wiring board 500 described with reference to FIGS. 1 to 4. FIG. 17 is a cross-sectional view showing a wiring board according to an embodiment of the inventive concept. For simplicity, the features different from the wiring board described with reference to FIGS. 1 to 4 will be mainly described below. Referring to FIG. 17, the capacitor line WCAP may be disposed on the first surface S1 of the insulating layer IL and may be connected to the corresponding upper wiring pattern 122 in the upper wiring pattern 122. The wiring board 500 may further include an upper mask layer 150A disposed on the first surface S1 of the insulating layer IL to cover the upper wiring pattern 122, and the capacitor line WCAP may be disposed in the upper mask layer 150A. In an embodiment, the height of the topmost surface WCAP_U of the capacitor line WCAP may be higher than or lower than the top surface 150AU of the upper mask layer 150A. Here, the height may be the distance from the first surface S1 of the insulating layer IL in the vertical direction VD. In the case where the height of the topmost surface WCAP_U of the capacitor line WCAP is lower than the top surface 150AU of the upper mask layer 150A, the capacitor line WCAP may be completely embedded in the upper mask layer 150A. In the case where the height of the topmost surface WCAP_U of the capacitor line WCAP is higher than the top surface 150AU of the upper mask layer 150A, the lower portion of the capacitor line WCAP may be embedded in the upper mask layer 150A, and the upper portion of the capacitor line WCAP may protrude from the upper mask layer 150A. The upper mask layer 150A may include an upper opening OP_A. The upper opening OP_A may vertically overlap (e.g., in the vertical direction VD) with the corresponding upper wiring pattern 122 in the upper wiring pattern 122 and may expose the protective layer 160 on the corresponding upper wiring pattern 122. In an embodiment, the capacitor line WCAP may be disposed in a corresponding upper opening OP_A of the upper opening OP_A and may be connected to the upper wiring pattern 122 that vertically overlaps with the corresponding upper opening OP_A. The capacitor line WCAP may be disposed on the second surface S2 of the insulating layer IL and may be connected to the corresponding lower wiring pattern 132 in the lower wiring pattern 132. The wiring board 500 may further include a lower mask layer 150B disposed on the second surface S2 of the insulating layer IL to cover the lower wiring pattern 132, and the capacitor line WCAP may be disposed in the lower mask layer 150B. Although not shown, the heights of the capacitor line WCAP and the lower mask layer 150B may be configured to have the same characteristics as the heights of the capacitor line WCAP and the upper mask layer 150A. FIG. 18 is a cross-sectional view showing a wiring board according to an embodiment of the inventive concept. For simplicity, the following will mainly describe the features different from the wiring board described with reference to FIGS. 1 to 4. Referring to FIG. 18, in an embodiment, the capacitor line WCAP may be connected to a side surface of a corresponding upper wiring pattern 122 in the upper wiring pattern 122, and may have a linear shape extending in a horizontal direction HD parallel to the first surface S1 of the insulating layer IL. In another embodiment, the capacitor line WCAP may be connected to a side surface of a corresponding first intermediate wiring pattern 112 in the first intermediate wiring pattern 112, and may have a linear shape extending in the horizontal direction HD. Although not shown, the capacitor line WCAP may be connected to a side surface of a corresponding second intermediate wiring pattern 114 in the second intermediate wiring pattern 114 or connected to a side surface of a corresponding lower wiring pattern 132 in the lower wiring pattern 132, and may have a linear shape extending in the horizontal direction HD. In an embodiment, the upper insulating layer 120 may include a cavity CV formed to penetrate the upper insulating layer 120, and the capacitor line WCAP having a linear shape extending in the horizontal direction HD may be disposed in the cavity CV. In another embodiment, the capacitor line WCAP may be disposed between a corresponding upper wiring pattern 122 in the upper wiring pattern 122 and a corresponding first intermediate wiring pattern 112 in the first intermediate wiring pattern 112, and may be connected to the corresponding upper wiring pattern 122 and the corresponding first intermediate wiring pattern 112. The capacitor line WCAP may have a linear shape extending in a vertical direction VD between the corresponding upper wiring pattern 122 and the corresponding first intermediate wiring pattern 112. In such a case, the capacitor line WCAP may be disposed in the upper insulating layer 120. Although not shown, the capacitor line WCAP may be connected to one of the first intermediate wiring patterns 112 and one of the second intermediate wiring patterns 114, or may be connected to one of the second intermediate wiring patterns 114 and one of the lower wiring patterns 132, and may have a linear shape extending in the vertical direction VD. FIG. 19 is a schematic diagram showing a capacitor line embedded in a wiring board according to an embodiment of the inventive concept. For simplicity, the following will mainly describe features different from the wiring board described with reference to FIGS. 1 to 4. Referring to FIG. 19, the capacitor line WCAP may be disposed on the first surface S1 of the insulating layer IL, and may be connected to a plurality of upper wiring patterns 122 in the upper wiring pattern 122 by a pin bonding method. In such a case, the capacitor line WCAP may include external electrode segments spaced apart from each other in the longitudinal or extending direction of the capacitor line WCAP, and the external electrode segments may be respectively connected to the upper wiring patterns 122 by a pin bonding method. The capacitor line WCAP connected to the upper wiring pattern 122 may have a plurality of arc-shaped portions. The insulating layer IL may have a side surface S3 between the first surface S1 and the second surface S2. Some of the wiring patterns 122, 112, 114, and 132 may be exposed via the side surface S3 of the insulating layer IL. On the side surface S3 of the insulating layer IL, the capacitor line WCAP may be connected to the corresponding exposed wiring patterns 122, 112, 114, and 132 among the exposed wiring patterns 122, 112, 114, and 132 by a wire bonding method. For example, some of the intermediate wiring patterns 112 and 114 may be exposed via the side surface S3 of the insulating layer IL, and on the side surface S3 of the insulating layer IL, the capacitor line WCAP may be connected to the exposed intermediate wiring patterns 112 and 114 by a wire bonding method. FIGS. 20 to 23 are perspective views schematically showing a part of a wiring board according to an embodiment of the concept of the present invention. For simplicity, the features different from the wiring board described with reference to FIGS. 1 to 4 will be mainly described below. Referring to FIGS. 20 to 23, the wiring board 500 may further include at least one pillar structure 140 provided on the first surface S1 of the insulating layer IL. The pillar structure 140 may be an insulating pillar formed of an insulating material or a conductive pillar formed of a conductive material. In the case where the pillar structure 140 is a conductive pillar, the pillar structure 140 may be formed of the same material (e.g., the same metal material) as the upper wiring pattern 122 or include the same material (e.g., the same metal material) as the upper wiring pattern 122, and may be electrically connected to the intermediate wiring patterns 112 and 114 and the lower wiring pattern 132 in FIG. 1. The height of the pillar structure 140 may be a height 140H. When measured in the vertical direction VD perpendicular to the first surface S1 of the insulating layer IL, the height 140H may have a value selected from the range between 30 micrometers and 150 micrometers. The diameter of the pillar structure 140 measured in the horizontal direction HD parallel to the first surface S1 of the insulating layer IL may be a diameter 140D of about 120 micrometers. In the case where the upper mask layer 150A is provided on the first surface S1 of the insulating layer IL, at least a part of the pillar structure 140 may be embedded in the upper mask layer 150A. According to an embodiment of the concept of the present invention, in this case, the height 140H of the pillar structure 140 may be about 35 micrometers, and the pitch (e.g., distance) between the pillar structures 140 may be about 140 micrometers. As described with reference to FIGS. 5 to 12, the capacitor line WCAP may have a first end portion E1 and a second end portion E2 that are opposite to each other in the longitudinal direction of the capacitor line WCAP (e.g., in the longitudinal or extending direction LD of the core electrode line 10 described with reference to FIGS. 2 to 4). The capacitor line WCAP may be provided on the first surface S1 of the insulating layer IL and may be wound around at least one pillar structure 140. In an embodiment, as shown in FIG. 20, the capacitor line WCAP can be wound around the column structure 140, and the first end portion E1 of the capacitor line WCAP can be connected to one of the upper wiring patterns 122. The second end portion E2 of the capacitor line WCAP can be connected to the other of the upper wiring patterns 122. In another embodiment, as shown in FIG. 21, the capacitor line WCAP can be arranged to wind around the plurality of column structures 140a and 140b. The first end portion E1 of the capacitor line WCAP can be connected to one of the upper wiring patterns 122, and the second end portion E2 of the capacitor line WCAP can be connected to one of the column structures 140a and 140b (e.g., 140b). In this case, one of the column structures 140a and 140b, 140b, can be a conductive column. In yet another embodiment, as shown in FIG. 22, a plurality of capacitor lines WCAP1, WCAP2, and WCAP3 can be disposed on the first surface S1 of the insulating layer IL, and each of the capacitor lines WCAP1, WCAP2, and WCAP3 can be arranged to wind around at least one column structure 140. The first end portions E1 of the capacitor lines WCAP1, WCAP2, and WCAP3 can be commonly connected to one of the upper wiring patterns 122, and the second end portions E2 of the capacitor lines WCAP1, WCAP2, and WCAP3 can be commonly connected to the other of the upper wiring patterns 122. In yet another embodiment, as shown in FIG. 23, a plurality of capacitor lines WCAP1 and WCAP2 can be disposed on the first surface S1 of the insulating layer IL, and each of the capacitor lines WCAP1 and WCAP2 can be arranged to wind around at least one column structure 140. The first capacitor line WCAP1, which is one of the capacitor lines WCAP1 and WCAP2, can wind around at least one column structure 140 in the clockwise direction, while the second capacitor line WCAP2, which is the other of the capacitor lines WCAP1 and WCAP2, can wind around at least one column structure 140 in the counterclockwise direction. The first end portion E1a of the first capacitor line WCAP1 and the first end portion E1b of the second capacitor line WCAP2 can be commonly connected to one of the upper wiring patterns 122, while the second end portion E2a of the first capacitor line WCAP1 and the second end portion E2b of the second capacitor line WCAP2 can be commonly connected to the other of the upper wiring patterns 122. According to this embodiment, since the capacitor line WCAP is disposed to wind around at least one pillar structure 140, the capacitance of the capacitor line WCAP can be increased. In addition, as described with reference to FIG. 23, in a case where the capacitor lines WCAP1 and WCAP2 wind around at least one pillar structure 140 in opposite directions, the inductance of the capacitor line WCAP1 and the inductance of WCAP2 can be canceled out, and thus, the influence of the inductance of the capacitor lines WCAP1 and WCAP2 on a circuit disposed near the capacitor lines WCAP1 and WCAP2 can be prevented or suppressed. FIG. 24 is a cross-sectional view showing an exemplary manufacturing method of a wiring board according to an embodiment of the inventive concept. For simplicity, elements in the wiring board described with reference to FIGS. 1 to 4 may be identified by the same reference numerals, and a description thereof will not be repeated. Referring to FIG. 24, an intermediate layer 100 may be provided. The intermediate layer 100 may include a core substrate. The core substrate may be formed of or include an insulating polymer material, and may further include glass fibers. As an alternative, the core substrate may be formed of or include a metal material (e.g., copper and aluminum). In an embodiment, the intermediate layer 100 may include a plurality of intermediate insulating layers stacked in a vertical direction VD, and a core substrate interposed between the intermediate insulating layers. A first intermediate wiring pattern 112 may be formed on one surface of the intermediate layer 100, and a second intermediate wiring pattern 114 may be formed on an opposite surface of the intermediate layer 100. An intermediate through hole 116 may be formed in the intermediate layer 100. The intermediate through hole 116 may be formed to penetrate the intermediate layer 100, and may electrically connect the first intermediate wiring pattern 112 to the second intermediate wiring pattern 114. In an embodiment, the formation of the first intermediate wiring pattern 112 may include forming a conductive layer on one surface of the intermediate layer 100 and patterning the conductive layer. The second intermediate wiring pattern 114 may be formed by substantially the same method as the formation method of the first intermediate wiring pattern 112. In an embodiment, the formation of the intermediate through hole 116 may include forming an intermediate through hole hole penetrating the intermediate layer 100, and performing a plating process to form the intermediate through hole 116 filling the intermediate through hole hole. A protective layer 160 may be formed on one surface of the intermediate layer 100 to cover the surface of the first intermediate wiring pattern 112. In addition, a protective layer 160 may be formed on an opposite surface of the intermediate layer 100 to cover the surface of the second intermediate wiring pattern 114. An upper insulating layer 120 may be formed on one surface of the intermediate layer 100 to cover the first intermediate wiring pattern 112 and the protective layer 160. A lower insulating layer 130 may be formed on the opposite surface of the intermediate layer 100 to cover the second intermediate wiring pattern 114 and the protective layer 160. In an embodiment, the formation of the upper insulating layer 120 and the lower insulating layer 130 may include forming corresponding insulating layers on opposite surfaces of the intermediate layer 100 and performing a thermal compression process on the insulating layers. An upper wiring pattern 122 may be formed on the upper insulating layer 120. In an embodiment, the formation of the upper wiring pattern 122 may include forming an upper conductive layer on the upper insulating layer 120 and patterning the upper conductive layer. An upper through hole 126 may be formed in the upper insulating layer 120 to electrically connect the upper wiring pattern 122 to the first intermediate wiring pattern 112. The upper through hole 126 may be formed by a method substantially the same as the method for forming the intermediate through hole 116. A protective layer 160 may be formed on the upper insulating layer 120 to cover the surface of the upper wiring pattern 122. A lower wiring pattern 132 may be formed on the lower insulating layer 130. In an embodiment, the formation of the lower wiring pattern 132 may include forming a lower conductive layer on the lower insulating layer 130 and patterning the lower conductive layer. A lower through hole 136 may be formed in the lower insulating layer 130 to electrically connect the lower wiring pattern 132 to the second intermediate wiring pattern 114. The lower through hole 136 may be formed by a method substantially the same as the method for forming the intermediate through hole 116. A protective layer 160 may be formed on the lower insulating layer 130 to cover the surface of the lower wiring pattern 132. A capacitor line WCAP may be disposed on the upper insulating layer 120, and the capacitor line WCAP may be electrically connected to a corresponding upper wiring pattern 122 in the upper wiring pattern 122. In addition, a capacitor line WCAP may be disposed on the lower insulating layer 130, and the capacitor line WCAP may be electrically connected to a corresponding lower wiring pattern 132 in the lower wiring pattern 132. The capacitor line WCAP may be disposed to penetrate the protective layer 160 and may be connected to the corresponding upper wiring pattern 122 or the corresponding lower wiring pattern 132. The capacitor line WCAP may be connected to the corresponding upper wiring pattern 122 or the corresponding lower wiring pattern 132 by a wire bonding method. In an embodiment, the formation of the protective layer 160 may be omitted. Referring back to FIGS. 1 and 13, a lower mask layer 150B may be formed on the lower insulating layer 130 to cover the lower wiring pattern 132 and the protective layer 160. The lower mask layer 150B may cover the capacitor line WCAP connected to the corresponding lower wiring pattern 132. In an embodiment, as described with reference to FIG. 1, an upper mask layer 150A may be formed on the upper insulating layer 120 to cover the upper wiring pattern 122 and the protective layer 160. The upper mask layer 150A may cover the capacitor line WCAP connected to the corresponding upper wiring pattern 122. In another embodiment, as described with reference to FIG. 13, the formation of the upper mask layer 150A may be omitted. FIG. 25 is a cross-sectional view showing an exemplary manufacturing method of a wiring board according to an embodiment of the inventive concept. For simplicity, features different from the manufacturing method described with reference to FIG. 24 will be described below. Referring to FIG. 25, a first intermediate wiring pattern 112 may be formed on one surface of the intermediate layer 100, and a second intermediate wiring pattern 114 may be formed on the opposite surface of the intermediate layer 100. An intermediate through-hole 116 may be formed in the intermediate layer 100. A protective layer 160 may be formed to cover the surface of the first intermediate wiring pattern 112 and the surface of the second intermediate wiring pattern 114. The capacitor line WCAP may be disposed on one surface of the intermediate layer 100, and the capacitor line WCAP may be electrically connected to the corresponding first intermediate wiring pattern 112 in the first intermediate wiring pattern 112. The capacitor line WCAP may be disposed to penetrate the protective layer 160 and may be connected to the corresponding first intermediate wiring pattern 112. The capacitor line WCAP may be connected to the corresponding first intermediate wiring pattern 112 by a wire bonding method. An upper insulating layer 120 may be formed on one surface of the intermediate layer 100 to cover the first intermediate wiring pattern 112, the protective layer 160, and the capacitor line WCAP. A lower insulating layer 130 may be formed on the opposite surface of the intermediate layer 100 to cover the second intermediate wiring pattern 114 and the protective layer 160. Different from that shown in the drawings, the capacitor line WCAP may be electrically connected to the corresponding second intermediate wiring pattern 114 in the second intermediate wiring pattern 114. In this case, the lower insulating layer 130 may cover the second intermediate wiring pattern 114, the protective layer 160, and the capacitor line WCAP. In an embodiment, a cavity CV penetrating the upper insulating layer 120 may be formed. The cavity CV may be formed to expose the corresponding first intermediate wiring pattern 112 in the first intermediate wiring pattern 112 and the protective layer 160 located on the corresponding first intermediate wiring pattern 112. An upper wiring pattern 122 and a lower wiring pattern 132 can be respectively formed on the upper insulating layer 120 and the lower insulating layer 130. A protective layer 160 can be formed on the upper insulating layer 120 and the lower insulating layer 130 to cover the surfaces of the upper wiring pattern 122 and the lower wiring pattern 132. In an embodiment, the formation of the protective layer 160 can be omitted. Referring back to FIG. 14, in an embodiment, a capacitor line WCAP can be disposed in the cavity CV, and the capacitor line WCAP can be connected to one of the upper wiring patterns 122 and one of the first intermediate wiring patterns 112 by a wire bonding method. A lower mask layer 150B can be formed on the lower insulating layer 130 to cover the lower wiring pattern 132 and the protective layer 160. An upper mask layer 150A can be formed on the upper insulating layer 120 to cover the upper wiring pattern 122 and the protective layer 160. FIG. 26 is a cross-sectional view showing an exemplary manufacturing method of a wiring board according to an embodiment of the inventive concept. For simplicity, features different from the manufacturing method described with reference to FIG. 24 will be described below. Referring to FIG. 26, a first upper insulating layer 120a can be formed on one surface of the intermediate layer 100 to cover the first intermediate wiring pattern 112 and the protective layer 160. A lower insulating layer 130 can be formed on the opposite surface of the intermediate layer 100 to cover the second intermediate wiring pattern 114 and the protective layer 160. In an embodiment, the formation of the first upper insulating layer 120a and the lower insulating layer 130 can include forming corresponding insulating layers on opposite surfaces of the intermediate layer 100 and performing a thermal compression process on the insulating layers. In an embodiment, a cavity CV penetrating the first upper insulating layer 120a can be formed. The cavity CV can be formed to expose the corresponding first intermediate wiring pattern 112 in the first intermediate wiring pattern 112 and the protective layer 160 located on the corresponding first intermediate wiring pattern 112. The capacitor line WCAP can be disposed in the cavity CV of the first upper insulating layer 120a and can be connected to the corresponding first intermediate wiring pattern 112 in the first intermediate wiring pattern 112 by a wire bonding method. Referring back to FIG. 15, a molding layer 170 can be formed to fill the cavity CV and cover the capacitor line WCAP. A second upper insulating layer 120b can be formed to cover the first upper insulating layer 120a and the molding layer 170. The first upper insulating layer 120a and the second upper insulating layer 120b can constitute the upper insulating layer 120. In an embodiment, an additional cavity CV penetrating the first upper insulating layer 120a and the second upper insulating layer 120b can be formed. The additional cavity CV can be formed to expose the corresponding first intermediate wiring pattern 112 in the first intermediate wiring pattern 112 and the protective layer 160 located on the corresponding first intermediate wiring pattern 112. An upper wiring pattern 122 and a lower wiring pattern 132 may be formed on the upper insulating layer 120 (e.g., the second upper insulating layer 120b) and the lower insulating layer 130, respectively. A protective layer 160 may be formed on the upper insulating layer 120 (e.g., the second upper insulating layer 120b) and the lower insulating layer 130, and the protective layer 160 may cover the surfaces of the upper wiring pattern 122 and the lower wiring pattern 132. An additional capacitive line WCAP may be disposed in an additional cavity CV, and the additional capacitive line WCAP may be connected to one of the upper wiring patterns 122 and one of the first intermediate wiring patterns 112 by a wire bonding method. A lower mask layer 150B may be formed on the lower insulating layer 130 to cover the lower wiring pattern 132 and the protective layer 160. An upper mask layer 150A may be formed on the upper insulating layer 120 (e.g., the second upper insulating layer 120b) to cover the upper wiring pattern 122 and the protective layer 160. FIGS. 27A and 27B are cross-sectional views showing an exemplary manufacturing method of a wiring board according to an embodiment of the inventive concept. Referring to FIG. 27A, an upper wiring pattern 122 may be formed on a carrier substrate 400. In an embodiment, the formation of the upper wiring pattern 122 may include forming a conductive layer on the carrier substrate 400 using a plating process and patterning the conductive layer. A protective layer 160 may be formed on the carrier substrate 400 to cover the surface of the upper wiring pattern 122. An upper insulating layer 120 may be formed on the carrier substrate 400 to cover the upper wiring pattern 122 and the protective layer 160. An upper via hole 126 may be formed in the upper insulating layer 120, and an intermediate wiring pattern 134 may be formed on the upper insulating layer 120. In an embodiment, the formation of the upper via hole 126 may include forming an upper via hole through-hole penetrating the upper insulating layer 120 and performing a plating process to form the upper via hole 126 filling the upper via hole through-hole. The intermediate wiring pattern 134 may be formed by substantially the same method as the formation method of the upper wiring pattern 122. The upper via hole 126 may electrically connect the upper wiring pattern 122 to the intermediate wiring pattern 134. A protective layer 160 may be formed on the upper insulating layer 120 to cover the surface of the intermediate wiring pattern 134. A lower insulating layer 130 may be formed on the upper insulating layer 120 to cover the intermediate wiring pattern 134 and the protective layer 160. A lower through hole 136 may be formed in the lower insulating layer 130, and a lower wiring pattern 132 may be formed on the lower insulating layer 130. The lower through hole 136 may be formed by a method substantially the same as the method for forming the upper through hole 126, and the lower wiring pattern 132 may be formed by a method substantially the same as the method for forming the upper wiring pattern 122. The lower through hole 136 may electrically connect the lower wiring pattern 132 to the intermediate wiring pattern 134. A protective layer 160 may be formed on the lower insulating layer 130 to cover the surface of the lower wiring pattern 132. In an embodiment, the formation of the protective layer 160 may be omitted. Referring to FIG. 27B, the carrier substrate 400 may be removed. In an embodiment, the removal of the carrier substrate 400 may include separating the carrier substrate 400 from the upper insulating layer 120 and the upper wiring pattern 122. Due to the removal of the carrier substrate 400, some portions of the protective layer 160 located on one surface of the upper insulating layer 120 and some portions of the upper wiring pattern 122 may be exposed. Another protective layer 160 may be formed on the exposed surface of the initial protective layer 160, and the another protective layer 160 may be formed to cover the exposed portions of the upper wiring pattern 122. The upper wiring pattern 122 may be embedded in the upper insulating layer 120. The protective layer 160 may be embedded in the upper insulating layer 120 and may be sandwiched between the upper wiring pattern 122 and the upper insulating layer 120. When the protective layer 160 is omitted, due to the removal of the carrier substrate 400, one surface of the upper insulating layer 120 and some portions of the upper wiring pattern 122 may be exposed. The capacitor wire WCAP may be connected to the corresponding upper wiring pattern 122 in the upper wiring pattern 122 and / or the corresponding lower wiring pattern 132 in the lower wiring pattern 132 by a wire bonding method. Referring back to FIG. 16, an upper mask layer 150A may be formed on the upper insulating layer 120 to cover the capacitor wire WCAP connected to the corresponding upper wiring pattern 122. A lower mask layer 150B may be formed on the lower insulating layer 130 to cover the capacitor wire WCAP connected to the corresponding lower wiring pattern 132. FIGS. 28A and 28B are cross-sectional views showing a wiring board according to an embodiment of the inventive concept. For simplicity, the following will mainly describe features different from the wiring board described with reference to FIGS. 1 to 4. Referring to FIGS. 28A and 28B, the wiring board 500 may include a capacitor chip 350 electrically connected to the corresponding intermediate wiring patterns 112 and 114 in the intermediate wiring patterns 112 and 114. The insulating layer IL may include a cavity CV formed to penetrate the insulating layer IL, and the capacitor chip 350 may be disposed in the cavity CV. In an embodiment, the upper insulating layer 120 may include a cavity CV formed to penetrate the upper insulating layer 120 and expose the corresponding first intermediate wiring pattern 112 in the first intermediate wiring pattern 112 and the protective layer 160. The capacitor chip 350 may be disposed in the cavity CV of the upper insulating layer 120 and may be electrically connected to the corresponding first intermediate wiring pattern 112. The capacitor chip 350 may include a substrate 300, a plurality of capacitor lines WCAP mounted on the top surface of the substrate 300, and a chip molding layer 340 disposed on the top surface of the substrate 300 to cover the capacitor lines WCAP. The substrate 300 may include a first substrate pad 310 adjacent to the top surface of the substrate 300 and a second substrate pad 320 adjacent to the bottom surface of the substrate 300, and the first substrate pad 310 may be electrically connected to the second substrate pad 320 via internal lines in the substrate 300. In an embodiment, the substrate 300 may be a printed circuit board. The capacitor lines WCAP may be electrically connected to the first substrate pad 310. Each of the capacitor lines WCAP may be connected to the corresponding first substrate pad 310 in the first substrate pad 310 by a wire bonding method. Each of the capacitor lines WCAP may be substantially the same as the capacitor lines WCAP described with reference to FIGS. 2 to 4. The chip molding layer 340 may seal the capacitor lines WCAP. The chip molding layer 340 may be formed of at least one of insulating materials (e.g., epoxy molding compound) or include at least one of insulating materials (e.g., epoxy molding compound). In an embodiment, as shown in FIG. 28A, the capacitor chip 350 may further include connection terminals 330 disposed on the bottom surface of the substrate 300. The connection terminals 330 may be electrically connected to the second substrate pads 320. The connection terminals 330 may be formed of or include at least one of a pillar, a bump, or a solder ball, and may be formed of or contain a conductive material. The connection terminals 330 of the capacitor chip 350 may be configured to penetrate the protective layer 160 and may be electrically connected to the corresponding first intermediate wiring pattern 112. In another embodiment, as shown in FIG. 28B, the second substrate pads 320 of the substrate 300 may be directly bonded to the corresponding first intermediate wiring pattern 112. For example, the second substrate pads 320 of the substrate 300 may be directly bonded to the corresponding first intermediate wiring pattern 112 by a copper-copper bonding process. The wiring board 500 may further include an upper mask layer 150A and a lower mask layer 150B. The upper mask layer 150A is disposed on the first surface S1 of the insulating layer IL to cover the upper wiring pattern 122, and the lower mask layer 150B is disposed on the second surface S2 of the insulating layer IL to cover the lower wiring pattern 132. The upper mask layer 150A may include an upper opening OP_A. The upper opening OP_A may be configured to expose the corresponding upper wiring pattern 122 in the upper wiring pattern 122 and the protective layer 160 located on the corresponding upper wiring pattern 122. In an embodiment, the capacitor chip 350 may not be covered by the upper mask layer 150A and may be exposed. The lower mask layer 150B may include a lower opening OP_B. The lower opening OP_B may expose the corresponding lower wiring pattern 132 in the lower wiring pattern 132 and the protective layer 160 located on the corresponding lower wiring pattern 132. In an embodiment, the protective layer 160 may be omitted. In addition to the foregoing features, the wiring board 500 according to the present embodiment may be substantially the same as the wiring board 500 described with reference to FIGS. 1 to 4. FIG. 29 is a cross-sectional view showing a wiring board according to an embodiment of the inventive concept. For simplicity, the following will mainly describe the features different from the wiring board described with reference to FIGS. 1 to 4. Referring to FIG. 29, the wiring board 500 may include a capacitor chip 350 electrically connected to the corresponding intermediate wiring patterns 112 and 114 in the intermediate wiring patterns 112 and 114. The insulating layer IL may include a cavity CV formed to penetrate the insulating layer IL, and the capacitor chip 350 may be disposed in the cavity CV. For example, the upper insulating layer 120 may include a first upper insulating layer 120a and a second upper insulating layer 120b sequentially stacked on the intermediate layer 100, and the first upper insulating layer 120a may include a cavity CV formed to penetrate the first upper insulating layer 120a. The capacitor chip 350 may be disposed in the cavity CV of the first upper insulating layer 120a and may be connected to the corresponding first intermediate wiring pattern 112 in the first intermediate wiring pattern 112. In an embodiment, the capacitor chip 350 may be configured to have substantially the same characteristics as the capacitor chip 350 described with reference to FIG. 28A. In an embodiment, different from that shown in the drawings, the capacitor chip 350 may be configured to have substantially the same characteristics as the capacitor chip 350 described with reference to FIG. 28B. The wiring board 500 may further include a molding layer 170 disposed to fill the cavity CV and cover the capacitor chip 350. The second upper insulating layer 120b may be disposed on the first upper insulating layer 120a and may extend to an area located on the capacitor chip 350 and the molding layer 170. The capacitor chip 350 may be covered by the second upper insulating layer 120b and may be embedded in the upper insulating layer 120. The wiring board 500 may further include an upper mask layer 150A and a lower mask layer 150B. The upper mask layer 150A is disposed on the first surface S1 of the insulating layer IL to cover the upper wiring pattern 122, and the lower mask layer 150B is disposed on the second surface S2 of the insulating layer IL to cover the lower wiring pattern 132. The upper mask layer 150A may include an upper opening OP_A. The upper opening OP_A may be configured to expose the corresponding upper wiring pattern 122 in the upper wiring pattern 122 and the protective layer 160 located on the corresponding upper wiring pattern 122. The lower mask layer 150B may include a lower opening OP_B. The lower opening OP_B may be configured to expose the corresponding lower wiring pattern 132 in the lower wiring pattern 132 and the protective layer 160 located on the corresponding lower wiring pattern 132. In an embodiment, the protective layer 160 may be omitted. In addition to the foregoing features, the wiring board 500 according to the present embodiment may be substantially the same as the wiring board 500 described with reference to FIGS. 1 to 4. FIGS. 30 and 31 are cross-sectional views showing a semiconductor package including a wiring board according to an embodiment of the inventive concept. Referring to FIGS. 30 and 31, the semiconductor package 1000 may include a wiring board 500, a semiconductor chip 600 mounted on the wiring board 500, and an upper molding layer 640 disposed on the wiring board 500 to cover the upper portion of the semiconductor chip 600. The wiring board 500 may be configured to have substantially the same features as the wiring board 500 described with reference to FIGS. 1 to 29. The semiconductor chip 600 may be a memory chip, a logic chip, an application processor (AP) chip, or a system-on-chip (SOC), and may have a top surface 600U and a bottom surface 600L opposite to each other. The semiconductor chip 600 may include a circuit layer 610 adjacent to the bottom surface 600L of the semiconductor chip 600, and chip pads 620 disposed on the bottom surface 600L of the semiconductor chip 600. The chip pads 620 may be electrically connected to the circuit layer 610. Upper connection bumps 630 may be respectively disposed on the chip pads 620, and may be electrically connected to the chip pads 620. The upper connection bumps 630 may be formed of or include at least one of a pillar, a bump, or a solder ball, and may be formed of or contain a conductive material. In an embodiment, as shown in FIG. 30, the wiring board 500 may include an upper wiring pattern 122 and an upper mask layer 150A covering the upper wiring pattern 122. The upper mask layer 150A may include upper openings OP_A formed to expose corresponding upper wiring patterns 122 in the upper wiring pattern 122. The upper connection bumps 630 may be disposed in the upper openings OP_A, and may be electrically connected to the corresponding upper wiring patterns 122. The semiconductor chip 600 may be electrically connected to the wiring board 500 via the upper connection bumps 630 and the corresponding upper wiring patterns 122. The wiring board 500 may include a capacitor line WCAP embedded therein. For example, the capacitor line WCAP may be embedded in the upper mask layer 150A, and may be connected to the corresponding upper wiring pattern 122 in the upper wiring pattern 122 by a wire bonding method. In another embodiment, as shown in FIG. 31, the wiring board 500 may not include the upper mask layer 150A. The upper connection bumps 630 may be electrically connected to the corresponding upper wiring patterns 122 in the upper wiring pattern 122. The semiconductor chip 600 may be electrically connected to the wiring board 500 via the upper connection bumps 630 and the corresponding upper wiring patterns 122. The wiring board 500 may include a capacitor line WCAP connected to the corresponding upper wiring pattern 122 in the upper wiring pattern 122. The capacitor line WCAP may be connected to the corresponding upper wiring pattern 122 by a wire bonding method. The capacitor line WCAP may be covered by the upper molding layer 640, and may be disposed in the upper molding layer 640. Referring back to FIGS. 30 and 31, the wiring board 500 may include a lower wiring pattern 132 and a lower mask layer 150B covering the lower wiring pattern 132. The lower mask layer 150B may include a lower opening OP_B formed to expose a corresponding lower wiring pattern 132 in the lower wiring pattern 132. The lower connection bump 650 may be disposed in the lower opening OP_B and may be electrically connected to the corresponding lower wiring pattern 132. The lower connection bump 650 may be formed of or include at least one of a pillar, a bump, or a solder ball, and may be formed of or contain a conductive material. The lower connection bump 650 may be connected to an external terminal. The wiring board 500 may include a capacitor line WCAP embedded therein. For example, the capacitor line WCAP may be embedded in the lower mask layer 150B and may be connected to a corresponding lower wiring pattern 132 in the lower wiring pattern 132 by a wire bonding method. The upper molding layer 640 may be disposed on the wiring board 500 to seal the semiconductor chip 600. The upper molding layer 640 may be formed of or contain at least one of insulating materials (e.g., an epoxy molding compound). According to an embodiment of the inventive concept, an embedded wiring board in which a capacitor line is embedded may be provided. The capacitor line may have a wire shape and may be connected to a corresponding wiring pattern provided in the wiring board by a wire bonding method. Since the capacitor line has a wire shape, the size of the capacitor line may be easily reduced. In addition, since the capacitor line is connected to the corresponding wiring pattern by a wire bonding method, the capacitor line may be easily installed in the wiring board. Therefore, the integration density of the capacitor line embedded in the wiring board may be easily increased. Therefore, not only the size and thickness of the wiring board may be easily reduced, but also the performance characteristics and reliability characteristics of the wiring board may be improved. Although exemplary embodiments of the inventive concept have been specifically shown and described, those of ordinary skill in the art will understand that various changes in form and detail may be made thereto without departing from the spirit and scope of the appended claims. 10: Core electrode line 10E, 20E, 30E: End portion 10os, 20os, 30os: Outer peripheral surface 20: Dielectric line 30: External electrode line 40: Passivation line 100: Intermediate layer 112: First intermediate wiring pattern / Wiring pattern / Intermediate wiring pattern 114: Second intermediate wiring pattern / Wiring pattern / Intermediate wiring pattern 116: Intermediate via hole 120: Upper insulating layer 120a: First upper insulating layer 120b: Second upper insulating layer 122: Upper wiring pattern / Wiring pattern 126: Upper via hole 130: Lower insulating layer 132: Lower wiring pattern / Wiring pattern 134: Intermediate wiring pattern / Wiring pattern 136: Lower via hole 140, 140a, 140b: Column structure 140D: Diameter 140H: Height 150A: Upper mask layer 150AU, 600U: Top surface 150B: Lower mask layer 160: Protective layer 170: Molded layer 200: Solder ball 210: Conductive bump 220: Reinforcing pattern 300: Substrate 310: First substrate pad 320: Second substrate pad 330: Connection terminal 340: Chip molding layer 350: Capacitor chip 400: Carrier substrate 500: Wiring board 600: Semiconductor chip 600L: Bottom surface 610: Circuit layer 620: Chip pad 630: Upper connection bump 640: Upper molding layer 650: Lower connection bump 1000: Semiconductor package A - A', B - B': Line CV: Cavity E1, E1a, E1b: First end portion E2, E2a, E2b: Second end portion HD: Horizontal direction IL: Insulating layer LD: Longitudinal direction / Extension direction OP_A: Upper opening OP_B: Lower opening S1: First surface S2: Second surface S3: Side surface V1: First voltage V2: Second voltage VD: Vertical direction WCAP, WCAP3: Capacitance line WCAP1: First capacitance line / Capacitance line WCAP2: Second capacitance line / Capacitance line WCAP_U: Topmost surface WD: Width direction FIG. 1 is a cross-sectional view showing a wiring board according to an embodiment of the concept of the present invention. FIG. 2 is a perspective view schematically showing the capacitor line of FIG. 1. FIG. 3A is a cross-sectional view taken along line A-A' of FIG. 2, and FIG. 3B is a cross-sectional view taken along line B-B' of FIG. 2. FIG. 4 is a conceptual diagram showing an exemplary method of joining the capacitor line of FIG. 2. FIGS. 5 to 12 are conceptual diagrams exemplarily showing some methods of mounting the capacitor line on the wiring board of FIG. 1. FIGS. 13 to 18 are cross-sectional views each showing a wiring board according to an embodiment of the concept of the present invention. FIG. 19 is a diagram schematically showing the capacitor line embedded in the wiring board according to an embodiment of the concept of the present invention. FIGS. 20 to 23 are perspective views schematically showing a part of the wiring board according to an embodiment of the concept of the present invention. FIG. 24 is a cross-sectional view showing an exemplary manufacturing method of the wiring board according to an embodiment of the concept of the present invention. FIGS. 25, 26, 27A and 27B are cross-sectional views showing an exemplary manufacturing method of the wiring board according to an embodiment of the concept of the present invention. FIGS. 28A, 28B and 29 are cross-sectional views each showing a wiring board according to an embodiment of the concept of the present invention. FIGS. 30 and 31 are cross-sectional views showing a semiconductor package including the wiring board according to an embodiment of the concept of the present invention. 100: Intermediate layer 112: First intermediate wiring pattern / Wiring pattern / Intermediate wiring pattern 114: Second intermediate wiring pattern / Wiring pattern / Intermediate wiring pattern 116: Intermediate via hole 120: Upper insulating layer 122: Upper wiring pattern / Wiring pattern 126: Upper via hole 130: Lower insulating layer 132: Lower wiring pattern / Wiring pattern 136: Lower via hole 150A: Upper mask layer 150B: Lower mask layer 160: Protective layer 500: Wiring board HD: Horizontal direction IL: Insulating layer OP_A: Upper opening OP_B: Lower opening S1: First surface S2: Second surface VD: Vertical direction WCAP: Capacitor line

Claims

1. A power strip, comprising: An insulating layer having a first surface and a second surface that are opposite to each other; The upper wiring pattern is located on the first surface of the insulating layer; A lower wiring pattern is located on the second surface of the insulating layer; a middle wiring pattern is disposed in the insulating layer and electrically connected to the upper wiring pattern and the lower wiring pattern; and a capacitor line is connected to the corresponding wiring pattern among the upper wiring pattern, the lower wiring pattern and the middle wiring pattern, wherein the capacitor line includes: a core electrode line having a linear shape; and an outer electrode line covering at least a portion of the core electrode line; The insulating layer includes a dielectric circuit sandwiched between the core electrode circuit and the external electrode circuit. The insulating layer comprises an upper insulating layer adjacent to the first surface, a lower insulating layer adjacent to the second surface, and an intermediate layer located between the upper and lower insulating layers. The upper wiring pattern is disposed on the upper insulating layer, and the lower wiring pattern is disposed on the lower insulating layer. The intermediate wiring pattern includes a first intermediate wiring pattern disposed between the intermediate layer and the upper insulating layer, and a second intermediate wiring pattern disposed between the intermediate layer and the lower insulating layer. The first intermediate wiring pattern is electrically connected to the second intermediate wiring pattern through a central through-hole disposed in the intermediate layer.

2. The terminal block as claimed in claim 1, wherein the external electrode circuitry comprises a material having a melting point lower than that of the core electrode circuitry.

3. The terminal block as claimed in claim 1, wherein the core electrode lines comprise a first metal and the external electrode lines comprise a second metal different from the first metal.

4. The terminal block as claimed in claim 1, wherein the capacitor line has a first end portion and a second end portion opposite to each other in the longitudinal direction of the core electrode line, and at the first end portion of the capacitor line, the core electrode line is connected to a first wiring pattern in the corresponding wiring pattern by a wire bonding method, and at the second end portion of the capacitor line, the external electrode line is connected to a second wiring pattern in the corresponding wiring pattern by the wire bonding method.

5. The terminal block as claimed in claim 1, wherein the capacitor wire has a first end portion and a second end portion opposite to each other in the longitudinal direction of the core electrode line, and at the first end portion of the capacitor wire, the core electrode line is connected to one of the corresponding wiring patterns by a ball joint method or a wedge joint method.

6. The junction box as described in claim 5, wherein, At the second end portion of the capacitor line, the external electrode line is connected to the other of the corresponding wiring pattern by a wedge engagement method.

7. The terminal block as claimed in claim 1 further includes a lower shielding layer disposed on the second surface of the insulating layer to cover the lower wiring pattern, wherein the capacitor wire is connected to a corresponding lower wiring pattern in the lower wiring pattern and disposed in the lower shielding layer.

8. The terminal block as claimed in claim 1 further includes an upper shielding layer disposed on the first surface of the insulating layer to cover the upper wiring pattern, wherein the capacitor wires are connected to corresponding upper wiring patterns in the upper wiring pattern and are disposed in the upper shielding layer.

9. The terminal block as claimed in claim 1, wherein the capacitor wire is connected to the corresponding intermediate wiring pattern in the intermediate wiring pattern and is disposed in the insulating layer.

10. The terminal block as claimed in claim 1, wherein the insulating layer includes a cavity, and the capacitor wire is disposed in the cavity.

11. The terminal block as claimed in claim 10 further includes a molding layer configured to fill the cavity and cover the capacitor wires.

12. The terminal block as claimed in claim 1, wherein the upper wiring pattern is embedded in the upper insulating layer.

13. The terminal block as claimed in claim 1, wherein the insulating layer has a side surface located between the first surface and the second surface, and the capacitor wire is connected to the corresponding wiring pattern on the side surface of the insulating layer.

14. The terminal block as claimed in claim 1 further includes a pillar structure disposed on the first surface of the insulating layer, wherein the capacitor wire has a first end portion and a second end portion opposite to each other in the longitudinal direction of the core electrode line, the capacitor wire is wound around the pillar structure, and the first end portion of the capacitor wire is connected to one of the upper wiring patterns.

15. The terminal block as claimed in claim 14, wherein the second end portion of the capacitor wire is connected to another of the upper wiring patterns.

16. The terminal block as claimed in claim 14, wherein the post structure is a conductive post, and the second end portion of the capacitor line is electrically connected to the post structure.

17. A power strip, comprising: An insulating layer having a first surface and a second surface that are opposite to each other; The upper wiring pattern is located on the first surface of the insulating layer; A lower wiring pattern is located on the second surface of the insulating layer; an intermediate wiring pattern is disposed in the insulating layer and electrically connected to the upper wiring pattern and the lower wiring pattern; and a capacitor line is connected to the corresponding wiring pattern among the upper wiring pattern, the lower wiring pattern, and the intermediate wiring pattern; and at least one of an upper masking layer and a lower masking layer, wherein the upper masking layer is disposed on the first surface of the insulating layer to cover the upper wiring pattern, and the lower masking layer is disposed on the second surface of the insulating layer to cover the lower wiring pattern, wherein the capacitor line includes: a core electrode line having a linear shape and extending in a longitudinal direction; a dielectric line disposed to surround the outer peripheral surface of the core electrode line and extending in the longitudinal direction; and an outer electrode line disposed to surround the outer peripheral surface of the dielectric line and extending in the longitudinal direction, wherein the capacitor line is disposed in at least one of the upper masking layer, the lower masking layer, and the insulating layer.

18. The terminal block of claim 17, wherein the capacitor wire has a first end portion and a second end portion opposite to each other in the longitudinal direction, and at the first end portion of the capacitor wire, the end portion of the core electrode line is connected to one of the corresponding wiring patterns by a ball joint method or a wedge joint method.

19. The junction box as claimed in claim 18, wherein, At the second end portion of the capacitor line, the end portion of the external electrode line is connected to the other of the corresponding wiring pattern by a wedge engagement method.

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