Semiconductor device and method of forming an embedded redistribution layer

Abstract

A semiconductor device includes a semiconductor die. A first dielectric layer is formed over the semiconductor die. A second dielectric layer is formed over the first dielectric layer. A trench is formed in the second dielectric layer. A via opening is formed to expose a contact pad of the semiconductor die within the trench. A seed layer is formed over the second dielectric layer. The seed layer extends into the trench and the via opening. A conductive material is deposited into the via opening and the trench. The conductive material overflows from the trench. In a first etching step, the seed layer surrounding the conductive material is etched. In a second etching step, the conductive material is etched.

Description

Semiconductor devices and methods for forming embedded redistribution layers The present invention relates generally to a semiconductor device, and more specifically to a semiconductor device and a method for forming an embedded redistribution layer. Semiconductor devices are commonly found in modern electronic products. They perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electricity, and generating visual images for television displays. Semiconductor devices are found in communications, power conversion, networking, computers, entertainment, and consumer products. They are also found in military applications, aerospace, automotive, industrial controllers, and office equipment. Semiconductor packaging is increasingly shifting towards fan-out technology. In many cases, semiconductor packages will have multiple semiconductor dies and multiple redistribution layers (RDLs). The non-flat top surface of an RDL presents a challenge for forming the next RDL in that stack. Non-flat surfaces require greater depth of field and resolution for photolithography systems, among other issues. Bimetallic damascene processes are commonly used in CMOS manufacturing to give each RDL a flat top surface. However, bimetallic damascene processes require a chemical-mechanical planarization (CMP) step to remove excess conductive material. The CMP step increases the complexity and cost of the process and is an obstacle to advanced packaging. Therefore, there is a need for an improved semiconductor device and a method for forming embedded RDLs. One aspect of the present invention is a method for manufacturing a semiconductor device, comprising: providing a semiconductor die; forming a first dielectric layer over the semiconductor die; forming a second dielectric layer over the first dielectric layer; forming a trench in the second dielectric layer; forming a via opening to expose a contact pad of the semiconductor die within the trench; forming a seed layer over the second dielectric layer, wherein the seed layer extends into the trench and the via opening; depositing a conductive material in the via opening and the trench, wherein the conductive material overflows from the trench; etching the seed layer surrounding the conductive material in a first etching step; and etching the conductive material in a second etching step. The method described in this invention further includes etching the conductive material until one surface of the conductive material is coplanar with one surface of the second dielectric layer. The method described in this invention further includes using a bottom-up filling deposition technique to deposit the conductive material until the thickness of the conductive material above the second dielectric layer is between 1 micrometer (μm) and 2 μm. In the method described in this invention, the seed layer is etched to remove a portion of the seed layer surrounding the trench. The method described in this invention further includes: depositing an encapsulation around the semiconductor die; and forming a fan-out interconnect structure over the semiconductor die and the encapsulation. The method described in this invention further includes: forming a first photoresist layer over the trench; performing the first etching step over the first photoresist layer; forming a second photoresist layer around the trench; and performing the second etching step over the second photoresist layer. Another aspect of the present invention is a method for manufacturing a semiconductor device, comprising: forming an insulating layer; forming a trench in the insulating layer; forming a seed layer in the trench; depositing a conductive material in the trench; and etching the seed layer surrounding the conductive material. The method described in another embodiment of the invention further includes using a bottom-up filling technique to deposit the conductive material until the surface of the conductive material is coplanar with the surface of the insulating layer. The method as described in another embodiment of the present invention further includes: depositing the conductive material using a bottom-up fill deposition technique until the top surface of the conductive material is above the insulating layer; and etching the conductive material in a second etching step until the surface of the conductive material is coplanar with the surface of the insulating material, the second etching step being separate from the step of etching the seed layer surrounding the conductive material. In another embodiment of the invention, the seed layer is etched to remove a portion of the seed layer surrounding the trench. Another aspect of the present invention is a semiconductor device comprising: a first insulating layer; a trench formed in the first insulating layer; a seed layer disposed in the trench; and a conductive material disposed in the trench above the seed layer, wherein the surface of the conductive material is coplanar with the surface of the first insulating layer. The semiconductor device as described in another embodiment of the invention further includes a semiconductor die, wherein the first insulating layer is formed over the semiconductor die. The semiconductor device as described in another embodiment of the invention further includes an encapsulation deposited around the semiconductor die, wherein the first insulating layer is formed over the semiconductor die and the encapsulation. The semiconductor device as described in another embodiment of the present invention further includes: a second insulating layer formed beneath the first insulating layer; and a via opening formed through the second insulating layer, wherein the seed layer and the conductive material extend into the via opening. The semiconductor device, as described in another embodiment of the invention, further includes solder bumps formed on the conductive material. The invention is described in the following description with reference to the accompanying drawings, in which similar designations denote the same or similar elements. Although the invention is described according to the best mode for achieving the objectives of the invention, it will be understood by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents supported by the following disclosure and drawings. As used herein, the term "semiconductor die" refers to both the singular and plural forms of the word, and therefore may refer to both a single semiconductor device and multiple semiconductor devices. Semiconductor devices are typically manufactured using two complex processes: front-end fabrication and back-end fabrication. Front-end fabrication involves forming a plurality of dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, establish a relationship between the voltage and current required to perform the circuit function. Back-end manufacturing refers to the process of dicing or singulating finished wafers into individual semiconductor dies and encapsulating these dies for structural support, electrical interconnection, and environmental isolation. To singulate semiconductor dies, the wafer is scribed and broken along non-functional areas known as scribe lines or kerfs. Laser dicing tools or saw blades are used to singulate the wafer. After singulation, the individual semiconductor dies are mounted onto a package substrate, which includes pins or contact pads for interconnection with other system components. Contact pads formed on top of the semiconductor dies are then connected to contact pads within the package. Electrical connections can be made with conductive layers, bumps, column bumps, conductive paste, bonding wires, or other suitable interconnect structures. Encapsulation or other molding compounds are deposited on top of the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system, enabling the functionality of the semiconductor device to be used with other system components. Figure 1a illustrates a semiconductor wafer 100 having a substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk semiconductor materials. A plurality of semiconductor dies or components 104 are formed on the wafer 100 separated by inactive inter-die regions or saw teeth 106 as described above. The saw teeth 106 provide dicing areas to monolithize the semiconductor wafer 100 into individual semiconductor dies 104. In one specific example, the semiconductor wafer 100 has a width or diameter of 100 to 450 millimeters (mm). Figure 1b shows a cross-sectional view of a portion of a semiconductor wafer 100. Each semiconductor die 104 has a back or non-active surface 108 and an active surface 110, which contain analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers. These active devices, passive devices, conductive layers, and dielectric layers are formed within or above the die and electrically interconnected according to the die's electrical design and function. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuitry, such as a digital signal processor (DSP), ASIC, MEMS memory, or other signal processing circuitry. The semiconductor die 104 may also contain integrated passive devices (IPDs) such as inductors, capacitors, and resistors for RF signal processing. The back surface 108 of the semiconductor wafer 100 can be subjected to a back grinding operation, whichever is appropriate, by mechanical grinding or etching processes to remove a portion of the substrate material 102 and reduce the thickness of the semiconductor wafer 100 and the semiconductor die 104. The conductive layer 112 is formed on the active surface 110 using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. The conductive layer 112 comprises one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. The conductive layer 112 functions as a contact pad for electrical connections to circuitry on the active surface 110. The conductive layer 112 may be formed as contact pads arranged side-by-side with respect to the edge of the semiconductor die 104 at a first distance, as shown in FIG1b. Alternatively, the conductive layer 112 may be formed as contact pads offset in a plurality of columns such that a first column of contact pads is arranged at a first distance from the edge of the die, and a second column of contact pads alternates with the first column arranged at a second distance from the edge of the die. The conductive layer 112 represents only one conductive layer formed above the semiconductor die 104 having contact pads for subsequent electrical interconnection to a larger system. However, one or more intermediate conductive and insulating layers may be present between the actual semiconductor device formed on the active surface 110 and the contact pads 112 for signal routing. As part of the wafer fabrication process, a dielectric layer 116 is formed over the semiconductor wafer 100 to protect the active surface 110. Openings are typically formed through the dielectric layer 116 for electrical connections. The dielectric layer 116 is formed of polyimide (PI), polybenzoxazole (PBO), or another suitable dielectric, passivating, or insulating material. Dielectric layer 118 is formed over dielectric layer 116. Dielectric layer 118 is a repassivation layer, formed by an outsourced semiconductor assembly and test (OSAT) company for additional protection. Dielectric layer 118 may be formed from the materials mentioned above for dielectric layer 116 or any other suitable insulating material. Dielectric layers 116 and 118 may be formed from the same or different materials. In some specific instances, a single, thicker dielectric layer is used instead of two separate dielectric layers. In Figure 1c, openings are formed in an RDL pattern in dielectric layers 116 and 118 using laser 124 to ablate the desired pattern into the dielectric layers. Trench 122 is formed in the second dielectric layer 118 with the desired redistribution pattern (e.g., fan-in or fan-out pattern). Trench 122 will become a conductive trace after being filled with a conductive material. Trench 122 extends directly above contact pad 112, with via opening 120 formed downwards to the contact pad. The via opening 120 is formed through an opening in dielectric layer 116 or, if necessary, through the first dielectric layer to expose contact pad 112 to trench 122. In one specific example, the trench 122 is formed using a first laser ablation step, and then the via opening 120 is formed using a second laser ablation step. Compared to the rest of the RDL pattern, the opening 120 can be easily formed by focusing the laser 124 over the contact pad 112 for a longer period of time. In Figure 1d, a seed layer 130 is formed over the semiconductor wafer 100. The seed layer 130 is formed using any suitable metal deposition technique, such as chemical vapor deposition, physical vapor deposition, other sputtering methods, spraying, or plating. The sputtering material is typically titanium, titanium-tungsten, or titanium-copper, but may also be copper, steel, aluminum, gold, combinations thereof, or any other suitable conductive material. The seed layer 130 is a conformal layer, meaning that material of substantially uniform thickness is deposited on each exposed surface, including both horizontal and vertical surfaces. The seed layer 130 extends downward along the side surface of the second dielectric layer 118 into the trench 122 and downward along the side surface of the first dielectric layer 116 into the via opening 120. The seed layer 130 is substantially and electrically connected to the contact pads 112 in the via opening 120. The seed layer 130 extends across the top surface of the second dielectric layer 118 to completely cover the semiconductor wafer 100 and interconnect all contact pads 112. In Figure 1e, a photoresist layer 134 is formed above the seed layer 130. The photoresist layer 134 completely covers the wafer 100. The photoresist layer 134 is exposed to light by a photomask, so that light irradiates the photoresist layer in a pattern similar to that of the trench 122. In Figure 1f, a developer is used to wash away the light-exposed portions of the photoresist layer 134 to form trenches 136. Negative photoresist is used in other specific examples. The trenches 136 formed through the photoresist layer 134 fully expose the underlying vias 120 and the seed layer 130 within the trenches 122. The trenches 136 in the photoresist layer 134 are wider than the trenches 122 in the second dielectric layer 120, leaving exposed end edges 138 around each trench 122. In Figure 1g, conductive materials 140 to 144 are deposited into trench 136 using a bottom-up fill deposition method. The conductive material fills the conductive vias 140 within the via opening 120, the conductive traces 142 within the trench 122, and the flange 144 on the end edge 138. The conductive material is typically copper, but gold, aluminum, titanium, tin, iron, nickel, combinations thereof, and other suitable conductive materials may be used in other specific examples. The trench 122 of the second dielectric layer 118 is overfilled to form a sacrificial flange 144 on the end edge 138. The flange 144 binds to excess conductive material directly above the trench 122 and the via opening 120 to form a capping layer. Conductive material 140 to 144 fills the trench 136 until the conductive material protrudes from the top surface of the second dielectric layer 118. In one specific example, the conductive material deposited into the trench 136 up to the flange 144 is approximately 1 to 2 μm thick. In Figure 1h, the remaining portion of photoresist layer 134 is removed to allow conductive materials 140 to 144 in the pattern of conductive traces 142 to overflow, forming flange 144. A second photoresist layer 150 is formed that completely covers wafer 100 in Figure 1i. In Figure 1j, photoresist 150 is exposed to light and developed to remove portions of the second photoresist outside the conductive traces 142. The flange 144 and portions of the seed layer 130 not covered by conductive materials 140 to 144 are exposed through openings 152 in the photoresist 150. The remaining portion of photoresist 150 has an area similar to or the same as that of the respective underlying conductive traces 142. In Figure 1k, a seed etching step 160 is performed, indicated by the arrows drawn in the figure. Seed etching 160 is performed by a chemical or other mechanism that is selective to the material of the seed layer 130. Seed etching 160 can be a wet or dry method. The seed layer 130 is removed between the regions of conductive materials 140 and 144, while the photoresist layer 150 protects the conductive trace 142 from the etching process. The flange 144 may be slightly etched by seed etching 160, but is not completely removed due to the selective nature of the etching. The portion of the seed layer 130 below the flange 144 is not removed because it is protected from etching by the flange. In Figure 11, the remaining portion of the photoresist layer 150 is removed. The conductive materials 140 to 144, along with the portion of the seed layer 130 below the conductive material, are retained, while the seed layer has been removed between the discrete portions of the conductive material. The conductive materials 140 to 144 remain folded down against the second dielectric layer 118. In Figure 1m, a second etching step 166 is performed, indicated by the arrows in the figure. Etching 166 uses different chemicals or processes that can effectively remove both the conductive materials 140 to 144 and the seed layer 130. Etching 166 removes the top portions of the conductive materials 140 to 144 over time and continues until the flange 144 is removed, and the top surface of the conductive trace 142 is coplanar or substantially coplanar with the top surface of the second dielectric layer 118. The second dielectric layer 118 can be used as an etch stop layer by revealing when the flange 144 is completely removed, since more of the second dielectric layer is visible when etching is complete. The portion of the seed layer 130 below the flange 144 is also removed, but the seed layer remains below the conductive trace 142 and the conductive via 140. The conductive trace 142 retains the desired redistribution pattern, wherein its top surface is substantially coplanar with the top surface of the second dielectric layer 118. In some specific embodiments, the conductive trace 142 is shaped to include contact pads, to which subsequently formed RDL layers or other interconnect structures will be connected. In Figure 1n, semiconductor wafer 100 is monolithically divided into individual semiconductor dies 104 using a saw blade or laser dicing tool 168 via sawing kerf 106. Individual semiconductor dies 104 can be detected and electrically tested for identification after KGD monolithization. In other specific embodiments, additional conductive layers are formed prior to monolithization to allow for more complex wiring. Each layer of a plurality of RDL stacks on semiconductor die 104 can be formed as described above. Semiconductor die 104 can be stored in a tape or other storage area for later packaging or directly incorporated into a fan-out semiconductor package. Forming conductive traces 142 with a top surface coplanar with the surrounding dielectric layer 118 simplifies the processing requirements for packaging semiconductor die 104. Forming a coplanar surface without chemical mechanical planarization (CMP) means that the manufacturing process of semiconductor die 104 is cheaper and simpler. Figures 2a to 2d illustrate the use of double-exposure photolithography as an alternative to the laser ablation shown in Figure 1c to form the trench 122 and via opening 120. In Figure 2a, a first photomask 200 is positioned above the wafer 100. The photomask 200 includes openings 202 formed to the desired pattern for the trench 122, excluding the overlap between the trench and via opening 120. A second dielectric layer is photosensitive when the dielectric layer 118 is first deposited above the wafer 100. Radiation 204 exposes the wafer 100 via the photomask 200 and irradiates the dielectric layer 118 with the pattern of the openings 202. The radiation 204 is relatively weak, such that the material in the region 208 below the openings 202 is only partially crosslinked. The region 208 of the dielectric layer 118 is only partially hardened by the radiation 204 and remains slightly flexible. In Figure 2b, a second photomask 210 is positioned above wafer 100. The photomask 210 covers the desired pattern for trenches 122, including via openings 120, which are formed over other areas of wafer 100. Radiation 214 is exposed to dielectric layer 118 through openings 212. Radiation 214 is relatively stronger than radiation 204, causing region 218 of dielectric layer 118 to harden to a greater strength than region 208. Region 220 above contact pads 112 remains unexposed to both radiation 204 and 214. In Figure 2c, developer is used to wash away the portions of dielectric layer 118 that are not exposed to light. The area 220 above contact pad 112 is completely removed, while the area 208 exposed to weak light 204 is only partially removed. After development, dielectric layer 118 is cured as shown in Figure 2d. Figure 3 illustrates a halftone photomask 230 used to expose all desired areas of the dielectric layer 118 to light in a single step. The photomask 230 has different discrete regions with varying transmittance. Region 232 of the photomask 230 above the contact pad 112 is completely opaque, region 234 above the desired location of the trench 122 is partially transmissive, and region 236 around the trench is completely transmissive. In one specific example, region 232 has approximately 0% transmittance, region 234 has approximately 50% transmittance, and region 236 has approximately 100% transmittance. Radiation 240 is exposed onto wafer 100 via photomask 230. Radiation 240 passes through region 236 with a greater intensity than radiation passing through region 234. Region 232 completely blocks the transmission of radiation 240. Therefore, region 218 of dielectric layer 118 is exposed to the stronger portion of light radiation 240 than region 208, and region 220 is not significantly exposed to radiation. As shown in Figures 2c and 2d above, dielectric layer 118 is developed and cured to complete the formation of trenches 122 and via openings 120 in dielectric layer 118. Figures 4a to 4d illustrate alternative processes to the processes shown in Figures 1f to 1m, where the trench 122 and via opening 120 are filled with conductive material. In Figure 4a, opening 236 is formed in photoresist layer 134. Opening 236 is similar to opening 136 described above, but slightly smaller. Opening 236 has the same or nearly the same area occupied as trench 122, while opening 136 is slightly larger. In Figure 4b, conductive material is deposited into opening 236 to form conductive vias 240 in via opening 120 and RDL pattern 242 in trench 122. The conductive material is filled from bottom to top to control the fill surface and form an RDL with a top surface coplanar with the top surface of dielectric layer 118. The conductive material may be deposited to slightly protrude from dielectric layer 118 and then removed as described above, but because opening 236 is smaller than opening 136, flange 144 is not formed as described above. Figure 4c shows the photoresist layer 134 removed as in Figure 1h. In Figure 4d, a seed layer etching step 160 is performed as described above to remove the seed layer 130 between portions of the RDL pattern 240. The semiconductor dies 104 are then monolithized from each other, as shown in Figure 1n. Figure 5 illustrates an exemplary fan-out package 300, which has semiconductor dies 104 formed after the formation of RDL patterns 142 or 242. The semiconductor dies 104 are embedded in a molding compound or encapsulation 304. The encapsulation 304 is deposited above the semiconductor dies 104, while a plurality of semiconductor dies are disposed on a carrier, wherein the active surface 110 is oriented toward the carrier. This downward orientation causes the semiconductor die 104 having the encapsulation 304 to have a surface coplanar with the top surface of the second dielectric layer 118, as the second dielectric layer contacts the carrier during molding. The encapsulation 304 extends above a back surface 108 opposite the carrier, but may be exposed via back-side grinding or film-assisted molding, depending on the situation. Encapsulation 304 can be a polymer composite material, such as epoxy resin, epoxy acrylate, or polymer with or without fillers. Encapsulation 304 is non-conductive and environmentally friendly, protecting the semiconductor device from external components and contaminants. Encapsulation 304 also protects the semiconductor die 104 from degradation due to light exposure. A build-up interconnect structure 310 is formed over the active surface 110 of the semiconductor die 104 and over the encapsulation 304. Due to the presence of the encapsulation 304, the build-up interconnect structure 310 is formed over a surface area larger than that of the semiconductor die 104. The encapsulation 304 provides additional surface area for the build-up interconnect structure 304 to fan out. In some specific examples, as part of forming the fan-out build-up interconnect structure 310, a first dielectric layer 116 is formed over the semiconductor die 104 at the end of the fabrication of the semiconductor wafer 100, and a second dielectric layer 118 is formed by OSAT over both the semiconductor die 104 and the encapsulation 304. Conductive traces 142 extend over the encapsulation 304 as appropriate. The cumulative interconnect structure 310 includes a first dielectric layer 312, a second dielectric layer 314, and a solder mask layer 316. A first conductive layer 320 is formed between dielectric layers 312 and 314. The conductive layer 320 includes a conductive via penetrating the insulating layer 312 to contact the conductive trace 142. A second conductive layer 322 is formed above or in the dielectric layer 314. The conductive layer 322 includes a conductive via penetrating the insulating layer 314 to contact the conductive layer 320. As described above, the conductive layers 320 and 322 can be formed to be embedded in the insulating layers 312 and 314, respectively, without the need for chemical mechanical planarization. Each RDL layer, composed of conductive and insulating layer pairs, has a flat top surface, which simplifies the requirements for subsequent layer formation. Any number of insulating and conductive layer pairs can be interleaved over the semiconductor die 104 and encapsulation 304 as needed to implement desired signal routing. In other specific embodiments, cumulative interconnect structures are formed over the semiconductor die 104 and encapsulation 304 using any suitable process. Conductive bump material is deposited on top of conductive layer 322 within openings in solder mask layer 316 using evaporation, electrolytic plating, electroless plating, drop ball, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, or combinations thereof, with a flux solution selected as appropriate. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer 322 using a suitable attachment or bonding process. The bump material can be reflowed by heating the material above its melting point to form conductive balls or bumps 324. In one specific example, conductive bumps 324 are formed on top of under-bump metallization (UBM) having a wetting layer, a barrier layer, and an adhesive layer. Conductive bumps 324 can also be compression bonded or thermocompressed to conductive layer 322. Conductive bump 324 represents a type of interconnect structure that can be formed above conductive layer 322 for electrical connection to a substrate. Interconnect structures may also use bonding wires, conductive paste, pillar bumps, microbumps, conductive pillars, or other electrical interconnects. A plurality of semiconductor packages 300 are typically formed in a panel or reconstructed wafer and then monolithically encapsulated by encapsulation 304 after completion. Figures 6a and 6b illustrate the integration of, for example, semiconductor package 300, as described above, into a larger electronic device 340. Figure 6a shows a partial cross-section of the semiconductor package 300, as part of the electronic device 340, mounted on a printed circuit board (PCB) or other substrate 342. Bumps 324 are reflowed to the conductive layer 344 of the PCB 342 to physically attach and electrically connect the semiconductor package 300 to the PCB. In other embodiments, thermoforming or other suitable attachment and connection methods are used. In some embodiments, an adhesive or underfill layer is used between the semiconductor package 300 and the PCB 342. The semiconductor die 104 is electrically coupled to the conductive layer 344 via accumulated interconnect structures 310, conductive traces 142, and conductive vias 140. Figure 6b illustrates an electronic device 340 including a PCB 342, wherein a plurality of semiconductor packages (including semiconductor package 300) are mounted on the surface of the PCB. Depending on the application, the electronic device 340 may have one type or multiple types of semiconductor packages. The electronic device 340 may be a standalone system using semiconductor packages to perform one or more electrical functions. Alternatively, the electronic device 340 may be a sub-component of a larger system. For example, the electronic device 340 may be part of a tablet computer, a cell phone, a digital camera, a communication system, or other electronic device. The electronic device 340 may also be a graphics card, a network interface card, or another signal processing card inserted into a computer. Semiconductor packages may include microprocessors, memory, ASICs, logic circuits, analog circuits, RF circuits, discrete active or passive devices, or other semiconductor chips or electrical components. PCB 342 provides a general-purpose substrate for structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 344 are formed on or within the surface of PCB 342 using evaporation, electroplating, electroless plating, screen printing, or other suitable metal deposition processes. Signal traces 344 provide electrical communication between semiconductor packages, mounted components, and other external systems or components. If necessary, traces 344 also provide power connections to the semiconductor packages and ground connections. In some specific examples, the semiconductor device has two packaging levels. The first-level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. The second-level packaging involves mechanically and electrically attaching the intermediate substrate to the PCB 342. In other specific examples, the semiconductor device may only have a first-level package, in which the die is directly mounted to the PCB 342 mechanically and electrically. For illustrative purposes, several types of first-level packages, including wire bond package 346 and flip chip 348, are shown on PCB 342. Additionally, several types of second-level packages, including ball grid array (BGA) 350, bump chip carrier (BCC) 352, land grid array (LGA) 356, multi-chip module (MCM) 358, quad flat non-leaded (QFN) package 360, quad flat package 362, and embedded wafer level ball grid array (eWLB) 366, are shown mounted on PCB 342 together with semiconductor package 300. Conductive traces 344 electrically couple the various packages and components mounted on PCB 342 to semiconductor package 300, thereby enabling semiconductor die 104 to be used for other components on the PCB. Depending on system requirements, any combination of semiconductor packages configured with first and second-level package designs and other electronic components can be connected to PCB 342. In some specific instances, electronic device 340 includes a single attached semiconductor package, while other specific instances require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate pre-fabricated components into electronic devices and systems. Because semiconductor packages include complex functions, electronic devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting devices are less prone to failure and less expensive to manufacture, thereby reducing consumer costs. Although one or more specific embodiments of the invention have been described in detail, those skilled in the art will understand that modifications and adaptations can be made to these specific embodiments without departing from the scope of the invention as set forth in the following claims. 100: Semiconductor wafer; 102: Substrate material; 104: Semiconductor die or component; 106: Non-active die-to-die area or kerf; 108: Back or non-active surface; 110: Active surface; 112: Conductive layer; 116: Dielectric layer; 118: Dielectric layer; 120: Via opening; 122: Trench; 124: Laser; 130: Seed layer; 134: Photoresist layer; 136: Trench; 138: Edge; 140: Conductive via; 142: Conductive trace; 144: Flange; 150: Second photoresist layer; 152: Opening; 160: Seed etching; 166: Second etching; 168: Saw blade or laser cutting tool. 00: First photomask 202: Opening 204: Radiation 208: Area 210: Second photomask 212: Opening 214: Radiation 218: Area 220: Area 230: Halftone photomask 232: Area 234: Area 236: Area 240: Radiation 242: RDL pattern 300: Indicative fan-out package 304: Molded compound or encapsulation 310: Accumulated interconnect structure 312: First dielectric layer 314: Second dielectric layer 316: Solder photomask layer 320: First conductive layer 322: Second conductive layer 324: Conductive ball or bump 340: Larger electronic device 342: PCB 344: Conductive layer; 346: Wire bond package; 348: Flip chip; 350: Ball grid array; 352: Bump die carrier; 356: Planar grid array; 358: Multi-chip module; 360: Quad Flat No-Leader Package; 362: Quad Flat Package; 366: Embedded Wafer-Level Ball Grid Array [Fig. 1a] to [Fig. 1n] illustrate a semiconductor wafer having a plurality of semiconductor dies and an RDL formed on top of the semiconductor dies; [Fig. 2a] to [Fig. 2d] illustrate a double exposure method for patterning an RDL; [Fig. 3] illustrates a halftone mask for patterning an RDL; [Fig. 4a] to [Fig. 4d] illustrate alternative process flows for depositing conductive materials to form an RDL; [Fig. 5] illustrates a fan-out semiconductor package having semiconductor dies; and [Fig. 6a] and [Fig. 6b] illustrate the integration of the semiconductor package into an electronic device. 100: Semiconductor wafers 102: Substrate Material 104: Semiconductor chips or components 106: Non-active inter-grain wafer region or saw cut. 108: Back or non-active surface 110: Active Surface 112: Conductive layer 116: Dielectric layer 118: Dielectric layer 120: Through-hole opening 130: Seed layer 140: Conductive via 142: Conductive traces 144: Flange 150: Second photoresist layer 160: Seed Etching

Claims

1. A method of manufacturing a semiconductor device, comprising: providing a semiconductor die; forming a first dielectric layer over the semiconductor die; forming a second dielectric layer over the first dielectric layer; forming a trench in the second dielectric layer; forming a via opening to expose a contact pad of the semiconductor die within the trench; forming a seed layer over the second dielectric layer, wherein the seed layer extends into the trench and the via opening; depositing a conductive material in the via opening and the trench, wherein the conductive material overflows from the trench and a portion of the seed layer remains exposed outside the conductive material; forming a photoresist layer over the conductive material in the trench, wherein a portion of the conductive material located outside the occupied area of ​​the trench remains exposed outside the photoresist layer; using the photoresist layer as a photomask in a first etching step to etch the seed layer surrounding the conductive material, comprising the portion of the seed layer, wherein the portion of the conductive material is retained after etching the seed layer; The photoresist layer is removed after the first etching step; and the conductive material is etched in the second etching step after the photoresist layer is removed, wherein the portion of the conductive material is removed.

2. The method of claim 1, further comprising etching the conductive material until the surface of the conductive material is coplanar with the surface of the second dielectric layer.

3. The method of claim 1, further comprising depositing the conductive material using a bottom-up fill deposition technique until the thickness of the conductive material above the second dielectric layer is between 1 micrometer (μm) and 2 μm.

4. The method of claim 1, wherein etching the seed layer removes a portion of the seed layer around the trench.

5. The method of claim 1, further comprising: Encapsulation is deposited around the semiconductor grain; A fan-out interconnect structure is formed above the semiconductor die and the encapsulation.

6. A method of manufacturing a semiconductor device, comprising: forming an insulating layer; forming a trench in the insulating layer; forming a seed layer in the trench; depositing a conductive material in the trench, wherein the conductive material overflows from the trench and a portion of the seed layer remains exposed outside the conductive material; forming a photoresist layer in the trench above the conductive material, wherein a portion of the conductive material located outside the occupied area of ​​the trench remains exposed outside the photoresist layer; using the photoresist layer as a photomask to etch the seed layer surrounding the conductive material, including the portion of the seed layer, wherein the portion of the conductive material is retained after etching the seed layer; removing the photoresist layer after etching the seed layer; and etching the conductive material after removing the photoresist layer, wherein the portion of the conductive material is removed.

7. The method of claim 6, further comprising using a bottom-up filling technique to deposit the conductive material until the surface of the conductive material is coplanar with the surface of the insulating layer.

8. The method of claim 6, further comprising: In the second etching step, the conductive material is etched until the surface of the conductive material is coplanar with the surface of the insulating layer. This second etching step is separated from the step of etching the seed layer around the conductive material.

9. The method of claim 6, further comprising forming a fan-out interconnect structure over the conductive material and the insulating layer.

10. The method of claim 7, wherein the conductive material comprises copper and the seed layer comprises titanium.

11. The method of claim 7, further comprising: Provide semiconductor chips; Deposit an encapsulation around the semiconductor grain; A dielectric layer is formed over the semiconductor die and the encapsulation.

12. The method of claim 7, wherein the step of etching the conductive material is performed by chemical etching, and a coplanar top surface is formed of the conductive material and the insulating layer.

13. A method for manufacturing a semiconductor device, comprising: Forming a dielectric layer; Trenches are formed in the dielectric layer; A seed layer is formed in the trench; A conductive material is deposited in the trench; A photoresist layer is formed in the trench above the conductive material, wherein a portion of the conductive material remains exposed outside the photoresist layer; In the first etching step, the photoresist layer and the portion of the conductive material are used as a photomask to etch the seed layer around the conductive material; after the first etching step, the photoresist layer is removed; and after the photoresist layer is removed, the conductive material is etched in the second etching step.

14. The method of claim 13, further comprising continuing the second etching step until the surface of the conductive material is coplanar with the surface of the dielectric layer.

15. The method of claim 13, further comprising depositing the conductive material using a bottom-up fill deposition technique until the surface of the conductive material is coplanar with the surface of the dielectric layer.

16. The method of claim 13, wherein the first etching step removes the portion of the seed layer surrounding the trench.

17. The method of claim 13, further comprising forming a fan-out interconnect structure over the conductive material and the dielectric layer.

18. The method of claim 13, wherein the conductive material comprises copper and the seed layer comprises titanium.

19. The method of claim 13, further comprising: Provide semiconductor chips; Encapsulation is deposited around the semiconductor grain; The dielectric layer is formed over the semiconductor die and the encapsulation.

20. A method of manufacturing a semiconductor device, comprising: forming an insulating layer; forming a trench in the insulating layer; forming a seed layer in the trench; depositing a conductive material in the trench above the seed layer; forming a photoresist layer above the trench, wherein a portion of the conductive material remains exposed outside the photoresist layer; using the photoresist layer and the portion of the conductive material as a photomask to etch the seed layer surrounding the trench; and etching the conductive material in a second etching step after etching the seed layer.

21. The method of claim 20, wherein etching the seed layer removes a portion of the seed layer around the trench.

22. The method of claim 20, further comprising forming a fan-out interconnect structure over the insulating layer.

23. The method of claim 20, further comprising: Provide semiconductor chips; Encapsulation is deposited around the semiconductor grain; A fan-out interconnect structure is formed above the semiconductor die and the encapsulation.

24. The method of claim 20, further comprising forming a through hole in the trench.

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