Waveguide device and manufacturing method of the same

Abstract

This disclosure provides a waveguide device including a glass substrate, a first metal layer, a second metal layer, and a third metal layer. The glass substrate includes a first surface, a second surface corresponding to the first surface, and at least two first through-holes, wherein the first through-holes include the third surface, and the third surface is connected to the first surface and the second surface. A first conductive layer is disposed on the first surface. A second conductive layer is disposed on the second surface. A third conductive layer is disposed on the third surface and electrically connects the first conductive layer and the second conductive layer. In a top view, the first through-holes have a major axis and a minor axis. This disclosure also provides a method for manufacturing the waveguide device.

Description

Technical Field

[0001] The present disclosure relates to an electronic device and a method for manufacturing the electronic device, and in particular to an electronic device including a waveguide structure and a method for manufacturing the same. Prior Art

[0002] A substrate-integrated waveguide (SIW) is a waveguide structure commonly used to transmit high-frequency signals. It comprises a dielectric layer, metal layers disposed on opposite surfaces of the dielectric layer, and multiple through-holes extending through the dielectric layer. The intensity of high-frequency signals is attenuated by dielectric loss in the dielectric layer, metal loss in the metal layer, and / or signal leakage between adjacent through-holes. To minimize the attenuation of high-frequency signals caused by the dielectric layer, a dielectric layer with a relatively low dissipation factor is typically selected to form the SIW. However, existing SIWs are mostly formed using printed circuit boards (PCBs). The material selection for the dielectric layer in the PCB is limited by these factors, increasing the cost of SIW production. Summary of the Invention

[0003] The present disclosure provides an electronic device and a method for manufacturing the electronic device, wherein the cost of the electronic device can be reduced and the electronic device can have relatively low signal strength attenuation when used to transmit high-frequency signals.

[0004] According to some embodiments of the present disclosure, an electronic device is provided, comprising a glass substrate, a first metal layer, a second metal layer, and a third metal layer. The glass substrate comprises a first surface, a second surface corresponding to the first surface, and at least two first through-holes, wherein the first through-hole comprises a third surface, and the third surface is connected to the first surface and the second surface. A first conductive layer is disposed on the first surface. A second conductive layer is disposed on the second surface. A third conductive layer is disposed on the third surface and electrically connects the first conductive layer and the second conductive layer. In a top view, the first through-hole has a major axis and a minor axis.

[0005] According to some embodiments of the present disclosure, a method for manufacturing an electronic device includes the following steps: providing a glass substrate, wherein the glass substrate includes a first surface and a second surface corresponding to the first surface; patterning the glass substrate to form at least two first through-holes, wherein the first through-holes form a third surface in the glass substrate, and the third surface connects the first surface and the second surface; forming a first conductive layer on the first surface; forming a second conductive layer on the second surface; and forming a third conductive layer on the third surface, such that the third conductive layer is electrically connected to the first conductive layer and the second conductive layer. The first through-holes have a major axis and a minor axis when viewed from above.

[0006] To make the above features and advantages of the present disclosure more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. Simple diagram description

[0007] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. FIG. 1A is a flow chart of a method for manufacturing an electronic device according to an embodiment of the present disclosure. FIG. 1B is an exploded view of the electronic device according to the first embodiment of the present disclosure. FIG. 1C is a schematic top view of the electronic device according to the first embodiment of the present disclosure. FIG. 2 is a schematic three-dimensional diagram of an electronic device according to a second embodiment of the present disclosure. FIG. 3 is a schematic three-dimensional diagram of an electronic device according to a third embodiment of the present disclosure. FIG. 4A is a graph showing the relationship between S parameters and frequency of the electronic device according to the second embodiment and the electronic device according to the third embodiment of the present disclosure. FIG. 4B is an enlarged schematic diagram of the curve S21 - 10b and the curve S21 - 10c in FIG. 4A . FIG. 5A is a graph showing the relationship between S parameters and frequency of the electronic device in the TE10 mode and the TE20 mode according to the second embodiment of the present disclosure. FIG. 5B is a graph showing the relationship between S parameters and frequency of the electronic device in the TE10 mode and the TE20 mode according to the third embodiment of the present disclosure. FIG. 6 is a schematic three-dimensional diagram of an electronic device according to a fourth embodiment of the present disclosure. FIG. 7A is a graph showing the relationship between S parameters and frequency of the electronic device according to the third embodiment and the electronic device according to the fourth embodiment of the present disclosure. FIG. 7B is an enlarged schematic diagram of the curve S21 - 10 c and the curve S21 - 10 d in FIG. 7A . FIG. 8A is an exploded view of an electronic device according to a fifth embodiment of the present disclosure. FIG. 8B is a schematic top view of an electronic device according to a fifth embodiment of the present disclosure. FIG. 9 is a schematic three-dimensional diagram of an electronic device according to a sixth embodiment of the present disclosure. FIG. 10A is a graph showing the relationship between the S parameters and the frequency of the electronic device according to the second embodiment and the electronic device according to the sixth embodiment of the present disclosure. FIG10B is an enlarged schematic diagram of the curve S21 - 10b and the curve S21 - 10f in FIG10A . FIG. 11 is a schematic three-dimensional diagram of an electronic device according to a seventh embodiment of the present disclosure. FIG. 12 is a graph showing the relationship between S parameters and frequency of the electronic device according to the sixth embodiment and the electronic device according to the seventh embodiment of the present disclosure. FIG. 13A is a flow chart of a method for manufacturing an electronic device according to another embodiment of the present disclosure. FIG. 13B is a schematic three-dimensional diagram of an electronic device according to an eighth embodiment of the present disclosure. FIG. 14A is a flow chart of a method for manufacturing an electronic device according to another embodiment of the present disclosure. FIG. 14B is a schematic three-dimensional diagram of an electronic device according to a ninth embodiment of the present disclosure. Implementation Method

[0008] The present disclosure will be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, for ease of understanding and simplicity, many of the drawings in this disclosure depict only a portion of an electronic device, and certain components in the drawings are not drawn to scale. Furthermore, the number and size of components in the drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0009] Throughout this disclosure and the appended claims, certain terms are used to refer to specific components. Those skilled in the art will appreciate that electronic device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but different names. In the following description and claims, words such as "include," "contain," and "have" are open-ended and should be interpreted as meaning "including, but not limited to..." Therefore, when the terms "include," "contain," and / or "have" are used in the description of this disclosure, they specify the presence of corresponding features, regions, steps, operations, and / or components, but do not preclude the presence of one or more corresponding features, regions, steps, operations, and / or components.

[0010] Directional terms used herein, such as "up," "down," "front," "back," "left," and "right," refer only to the directions in the accompanying drawings. Therefore, the directional terms used are for illustrative purposes only and are not intended to limit the present disclosure. In the accompanying drawings, each diagram depicts the general characteristics of methods, structures, and / or materials used in specific embodiments. However, these diagrams should not be construed as defining or limiting the scope or nature of the embodiments. For example, the relative sizes, thicknesses, and positions of various layers, regions, and / or structures may be exaggerated or reduced for clarity.

[0011] When a component (such as a layer or region) is referred to as being "on" another component, it can be directly on the other component or with other components interposed between the two. On the other hand, when a component is referred to as being "directly on" another component, no components are interposed between the two components. Furthermore, when a component is referred to as being "on" another component, the two components have a top-to-bottom relationship in a top-down view, and the component can be above or below the other component, depending on the orientation of the device.

[0012] The terms "about," "equal to," "equal" or "same," "substantially" or "approximately" are generally interpreted as meaning within a range of 20% of a given value, or within a range of 10%, 5%, 3%, 2%, 1% or 0.5% of a given value or range.

[0013] The use of ordinal numbers such as "first" and "second" in the specification and claims to modify an element does not, by itself, imply or indicate any prior ordinal number of the element(s), nor does it indicate the order of one element relative to another, or the order of manufacturing methods. Such ordinal numbers are used solely to clearly distinguish a named element from another element with the same name. The claims and the specification may not use the same terminology; thus, the first element in the specification may be the second element in the claims.

[0014] It should be noted that the following embodiments may be implemented by replacing, recombining, or combining features from various embodiments to create other embodiments without departing from the spirit of the present disclosure. Features from various embodiments may be mixed and matched as needed, as long as they do not violate the spirit of the invention or conflict with it.

[0015] The electrical connection or coupling described in this disclosure may refer to direct connection or indirect connection. In the case of direct connection, the endpoints of two circuit components are directly connected or connected to each other via a conductor segment. In the case of indirect connection, the endpoints of the two circuit components are connected by a switch, diode, capacitor, inductor, other suitable element, or a combination of the above elements, but is not limited to these.

[0016] In the present disclosure, thickness, length, and width can be measured using an optical microscope, and thickness can be measured using cross-sectional images obtained through an electron microscope, but this is not limited to these measurements. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If a first value is equal to a second value, this implies that there may be an error of approximately 10% between the first and second values. If a first direction is perpendicular to a second direction, the angle between the first and second directions may be between 80 and 100 degrees. If a first direction is parallel to a second direction, the angle between the first and second directions may be between 0 and 10 degrees.

[0017] The electronic devices disclosed herein may include, but are not limited to, antennas (e.g., liquid crystal antennas), displays, lighting, sensing, touch, splicing, other suitable functions, or combinations of the above. Electronic devices include, but are not limited to, rollable or flexible electronic devices. Display devices may include, for example, liquid crystal, light-emitting diodes (LEDs), quantum dots (QDs), fluorescence, phosphors, other suitable materials, or combinations thereof. Light-emitting diodes may include, but are not limited to, organic light-emitting diodes (OLEDs), micro-LEDs (micro-LEDs, mini-LEDs), or quantum dot light-emitting diodes (QLEDs, QDLEDs). Electronic components may include, but are not limited to, transistors, circuit boards, chips, dies, integrated circuits (ICs), combinations of the above, or other suitable electronic components.

[0018] The following examples illustrate exemplary embodiments of the present disclosure, and the same reference numerals are used in the drawings and description to represent the same or similar parts.

[0019] 1A is a flow chart of a method for manufacturing an electronic device according to an embodiment of the present disclosure, FIG. 1B is an exploded schematic diagram of the electronic device according to the first embodiment of the present disclosure, and FIG. 1C is a top schematic diagram of the electronic device according to the first embodiment of the present disclosure.

[0020] 1A , 1B , and 1C , the manufacturing method of the electronic device 10 a of this embodiment includes the following steps, for example, but the present disclosure is not limited thereto.

[0021] In step S10 , a glass substrate SB is provided, wherein the glass substrate SB includes a first surface SB_S1 and a second surface SB_S2 corresponding to the first surface SB_S1 .

[0022] In this embodiment, the glass substrate SB serves as the dielectric layer of the electronic device 10a. The glass substrate SB's regular molecular arrangement and compact structure reduce dielectric loss during signal transmission. Furthermore, in this embodiment, the first surface SB_S1 and the second surface SB_S2 of the electronic device 10a correspond to each other in the top-view direction n of the electronic device 10a, but the present disclosure is not limited to this.

[0023] In step S20, the glass substrate SB is patterned to form at least two first through holes SB_H1. The first through holes SB_H1 form a third surface SB_S3 in the glass substrate SB, and the third surface SB_S2 connects the first surface SB_S1 and the second surface SB_S2. In some embodiments, the at least two first through holes SB_H1 can be formed using a laser device, a CNC machine tool, or other equipment suitable for glass etching processes, but the present disclosure is not limited thereto. The first through holes SB_H1 can, for example, be formed on two corresponding sides of the glass substrate SB to form a waveguide. Specifically, the first through holes SB_H1 can extend in a first direction d1, and two adjacent first through holes SB_H1 in a second direction d2 can define a signal transmission area of ​​the electronic device 10a. The first direction d1 can be orthogonal to the second direction d2, and both the first direction d1 and the second direction d2 can be orthogonal to the top-view direction n of the electronic device 10a, but the present disclosure is not limited thereto. In this embodiment, the first through hole SB_H1 has a major axis and a minor axis. The major axis of the first through hole SB_H1 may extend in the first direction d1 (signal transmission direction), and the minor axis of the first through hole SB_H1 may extend in the second direction d2. From another perspective, the first through hole SB_H1 may have a closed elliptical shape when viewed from above in the direction n of the electronic device 10a, but the present disclosure is not limited to this. In other embodiments, the first through hole SB_H1 may have a closed shape such as a circle, a rectangle, other geometric shapes, or a combination thereof when viewed from above in the direction n of the electronic device 10a.

[0024] It is worth noting that although FIG1B and FIG1C show that the number of the first through hole SB_H1 in the first direction d1 is one, this embodiment is not limited thereto. That is, the number of the first through hole SB_H1 shown in FIG1B and FIG1C can be multiple in the first direction d1.

[0025] In step S30, a first conductive layer M1 is formed on the first surface SB_S1 of the glass substrate SB. The first conductive layer M1 may be formed by, for example, first forming a first conductive material layer (not shown) on the first surface SB_S1 of the glass substrate SB using an electroplating process and then performing a patterning process. This patterning process may be, for example, a photolithography process, but the present disclosure is not limited thereto. In some embodiments, the material of the first conductive layer M1 may include a high-conductivity material such as copper, silver, gold, other suitable materials, or combinations thereof. In this embodiment, the first conductive layer M1 includes a microstrip line M11, a microstrip gradient line M12, and a conductive portion M13. The microstrip gradient line M12 has two opposite ends connected to the microstrip line M11 and the conductive portion M13, thereby converting a signal transmitted in the TEM mode (where the electric and magnetic field components in the signal transmission direction are zero) into a signal transmitted in the TE mode (where the electric field component in the signal transmission direction is zero). In other words, the electronic device 10a is, for example, a microstrip line-substrate integrated waveguide conversion structure, but the present disclosure is not limited thereto. In some embodiments, the first conductive layer M1 may not include the microstrip gradient line M12. In some embodiments, the first conductive layer M1 may have a signal input terminal and a signal output terminal. Specifically, a signal source (not shown) may be disposed on one side of the glass substrate SB, where this signal source can provide radio waves, microwaves, or other electromagnetic waves of varying wavelengths. In this embodiment, the signal provided by the signal source may be transmitted from the signal input end to the signal output end along the first direction d1, but the present disclosure is not limited thereto.

[0026] In step S40, a second conductive layer M2 is formed on the second surface SB_S2 of the glass substrate SB. The second conductive layer M2 can be formed by, for example, first forming a second conductive material layer (not shown) on the second surface SB_S2 of the glass substrate SB using an electroplating process and then performing a patterning process. This patterning process can be, for example, photolithography, but the present disclosure is not limited thereto. In some embodiments, the material of the second conductive layer M2 can be the same or similar to that of the first conductive layer M1, which will not be described in detail here. The second conductive layer M2 can, for example, be a ground plane. Specifically, the second conductive layer M2 can be used to transmit a ground signal, but the present disclosure is not limited thereto. Furthermore, in this embodiment, the second conductive layer M2 can have a shape corresponding to that of the glass substrate SB. That is, the second conductive layer M2 can also have a through hole M2_H corresponding to the first through hole SB_H1 of the glass substrate SB, but the present disclosure is not limited thereto. In other embodiments, the second conductive layer M2 can have a shape corresponding to that of the first conductive layer M1.

[0027] In step S50, a third conductive layer M3 is formed on the third surface SB_S3 of the glass substrate SB, such that the third conductive layer M3 electrically connects the first conductive layer M1 and the second conductive layer M2. Specifically, the third conductive layer M3 can be formed in the first through hole SB_H1 of the glass substrate SB via a coating process, thereby electrically connecting the first conductive layer M1 disposed on the first surface SB_S1 of the glass substrate SB and the second conductive layer M2 disposed on the second surface SB_S2 of the glass substrate SB, but the present disclosure is not limited thereto. In other embodiments, the third conductive layer M3 can be formed in the first through hole SB_H1 of the glass substrate SB via an electroplating process, wherein the first conductive layer M1 and / or the second conductive layer M2 can be selectively formed together with the third conductive layer M3 via this electroplating process, but the present disclosure is not limited thereto. In some embodiments, the material of the third conductive layer M3 can be the same as or similar to the materials of the first conductive layer M1 and the second conductive layer M2. For example, the material of the third conductive layer M3 can include silver paste or copper paste. The third conductive layer M3 disposed in the first through hole SB_H1 of the glass substrate SB can, for example, serve as a barrier for signal transmission in the electronic device 10a, so that two adjacent first through holes SB_H1 in the second direction d2 can define a signal transmission area of ​​the electronic device 10a.

[0028] At this point, the fabrication of the electronic device 10a is complete. However, the disclosed method for fabricating the electronic device 10a is not limited thereto. For example, the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3 may be formed in a different order than in the above-described embodiment. Specifically, in other embodiments, after step S20, steps S50, S30, and S40 may be performed sequentially, with at least two of these steps S50, S30, and S40 being performed simultaneously. Specifically, the first conductive layer M1 and the third conductive layer M3 may be formed simultaneously using an electroplating process, or the second conductive layer M2 and the third conductive layer M3 may be formed simultaneously using an electroplating process.

[0029] Based on the above, the electronic device 10a of this embodiment uses a glass substrate SB as the dielectric layer of the microstrip line-to-substrate integrated waveguide conversion structure. This can be relatively low-cost compared to printed circuit boards or other dielectric layers. Furthermore, the glass substrate SB has a relatively low dielectric loss factor, which can reduce signal attenuation during transmission within the electronic device 10a.

[0030] FIG2 is a perspective schematic diagram of an electronic device according to a second embodiment of the present disclosure. It should be noted that the embodiment of FIG2 may utilize component numbers and some details from the embodiments of FIG1B and / or FIG1C , wherein identical or similar reference numbers are used to represent identical or similar components, and descriptions of identical technical details are omitted.

[0031] 2 , the main difference between the electronic device 10b of this embodiment and the aforementioned electronic device 10a is that the number of the first through holes SB_H2 in the glass substrate SB is plural in the first direction d1.

[0032] In addition, in this embodiment, the first through hole SB_H2 of the glass substrate SB may have a circular closed shape in the top-view direction n of the electronic device 10b, but the present disclosure is not limited thereto.

[0033] FIG3 is a perspective schematic diagram of an electronic device according to a third embodiment of the present disclosure. It should be noted that the embodiment of FIG3 may utilize the same component numbers and some of the details as the embodiment of FIG2 , with identical or similar components being designated by the same or similar numbers and descriptions of identical technical details being omitted.

[0034] 3 , the main difference between the electronic device 10c of this embodiment and the aforementioned electronic device 10b is that the number of the first through hole SB_H3 in the glass substrate SB in the first direction d1 is one.

[0035] In addition, in this embodiment, the first through hole SB_H3 of the glass substrate SB may have an elliptical closed shape in the top-view direction n of the electronic device 10c, but the present disclosure is not limited thereto.

[0036] In addition, since the number of the first through hole SB_H3 of the electronic device 10c in the first direction d1 is one, it can be formed through a relatively simple process.

[0037] FIG4A is a graph showing the relationship between S parameters and frequency for the electronic devices of the second and third embodiments of the present disclosure, and FIG4B is an enlarged schematic diagram of curves S11-10b and S11-10c in FIG4A . It is worth noting that in the embodiments shown in FIG4A and FIG4B , the cutoff frequency (fc) of the signals of electronic devices 10b and 10c can be, for example, 20 GHz.

[0038] Referring to FIG. 4A , curve S11-10b shows the relationship between the input reflection coefficient (IRC) and signal frequency, as measured and calculated at the signal input end of electronic device 10b. Curve S11-10c shows the relationship between the IRC and signal frequency, as measured and calculated at the signal input end of electronic device 10c. Curves S11-10b and S11-10c indicate that both electronic devices 10b and 10c generally have relatively low and similar IRCs (e.g., less than -10 dB) at high frequencies (e.g., frequencies above 20 GHz or millimeter-wave frequencies). This means that both devices can achieve relatively low signal reflection loss.

[0039] Referring to FIG. 4A and FIG. 4B , curve S21-10b shows the relationship between the forward transmission coefficient (FTC) and signal frequency, as measured and calculated at the signal output end of electronic device 10b. Curve S21-10c shows the relationship between the FTC and signal frequency, as measured and calculated at the signal output end of electronic device 10c. Curves S21-10b and S21-10c indicate that both electronic devices 10b and 10c generally have relatively high and similar FTCs (e.g., FTCs greater than -3dB) at high frequencies (e.g., frequencies above 20 GHz or millimeter-wave frequencies). This means that both devices can achieve relatively low signal loss during transmission.

[0040] Figure 5A is a graph showing the relationship between S parameters and frequency for the electronic device in the TE10 and TE20 modes according to the second embodiment of the present disclosure, and Figure 5B is a graph showing the relationship between S parameters and frequency for the electronic device in the TE10 and TE20 modes according to the third embodiment of the present disclosure. It is worth noting that the TE10 mode can be considered as the wavelength of the signal changing along the second direction d2 by one half-cycle, and the TE20 mode can be considered as the wavelength of the signal changing along the second direction d2 by two half-cycles. Furthermore, in the embodiments shown in Figures 5A and 5B , the cutoff frequency of the signals of electronic devices 10b and 10c can be, for example, 20 GHz.

[0041] 5A and 5B , curve TE10-10b is a curve showing the relationship between the forward transmission coefficient and the signal frequency measured and calculated at the signal output end of the electronic device 10b in the TE10 mode, and curve TE10-10c is a curve showing the relationship between the forward transmission coefficient and the signal frequency measured and calculated at the signal output end of the electronic device 10c in the TE10 mode; curve TE20-10b is a curve showing the relationship between the forward transmission coefficient and the signal frequency measured and calculated at the signal output end of the electronic device 10b in the TE20 mode, and curve TE20-10c is a curve showing the relationship between the forward transmission coefficient and the signal frequency measured and calculated at the signal output end of the electronic device 10c in the TE20 mode. Table 1 summarizes the cutoff frequencies of the electronic devices 10b and 10c in the TE10 mode and TE20 mode, respectively.

[0042] [Table 1] Cutoff frequency in TE10 mode (fc) Cutoff frequency in TE20 mode (fc) bandwidth Electronic device 10b 24.65 GHz 48.92 GHz About 24 GHz Electronic device 10c 25.83 GHz 51.79 GHz About 26 GHz

[0043] As can be seen from FIG. 5A , FIG. 5B and Table 1, the electronic device 10b including a plurality of circular first through holes SB_H2 in the first direction d1 has a bandwidth of approximately 24 GHz, and the electronic device 10c including an elliptical first through hole SB_H3 in the first direction d1 has a bandwidth of approximately 26 GHz.

[0044] FIG6 is a perspective schematic diagram of an electronic device according to a fourth embodiment of the present disclosure. It should be noted that the embodiment of FIG6 may utilize the same component numbers and some of the same content as the embodiment of FIG3 , wherein identical or similar components are represented by the same or similar numbers, and descriptions of identical technical content are omitted.

[0045] 6 , the main difference between the electronic device 10d of this embodiment and the aforementioned electronic device 10c is that the glass substrate SB further includes at least one second through hole SB_V1 , wherein the second through hole SB_V1 is adjacent to the first through hole SB_H4 in the first direction d1 .

[0046] Specifically, compared to the aforementioned electronic device 10c, the second through hole SB_V1 of the electronic device 10d truncates the originally elongated first through hole SB_H2 in the first direction d1, so that the glass substrate SB of the electronic device 10d can have two first through holes SB_H4 and one second through hole SB_V1, wherein the second through hole SB_V1 is disposed between the two first through holes SB_H4 in the first direction d1.

[0047] In this embodiment, the second through-hole SB_V1 and the first through-hole SB_H4 are used to transmit different signals. For example, the second through-hole SB_V1 can be used to transmit a DC signal to an electronic component (not shown) in the electronic device 10d. By varying the voltage applied to the electronic component, the phase and / or amplitude of the signal can be changed, thereby controlling the signal transmission direction and / or improving the directivity of the electronic component. However, the present disclosure is not limited to this.

[0048] In addition, in this embodiment, the second through hole SB_V1 of the glass substrate SB may have a circular closed shape in the top-view direction n of the electronic device 10d, but the present disclosure is not limited thereto.

[0049] FIG7A is a graph showing the relationship between S parameters and frequency for the electronic devices of the third and fourth embodiments of the present disclosure, and FIG7B is an enlarged schematic diagram of curves S21-10c and S21-10d in FIG7A . It should be noted that in the embodiments shown in FIG7A and FIG7B , the cutoff frequency of the signals of electronic devices 10c and 10d may be, for example, 20 GHz.

[0050] Referring to FIG7A , curve S11-10c shows the relationship between the input reflection coefficient and signal frequency, as measured and calculated at the signal input end of electronic device 10c. Curve S11-10d shows the relationship between the input reflection coefficient and signal frequency, as measured and calculated at the signal input end of electronic device 10d. Curves S11-10c and S11-10d indicate that electronic devices 10c and 10d generally have relatively low and similar input reflection coefficients (e.g., input reflection coefficients less than -10 dB) at high frequencies (e.g., frequencies above 20 GHz or millimeter-wave frequencies). This means that both devices can achieve relatively low signal reflection losses.

[0051] Referring to FIG. 7A and FIG. 7B , curve S21-10c shows the relationship between the forward transmission coefficient and the signal frequency, as measured and calculated at the signal output end of electronic device 10c. Curve S21-10d shows the relationship between the forward transmission coefficient and the signal frequency, as measured and calculated at the signal output end of electronic device 10d. Curves S21-10c and S21-10d indicate that electronic devices 10c and 10d both have relatively high and similar forward transmission coefficients (e.g., forward transmission coefficients greater than -3dB) at high frequencies (e.g., frequencies above 20 GHz or millimeter-wave frequencies). This means that both devices can achieve relatively low signal loss during transmission.

[0052] Based on the above, the provision of the second through hole SB_V1 can control the transmission direction of the signal and / or enhance the directivity of the electronic component without substantially affecting the frequency response of the electronic device 10d.

[0053] FIG8A is an exploded schematic diagram of an electronic device according to a fifth embodiment of the present disclosure, and FIG8B is a top schematic diagram of the electronic device according to the fifth embodiment of the present disclosure.

[0054] 8A and 8B , the main differences between the electronic device 10e of this embodiment and the aforementioned electronic device 10d are: (1) the first through hole SB_H5 and the second through hole SB_V2 of the glass substrate SB are disposed at the edge of the first surface SB_S1 and the edge of the second surface SB_S2 of the glass substrate SB; and (2) the electronic component EC is further included.

[0055] Specifically, the first through-hole SB_H5 and the second through-hole SB_V2 can be formed, for example, by removing the side surface of the original glass substrate SB. They can also be formed using a laser device, a CNC machine tool, or other equipment suitable for glass etching processes, but the present disclosure is not limited thereto. In this embodiment, the first through-hole SB_H5 of the glass substrate SB can have a rectangular shape when viewed from above in the direction n of the electronic device 10e, and the second through-hole SB_V2 of the glass substrate SB can have a semicircular shape when viewed from above in the direction n of the electronic device 10e, but the present disclosure is not limited thereto. In some embodiments, the first through-hole SB_H5 and the second through-hole SB_V2 can have the same shape. Furthermore, the second through-hole SB_V2 and the first through-hole SB_H5 can also be used to transmit different signals, which will not be further described here.

[0056] In this embodiment, the electronic component EC is disposed on the first surface SB_S1 of the glass substrate SB and electrically connected to the first conductive layer M1. The electronic component EC receives a DC signal through the second through-hole SB_V2 and a ground signal through the first through-hole SB_H5. In some embodiments, the electronic component EC comprises a radio frequency component, i.e., an electronic component applicable to communications, radar / LiDAR, Reconfigurable Intelligent Surface (RIS) technology, or other suitable fields / technologies, but the present disclosure is not limited thereto. In some embodiments, the electronic component EC may comprise a variable capacitor, a variable resistor, a varactor diode, a phase shifter, an amplifier, an antenna, a biometric sensor, a graphene sensor, other suitable electronic components, or a combination thereof. Furthermore, the electronic component EC may, for example, control the signal transmission direction and / or enhance the directivity of the electronic component by receiving the DC signal from the second through-hole SB_V2, but the present disclosure is not limited thereto.

[0057] FIG9 is a perspective schematic diagram of an electronic device according to a sixth embodiment of the present disclosure. It should be noted that the embodiment of FIG9 may utilize the same component numbers and some of the details as the embodiment of FIG2 , with identical or similar components being designated by the same or similar numbers and descriptions of the same technical details being omitted.

[0058] 9 , the main difference between the electronic device 10f of this embodiment and the aforementioned electronic device 10b is that the first through hole SB_H6 of the glass substrate SB is disposed at the edge of the first surface SB_S1 and the edge of the second surface SB_S2 of the glass substrate SB, and has a rectangular shape in the top view direction n of the electronic device 10f.

[0059] It is worth noting that while this embodiment illustrates that the first through hole SB_H6 of the glass substrate SB is disposed at the edges of the first surface SB_S1 and the second surface SB_S2 of the glass substrate SB and has a non-enclosed shape, the present disclosure is not limited to this. In other embodiments, the first through hole SB_H6 of the glass substrate SB may have a rectangular, enclosed shape when viewed in the top direction n of the electronic device 10f.

[0060] FIG10A is a graph showing the relationship between S parameters and frequency for the electronic devices of the second embodiment and the sixth embodiment of the present disclosure, and FIG10B is an enlarged schematic diagram of curves S21-10b and S21-10f in FIG10A . It is worth noting that in the embodiments shown in FIG10A and FIG10B , the cutoff frequency of the signals of electronic devices 10b and 10f may be, for example, 20 GHz.

[0061] Referring to FIG10A , curve S11-10b shows the relationship between the input reflection coefficient and signal frequency, as measured and calculated at the signal input end of electronic device 10b. Curve S11-10f shows the relationship between the input reflection coefficient and signal frequency, as measured and calculated at the signal input end of electronic device 10f. Curves S11-10b and S11-10f indicate that electronic devices 10b and 10f generally have relatively low and similar input reflection coefficients (e.g., input reflection coefficients less than -10 dB) at high frequencies (e.g., frequencies above 20 GHz or millimeter-wave frequencies). This means that both devices can achieve relatively low signal reflection losses.

[0062] Referring to FIG. 10A and FIG. 10B , curve S21-10b shows the relationship between the forward transmission coefficient and the signal frequency, as measured and calculated at the signal output end of electronic device 10b. Curve S21-10f shows the relationship between the forward transmission coefficient and the signal frequency, as measured and calculated at the signal output end of electronic device 10f. Curves S21-10b and S21-10f indicate that electronic devices 10b and 10f generally have relatively high and similar forward transmission coefficients (e.g., forward transmission coefficients greater than -3dB) at high frequencies (e.g., frequencies above 20 GHz or millimeter wave frequencies). This means that both devices can achieve relatively low signal loss during transmission.

[0063] Based on the above, compared with the electronic device 10b, disposing the first through hole SB_H6 of the glass substrate SB at the edge of the first surface SB_S1 and the edge of the second surface SB_S2 of the glass substrate SB and disposing it in a rectangular shape in the top view direction n of the electronic device 10f can substantially not affect the frequency response of the electronic device 10f.

[0064] FIG11 is a perspective schematic diagram of an electronic device according to a seventh embodiment of the present disclosure. It should be noted that the embodiment of FIG11 may utilize the same component numbers and some of the details as the embodiment of FIG10 , wherein identical or similar components are represented by the same or similar numbers, and descriptions of identical technical details are omitted.

[0065] 11 , the main difference between the electronic device 10g of this embodiment and the aforementioned electronic device 10f is that the glass substrate SB further includes at least one second through hole SB_V3 , wherein the second through hole SB_V3 is adjacent to the first through hole SB_H7 in the first direction d1 .

[0066] Specifically, compared with the aforementioned electronic device 10f, the electronic device 10g further includes at least one second through hole SB_V3 arranged in the first direction d1, wherein one second through hole SB_V3 of the electronic device 10g is disposed between two adjacent first through holes SB_H7.

[0067] In this embodiment, the second through-hole SB_V3 and the first through-hole SB_H7 are used to transmit different signals. For example, the second through-hole SB_V3 can be used to transmit a DC signal to an electronic component (not shown) in the electronic device 10g. By varying the voltage applied to the electronic component, the phase and amplitude of the signal can be changed, thereby controlling the signal transmission direction and / or improving the directivity of the electronic component. However, the present disclosure is not limited to this.

[0068] In addition, in this embodiment, the second through hole SB_V3 of the glass substrate SB may have a semicircular closed shape in the top view direction n of the electronic device 10g; or may be set at the edge of the first surface SB_S1 and the edge of the second surface SB_S2 of the glass substrate SB, but the present disclosure is not limited thereto.

[0069] FIG. 12 is a graph showing the relationship between S parameters and frequency of the electronic device according to the sixth embodiment and the electronic device according to the seventh embodiment of the present disclosure.

[0070] Referring to Figure 12 , curve S11-10f shows the relationship between the input reflection coefficient and signal frequency, as measured and calculated at the signal input end of electronic device 10f. Curve S11-10g shows the relationship between the input reflection coefficient and signal frequency, as measured and calculated at the signal input end of electronic device 10g. Curves S11-10f and S11-10g show that electronic devices 10f and 10g generally have relatively low and similar input reflection coefficients (e.g., input reflection coefficients less than -10 dB) at high frequencies (e.g., frequencies above 20 GHz or millimeter-wave frequencies). This means that both devices can achieve relatively low signal reflection losses.

[0071] Continuing with FIG12 , curve S21-10f shows the relationship between the forward transmission coefficient and signal frequency, as measured and calculated at the signal output end of electronic device 10f. Curve S21-10g shows the relationship between the forward transmission coefficient and signal frequency, as measured and calculated at the signal output end of electronic device 10g. Curves S21-10f and S21-10g show that electronic devices 10f and 10g generally have relatively high and similar forward transmission coefficients (e.g., forward transmission coefficients greater than -3dB) at high frequencies (e.g., frequencies above 20 GHz or millimeter wave frequencies). This means that both devices can achieve relatively low signal loss during transmission.

[0072] Based on the above, the provision of the second through hole SB_V3 can control the transmission direction of the signal and / or enhance the directivity of the electronic component without substantially affecting the frequency response of the electronic device 10g.

[0073] FIG13A is a flow chart of a method for manufacturing an electronic device according to another embodiment of the present disclosure, and FIG13B is a schematic perspective view of an electronic device according to an eighth embodiment of the present disclosure. It should be noted that the embodiments of FIG13A and FIG13B may share component numbers and some details from the embodiments of FIG1A through FIG1C , with identical or similar reference numbers used to represent identical or similar components, and descriptions of identical technical details omitted.

[0074] Referring simultaneously to FIG. 13A and FIG. 13B , the manufacturing method of the electronic device 10h of this embodiment includes the following steps, wherein the detailed process flow of steps S10 to S50 can be referred to the aforementioned embodiment and will not be repeated here. It is worth noting that at least two first through holes SB_H8 are provided in the substrate SB on opposite sides of each first metal layer M1. Although the first through holes SB_H8 are shown as having a closed elliptical shape when viewed from above in the direction n of the electronic device 10h, this is not a limitation of the present disclosure. Other aspects of the first through holes SB_H8 can be referred to the aforementioned embodiment and will not be repeated here.

[0075] After step S50, in step S60, a substrate SB' is provided and a first adhesive layer AL1 is formed on the substrate SB'. In this embodiment, the substrate SB' can be a rigid substrate, a bendable substrate, or a flexible substrate. For example, the substrate SB' can include a printed circuit board, a glass substrate, a ceramic substrate, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the substrate SB' can be used to support suitable electronic components, but the present disclosure is not limited thereto.

[0076] The first adhesive layer AL1 may include, for example, a suitable adhesive material, but the present disclosure is not limited thereto.

[0077] Next, in step S70, the glass substrate SB is bonded to the substrate SB' via the first adhesive layer AL1. Specifically, the surface SB_S2 of the glass substrate SB, on which the second metal layer M2 is disposed, may face the surface of the substrate SB', on which the first adhesive layer AL1 is disposed. The glass substrate SB may be bonded to the substrate SB' via the first adhesive layer AL1.

[0078] At this point, the manufacturing of the electronic device 10h is completed. However, the manufacturing method of the electronic device 10h disclosed herein is not limited thereto.

[0079] FIG14A is a flow chart of a method for manufacturing an electronic device according to another embodiment of the present disclosure, and FIG14B is a schematic perspective view of an electronic device according to a ninth embodiment of the present disclosure. It should be noted that the embodiments of FIG14A and FIG14B may utilize the same component numbers and some details as the embodiments of FIG13A and FIG13B , with identical or similar reference numbers being used to represent identical or similar components, and descriptions of identical technical details being omitted.

[0080] 14A and 14B , the manufacturing method of the electronic device 10i of this embodiment includes the following steps, wherein the detailed process of steps S10 to S50 can be referred to the aforementioned embodiment and will not be repeated here.

[0081] After step S50, in step S52, the glass substrate SB is cut to form a plurality of sub-units SUB. In some embodiments, the glass substrate SB can be cut using a laser cutting process or a knife wheel cutting process, but the present disclosure is not limited thereto. Furthermore, in some embodiments, the second metal layer M2 can also be cut using a laser cutting process or a knife wheel cutting process, wherein the cut second metal layer M2 and the glass substrate SB can have the same or similar shapes, but the present disclosure is not limited thereto. Therefore, the sub-units SUB may, for example, include a first metal layer M1, a cut second metal layer M2, a third metal layer M3, and a cut glass substrate SB. Furthermore, each sub-unit SUB may have at least two first through holes SB_H9 formed on opposite sides of the glass substrate SB to form a waveguide. Although the first through holes SB_H9 are shown as having a closed elliptical shape when viewed from above in the direction n of the electronic device 10i, the present disclosure is not limited thereto. Other aspects of the first through holes SB_H9 can be referred to in the previous embodiments and will not be further described here.

[0082] In step S70, the plurality of sub-units SUB are bonded to the substrate SB' via a first adhesive layer AL1. Specifically, the first adhesive layer AL1 can be formed on the substrate SB', for example. The first adhesive layer AL1 can comprise a suitable adhesive material, but the present disclosure is not limited thereto. Subsequently, the surfaces SB_S2 of the plurality of sub-units SUB, on which the second metal layer M2 is disposed, are positioned facing the surface of the substrate SB', on which the first adhesive layer AL1 is disposed, and the plurality of sub-units SUB are bonded to the substrate SB' via the first adhesive layer AL1.

[0083] In some embodiments, before performing step S70, the following steps S54, S56, and S60 may be further performed.

[0084] First, in step S24, a second adhesive layer AL2 is formed between at least two sub-units SUB. The second adhesive layer AL2 may be disposed between adjacent sub-units SUB in the second direction d2. The second adhesive layer AL2 may, for example, comprise a suitable adhesive material, although the present disclosure is not limited thereto. In the embodiment shown in FIG14B , prior to forming the second adhesive layer AL2, a protective layer RS ​​may be formed between at least two sub-units SUB. The protective layer RS ​​may, for example, be used to further secure the shape of the sub-units SUB and to protect the first metal layer M1, the second metal layer M2, the third metal layer M3, and the glass substrate SB within the sub-units SUB, although the present disclosure is not limited thereto.

[0085] Next, in step S56, at least two sub-units SUB are bonded together via the second adhesive layer AL2. That is, adjacent sub-units SUB in the second direction d2 are bonded together via the second adhesive layer AL2. Next, step S60 is performed. The detailed process of step S60 can be referred to the previous embodiment and will not be repeated here.

[0086] In summary, some embodiments of the present disclosure use a glass substrate as a dielectric layer of an electronic device, which can have a relatively low cost compared to a printed circuit board or other dielectric layers, and can reduce signal attenuation during transmission in the electronic device.

[0087] Other embodiments disclosed herein provide various structures for forming first through-holes that define signal transmission areas of electronic devices. Compared to conventional techniques, these structures can be formed through relatively simple processes and can also achieve relatively low signal loss during transmission.

[0088] Still other embodiments of the present disclosure include a second through-hole disposed on the glass substrate, adjacent to the first through-hole and transmitting a different signal than the first through-hole. The provision of the second through-hole can control the direction of signal transmission and / or enhance the directivity of the electronic component without substantially affecting the frequency response of the electronic device.

[0089] 10a, 10b, 10c, 10d, 10e, 10f, 10g, 10h, 10i: Electronic devices AL1: First adhesive layer AL2: Second adhesive layer d1: first direction d2: second direction EC: Electronic Components M1: First metal layer M11: Microstrip line M12: Microstrip gradient line M13: Conductive part M2: Second metal layer M2_H: Through hole M3: The third metal layer n: looking down RS: Protective layer S11-10b, S11-10c, S11-10d, S11-10f, S11-10g, S21-10b, S21-10c, S21-10d, S21-10f, S21-10g, TE10-10b, TE10-10c, TE20-10b, TE20-10c: curve S10, S20, S30, S40, S50, S52, S54, S56, S60, S70: Steps SB: Glass substrate SB':Substrate SB_H1, SB_H2, SB_H3, SB_H4, SB_H5, SB_H6, SB_H7, SB_H8, SB_H9: First through hole SB_S1, SB_S2, SB_S3: Surface SB_V1, SB_V2, SB_V3: Second through hole SUB: Subunit

Claims

1. A waveguide device, comprising: substrate; The system comprises a plurality of sub-units bonded to the substrate via an adhesive layer, and at least one of the plurality of sub-units includes: a glass substrate including a first surface, a second surface corresponding to the first surface, a plurality of first through-holes arranged along a first direction, and a plurality of second through-holes arranged along a second direction, wherein the first through-holes include a third surface and the third surface is connected to the first surface and the second surface; a first conductive layer disposed on the first surface; a second conductive layer disposed on the second surface; and a third conductive layer disposed on the third surface and electrically connecting the first conductive layer and the second conductive layer, wherein, in a top view, the first through-hole has a major axis and a minor axis extending along the first direction, and wherein the second through-holes and the first through-hole transmit different signals.

2. The waveguide device as claimed in claim 1, wherein the at least two first through holes are respectively disposed on opposite sides of the glass substrate to form a waveguide.

3. The waveguide device as claimed in claim 1, wherein the second via is adjacent to the first via.

4. The waveguide device as claimed in claim 3, further comprising electronic components disposed on the glass substrate, the electronic components being used to receive DC signals through the second via.

5. The waveguide device as claimed in claim 1, wherein the first via includes a closed shape.

6. The waveguide device as claimed in claim 1, wherein the first via is disposed at the edge of the first surface and the edge of the second surface.

7. A method for manufacturing a waveguide device, comprising: A glass substrate is provided, wherein the glass substrate includes a first surface and a second surface corresponding to the first surface; the glass substrate is patterned to form a plurality of first through holes arranged along a first direction and a plurality of second through holes arranged along a second direction, wherein the first through holes form a third surface in the glass substrate, and the third surface connects the first surface and the second surface; a first conductive layer is formed on the first surface; a second conductive layer is formed on the second surface; The manufacturing method further includes: forming a third conductive layer on the third surface, such that the third conductive layer is electrically connected to the first conductive layer and the second conductive layer; wherein, in a top view, the first via has a major axis and a minor axis extending along the first direction; wherein the second via transmits different signals from the first via; and wherein the manufacturing method further includes: providing another substrate; forming a first adhesive layer on the other substrate; cutting the glass substrate to form a plurality of sub-units; and bonding the plurality of sub-units to the other substrate through the first adhesive layer.

8. A method of manufacturing a waveguide device as claimed in claim 7, wherein the at least two first through holes are respectively formed on opposite sides of the glass substrate to form a waveguide.

9. A method of manufacturing a waveguide device as claimed in claim 7, wherein the second via is used to transmit a DC signal.

10. A method of manufacturing a waveguide device as claimed in claim 7, wherein the step of forming the first conductive layer on the first surface includes a patterning process.

11. A method of manufacturing a waveguide device as claimed in claim 7, wherein the step of forming the second conductive layer on the second surface includes a patterning process.

12. A method of manufacturing a waveguide device as claimed in claim 7, wherein the first via is formed in a closed shape or formed on the edge of the first surface and the edge of the second surface.

13. The method of manufacturing the waveguide device as described in claim 7, further comprising: A second adhesive layer is formed between at least two of the plurality of sub-units; And the at least two or more sub-units are bonded together through the second adhesive layer.

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