Semiconductor package

Abstract

A semiconductor package is provided. A semiconductor package includes a first structure and a second structure. The first structure includes: a first semiconductor substrate having an effective surface and a non-effective surface opposite the effective surface, a first semiconductor device being configured to be disposed on the effective surface; a first through-hole perpendicularly penetrating the first semiconductor substrate and protruding from the non-effective surface of the first semiconductor substrate; a first protective layer covering the non-effective surface of the first semiconductor substrate and burying the first through-hole; and a first pad penetrating at least a portion of the first protective layer and coupled to the first through-hole. The second structure includes a second pad, the first structure and the second structure being joined to each other, and the first pad and the second pad being in contact with each other.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a direct bonding semiconductor package and a method of manufacturing the same. [Cross-reference to Related Applications]

[0002] This application claims priority to Korean Patent Application No. 10-2023-0051465, filed with the Korean Intellectual Property Office on April 19, 2023, the entire disclosure of which is incorporated herein by reference. Background Art

[0003] In the semiconductor industry, there is a need for semiconductor devices with higher capacity, thinner and smaller size, and electronic products using the semiconductor devices, and thus various packaging technologies have been proposed. The various packaging technologies include a packaging technology for vertically stacking a plurality of semiconductor wafers to achieve a high-density wafer stack. Such a packaging technology can integrate semiconductor wafers with various functions in an area smaller than that of a conventional package composed of a single semiconductor wafer.

[0004] A semiconductor package is provided to implement an integrated circuit chip for use in an electronic product. A semiconductor package is generally configured such that a semiconductor wafer is mounted on a printed circuit board (PCB), and bonding wires or bonding bumps are used to electrically connect the semiconductor wafer to the printed circuit board. With the development of the electronics industry, research has been conducted to improve the reliability and durability of semiconductor packages. Summary of the Invention

[0005] Some embodiments of the present disclosure provide a semiconductor package having improved structural stability and a method of manufacturing the same.

[0006] Some embodiments of the present disclosure provide a method of manufacturing a semiconductor package having a lower failure rate and a semiconductor package manufactured by the method.

[0007] According to an embodiment of the present disclosure, a semiconductor package is provided, and the semiconductor package includes a first structure and a second structure. The first structure includes: a first semiconductor substrate having an active surface and an inactive surface opposite to the active surface, a first semiconductor device configured to be disposed on the active surface; a first via vertically penetrating the first semiconductor substrate and protruding from the inactive surface of the first semiconductor substrate; a first protective layer covering the inactive surface of the first semiconductor substrate and burying the first via; and a first pad penetrating at least a portion of the first protective layer and coupled to the first via. The first protective layer includes: a first dielectric layer located on the inactive surface of the first semiconductor substrate; a second dielectric layer located on the first dielectric layer; and an etch stop layer located between the first dielectric layer and the second dielectric layer and in contact with a lateral surface of the first pad. The second structure includes a second pad, the first structure and the second structure are joined to each other, and the first pad and the second pad are in contact with each other.

[0008] According to an embodiment of the present disclosure, a semiconductor package is provided, and the semiconductor package includes: a substrate; a semiconductor chip located on the substrate; and a molding layer located on the substrate, the molding layer surrounding the semiconductor chip. Each of the semiconductor chips includes: a semiconductor substrate; a first pad located on an active surface of the semiconductor substrate; a dielectric pattern surrounding the first pad and exposing one surface of the first pad; a second pad located on an inactive surface of the semiconductor substrate; a protective layer surrounding the second pad and exposing one surface of the second pad; and a via vertically penetrating the semiconductor substrate and connected to the second pad, wherein the protective layer includes a first dielectric layer, an etch stop layer, and a second dielectric layer stacked in sequence, the first dielectric layer and the second dielectric layer are spaced apart from each other across the etch stop layer, wherein a distance from the etch stop layer to the semiconductor substrate is greater than a distance from a bottom surface of the second pad to the semiconductor substrate, and wherein one of the semiconductor chips is directly bonded to another of the semiconductor chips, and the first pad of the one of the semiconductor chips is in contact with the second pad of the other of the semiconductor chips.

[0009] According to an embodiment of the present disclosure, a semiconductor package is provided, and the semiconductor package includes: a substrate; semiconductor wafers stacked on the substrate; and a molding layer located on the substrate, the molding layer surrounding the semiconductor wafers. Each of the semiconductor wafers includes: a semiconductor substrate; a first pad located on an active surface of the semiconductor substrate; a dielectric pattern surrounding the first pad and exposing one surface of the first pad; a protective layer located on a non-active surface of the semiconductor substrate and including a first dielectric layer, an etch stop layer, a second dielectric layer, and a polish stop layer stacked in sequence; a second pad located in the protective layer and having one surface exposed through the protective layer; and a via vertically penetrating the semiconductor substrate and connected to the second pad, wherein the etch stop layer is in contact with the second pad, and wherein one of the semiconductor wafers is directly bonded to another of the semiconductor wafers, and the first pad of the one of the semiconductor wafers is in contact with the second pad of the another of the semiconductor wafers.

[0010] According to an embodiment of the present disclosure, a method of manufacturing a semiconductor package is provided, and the method includes: providing a semiconductor substrate; forming a via in the semiconductor substrate extending from an active surface of the semiconductor substrate into the semiconductor substrate; performing a first thinning process on a non-active surface of the semiconductor substrate, which causes the via to protrude from the non-active surface of the semiconductor substrate; forming a first dielectric layer on the non-active surface of the semiconductor substrate, wherein the first dielectric layer buries the via; performing a second thinning process on the first dielectric layer, further causing the via to be exposed from the first dielectric layer; sequentially forming an etch stop layer and a second dielectric layer on the first dielectric layer and the via; forming a recess exposing the via by patterning the second dielectric layer and the etch stop layer, the etch stop layer defining an inner wall of the recess; and forming a pad connected to the via by filling the recess with a conductive material. Brief Description of the Drawings

[0011] FIG. 1 shows a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. FIGS. 2A to 2E show enlarged views of section A shown in FIG. 1. FIG. 3 shows a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. FIG. 4 shows an enlarged view of section B shown in FIG. 3. FIG. 5 shows a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. FIG. 6 shows a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. FIG. 7 shows an enlarged view of section C shown in FIG. 6. FIG. 8 shows a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. FIG. 9A shows a cross-sectional view of a part of a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. FIG. 9B shows an enlarged view of section D1 shown in FIG. 9A. FIG. 10A shows a cross-sectional view of a part of a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. FIG. 10B shows an enlarged view of section D2 shown in FIG. 10A. FIG. 11A shows a cross-sectional view of a part of a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. FIG. 11B shows an enlarged view of section D3 shown in FIG. 11A. FIG. 12A shows a cross-sectional view of a part of a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. FIG. 12B shows an enlarged view of section D4 shown in FIG. 12A. FIG. 13A shows a cross-sectional view of a part of a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. FIG. 13B shows an enlarged view of section D5 shown in FIG. 13A. FIG. 14A shows a cross-sectional view of a part of a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. FIG. 14B shows an enlarged view of section D6 shown in FIG. 14A. FIG. 15A shows a cross-sectional view of a part of a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. FIG. 15B shows an enlarged view of section D7 shown in FIG. 15A. FIG. 16A shows a cross-sectional view of steps of a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. FIG. 16B shows an enlarged view of section E1 shown in FIG. 16A. FIG. 17A shows a cross-sectional view of steps of a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. FIG. 17B shows an enlarged view of section E2 shown in FIG. 17A. FIG. 18A shows a cross-sectional view of steps of a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. FIG. 18B shows an enlarged view of section E3 shown in FIG. 18A. FIG. 19A shows a cross-sectional view of steps of a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. FIG. 19B shows an enlarged view of section E4 shown in FIG. 19A. FIG. 20A shows a cross-sectional view of steps of a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. FIG. 20B shows an enlarged view of section E5 shown in FIG. 20A. FIG. 21A shows a cross-sectional view of steps of a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. FIG. 21B shows an enlarged view of section E6 shown in FIG. 21A. FIG. 22A shows a cross-sectional view of steps of a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. FIG. 22B shows an enlarged view of section E7 shown in FIG. 22A. FIG. 23A shows a cross-sectional view of steps of a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. FIG. 23B shows an enlarged view of section E8 shown in FIG. 23A. FIGS. 24 to 29 show cross-sectional views of a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. Embodiments

[0012] A semiconductor package according to non-limiting exemplary embodiments of the present disclosure will now be described with reference to the accompanying drawings.

[0013] It should be understood that when an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, the element or layer can be directly on, directly connected to or directly coupled to the other element or layer, or there may also be intermediate elements or layers. In contrast, when an element or layer is referred to as being "directly on", "directly connected to" or "directly coupled to" another element or layer, there are no intermediate elements or layers.

[0014] FIG. 1 shows a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. FIGS. 2A and 2B show enlarged views of section A shown in FIG. 1.

[0015] Referring to FIGS. 1 and 2A, the semiconductor package may include at least one semiconductor die 100.

[0016] The semiconductor wafer 100 can be a logic wafer. As an alternative, the semiconductor wafer 100 can be a memory wafer such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a magnetic random access memory (MRAM), or a flash memory. The semiconductor wafer 100 can have a front surface and a back surface. In this description, the term "front surface" can be defined as the effective surface of the integrated components in the semiconductor wafer or the surface on which multiple pads are formed on the upper surface of the semiconductor wafer, and the term "back surface" can be defined as the opposite surface facing in the direction opposite to the facing direction of the front surface. The semiconductor wafer 100 can include a base layer 110, a circuit layer 120, a protective layer 140, and at least one via 130. The circuit layer 120 is disposed on the bottom surface 110a of the base layer 110, the protective layer 140 is disposed on the top surface 110b of the base layer 110, and the at least one via 130 penetrates the base layer 110.

[0017] The base layer 110 can include a semiconductor material. For example, the base layer 110 can be a single crystal silicon (Si) substrate. Semiconductor devices can be disposed on the base layer 110. Specifically, integrated components or integrated circuits can be formed on the lower portion of the base layer 110. For example, a wiring pattern, integrated components (such as transistors), or passive components (such as resistors, capacitors, or inductors) can be formed on the bottom surface 110a of the base layer 110. The bottom surface 110a can be the front surface of the base layer 110, and the top surface 110b can be the back surface of the base layer 110.

[0018] The circuit layer 120 can be disposed on the bottom surface 110a of the base layer 110. The circuit layer 120 can be electrically connected to the integrated components or integrated circuits formed in the base layer 110. For example, the circuit layer 120 can have a dielectric pattern 122 and a wiring pattern 124 disposed in the dielectric pattern 122, and the wiring pattern 124 can be coupled to the integrated components or integrated circuits formed in the base layer 110. A portion of the wiring pattern 124 can be exposed at the bottom of the circuit layer 120, and the exposed portion of the wiring pattern 124 can be the first wafer pad 125 of the semiconductor wafer 100. Multiple first wafer pads 125 can be provided. The semiconductor wafer 100 can have a bottom surface or an effective surface on which the circuit layer 120 is disposed.

[0019] The via 130 may vertically penetrate the base layer 110. One end of the via 130 may be exposed at the top surface 110b of the base layer 110. The via 130 may protrude from the top surface 110b of the base layer 110 or the back surface of the semiconductor wafer 100. For example, the one end of the via 130 may be at a level higher than the level of the top surface 110b of the base layer 110. The other end of the via 130 may extend toward the front surface of the semiconductor wafer 100 to connect to the circuit layer 120. The via 130 may be coupled to the wiring pattern 124 of the circuit layer 120.

[0020] The via 130 may include a conductive layer 132 and a via barrier layer 134. The conductive layer 132 may have a columnar shape that vertically penetrates the base layer 110. The conductive layer 132 may contain a metallic material such as copper (Cu) or tungsten (W). The via barrier layer 134 may surround the circumferential surface of the conductive layer 132. The via barrier layer 134 may not cover the top surface of the conductive layer 132. For example, the top surface of the conductive layer 132 may be exposed and not covered by the via barrier layer 134. The via barrier layer 134 may be provided to insulate the conductive layer 132 and the base layer 110 from each other, or may be provided to prevent the material of the conductive layer 132 from diffusing into the base layer 110. The via barrier layer 134 may contain a conductive metal nitride such as titanium nitride (TiN) or tantalum nitride (TaN). As an alternative, the via barrier layer 134 may include a dielectric layer.

[0021] On the top surface 110b of the base layer 110, a second chip pad 150 may be provided. The second chip pad 150 may be located on the via hole 130. For example, the second chip pad 150 may be in contact with the top surface of the via hole 130. The bottom surface of the second chip pad 150 may be in contact with the top surface of the conductive layer 132 and the top surface of the via hole barrier layer 134. The second chip pad 150 may not be in contact with the circumferential surface of the via hole 130 protruding from the top surface 110b of the base layer 110. As an alternative, the second chip pad 150 may be in contact with at least a portion of the circumferential surface of the via hole 130 protruding from the top surface 110b of the base layer 110. Hereinafter, the embodiment shown in FIG. 2A will be described, in which the circumferential surface of the via hole 130 is not in contact with the second chip pad 150. Since the via hole 130 protrudes from the top surface 110b of the base layer 110, the second chip pad 150 may be spaced apart from the top surface 110b of the base layer 110. The width of the bottom surface of the second chip pad 150 may be greater than the width of the top surface of the via hole 130. For example, the via hole 130 may cover the center of the top surface of the second chip pad 150, and the edges of the bottom surface of the second chip pad 150 may be exposed and not covered by the via hole 130. The second chip pad 150 may have a width that increases as the distance from the base layer 110 increases. A plurality of second chip pads 150 may be provided. In such a case, each of the second chip pads 150 may be connected to one of the plurality of via holes 130. The second chip pad 150 may include a metallic material such as copper (Cu).

[0022] According to an embodiment, the second chip pad 150 may further include a seed layer covering the bottom surface and the lateral surface of the second chip pad 150. The seed layer may include a metal such as gold (Au).

[0023] The protective layer 140 may be disposed on the top surface 110b of the base layer 110. The protective layer 140 may cover the top surface 110b of the base layer 110 and may bury the vias 130 protruding from the top surface 110b of the base layer 110. For example, the vias 130 may penetrate a portion of the protective layer 140. The protective layer 140 may surround the second chip pad 150 on the top surface 110b of the base layer 110. The top surface of the protective layer 140 and the top surface of the second chip pad 150 may be substantially flat and may be coplanar with each other. For example, the second chip pad 150 may be located in the upper portion of the protective layer 140, and the vias 130 may penetrate the lower portion of the protective layer 140 to be coupled to the bottom surface of the second chip pad 150. The protective layer 140 may contact the bottom surface and the outer lateral surfaces of the second chip pad 150 and the circumferential surface of the vias 130. The protective layer 140 may include a pad layer 141, a first dielectric layer 142, an etch stop layer 143, a second dielectric layer 144, and a polish stop layer 145 that are sequentially disposed on the top surface 110b of the base layer 110.

[0024] The pad layer 141 may be disposed on the top surface 110b of the base layer 110. The pad layer 141 may conformally cover the top surface 110b of the base layer 110 and the circumferential surface of the vias 130. The pad layer 141 may extend along the circumferential surface of the vias 130 from the top surface 110b of the base layer 110, and one end of the pad layer 141 may contact the bottom surface of the second chip pad 150. The pad layer 141 may have a thickness smaller than the distance by which the vias 130 protrude from the top surface 110b of the base layer 110. The pad layer 141 may comprise a dielectric material. For example, the pad layer 141 may comprise silicon nitride (SiN).

[0025] The first dielectric layer 142 may be disposed on the cushion layer 141. The first dielectric layer 142 may cover the top surface 110b of the base layer 110 and may surround the via 130. For example, the cushion layer 141 may be sandwiched between the first dielectric layer 142 and the base layer 110 and may extend between the first dielectric layer 142 and the circumferential surface of the via 130. The top surface of the first dielectric layer 142 may be at a level higher than the level of the top surface of the via 130. The distance between the contact interface between the via 130 and the second chip pad 150 and the base layer 110 may be less than the distance between the top surface of the first dielectric layer 142 and the base layer 110, and / or the contact interface between the via 130 and the second chip pad 150 may be lower than the level of the top surface of the first dielectric layer 142. Thus, the first dielectric layer 142 may contact the bottom surface of the second chip pad 150 and the lower portion of the lateral surface of the second chip pad 150. The top surface of the first dielectric layer 142 may be substantially flat. The first dielectric layer 142 may comprise a dielectric material. The first dielectric layer 142 may comprise a material different from that of the cushion layer 141. For example, the first dielectric layer 142 may comprise silicon oxide (SiO).

[0026] The etch stop layer 143 may be disposed on the first dielectric layer 142. The etch stop layer 143 may completely cover the top surface of the first dielectric layer 142. The etch stop layer 143 may extend along the top surface of the first dielectric layer 142 to contact the lateral surface of the second chip pad 150. The bottom surface of the etch stop layer 143 may be at a level higher than the level of the bottom surface of the second chip pad 150. As an alternative, as shown in FIG. 2B, the top surface of the first dielectric layer 142 and the bottom surface of the etch stop layer 143 may be at the same level as the level of the bottom surface of the second chip pad 150 or the level of the contact point between the via 130 and the second chip pad 150. For example, the bottom surface of the second chip pad 150 may be coplanar with the bottom surface of the etch stop layer 143. The following description will now focus on the embodiment shown in FIG. 2A. The etch stop layer 143 may be shaped as a substantially flat planarized layer. For example, the top surface of the etch stop layer 143 may be substantially flat. The etch stop layer 143 may comprise a dielectric material. The etch stop layer 143 may comprise a material having an etch selectivity with respect to the first dielectric layer 142 and the second dielectric layer 144, which will be discussed below. For example, the etch stop layer 143 may comprise silicon nitride (SiN).

[0027] The second dielectric layer 144 may be disposed on the etching stop layer 143. The second dielectric layer 144 may cover the top surface of the etching stop layer 143. The second dielectric layer 144 may extend along the top surface of the etching stop layer 143 to contact the lateral surface of the second chip pad 150. The etching stop layer 143 may separate the second dielectric layer 144 and the first dielectric layer 142 from each other. For example, the etching stop layer 143 may be arranged between the first dielectric layer 142 and the second dielectric layer 144 to contact the second chip pad 150, and may separate the first dielectric layer 142 and the second dielectric layer 144 from each other. The second dielectric layer 144 may have a uniform thickness. Since the etching stop layer 143 completely covers the top surface of the first dielectric layer 142 and since the etching stop layer 143 is shaped as a flat planarization layer, the second dielectric layer 144 may have a plate shape, and the top surface of the second dielectric layer 144 may be substantially flat. This will be further described in detail when describing the method of manufacturing a semiconductor package below. The top surface of the second dielectric layer 144 may be at a level lower than the level of the top surface of the second chip pad 150. The second dielectric layer 144 may include a dielectric material. For example, the second dielectric layer 144 may include silicon oxide (SiO).

[0028] The polishing stop layer 145 may be disposed on the second dielectric layer 144. The polishing stop layer 145 may cover the top surface of the second dielectric layer 144. The polishing stop layer 145 may extend along the top surface of the second dielectric layer 144 to contact the lateral surface of the second chip pad 150. The polishing stop layer 145 may be shaped as a substantially flat planarization layer. The polishing stop layer 145 may have a substantially flat top surface. The top surface of the polishing stop layer 145 may be coplanar with the top surface of the second chip pad 150. The polishing stop layer 145 may include a dielectric material. For example, the polishing stop layer 145 may include silicon nitride (SiN).

[0029] According to some embodiments of the present disclosure, the etching stop layer 143 sandwiched between the first dielectric layer 142 and the second dielectric layer 144 may completely cover the top surface of the first dielectric layer 142 and the bottom surface of the second dielectric layer 144, and may be shaped as a planarization layer. The second dielectric layer 144 and the polishing stop layer 145 formed on the etching stop layer 143 may also be shaped as a planarization layer or may be shaped as a plate, and the protective layer 140 and the second chip pad 150 may have substantially flat and coplanar top surfaces. Therefore, in a direct bonding process in which semiconductor wafers are in direct contact with each other, it is possible to easily bond another semiconductor wafer to the top surface of the semiconductor wafer 100.

[0030] In the following embodiments, components that are the same as those discussed with reference to FIGS. 1, 2A, and 2B are assigned the same reference numerals, and for the sake of convenience of description, they may not be described again or may be omitted. The following mainly describes the differences between the embodiments shown in FIGS. 1, 2A, and 2B and other embodiments described below.

[0031] FIGS. 2C to 2E show enlarged views of section A shown in FIG. 1.

[0032] Referring to FIGS. 1 and 2C, the protective layer 140 of the semiconductor wafer 100 may not include a polishing stop layer 145. In this case, the top surface of the second dielectric layer 144 may be at the same level as the top surface of the second wafer pad 150. The second dielectric layer 144 and the second wafer pad 150 may have substantially flat and coplanar top surfaces.

[0033] As another alternative, referring to FIGS. 1 and 2D, the protective layer 140 of the semiconductor wafer 100 may not include a liner layer 141. In this case, the first dielectric layer 142 may contact the top surface 110b of the base layer 110 and may extend along the top surface 110b of the base layer 110 to contact the circumferential surface of the via 130 and the bottom surface of the second wafer pad 150.

[0034] As another alternative, referring to FIGS. 1 and 2E, the semiconductor wafer 100 may neither include a liner layer 141 nor a polishing stop layer 145. In this case, the first dielectric layer 142 may contact the top surface 110b of the base layer 110 and may extend along the top surface 110b of the base layer 110 to contact the circumferential surface of the via 130 and the bottom surface of the second wafer pad 150. The second dielectric layer 144 and the second wafer pad 150 may have top surfaces located at the same level. The top surface of the second dielectric layer 144 and the top surface of the second wafer pad 150 may be substantially flat and coplanar.

[0035] FIG. 3 shows a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. FIG. 4 shows an enlarged view of section B shown in FIG. 3.

[0036] Referring to FIGS. 3 and 4, the semiconductor package may include a lower structure and an upper structure stacked on each other. In the embodiments shown in FIGS. 3 and 4, the lower structure may include a first semiconductor wafer 101, and the upper structure may include a second semiconductor wafer 102. For example, the semiconductor package may include the first semiconductor wafer 101 and the second semiconductor wafer 102 joined to each other. Each of the first semiconductor wafer 101 and the second semiconductor wafer 102 may be the semiconductor wafer 100 discussed with reference to FIGS. 1 and 2A to 2E.

[0037] The second semiconductor wafer 102 may be mounted on the first semiconductor wafer 101. For example, the second semiconductor wafer 102 may be disposed on the first semiconductor wafer 101. The front surface of the second semiconductor wafer 102 may face the back surface of the first semiconductor wafer 101. The first semiconductor wafer 101 and the second semiconductor wafer 102 may be vertically aligned with each other. For example, the second wafer contact pad 150 of the first semiconductor wafer 101 may be vertically aligned with the first wafer contact pad 125 of the second semiconductor wafer 102. The front surface of the second semiconductor wafer 102 may be in contact with the back surface of the first semiconductor wafer 101.

[0038] At the interface between the first semiconductor wafer 101 and the second semiconductor wafer 102, the protective layer 140 of the first semiconductor wafer 101 may be in contact with the dielectric pattern 122 of the circuit layer 120 of the second semiconductor wafer 102. In such a case, the dielectric pattern 122 and the protective layer 140 may constitute a hybrid bonding between metals (e.g., copper (Cu)). In this description, the term "hybrid bonding" may mean a bonding in which two components of the same type are fused at the interface therebetween. The dielectric pattern 122 and the protective layer 140 joined to each other may have a continuous structure, and an invisible interface may exist between the dielectric pattern 122 and the protective layer 140. For example, the dielectric pattern 122 and the protective layer 140 may be formed of the same material, and thus there may be no interface between the dielectric pattern 122 and the protective layer 140. The dielectric pattern 122 and the protective layer 140 may be provided as one component. For example, the dielectric pattern 122 and the protective layer 140 may be combined to form a single unitary body. However, the embodiments of the present disclosure are not limited thereto. The dielectric pattern 122 and the protective layer 140 may be formed of different materials from each other. The dielectric pattern 122 and the protective layer 140 may not have a continuous structure, and a visible interface may exist between the dielectric pattern 122 and the protective layer 140.

[0039] According to some embodiments of the present disclosure, the protective layers 140 of the first semiconductor wafer 101 and the second semiconductor wafer 102 may have a flat shape. For example, the protective layer 140 of the first semiconductor wafer 101 may contact the second semiconductor wafer 102 and may have a flat shape. A flat bonding interface may exist between the protective layer 140 of the first semiconductor wafer 101 and the dielectric pattern 122 of the second semiconductor wafer 102, and there may be no gap between the dielectric pattern 122 and the protective layer 140. Therefore, a semiconductor package with improved structural stability and good bonding between the dielectric pattern 122 and the protective layer 140 or between the first semiconductor wafer 101 and the second semiconductor wafer 102 can be provided.

[0040] The first semiconductor wafer 101 may be connected to the second semiconductor wafer 102. For example, the first semiconductor wafer 101 and the second semiconductor wafer 102 may contact each other. On the interface between the first semiconductor wafer 101 and the second semiconductor wafer 102, the second wafer contact pad 150 of the first semiconductor wafer 101 may be bonded to the first wafer contact pad 125 of the second semiconductor wafer 102. In such a case, the second wafer contact pad 150 and the first wafer contact pad 125 may form an intermetallic hybrid bonding. For example, the second wafer contact pad 150 and the first wafer contact pad 125 bonded to each other may have a continuous structure, and an invisible interface may exist between the second wafer contact pad 150 and the first wafer contact pad 125. The second wafer contact pad 150 and the first wafer contact pad 125 may be formed of the same material, and thus no interface may be provided between the second wafer contact pad 150 and the first wafer contact pad 125. The second wafer contact pad 150 and the first wafer contact pad 125 may be provided as a component. For example, the second wafer contact pad 150 and the first wafer contact pad 125 may be bonded to form a single entity.

[0041] According to some embodiments of the present disclosure, a flat bonding interface may exist between the second wafer contact pad 150 of the first semiconductor wafer 101 and the first wafer contact pad 125 of the second semiconductor wafer 102, and there may be no gap between the second wafer contact pad 150 and the first wafer contact pad 125. Therefore, a semiconductor package with good bonding between the second wafer contact pad 150 and the first wafer contact pad 125 and good electrical connection between the first semiconductor wafer 101 and the second semiconductor wafer 102 can be provided.

[0042] FIG. 5 shows a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

[0043] Referring to FIG. 5, a base substrate 200 may be provided. The base substrate 200 may include an integrated circuit. For example, the base substrate 200 may be a semiconductor wafer including electronic components such as transistors. For example, the base substrate 200 may be a wafer-level die formed of a semiconductor such as silicon (Si). FIG. 5 shows the base substrate 200 as a semiconductor wafer, but the embodiments of the present disclosure are not limited thereto. According to some embodiments of the present disclosure, the base substrate 200 may be a substrate such as a printed circuit board (PCB) that does not include electronic components such as transistors. The silicon wafer may have a thickness smaller than that of the printed circuit board (PCB). Examples in which the base substrate 200 is a base semiconductor wafer will be described below.

[0044] The base substrate 200 (e.g., the base semiconductor wafer) may include a base semiconductor substrate 210, a base circuit layer 220, and base vias 230.

[0045] The base semiconductor substrate 210 may include semiconductor material. For example, the base semiconductor substrate 210 may be a single-crystal silicon (Si) substrate. Integrated elements or integrated circuits may be formed on a lower portion of the base semiconductor substrate 210. For example, a wiring pattern, integrated elements (such as transistors), or passive elements (such as resistors, capacitors, or inductors) may be provided on a bottom surface of the base semiconductor substrate 210. The bottom surface of the base semiconductor substrate 210 may be the front surface of the base semiconductor substrate 210, and the top surface of the base semiconductor substrate 210 may be the back surface of the base semiconductor substrate 210. For example, the base substrate 200 may be a logic chip.

[0046] The base circuit layer 220 may be provided on the bottom surface of the base semiconductor substrate 210. The base circuit layer 220 may be electrically connected to the integrated elements or integrated circuits formed in the base semiconductor substrate 210. For example, the base circuit layer 220 may include a dielectric pattern 222 and a wiring pattern 224 provided in the dielectric pattern 222, and the wiring pattern 224 may be coupled to the integrated elements or integrated circuits formed in the base semiconductor substrate 210. A portion of the wiring pattern 224 may be exposed at the bottom surface of the base circuit layer 220, and the exposed portion of the wiring pattern 224 may be an external pad 225 of the base substrate 200. A plurality of external pads 225 may be provided. According to some embodiments, the base circuit layer 220 may not be provided.

[0047] The base through-hole 230 can vertically penetrate the base semiconductor substrate 210. For example, the base through-hole 230 can be exposed at the top surface of the base semiconductor substrate 210. A dielectric layer can be provided to surround the base through-hole 230. For example, the dielectric layer can include at least one selected from silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and low-k dielectric.

[0048] External terminals 260 can be provided on the bottom surface of the base substrate 200. The external terminals 260 can be disposed on the external pads 225. The external terminals 260 can be electrically connected to the base circuit layer 220 and the base through-hole 230. The external terminals 260 can be an alloy including at least one selected from tin (Sn), silver (Ag), copper (Cu), nickel (Ni), bismuth (Bi), indium (In), antimony (Sb), and cerium (Ce).

[0049] The base substrate 200 can further include mounting pads 250 and a base protective layer 240.

[0050] The mounting pads 250 can be provided on the top surface of the base semiconductor substrate 210. The mounting pads 250 can be disposed on the base through-hole 230 and can be coupled to the base through-hole 230. The mounting pads 250 can be coupled to the base circuit layer 220 through the base through-hole 230.

[0051] A base protective layer 240 can be provided on the top surface of the base semiconductor substrate 210. The base protective layer 240 surrounds the mounting pads 250 and the portion of the base through-hole 230 protruding from the top surface of the base semiconductor substrate 210. The base protective layer 240 can expose the mounting pads 250. The top surface of the base protective layer 240 can be coplanar with the top surface of the mounting pads 250. The base protective layer 240 can be substantially the same as or similar to the protective layer 140 discussed with reference to FIGS. 1 and 2A to 2E. For example, the base protective layer 240 can include a pad layer, a first dielectric layer, an etching stop layer, a second dielectric layer, and a polishing stop layer located on the base semiconductor substrate 210. However, the embodiments of the present disclosure are not limited thereto.

[0052] A chip stack may be disposed on a base substrate 200. The chip stack may include a plurality of semiconductor chips 100 and 103. The semiconductor chips 100 and 103 may be of the same type. For example, each of the semiconductor chips 100 and 103 may be the same as the semiconductor chip 100 discussed with reference to FIGS. 1 and 2A to 2E. Among the semiconductor chips 100 and 103, the uppermost semiconductor chip 103 may have a structure similar to that of the other semiconductor chips 100, but may not include any of the vias 130, the protective layer 140, and the second chip pads 150. The uppermost semiconductor chip 103 may have a thickness greater than that of the other semiconductor chips 100. The semiconductor chips 100 and 103 may be memory chips. The semiconductor chips 100 and 103 may be stacked on the base substrate 200 in sequence. In this embodiment, four semiconductor chips (for example, three semiconductor chips 100 and one semiconductor chip 103) are stacked on the base substrate 200, but two or four or more semiconductor chips may also be provided. The semiconductor chips 100 and 103 may each have a width greater than the width of the base substrate 200. The semiconductor chips 100 and 103 may be aligned perpendicular to each other. The mounting or bonding between adjacent semiconductor chips 100 and 103 may be the same as or similar to the mounting or bonding discussed with reference to FIGS. 3 and 4.

[0053] The chip stack may be mounted on the base substrate 200. The first chip pad 125 of the lowermost semiconductor chip 100 among the semiconductor chips 100 may be aligned perpendicular to the mounting pad 250 of the base substrate 200. The base substrate 200 and the lowermost semiconductor chip 100 among the semiconductor chips 100 may be in contact with each other. At the interface between the base substrate 200 and the lowermost semiconductor chip 100 among the semiconductor chips 100, the mounting pad 250 of the base substrate 200 may be bonded to the first chip pad 125 of the lowermost semiconductor chip 100 among the semiconductor chips 100. In this case, the mounting pad 250 and the first chip pad 125 may form an intermetallic hybrid bond. Alternatively, different from what is shown, the chip stack may be mounted on the base substrate 200 in a flip-chip manner. For example, connection terminals such as solder balls may be provided between the mounting pad 250 of the base substrate 200 and the first chip pad 125 of the lowermost semiconductor chip 100 among the semiconductor chips 100.

[0054] FIG. 5 illustrates the effective surface of the lowermost semiconductor wafer 100 in the semiconductor wafer 100 bonded to the non-effective surface of the base substrate 200, but the embodiments of the present disclosure are not limited thereto. According to some embodiments, the effective surface of the base substrate 200 may face the effective surface of the lowermost semiconductor wafer 100 in the semiconductor wafer 100. In such a case, the base circuit layer 220 of the base substrate 200 may be in contact with the circuit layer 120 of the lowermost semiconductor wafer 100 in the semiconductor wafer 100, and the external pads 225 of the base circuit layer 220 may be bonded to the first wafer pads 125 of the circuit layer 120. The external terminals 260 may be disposed on the mounting pads 250 of the base substrate 200, wherein the mounting pads 250 are oriented downward. The following description will focus on the embodiment shown in FIG. 5.

[0055] A molding layer 300 may be disposed on the base substrate 200. The molding layer 300 may cover the top surface of the base substrate 200. The molding layer 300 may surround the wafer stack. For example, the molding layer 300 may cover the lateral surfaces of the semiconductor wafers 100 and 103. The top surface of the molding layer 300 may be coplanar with the top surface of the uppermost semiconductor wafer 103. The molding layer 300 may protect the wafer stack. The molding layer 300 may include a dielectric material. For example, the molding layer 300 may include an epoxy molding compound (EMC). Different from that shown, the molding layer 300 may be formed to cover the wafer stack. For example, the molding layer 300 may cover the back surface of the uppermost semiconductor wafer 103.

[0056] FIG. 6 shows a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. FIG. 7 shows an enlarged view of section C shown in FIG. 6.

[0057] Referring to FIGS. 6 and 7, the semiconductor package may include at least one semiconductor wafer 104. The semiconductor wafer 104 may include a base layer 110, a circuit layer 120, a protection layer 140, and vias 130, the circuit layer 120 being disposed on the bottom surface 110a (e.g., the front surface) of the base layer 110, the protection layer 140 being disposed on the top surface 110b (e.g., the back surface) of the base layer 110, and the vias 130 penetrating the base layer 110.

[0058] Different from the embodiments shown in FIGS. 1 and 2A to 2E, the protection layer 140 of the semiconductor wafer 104 may extend to one side of the base layer 110. The following description will focus on the protection layer 140 of the semiconductor wafer 104.

[0059] A first dielectric layer 142 may be disposed on the top surface 110b of the base layer 110. The first dielectric layer 142 may cover the top surface 110b of the base layer 110 and may extend onto a side of the base layer 110 to cover the lateral surface of the base layer 110 and the lateral surface of the circuit layer 120. The first dielectric layer 142 may surround the via 130 on the top surface 110b of the base layer 110. The top surface of the first dielectric layer 142 may be at a level higher than the level of the top surface of the via 130. The contact interface between the via 130 and the second chip pad 150 may be closer to the base layer 110 than the top surface of the first dielectric layer 142.

[0060] A cushion layer 141 may be sandwiched between the first dielectric layer 142 and the base layer 110. For example, the cushion layer 141 may be sandwiched between the first dielectric layer 142 and the top surface 110b of the base layer 110, between the first dielectric layer 142 and the lateral surface of the base layer 110, and between the first dielectric layer 142 and the lateral surface of the circuit layer 120. The cushion layer 141 may extend from the top surface 110b of the base layer 110 toward the space between the first dielectric layer 142 and the circumferential surface of the via 130, and thus one end of the cushion layer 141 may contact the bottom surface of the second chip pad 150. Additionally, the cushion layer 141 may extend onto the bottom surface of the first dielectric layer 142. However, the embodiments of the present disclosure are not limited thereto, and the cushion layer 141 may not cover the bottom surface of the first dielectric layer 142.

[0061] An etch stop layer 143 may be disposed on the first dielectric layer 142. The etch stop layer 143 may completely cover the top surface of the first dielectric layer 142. The etch stop layer 143 may extend along the top surface of the first dielectric layer 142 to contact the lateral surface of the second chip pad 150. The bottom surface of the etch stop layer 143 may be at a level higher than the level of the bottom surface of the second chip pad 150. As an alternative, the top surface of the first dielectric layer 142 and the bottom surface of the etch stop layer 143 may be at the same level as the level of the bottom surface of the second chip pad 150 and the level of the contact interface between the via 130 and the second chip pad 150. The etch stop layer 143 may be shaped as a substantially flat planarization layer.

[0062] A second dielectric layer 144 may be disposed on the etch stop layer 143. The second dielectric layer 144 may cover the top surface of the etch stop layer 143. The second dielectric layer 144 may extend along the top surface of the etch stop layer 143 to contact the lateral surface of the second chip pad 150. The etch stop layer 143 may separate the second dielectric layer 144 from the first dielectric layer 142. The second dielectric layer 144 may have a uniform thickness. The second dielectric layer 144 may have a plate shape, and the top surface of the second dielectric layer 144 may be substantially flat. The top surface of the second dielectric layer 144 may be at a level lower than the level of the top surface of the second chip pad 150.

[0063] A polish stop layer 145 may be disposed on the second dielectric layer 144. The polish stop layer 145 may cover the top surface of the second dielectric layer 144. The polish stop layer 145 may extend along the top surface of the second dielectric layer 144 to contact the lateral surface of the second chip pad 150. The polish stop layer 145 may be shaped as a substantially flat planarization layer. The polish stop layer 145 may have a substantially flat top surface. The top surface of the polish stop layer 145 may be coplanar with the top surface of the second chip pad 150.

[0064] According to some embodiments of the present disclosure, the protective layer 140 extending to the lateral surface of the base layer 110 may be used to adjust the width of the semiconductor wafer 104. Accordingly, the semiconductor wafer 104 can be easily bonded to another semiconductor wafer or electronic component each having a size different from the size of the semiconductor wafer 104.

[0065] FIG. 8 shows a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

[0066] Referring to FIG. 8, a third semiconductor wafer 104 can be provided. The third semiconductor wafer 104 can be substantially the same as or similar to the semiconductor wafer 104 discussed with respect to FIGS. 6 and 7. Additionally, the third semiconductor wafer 104 can further include conductive posts 147. On one side of the base layer 110, the conductive posts 147 can vertically penetrate the protective layer 140. For example, one end of the conductive post 147 can penetrate the cushion layer 141 to be exposed at a surface of the cushion layer 141. The other end of the conductive post 147 can vertically penetrate the first dielectric layer 142. A plurality of conductive posts 147 can be provided. The conductive posts 147 can include a metal such as copper (Cu) or tungsten (W), for example. According to an embodiment, the conductive posts 147 can further include a seed layer or a barrier layer, each of the seed layer or the barrier layer surrounding the circumferential surface of the conductive post 147. One of the plurality of second chip pads 150 in the third semiconductor wafer 104 can be coupled to the conductive post 147. For example, the one of the second chip pads 150 can vertically penetrate the polishing stop layer 145, the second dielectric layer 144, and the etching stop layer 143, thereby being coupled to the conductive post 147.

[0067] A fourth semiconductor wafer 400 can be disposed on the third semiconductor wafer 104. The fourth semiconductor wafer 400 can be located on the active surface of the third semiconductor wafer 104. For example, the fourth semiconductor wafer 400 can be located on the circuit layer 120 of the third semiconductor wafer 104 and can be located on the protective layer 140 on one side of the circuit layer 120. The fourth semiconductor wafer 400 can include a semiconductor substrate 410 and a circuit layer 420.

[0068] The semiconductor substrate 410 can include a semiconductor material. For example, the semiconductor substrate 410 can be a single crystal silicon (Si) substrate. Integrated elements or integrated circuits can be formed on a lower portion of the semiconductor substrate 410. For example, wiring patterns, integrated elements (such as transistors), or passive elements (such as resistors, capacitors, or inductors) can be disposed on the bottom surface of the semiconductor substrate 410. The bottom surface of the semiconductor substrate 410 can be the front surface of the semiconductor substrate 410, and the top surface of the semiconductor substrate 410 can be the back surface of the semiconductor substrate 410.

[0069] The circuit layer 420 may be disposed on the bottom surface of the semiconductor substrate 410. The circuit layer 420 may be electrically connected to the integrated components or integrated circuits formed in the semiconductor substrate 410. For example, the circuit layer 420 may have a dielectric pattern 422 and a wiring pattern 424 disposed in the dielectric pattern 422, and the wiring pattern 424 may be coupled to the integrated components or integrated circuits formed in the semiconductor substrate 410. Portions of the wiring pattern 424 may be exposed on the bottom surface of the circuit layer 420, and the exposed portions of the wiring pattern 424 may be the third chip pads 425 of the fourth semiconductor chip 400. A plurality of the third chip pads 425 may be provided. The circuit layer 420 may be disposed on the bottom surface of the fourth semiconductor chip 400, and the bottom surface of the fourth semiconductor chip 400 may be the effective surface of the fourth semiconductor chip 400.

[0070] The fourth semiconductor chip 400 may be mounted on the third semiconductor chip 104. For example, the fourth semiconductor chip 400 may be disposed on the third semiconductor chip 104. The front surface of the fourth semiconductor chip 400 may face the front surface of the third semiconductor chip 104. The third semiconductor chip 104 and the fourth semiconductor chip 400 may be vertically aligned with each other. For example, the conductive pillars 147 and the first chip pads 125 of the third semiconductor chip 104 may be vertically aligned with the third chip pads 425 of the fourth semiconductor chip 400. The front surface of the third semiconductor chip 104 may be in contact with the front surface of the fourth semiconductor chip 400.

[0071] The third semiconductor chip 104 may be connected to the fourth semiconductor chip 400. For example, the third semiconductor chip 104 and the fourth semiconductor chip 400 may be in contact with each other. At the interface between the third semiconductor chip 104 and the fourth semiconductor chip 400, the conductive pillars 147 and the first chip pads 125 of the third semiconductor chip 104 may be bonded to the third chip pads 425 of the fourth semiconductor chip 400. In this case, an intermetallic hybrid bond may be achieved between the first chip pad 125 and the third chip pad 425 and between the conductive pillar 147 and the third chip pad 425. For example, the mutually bonded first chip pad 125 and the third chip pad 425 may have a continuous structure, and the mutually bonded conductive pillar 147 and the third chip pad 425 may have a continuous structure. An invisible interface may exist between the first chip pad 125 and the third chip pad 425 and between the conductive pillar 147 and the third chip pad 425.

[0072] A redistribution line substrate 500 may be disposed below the third semiconductor chip 104. The redistribution line substrate 500 may be in direct contact with the bottom surface of the third semiconductor chip 104 or the bottom surface of the protective layer 140 of the third semiconductor chip 104 and the bottom surface of the second chip pad 150.

[0073] The redistribution line substrate 500 may include one or more substrate wiring layers stacked on each other. Each of the substrate wiring layers may include a substrate dielectric pattern 510 and a substrate wiring pattern 520 located in the substrate dielectric pattern 510. When there are multiple substrate wiring layers, the substrate wiring pattern 520 of one of the substrate wiring layers may be electrically connected to the substrate wiring pattern 520 of an adjacent substrate wiring layer.

[0074] The substrate dielectric pattern 510 may include a dielectric polymer or a photo-imageable dielectric (PID). For example, the photo-imageable dielectric may include at least one selected from photosensitive polyimide (PI), polybenzoxazole (PBO), phenolic polymer, and benzocyclobutene polymer. As another option, the substrate dielectric pattern 510 may include a dielectric material. For example, the substrate dielectric pattern 510 may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or a dielectric polymer.

[0075] The substrate wiring pattern 520 can be disposed in the substrate dielectric pattern 510. The substrate wiring pattern 520 can be disposed on the bottom surface of the substrate dielectric pattern 510. The substrate wiring pattern 520 can horizontally extend on the bottom surface of the substrate dielectric pattern 510. The substrate wiring pattern 520 can protrude from the bottom surface of the substrate dielectric pattern 510. On the bottom surface of the substrate dielectric pattern 510, the substrate wiring pattern 520 can be covered by another substrate dielectric pattern 510 disposed below the substrate wiring pattern 520. The substrate wiring pattern 520 disposed in the lowermost substrate wiring layer can be a redistribution pad for mounting the semiconductor package on an external substrate, a motherboard, an external device, etc. As discussed above, the substrate wiring pattern 520 can be a line portion or a pad portion of the substrate wiring layer. In such a structure, the substrate wiring pattern 520 can be a component for horizontal redistribution lines in the substrate wiring layer. For example, as shown in FIG. 8, the substrate wiring pattern 520 can connect the redistribution pad to the second chip pad 150 of the third semiconductor chip 104. For example, the conductive pillar 147 can correspond to a vertical connector for electrically connecting the redistribution substrate 500 to the fourth semiconductor chip 400. FIG. 8 illustrates an exemplary electrical connection of the substrate wiring pattern 520, and the shape and arrangement of the substrate wiring pattern 520 are not limited to the shape and arrangement shown in FIG. 8. The substrate wiring pattern 520 can include a conductive material. For example, the substrate wiring pattern 520 can include copper (Cu).

[0076] The substrate wiring pattern 520 can have an embedded structure. For example, the substrate wiring pattern 520 can have a head portion and a tail portion integrally connected to each other. The head portion and the tail portion of the substrate wiring pattern 520 can have an inverse T-shape cross-section.

[0077] External terminals 530 can be disposed on the redistribution pads of the redistribution substrate 500. The external terminals 530 can include solder balls or solder bumps, and based on the type and arrangement of the external terminals 530, the semiconductor package can be provided in the form of one of a ball grid array (BGA) type, a fine ball-grid array (FBGA) type, and a land grid array (LGA) type.

[0078] FIG. 9A, FIG. 10A, FIG. 11A, FIG. 11A, FIG. 12A, FIG. 13A, FIG. 14A, and FIG. 15A illustrate cross-sectional views of a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. FIG. 9B, FIG. 10B, FIG. 11B, FIG. 12B, FIG. 13B, FIG. 14B, and FIG. 15B respectively illustrate enlarged views of sections D1, D2, D3, D4, D5, D6, and D7 shown in FIG. 9A, FIG. 10A, FIG. 11A, FIG. 11A, FIG. 12A, FIG. 13A, FIG. 14A, and FIG. 15A.

[0079] Referring to FIGS. 9A and 9B, a semiconductor wafer can be formed on a semiconductor substrate by a typical process. For example, an integrated circuit such as a transistor can be formed on an active surface of the semiconductor substrate. The semiconductor substrate can correspond to a base layer 110 of the semiconductor wafer. A through hole can be formed to extend from the active surface of the base layer 110 (e.g., the active surface of the semiconductor substrate) into the base layer 110, and then the through hole can be filled with a conductive layer 132 formed of a conductive material to form a via 130. The via 130 may not completely penetrate the base layer 110. For example, the via 130 can extend from the active surface of the base layer 110 but may not reach the non-active surface of the base layer 110. Before filling the through hole with the conductive layer 132, a via barrier layer 134 can be formed. The via barrier layer 134 can be formed to cover the inner lateral surface and the bottom surface of the through hole, and also cover the circumferential surface and the top surface of the via 130. A dielectric pattern 122 and a wiring pattern 124 can be formed on the active surface of the base layer 110, and thus a circuit layer 120 can be formed.

[0080] A carrier substrate 900 can be provided. The carrier substrate 900 can be a dielectric substrate including glass or polymer, or can be a conductive substrate including metal. According to an embodiment, an adhesive member can be disposed on the top surface of the carrier substrate 900. For example, the adhesive member can include a glue tape. According to some embodiments, a base wafer can be provided to replace the carrier substrate 900. In such a case, the circuit layer 120 of the semiconductor wafer can be coupled to a wafer pad of the base wafer.

[0081] The base layer 110 can be disposed on the carrier substrate 900. For example, the base layer 110 can be bonded to the carrier substrate 900 such that the circuit layer 120 can contact the carrier substrate 900. Thus, the non-active surface of the base layer 110 can be oriented in an upward direction from the carrier substrate 900.

[0082] Referring to FIGS. 10A and 10B, a portion of the base layer 110 can be removed. For example, the upper portion of the base layer 110 can be etched. The removal of the upper portion of the base layer 110 can be carried out until the top surface of the via 130 is exposed. The top surface 110b of the base layer 110 can be at a level different from the level of the top surface of the via 130. For example, in the process of removing the upper portion of the base layer 110, the base layer 110 formed of silicon can be etched or ground, and the via 130 formed of metal can be neither etched nor ground. Therefore, after removing the upper portion of the base layer 110, the via 130 can protrude from the top surface 110b of the base layer 110.

[0083] Referring to FIGS. 11A and 11B, a liner layer 141 can be formed on the base layer 110. The liner layer 141 can be formed to conformally cover the base layer 110 and the via 130 protruding from the top surface 110b of the base layer 110. For example, the liner layer 141 can conformally cover the top surface 110b of the base layer 110, and can also conformally cover the circumferential surface and the top surface of the via 130.

[0084] A first dielectric layer 142 can be formed on the liner layer 141. For example, a chemical vapor deposition (CVD) process can be used to form the first dielectric layer 142. The first dielectric layer 142 can completely bury the via 130 while covering the top surface 110b of the base layer 110. Therefore, the first dielectric layer 142 can completely cover the liner layer 141.

[0085] Referring to FIGS. 12A and 12B, a thinning process can be performed on the first dielectric layer 142. For example, a grinding process or a chemical mechanical polishing (CMP) process can be performed on the top surface of the first dielectric layer 142. The thinning process can be carried out until the top surface of the via 130 is exposed. For example, the thinning process can remove the portion of the first dielectric layer 142 located on the top surface of the conductive layer 132 of the via 130, the portion of the liner layer 141 located on the top surface of the conductive layer 132 of the via 130, and the portion of the via barrier layer 134 located on the top surface of the conductive layer 132 of the via 130. Therefore, the top surface of the conductive layer 132 of the via 130 can be exposed. After the thinning process, the top surface of the conductive layer 132, the top end of the via barrier layer 134, the top end of the liner layer 141, and the top surface of the first dielectric layer 142 can be substantially flat and coplanar with each other.

[0086] Referring to FIGS. 13A and 13B, an etch stop layer 143 may be formed on the base layer 110. The etch stop layer 143 may be formed to cover the first dielectric layer 142. For example, the etch stop layer 143 may conformally cover the top surface of the conductive layer 132, the top end of the via barrier layer 134, the top end of the pad layer 141, and the top surface of the first dielectric layer 142. According to the shapes of the top surface of the conductive layer 132, the top end of the via barrier layer 134, the top end of the pad layer 141, and the top surface of the first dielectric layer 142, the etch stop layer 143 may be shaped as a substantially flat planarization layer.

[0087] According to some embodiments of the present disclosure, the etch stop layer 143 may cover the entirety composed of the top surface of the via 130 formed on the base layer 110, the top surface of the pad layer 141 formed on the base layer 110, and the top surface of the first dielectric layer 142 formed on the base layer 110, and the top surface of the etch stop layer 143 may be flat. Therefore, other material layers (e.g., the second dielectric layer 144 and the polish stop layer 145) deposited on the etch stop layer 143 may each have a flat shape, and thus, a flat top surface may be given to the second dielectric layer 144 or the polish stop layer 145, each of the flat top surfaces corresponding to the non-active surface of the semiconductor wafer. When another semiconductor wafer (or wiring substrate) is directly bonded to the non-active surface of the semiconductor wafer, there may be no gap or void between the semiconductor wafers, and easy bonding may be achieved between the semiconductor wafers. In summary, a semiconductor wafer having improved structural stability and improved electrical connection properties may be provided, and a semiconductor package including the semiconductor wafer may also be provided.

[0088] As another alternative, in a comparative example, when the etch stop layer 143 exposes a portion of the first dielectric layer 142, there may be a step difference between the top surface of the etch stop layer 143 and the top surface of the first dielectric layer 142, and other material layers (e.g., the second dielectric layer 144 and the polish stop layer 145) formed on the etch stop layer 143 and the first dielectric layer 142 may not be given a flat shape. In such a case, when another semiconductor wafer is directly bonded to the non-active surface of the semiconductor wafer, there may be a gap or void between the semiconductor wafers, and the semiconductor wafer may experience a lamination issue or an electrical short.

[0089] A second dielectric layer 144 may be formed on the etch stop layer 143. For example, the second dielectric layer 144 may be formed using a chemical vapor deposition (CVD) process. Since the etch stop layer 143 covers the entirety composed of the top surface of the via 130, the top surface of the liner layer 141, and the top surface of the first dielectric layer 142, the etch stop layer 143 may separate the second dielectric layer 144 from the first dielectric layer 142. According to the shape of the top surface of the etch stop layer 143, the second dielectric layer 144 may be shaped into a substantially flat planarization layer.

[0090] A polish stop layer 145 may be formed on the second dielectric layer 144. The polish stop layer 145 may be formed to cover the second dielectric layer 144. According to the shape of the top surface of the second dielectric layer 144, the polish stop layer 145 may be shaped into a substantially flat planarization layer.

[0091] Referring to FIGS. 14A and 14B, a patterning process may be performed on the protective layer 140. In the patterning process, a recess RS may be formed in the protective layer 140 to expose the via 130. The patterning process may be performed until the bottom surface of the recess RS is at the same level as or lower than the bottom surface of the etch stop layer 143. The lateral surfaces of each of the etch stop layer 143, the second dielectric layer 144, and the polish stop layer 145 may be exposed at the inner wall of the recess RS.

[0092] A conductive layer 152 may be formed on the protective layer 140. The conductive layer 152 may fill the recess RS while covering the protective layer 140. For example, a seed layer may be formed on the protective layer 140 to conformally cover the top surface of the protective layer 140 and the inside of the recess RS, and then the seed layer may be used as a seed to perform a plating process for forming the conductive layer 152. The conductive layer 152 may include a conductive material such as copper (Cu).

[0093] Referring to FIGS. 15A and 15B, a planarization process may be performed on the conductive layer 152. The planarization process may include a chemical mechanical polishing (CMP) process. The planarization process may be performed until the top surface of the protective layer 140 and the top surface of the polish stop layer 145 are exposed. In the planarization process, the conductive layer 152 may be divided to form the second chip pad 150. After the planarization process, the top surface of the protective layer 140 may be coplanar with the top surface of the second chip pad 150. The top surface of the protective layer 140 and the top surface of the second chip pad 150 may be substantially flat.

[0094] Subsequently, the carrier substrate 900 can be removed.

[0095] FIGS. 16A, 17A, 18A, 19A, 20A, 21A, 22A, and 23A illustrate cross-sectional views of a method of manufacturing a semiconductor package according to some embodiments of the present disclosure. FIGS. 16B, 17B, 18B, 19B, 20B, 21B, 22B, and 23B respectively illustrate enlarged views of sections E1, E2, E3, E4, E5, E6, E7, and E8 shown in FIGS. 16A, 17A, 18A, 19A, 20A, 21A, 22A, and 23A.

[0096] Referring to FIGS. 16A and 16B, as discussed with reference to FIGS. 9A and 9B, the carrier substrate 900 can be provided. According to some embodiments, a base wafer can be provided to replace the carrier substrate 900. In such a case, the circuit layer 120 and the conductive pillars 147 of the semiconductor wafer described below can be coupled to the wafer pads of the base wafer.

[0097] An integrated circuit can be formed on the semiconductor substrate to form a base layer 110, vias 130 can be formed in the base layer 110, and a circuit layer 120 can be formed on the bottom surface 110a (e.g., the active surface) of the base layer 110.

[0098] The base layer 110 can be disposed on the carrier substrate 900. For example, the base layer 110 can be bonded to the carrier substrate 900 such that the circuit layer 120 can contact the carrier substrate 900. The width of the carrier substrate 900 can be greater than the width of the base layer 110. A portion of the top surface of the carrier substrate 900 may not be covered by the base layer 110.

[0099] Referring to FIGS. 17A and 17B, a portion of the base layer 110 can be removed. For example, the upper portion of the base layer 110 can be etched. After removing the upper portion of the base layer 110, the vias 130 can protrude from the top surface 110b of the base layer 110.

[0100] Referring to FIGS. 18A and 18B, a liner layer 141 can be formed on the carrier substrate 900. The liner layer 141 can be formed to conformally cover the base layer 110 and the vias 130 protruding from the top surface 110b of the base layer 110. The liner layer 141 can also be formed on one side of the base layer 110. For example, the liner layer 141 can cover the lateral surface of the base layer 110 and can cover the top surface of the carrier substrate 900 on the one side of the base layer 110.

[0101] A first dielectric layer 142 may be formed on the carrier substrate 900. On the carrier substrate 900, the first dielectric layer 142 may surround and completely bury the base layer 110. Accordingly, the first dielectric layer 142 may completely cover the liner layer 141.

[0102] Referring to FIGS. 19A and 19B, a thinning process may be performed on the first dielectric layer 142. For example, a grinding process or a chemical mechanical polishing (CMP) process may be performed on the top surface of the first dielectric layer 142. The thinning process may be performed until the top surface of the via 130 is exposed. After the thinning process, the top surface of the conductive layer 132, the top ends of the via barrier layer 134, the top end of the liner layer 141, and the top surface of the first dielectric layer 142 may be substantially flat and coplanar with each other.

[0103] FIGS. 18A, 18B, 19A, and 19B illustrate a single-layered liner layer 141 being provided, but embodiments of the present disclosure are not limited thereto. According to some embodiments, before forming the first dielectric layer 142 that completely buries the via 130, multiple layers may be formed to conformally cover the via 130 and the top surface 110b of the base layer 110. The multiple layers may include a liner layer, a dielectric layer, and a polish stop layer stacked in sequence. In such a configuration, the thickness of the dielectric layer may be less than the protrusion distance of the via 130. Thereafter, a thinning process may be performed on the multiple layers. The thinning process may be performed on the surface of the polish stop layer on one side of the via 130, and the top surface of the via 130 may be exposed. In the thinning process, the first dielectric layer 142 may be removed. The remaining portion of the polish stop layer may be removed by a subsequent process. Accordingly, a liner layer and a dielectric layer surrounding the via 130 may be formed. The liner layer remaining after the thinning process may be used as the liner layer 141 discussed with respect to FIGS. 18A, 18B, 19A, and 19B, and the dielectric layer remaining after the thinning process may be used as the first dielectric layer 142 discussed with respect to FIGS. 18A, 18B, 19A, and 19B. The following description will focus on the embodiments of FIGS. 18A, 18B, 19A, and 19B.

[0104] Referring to FIGS. 20A and 20B, conductive pillars 147 can be formed on one side of the base layer 110. For example, on the said one side of the base layer 110, through holes can be formed to vertically penetrate the first dielectric layer 142 and the cushion layer 141, thereby exposing the carrier substrate 900, and then the through holes can be filled with a conductive material to form the conductive pillars 147. The process for forming the conductive pillars 147 can include an electroplating process. In some embodiments, the conductive pillars 147 may not be formed. The following description will refer to the embodiments shown in FIGS. 19A and 19B.

[0105] Referring to FIGS. 21A and 21B, an etch stop layer 143 can be formed on the carrier substrate 900. The etch stop layer 143 can conformally cover the top surface of the conductive layer 132, the top ends of the via barrier layers 134, the top end of the cushion layer 141, and the top surface of the first dielectric layer 142. The etch stop layer 143 can be shaped as a substantially flat planarization layer.

[0106] A second dielectric layer 144 can be formed on the etch stop layer 143. The etch stop layer 143 can separate the second dielectric layer 144 from the first dielectric layer 142. The second dielectric layer 144 can be shaped as a substantially flat planarization layer.

[0107] A polishing stop layer 145 can be formed on the second dielectric layer 144. The polishing stop layer 145 can be formed to cover the second dielectric layer 144. The polishing stop layer 145 can be shaped as a substantially flat planarization layer.

[0108] According to some embodiments of the present disclosure, the protective layer 140 can be formed to surround the base layer 110 and the circuit layer 120. Therefore, regardless of the size of the base layer 110 formed on the semiconductor substrate, the size of the semiconductor wafer can be determined based on the size of the protective layer 140. Semiconductor wafers with various sizes can be formed, and semiconductor packages in which different types of semiconductor wafers are bonded to each other can be easily manufactured.

[0109] Referring to FIGS. 22A and 22B, a patterning process can be performed on the protective layer 140. In the patterning process, a recess RS can be formed on the protective layer 140 to expose the through holes 130. The patterning process can be performed until the bottom surface of the recess RS is at the same level as or lower than the bottom surface of the etch stop layer 143.

[0110] A conductive layer 152 may be formed on the protective layer 140. The conductive layer 152 may fill the recess RS while covering the protective layer 140.

[0111] Referring to FIGS. 23A and 23B, a planarization process may be performed on the conductive layer 152. The planarization process may be performed until the top surfaces of the protective layer 140 and the polishing stop layer 145 are exposed. During the planarization process, the conductive layer 152 may be divided to form the second chip pad 150.

[0112] FIGS. 24 to 29 illustrate cross-sectional views of a method of manufacturing a semiconductor package according to some embodiments of the present disclosure.

[0113] Referring to FIG. 24, a base substrate 800 may be formed. For example, a typical process may be performed to form semiconductor devices such as transistors on the front surface of the base semiconductor substrate 810. The base circuit layer 820 may be formed by forming a dielectric pattern and a wiring pattern on the front surface of the base semiconductor substrate 810. The base vias 830 may be performed to vertically penetrate from the front surface into the base semiconductor substrate 810. Mounting pads 850 may be formed on the back surface of the base substrate 800.

[0114] The fifth semiconductor wafer 105 and the sixth semiconductor wafer 106 can be bonded to or mounted on the base substrate 800. Each of the fifth semiconductor wafer 105 and the sixth semiconductor wafer 106 can be substantially the same as one of the semiconductor wafers discussed with reference to FIGS. 1 and 2A-2E. Depending on the process variations in the manufacturing process of the fifth semiconductor wafer 105 and the sixth semiconductor wafer 106, the fifth semiconductor wafer 105 and the sixth semiconductor wafer 106 can have different thicknesses from each other. The vias 130 of the fifth semiconductor wafer 105 and the vias 130 of the sixth semiconductor wafer 106 can be located at the same level from the base substrate 800, and the top surfaces (or back surfaces) 110b1 and 110b2 of the base layers 110 of the fifth semiconductor wafer 105 and the sixth semiconductor wafer 106 can be located at different levels from the base substrate 800. For example, the fifth semiconductor wafer 105 and the sixth semiconductor wafer 106 can be formed from a single wafer. In this case, in the thinning process performed on the top surface 110b1 of the fifth semiconductor wafer 105 and the top surface 110b2 of the sixth semiconductor wafer 106, the grinding degree of the wafer can be changed depending on the positions of the fifth semiconductor wafer 105 and the sixth semiconductor wafer 106. FIG. 24 shows an example in which the top surface 110b1 of the base layer 110 included in the fifth semiconductor wafer 105 is located at a level higher than the level of the top surface 110b2 of the base layer 110 included in the sixth semiconductor wafer 106.

[0115] Referring to FIG. 25, a removal operation can be performed on the upper portions of the base layers 110 of each of the fifth semiconductor wafer 105 and the sixth semiconductor wafer 106. After removing the upper portions of the base layers 110, the vias 130 can protrude from the top surfaces of the base layers 110. In the process of removing the upper portions of the base layers 110, the grinding depth or etching depth of the base layer 110 included in the fifth semiconductor wafer 105 can be substantially the same as the grinding depth or etching depth of the base layer 110 included in the sixth semiconductor wafer 106. Therefore, the top surface 110b1 of the base layer 110 included in the fifth semiconductor wafer 105 and the top surface 110b2 of the base layer 110 included in the sixth semiconductor wafer 106 can be located at different levels from the base substrate 800. Additionally, the protruding distance of the via 130 protruding from the base layer 110 of the fifth semiconductor wafer 105 can be less than the protruding distance of the via 130 protruding from the base layer 110 of the sixth semiconductor wafer 106.

[0116] Referring to FIG. 26, a cushion layer 141 can be formed on the base substrate 800. The cushion layer 141 can be formed to conformally cover the fifth semiconductor wafer 105 and the sixth semiconductor wafer 106 and the top surface of the base substrate 800. On the base layers 110 of the fifth semiconductor wafer 105 and the sixth semiconductor wafer 106, the cushion layer 141 can conformally cover the vias 130 and the top surfaces 110b1 and 110b2 of the base layers 110.

[0117] A first dielectric layer 142 can be formed on the base substrate 800. On the base substrate 800, the first dielectric layer 142 can completely bury the fifth semiconductor wafer 105 and the sixth semiconductor wafer 106. For example, the first dielectric layer 142 can completely cover the cushion layer 141.

[0118] Referring to FIG. 27, a thinning process can be performed on the first dielectric layer 142. For example, a grinding process or a chemical mechanical polishing (CMP) process can be performed on the top surface of the first dielectric layer 142. The thinning process can continue until the top surfaces of the vias 130 of the fifth semiconductor wafer 105 and the top surfaces of the vias 130 of the sixth semiconductor wafer 106 are exposed. The first dielectric layer 142 and the vias 130 can have substantially flat and coplanar top surfaces. Since the fifth semiconductor wafer 105 and the sixth semiconductor wafer 106 have different thicknesses from each other, after the thinning process, the thickness of the first dielectric layer 142 on the base layer 110 of the fifth semiconductor wafer 105 can be less than the thickness of the first dielectric layer 142 on the base layer 110 of the sixth semiconductor wafer 106.

[0119] Referring to FIG. 28, an etch stop layer 143, a second dielectric layer 144, and a polish stop layer 145 can be sequentially formed on the base substrate 800. The etch stop layer 143, the second dielectric layer 144, and the polish stop layer 145 can each be shaped as a substantially flat planarization layer.

[0120] Referring to FIG. 29, the protective layer 140 can undergo a patterning process to form a recess that exposes the vias 130. A conductive layer can be formed to cover the protective layer 140 and fill the recess. A planarization process can be performed on the conductive layer 152, such that the conductive layer can be divided to form the second chip pads 150.

[0121] According to some embodiments of the present disclosure, in the process for exposing the vias 130, the vias 130 and the first dielectric layer 142 can be etched simultaneously, and the vias 130 and the first dielectric layer 142 can have top surfaces coplanar with each other. Therefore, the etch stop layer 143 can be at the same level on the fifth semiconductor wafer 105 and the sixth semiconductor wafer 106 having different heights, and each recess can have the same depth at the same level, wherein the recesses are formed by an etching process using the etch stop layer 143 as an etch stopper. For example, even when the base layers 110 having different thicknesses from each other are used, the protective layer 140 of the fifth semiconductor wafer 105 manufactured by the above process and the protective layer 140 of the sixth semiconductor wafer 106 manufactured by the above process can have top surfaces at the same level. Therefore, in the manufacturing process, a uniform process variation in the thickness of the semiconductor wafers can be achieved and a uniform process variation in the size and shape of the semiconductor package can also be achieved.

[0122] After that, other semiconductor wafers can be bonded to the fifth semiconductor wafer 105 and the sixth semiconductor wafer 106, and a molding layer can be formed on the base substrate 800 to cover the fifth semiconductor wafer 105 and the sixth semiconductor wafer 106.

[0123] In a semiconductor package according to some embodiments of the present disclosure, the etch stop layer sandwiched between the dielectric layers of the protective layer can completely cover the top surface of the lower dielectric layer and the bottom surface of the upper dielectric layer, and the etch stop layer can be shaped as a planarization layer. The polishing stop layer formed on the etch stop layer and the lower dielectric layer can also be shaped as a planarization layer, or the polishing stop layer formed on the etch stop layer and the lower dielectric layer can have a plate shape, and the top surface of the protective layer and the top surface of the chip pads can be substantially flat and coplanar with each other. Therefore, in the direct bonding process in which the semiconductor wafers are in direct contact with each other, it is possible to easily bond another semiconductor wafer to the top surface of the semiconductor wafer.

[0124] In a semiconductor package, there may be no gap between the semiconductor wafers or between the dielectric pattern and the protective layer. Therefore, good contact can be provided between the dielectric pattern and the protective layer or between the semiconductor wafers, and the semiconductor package can improve the structural stability. In addition, there may be no interval between the chip pads of the semiconductor wafers. Therefore, a semiconductor package having good bonding between the chip pads and good electrical connection between the semiconductor wafers can be provided.

[0125] In a semiconductor package, a protective layer extending to a lateral surface of a base layer can be used to adjust the width of a semiconductor wafer. Accordingly, the semiconductor wafer can be easily bonded to another semiconductor wafer or an electronic component having a size different from that of the semiconductor wafer.

[0126] 100: Semiconductor wafer 101: First semiconductor wafer 102: Second semiconductor wafer 103: Semiconductor wafer / uppermost semiconductor wafer 104: Semiconductor wafer / third semiconductor wafer 105: Fifth semiconductor wafer 106: Sixth semiconductor wafer 110: Base layer 110a: Bottom surface 110b, 110b1, 110b2: Top surface 120, 420: Circuit layer 122, 222, 422: Dielectric pattern 124, 224, 424: Wiring pattern 125: First chip pad 130: Via 132, 152: Conductive layer 134: Via barrier layer 140: Protective layer 141: Pad layer / single-layer pad layer 142: First dielectric layer 143: Etch stop layer 144: Second dielectric layer 145: Polish stop layer 147: Conductive pillar 150: Second chip pad 200, 800: Base substrate 210, 810: Base semiconductor substrate 220, 820: Base circuit layer 225: External pad 230, 830: Base via 240: Base protective layer 250, 850: Mounting pad 260, 530: External terminal 300: Molded layer 400: Fourth semiconductor wafer 410: Semiconductor substrate 425: Third chip pad 500: Redistribution substrate 510: Substrate dielectric pattern 520: Substrate wiring pattern 900: Carrier substrate A, B, C, D1, D2, D3, D4, D5, D6, D7, E1, E2, E3, E4, E5, E6, E7, E8: Sections RS: Depression

Claims

1. A semiconductor package, comprising: First structure; The first structure includes: a first semiconductor substrate having an effective surface and a non-effective surface opposite to the effective surface, a first semiconductor device being configured to be disposed on the effective surface; a first through-hole perpendicularly penetrating the first semiconductor substrate and protruding from the non-effective surface of the first semiconductor substrate; a first protective layer covering the non-effective surface of the first semiconductor substrate and burying the first through-hole; and a first pad penetrating at least a portion of the first protective layer and coupled to the first through-hole, wherein the first protective layer includes: a first dielectric layer located on the non-effective surface of the first semiconductor substrate; a second dielectric layer located on the first dielectric layer; and an etch stop layer located between the first dielectric layer and the second dielectric layer and contacting a lateral surface of the first pad, wherein the second structure includes a second pad, wherein the first structure and the second structure are bonded to each other, wherein the first pad and the second pad are in contact with each other, and wherein the first protective layer further includes a padding layer covering the side of the first dielectric layer facing the bottom surface of the first semiconductor substrate. The padding layer extends from between the first semiconductor substrate and the first dielectric layer to between the lateral surface of the first through-hole and the first dielectric layer.

2. The semiconductor package as claimed in claim 1, wherein the etch stop layer separates the first dielectric layer from the second dielectric layer.

3. The semiconductor package as claimed in claim 1, wherein the distance from the etch stop layer to the first semiconductor substrate is greater than the distance from the bottom surface of the first pad to the first semiconductor substrate.

4. The semiconductor package of claim 1, wherein the first through-hole perpendicularly penetrates at least a portion of the first dielectric layer, and wherein the first pad perpendicularly penetrates the second dielectric layer and the etch stop layer.

5. The semiconductor package of claim 1, wherein the distance between the contact interface located between the first through-hole and the first pad and the first semiconductor substrate is less than the distance between the top surface of the first dielectric layer and the first semiconductor substrate.

6. The semiconductor package as claimed in claim 1, wherein the first through-hole comprises: The conductive layer has a columnar shape; And a via barrier layer surrounding the circumferential surface of the conductive layer, wherein the first pad is in contact with the top surface of the conductive layer and the top surface of the via barrier layer.

7. The semiconductor package of claim 1, wherein one end of the pad layer extends along the lateral surface of the first through-hole and contacts the bottom surface of the first pad.

8. The semiconductor package of claim 1, wherein the first protective layer further includes a polishing termination layer covering the top surface of the second dielectric layer opposite to the first semiconductor substrate, wherein the top surface of the polishing termination layer is coplanar with the top surface of the first pad.

9. The semiconductor package of claim 1, wherein the top surface of the first pad and the top surface of the first protective layer are flat.

10. The semiconductor package of claim 1, wherein the first dielectric layer and the second dielectric layer comprise silicon oxide (SiO), and wherein the etch stop layer comprises silicon nitride (SiN).

11. A semiconductor package, comprising: substrate; A semiconductor wafer is located on the substrate; The semiconductor wafers include a molding layer located on the substrate, the molding layer surrounding the semiconductor wafers, each of the semiconductor wafers comprising: a semiconductor substrate; a first pad located on an effective surface of the semiconductor substrate; a dielectric pattern surrounding the first pad and exposing one surface of the first pad; a second pad located on a non-effective surface of the semiconductor substrate; a protective layer surrounding the second pad and exposing one surface of the second pad; and a through-hole perpendicularly penetrating the semiconductor substrate and connected to the second pad, wherein the protective layer comprises a first dielectric layer, an etch-stop layer, and a second dielectric layer stacked in sequence, the first dielectric layer and the second dielectric layer being spaced apart from each other across the etch-stop layer, wherein the distance from the etch-stop layer to the semiconductor substrate is greater than the distance from the bottom surface of the second pad to the semiconductor substrate, wherein one of the semiconductor wafers is directly bonded to the other of the semiconductor wafers, and the first pad of the one of the semiconductor wafers contacts the second pad of the other of the semiconductor wafers, wherein the protective layer further comprises a pad layer covering the side of the first dielectric layer facing the bottom surface of the semiconductor substrate. The padding layer extends from between the semiconductor substrate and the first dielectric layer to between the lateral surface of one of the through holes and the first dielectric layer.

12. The semiconductor package of claim 11, wherein the etch stop layer contacts the lateral surface of the second pad.

13. The semiconductor package of claim 11, wherein the via perpendicularly penetrates at least a portion of the first dielectric layer, wherein the second pad perpendicularly penetrates the second dielectric layer and the etch stop layer, and wherein the distance between the contact interface between one of the vias and one of the second pads and the semiconductor substrate is less than the distance between the top surface of the first dielectric layer and the semiconductor substrate.

14. The semiconductor package of claim 11, wherein each of the through-holes comprises: The conductive layer has a columnar shape; And a via barrier layer surrounding the circumferential surface of the conductive layer, wherein one of the second pads is in contact with the top surface of the conductive layer and the top surface of the via barrier layer.

15. The semiconductor package of claim 11, wherein one end of the pad layer extends along the lateral surface of one of the through-holes and contacts the bottom surface of one of the second pads.

16. The semiconductor package of claim 11, wherein the protective layer further includes a polishing termination layer covering the top surface of the second dielectric layer opposite to the semiconductor substrate, wherein the top surface of the polishing termination layer is coplanar with the top surface of the second pad.

17. The semiconductor package of claim 11, wherein the top surface of the second pad and the top surface of the protective layer are flat.

18. A semiconductor package, comprising: substrate; Semiconductor wafers are stacked on the substrate; The semiconductor wafers include a molding layer located on the substrate, the molding layer surrounding the semiconductor wafers, each of the semiconductor wafers comprising: a semiconductor substrate; a first pad located on an effective surface of the semiconductor substrate; a dielectric pattern surrounding the first pad and exposing one surface of the first pad; a protective layer located on a non-effective surface of the semiconductor substrate and comprising a first dielectric layer, an etch-stop layer, a second dielectric layer, and a polishing-stop layer stacked in sequence; a second pad located in the protective layer and having a surface exposed by the protective layer; and a through-hole perpendicularly penetrating the semiconductor substrate and connected to the second pad, wherein the etch-stop layer contacts the second pad, wherein one of the semiconductor wafers is directly bonded to the other of the semiconductor wafers, and the first pad of the one of the semiconductor wafers contacts the second pad of the other of the semiconductor wafers, wherein the protective layer further includes a pad layer covering the side of the first dielectric layer facing the bottom surface of the semiconductor substrate. The padding layer extends from between the semiconductor substrate and the first dielectric layer to between the lateral surface of one of the through holes and the first dielectric layer.

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