System and method for testing a non-volatile memory

Abstract

According to an embodiment of the present invention, a method for characterizing a non-volatile memory includes: applying a first voltage to a word line electrically coupled to a non-volatile memory cell, and measuring a current flowing through the non-volatile memory cell in response to the applied first voltage. Measuring the current includes: using a sensing amplifier to compare the current flowing through the non-volatile memory cell with a plurality of different first currents generated by an adjustable current source when the same first voltage is applied to the word line; and determining the measured current based on the aforementioned comparison.

Description

System and method for testing non-volatile memory The present invention relates to electronic systems and methods, and in particular embodiments, to systems and methods for testing non-volatile memory. Programmable non-volatile memories (NVMs) are useful in many applications because they retain stored information even when the memory is powered off. There are many different types of programmable non-volatile memories, including but not limited to programmable read-only memory (PROM), electrically erasable programmable ROM (EEPROM), and flash memory. These memory types use various charge storage methods, including but not limited to placing charge on floating gate or silicon-oxide-nitride-oxide-silicon (SONOS) storage materials or nodes. Like other types of memory, programmable NVM is typically constructed as an array of bit cells arranged in rows and columns. Each bit cell can include one, split gate, or two transistors (i.e., 1T, 1.5T, or 2T cells). During programming, charge is injected into the storage node of one of the multiple transistors. During normal operation of the NVM, bit cells are read by selecting a column of bit cells via a word line (WL) and measuring the output current of each bit cell via a sense amplifier coupled to the bit line. In practical memory applications, the device characteristics of bit cells can vary with respect to semiconductor process parameters and can vary randomly with respect to each other. Therefore, in some applications, the threshold of each bit cell is measured to determine read parameters, write parameters, and sense amplifier threshold current. In addition, some bit cells may be defective and need to be replaced with redundant bit cells. However, given the large size of modern non-volatile memories, measuring and characterizing each cell can take a long time, which increases test costs. According to an embodiment, a method for characterizing a non-volatile memory includes applying a first voltage to a word line electrically coupled to a non-volatile memory cell and measuring a current flowing through the non-volatile memory cell in response to the applied first voltage. Using a sense amplifier, the current flowing through the non-volatile memory cell is compared with a plurality of different first currents generated by an adjustable current source when the same first voltage is applied to the word line. The measured current is determined based on the comparison. According to another embodiment, a memory system includes an integrated circuit having a memory array including non-volatile memory cells; a plurality of word line drivers coupled to the memory array; a plurality of sense amplifiers coupled to the memory array and to an external data bus; an adjustable current source coupled to the plurality of sense amplifiers; a first control circuit configured to set the adjustable current source to a test current and apply a first address to the memory array to select a column of non-volatile memory cells; and a second control circuit configured to read the output of the sense amplifier and iteratively update the test current based on the read output of the sense amplifier to determine a current flowing through at least one non-volatile memory cell in the column of non-volatile memory cells. According to another embodiment, a method for characterizing a non-volatile memory includes operating the non-volatile memory in a test mode, including performing a test read of the non-volatile memory, including applying a column address to the non-volatile memory to select a column of non-volatile memory cells, grounding a word line coupled to the selected column of non-volatile memory cells, measuring a current of at least one non-volatile memory cell in the column via the grounded word line, and incrementing the column address; and repeatedly performing the test read using the incremented column address. The making and using of the presently preferred embodiments are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be implemented in a variety of specific circumstances. The specific embodiments discussed are merely illustrative of specific ways to implement and use the present invention and are not intended to limit the scope of the invention. In one embodiment, a non-volatile memory array features grounding the wordline of each column of memory cells and measuring the output current of each non-volatile memory cell. Current measurements can be performed by iteratively comparing the output current of each memory cell to an adjustable reference current using a sense amplifier to estimate the output current of the non-volatile memory cell. In some embodiments, these measurements can be performed rapidly on a column-by-column basis using the non-volatile memory's existing sense amplifiers, external data bus, and sense amplifier current reference circuitry used during normal read operations of the memory. Compared to conventional systems that measure memory cell thresholds by applying a variable voltage to the word lines, grounding the word lines in a non-volatile memory array during testing allows for faster characterization of memory cells. Conventional systems require additional time to charge and discharge the higher voltages applied to the word lines before and after each measurement. Embodiment memory systems also offer size advantages over conventional systems because the word line drivers do not need to include high-voltage circuitry for applying test voltages to the word lines. Using smaller word line drivers can reduce silicon area and lower costs. FIG1 illustrates an embodiment of a memory system including an integrated circuit 100 with non-volatile memory. As shown, integrated circuit 100 includes a memory array 104, a column decoder 102, a word line driver 103, a controller 106, a sense amplifier 112, a row decoder 110, I / O logic 114 coupled to an external data bus, a reference current generator 108, and a test controller 116. Reference current generator 108 may also be referred to as an adjustable current source. In some embodiments, when characterizing memory array 104, integrated circuit 100 may be coupled to an external tester 120. Additionally or in addition to tester 120, integrated circuit 100 may also include built-in self-test (BIST) circuitry 118, which performs one or more characterization functions on memory array 104. BIST circuitry 118 and tester 120 are shown in dashed lines to indicate that these blocks may or may not be present in some embodiments. In various embodiments, the components of the integrated circuit 100 may be implemented on a single monolithic semiconductor integrated circuit, such as a single semiconductor substrate, and / or on the same monolithic semiconductor integrated circuit as other disclosed system components. As shown, memory array 104 includes an array of non-volatile memory cells 105. Each non-volatile memory cell 105 is connected to a corresponding word line (WL1...WLn) and a corresponding bit line (BL1...BLm). During normal operation of the memory, row decoder 102 decodes a row address based on address data ADDR provided at the input of I / O logic 114. The decoded row address is used to select one of a plurality of word lines (WL1...WLn) via word line driver 103. Word line driver 103 activates a row of memory cells 105, which generates a corresponding read current on the corresponding bit line (BL1...BLm). Sense amplifier 112 is used to compare the current of each bit line with a reference current generated by reference current generator 108. Row decoder 110 selects multiple rows of memory array 104 to be routed to sense amplifiers 112. The output of sense amplifier 112 is routed to data line DATA via I / O logic 114. Controller 106 is a memory controller that controls the operation of the memory. In some embodiments, reference current generator 108 can be implemented using a current digital-to-analog converter (CDAC). In various embodiments, the non-volatile memory cells 105 of the memory array 104 are measured to (1) characterize the thresholds of programmed and / or unprogrammed memory cells; (2) determine operating parameters of the memory, such as sense amplifier thresholds, programming times, etc.; and / or (3) identify non-functional memory cells to be replaced by redundant memory cells. As described above, in various embodiments, the state of each memory cell is evaluated by determining whether the read current of each memory cell is greater than or less than a threshold current. FIG. 1B shows an exemplary distribution of read currents for N memory cells, which may represent, for example, N memory cells 105 within a row of a non-volatile memory array 104. As shown, each memory cell generates a first, lower current when the memory cell is written to the "1" state 134, and a second, higher current when the memory cell is written to the "0" state 132. In an alternative embodiment, the assignment of binary states "0" and "1" can be reversed. Current I NOM0 Represents the average or nominal current of N memory cells when writing the "0" state, current I NOM1 Represents the average or nominal current of N memory cells when writing the "1" state. Current I THRESH Represents the threshold current used by the sense amplifier 112 during a read operation to determine whether a particular bit is written to a "0" state or a "1" state. For example, during a read operation, when the current generated by the memory cell is greater than the threshold current I THRESH When the current generated by the memory cell is less than the threshold current I THRESH , it is determined that the memory cell 105 is written into the "1" state. In actual memory systems, the actual current I generated by each memory cell during operation is affected by variations in temperature, supply voltage, aging of the memory cell, and operating memory parameters including but not limited to write duration and write voltage. NOM0 and I NOM1 Therefore, the memory is designed to have a certain current margin I MARG At nominal "0" write current I NOM0 and critical current I THRESH Between, and at nominal "1" write current I NOM1 and critical current I THRESH Between. MARG It can be selected to ensure sufficient noise margin and accurate operation within the specified temperature and supply voltage range. THRESH To ensure that this margin meets the predetermined margin requirement, as shown in FIG1B , the dotted line is designated as I NOM0 –I THRESH For a "0" write bit, I NOM1 +I MARG For a "1" write bit. In various embodiments, a value greater than I NOM0 –I THRESH The measured current "0" is written into the bit and the generated current is less than I NOM1 + I MARG The measured current of the "1" written bit is considered to have sufficient margin. For example, the outlier measurement 136 of the "0" written bit has a current margin of I MARG Because its associated current is greater than I NOM0 –I THRESH On the other hand, the abnormal value of writing “1” to bit 138 is measured in the current margin I MARG In addition, because its associated current is greater than I NOM1 +I MARG . In various embodiments, the measurement of the current of one or more memory cells is determined by iteratively setting the current threshold of the sense amplifier 112 and reading the output of the sense amplifier 112. For example, in an embodiment, the current generated by the reference current generator is set to a first current value to be compared with a specific current threshold. Next, a column of memory cells is read using the first current value. The resulting read value provides an indication of which memory cells generate currents above and below the first current value. For example, referring to FIG. 1B , if the first current value is set to I after the column of memory cells is written with a "1" value, the first current value is set to I NOM1 +I MARG , all measured memory cells will return a "1" value except bit 138, which returns a "0" value to indicate that its current is greater than the first current value. This information can be used, for example, to replace bit 138 with a redundant memory cell or to replace an entire row with a redundant row of memory cells. In various embodiments, the memory cells in a column of memory cells may be written with a "1" value, a "0" value, or a combination of "1" and "0" values ​​according to a particular pattern. For example, in one embodiment, all memory cells in a particular column are written with a "0" value. Next, the reference current generated by the reference current generator 108 is continuously varied to determine one or more current levels to be written to the memory cells using a "linear search method." For example, referring to FIG. 1B , the initial reference current may be greater than the current I NOM0 The initial measurement returns a set of measurements indicating that the memory cells in the row have a current level less than the initial reference current. During each subsequent measurement, the reference current is continuously lowered so that the returned measurements indicate a mixture of memory cells having currents above and below the reference current. For example, when the reference current is I NOM0 , with a current higher than I NOM0 The memory cell returns the value "0" and has a current lower than I NOM1 The current of a particular memory cell can be estimated as a current between a first reference current that returns a "0" and a second reference current that returns a "1". These measurements can be continued until the current of each memory cell is determined. For example, once the reference current is lower than the current of the abnormal memory cell 136, all memory cells will return a "0" value. In an alternative embodiment, the linear search method can be used at lower currents (e.g., below I NOM0 -I MARG ) and increase sequentially. In some embodiments, the current of a subset of memory cells can be estimated. For example, the current threshold can be iteratively adjusted to determine the "worst case" memory cell (e.g., memory cell 136) that is written with a "0" or to determine a predetermined number of "worst case" memory cells with the lowest current, and then the memory measurement conclusion can be drawn. In some embodiments of the present invention, in addition to the linear search technique described above, different search techniques may be applied. For example, a binary search algorithm may be used to continuously approximate the current of a particular memory cell. In such an embodiment where a CDAC is used to implement reference current generator 108, the CDAC is initialized to an initial DAC word, where the MSB of the DAC is set to "1" and the remaining least significant bits are set to "0." Assuming all bits are written to "0," when the measurement result of a particular bit indicates "0," indicating that the reference current is less than the current generated by the particular memory cell, the MSB and the second most significant bit of the CDAC are set to "1" for the next measurement. On the other hand, when the measurement result of a particular bit indicates "1," indicating that the reference current is greater than the current generated by the particular memory cell, the MSB is set to "0" and the second most significant bit of the CDAC is set to "1" for the next measurement. Measurements are performed bit by bit until all bits of the CDAC input word have been used. In some embodiments, a successive approximation register can be used to store and update the CDAC word according to successive approximation techniques known in the art. In such embodiments, the final value stored in the successive approximation register at the end of the measurement represents the estimated value of the memory cell. In some embodiments, the measurement results of multiple memory cells can be used to determine a reference current when performing a binary search method to identify one or more outlier memory cells and / or to identify and measure the current of a "worst case" memory cell. In such an embodiment, the binary search method can be performed to minimize the number of bits that produce a "1" value when the bits are pre-programmed to a "0" state. For example, the current used for each successive approximation test can be determined by comparing the number of "1" values ​​produced between two consecutive cycles in order to converge to a current value where a single memory cell (e.g., outlier 136) returns a "1" value while the remaining memory cells return a "0" value. In other words, the system is configured to find the cell (or cells) with the lowest erase current. While the above current estimation technique is described with respect to measuring memory cells having a "0" value written thereto, it should be understood that similar measurement techniques can also be used to measure memory cells having a "1" value written thereto. In such an embodiment, the polarity of the measurements of the corresponding measurement sequence is reversed and adjusted to accommodate the reversed programmed polarity. For example, in such an embodiment, the current of one or more abnormal cells (e.g., cell 138) having the largest current is determined, rather than the current of the abnormal cell having the smallest current. Each measurement can be controlled, for example, using BIST 118, tester 120, controller 106, test controller 116, or a combination thereof. For example, one of these controllers provides a column address to column decoder 102, analyzes the resulting data output by sense amplifier 112, and determines the next current to be generated by reference current generator 108. In embodiments where test operation during test mode is controlled by external tester 120, the column address of the test column can be provided via address bits ADDR, and the measured bits can be read via data bus DATA coupled to I / O logic 114. The operation of reference current generator 108 and embodiment test mode can be controlled by tester 120 via control bus CTL coupled to I / O logic 114. In some embodiments, various test sequences can be controlled in part by test controller 116. For example, when the tester 120 places the integrated circuit 100 in a characterization test mode, the test controller 116 can configure the controller 106 to apply the necessary test control sequence and configure the reference current generator 108 to adjust its reference current to the desired test current or sequence of test currents as described above. In some embodiments, the tester 120 can only provide an initial column address for characterization. In such embodiments, the column address can be incremented internally by the test controller 116 and / or the BIST 118 after each row-by-row measurement. In some embodiments, tester 120 may analyze the output of each measurement iteration and determine the next current value to be provided by reference current generator 108. In alternative embodiments, the analysis of each measurement iteration and / or the determination of the next current value may be implemented internally by BIST 118. In some embodiments, the entire characterization method may be performed internally by BIST 118, and the characterization results may be obtained externally via I / O logic 114. In various embodiments, the characterization results can be tabulated in various formats. In one embodiment, the characterization results can include a list of memory cell address locations and their associated current thresholds. This list can detail each memory cell in each column or each memory cell in a subset of memory cells, such as one or more "worst case" memory cells and their associated current thresholds. These current thresholds can be expressed using CDAC input words provided to the reference current generator 108 and / or can be converted to equivalent current thresholds and / or equivalent voltage thresholds based on other physical measurements or characterization data. This conversion can be achieved using, for example, a database, a lookup table, or other data conversion methods known in the art. The memory systems described herein can be implemented in a variety of semiconductor processes, such as standard CMOS processes and / or CMOS processes that have been modified to accommodate one or more specific types of non-volatile memory. While embodiments of the memory architecture will be described herein with respect to silicon-oxide-nitride-oxide-silicon (SONOS) devices developed, for example, in accordance with Infineon Technologies' SONOS process technology, other embodiments of the present invention are not limited thereto and may include substantially any type of memory cell developed in accordance with substantially any non-volatile process technology. Figures 2A and 2B illustrate flow charts of methods according to embodiments of the present invention. More specifically, Figure 2A illustrates a method 200 for characterizing a non-volatile memory array in which each memory cell under test has been written with a "0," and Figure 2B illustrates a method 230 for characterizing a non-volatile memory array in which each memory cell under test has been written with a "1." In various embodiments, methods 200 and 230 may be performed under the control of test controller 116, BIST 118, and / or tester 120, depending on the specific system implementation and its specifications. 2A , method 200 begins when a "margin mode" (e.g., a mode for characterizing memory cells) is entered in step 202 . This margin mode can be externally entered via a command provided via control line CTL to I / O logic 114 shown in FIG. 1A . Next, in step 204 , a first column address is provided to column decoder 102 . As described above, the column address can be provided by tester 120 , BIST 118 , and / or test controller 116 . In step 206 , a first initial read current reference is set, for example, by providing a first CDAC input word to reference current generator 108 . This first initial read current can correspond to a first (e.g., MSB) estimate of a binary search successive approximation, for example. Once the initial regulation current has been set, the word line of the selected column is set to a reference voltage, such as 0V (e.g., ground), and a first measurement of the selected column is taken in step 212 by performing a memory read. The resulting memory output of the selected column (e.g., the output of the sense amplifier 112) is analyzed to determine whether the read passed a first set of conditions. In some embodiments, a read pass is defined as a memory read that produces all "0s" for each memory cell in the column. If a read pass is encountered in step 214, the reference current generated by the reference current generator 108 is increased in step 210, and step 212 is repeated with the increased reference current. In some implementations, the reference current is increased by incrementing a digital word provided to the CDAC of the reference current generator 108. On the other hand, if a read pass is not encountered in step 214 (e.g., one or more bits returned by the memory read indicate a "1"), the reference current generated by the reference current generator 108 is decreased in step 208, and step 212 is repeated with the decreased reference current. For example, the reference current may be reduced by reducing the digital word provided to the CDAC of the reference current generator 108 . In various embodiments, steps 212, 214, and steps 208 and / or 210 are repeated until the measurement is completed in step 213. In some embodiments, when all bits controlling the CDAC have been toggled and the current of the memory cell has been determined (within the accuracy of the CDAC), the measurement is complete, at which point the method proceeds to step 216, where the column address is incremented. If the measurement is not complete, the method proceeds to step 214 as described above. In embodiments utilizing a row decoder such as row decoder 110 shown in FIG. 1A , the current row decoder setting can be continuously incremented in step 216 so that the entire column is read before the column address is incremented. During step 218, a determination is made as to whether the incremented column address is greater than a predetermined maximum address. If the incremented column address is not greater than the maximum column address, the method proceeds to step 212, where the column corresponding to the incremented column address is measured. On the other hand, if the incremented column address is greater than the maximum column address, margin mode is exited in step 220. The predetermined maximum address may be the maximum address of the non-volatile memory, or may be a different address in embodiments where only a subset of the memory columns are measured. The method 230 shown in FIG2B is similar to the method 200 shown in FIG2A , except that the memory cells of a particular column are written to have a value of “1”. Thus, steps 212 and 214 are replaced by steps 232 and 234, respectively. In step 234, the word line of the selected column is set to 0V (e.g., ground voltage), and a first measurement of the selected column is performed by performing a memory read in step 234. The resulting memory output of the selected column (e.g., the output of the sense amplifier 112) is analyzed to determine whether the read passes the first set of conditions. A read pass is defined as a memory read that produces all “1s” for each memory cell in the column of memory cells. If a read pass is encountered in step 234, the reference current generated by the reference current generator 108 is reduced in step 208, and step 232 is repeated with the reduced reference current. On the other hand, if a read pass is not encountered in step 234 (e.g., one or more bits returned by the memory read indicate a "0"), then the reference current generated by the reference current generator 108 is increased in step 210, and step 234 is repeated with the increased reference current. The remaining steps of method 230 are performed as described above with respect to method 200 of FIG. 2A. Figures 3A, 3B, 3D, 3E, and 3F illustrate circuits that can be used to implement a memory system according to an embodiment of the present invention. Figure 3A shows an embodiment of a memory sensing system 300, which includes a memory cell 105 corresponding to the memory cell in the memory array 104 shown in Figure 1A, a sense amplifier 302 corresponding to the sense amplifiers included in the plurality of sense amplifiers in the sense amplifier block 112 shown in Figure 1A, and a reference current generator 108 corresponding to the reference current generator in Figure 1A. Memory cell 105 can be a non-volatile memory cell, such as a floating gate memory cell or a SONOS memory, configured to generate an output current Icell that depends on the memory state of the memory cell. For example, when memory cell 105 is in a programmed state (e.g., a "1" state), a lower bit line current Icell is generated. On the other hand, when memory cell 105 is in an erased or "0" state, a higher bit line current Icell is generated. Therefore, sense amplifier 302 can be used to determine the state of memory cell 105 by comparing the output current Icell of memory cell 105 provided to a sense input of sense amplifier 302 with a reference current Isense generated by current generator 108 provided to a reference current input of sense amplifier 302. During operation, the sense amplifier 302 generates a first logic state associated with the output signal Dout when the output current Icell of the memory cell 105 is less than the reference current Isense, and generates a second logic state when the output current Icell is greater than the reference current Isense. The first logic state and the second logic state can be referred to as a "low" state and a "high" state, or a "0" state and a "1" state, respectively. In some embodiments, this designation can be reversed, such that the first logic state and the second logic state are referred to as a "high" state and a "low" state, or a "1" state and a "0" state, respectively. Memory cell 105 and sense amplifier 302 can be implemented using memory cells and sense amplifier circuits known in the art. For example, memory cell 105 can be a SONOS or charge trap memory cell or a floating gate memory cell, and sense amplifier 302 can be implemented using a cross-coupled CMOS latch circuit. In alternative embodiments, other memory cells and sense amplifier circuits can be used. Reference current generator 108 can be implemented using a CDAC, such as CDAC 360 described below with reference to FIG. 3F . FIG3B illustrates an exemplary word line driver circuit 320, which can be used to implement each of the multiple word line driver circuits within word line driver 103 shown in FIG1A. As shown, word line driver 320 includes a p-channel MOS transistor P1 coupled between a positive bias node (also referred to as a "positive power supply node") and a word line driver node WLS, and an n-channel MOS transistor N1 coupled between word line driver node WLS and a negative bias node (also referred to as a "negative power supply node"). The positive bias node and the negative bias node are coupled to a positive power supply circuit and a negative power supply circuit (e.g., a positive charge pump and a negative charge pump), respectively. In some embodiments, the body connection NWELL of p-channel MOS transistor P1 can be coupled to the positive bias node, and the body connection PWELL of n-channel MOS transistor N1 can be coupled to the negative power supply node. Negative level shifter 322 and positive level shifter 324 provide gate drive signals to the gates of p-channel MOS transistor P1 and n-channel MOS transistor N1, respectively, based on signals received from low-voltage column control block 326. In one embodiment, low-voltage column control block 326 represents the output stage of column decoder 102 shown in FIG1A. During normal memory read and write operations, the positive bias node and the negative bias node provide the necessary voltages to word line WLS, as described below with reference to FIG5A, FIG5B, FIG5C, and FIG5D. However, during memory cell characterization operations in the embodiment described herein, the negative bias node is set to ground, causing word line WLS to be grounded. Embodiment device characterization systems and methods that allow the word line to be grounded during memory cell characterization are advantageous because they allow the use of physically compact word line drivers. This contrasts with voltage-mode characterization systems and methods, which apply a variable voltage to the word line and require additional circuitry to perform memory cell characterization. To determine the voltage threshold of a memory cell, a wide range of voltages is applied to the memory cell being measured. In some cases, devices rated to handle higher voltages are used to provide these voltages during the characterization process. In some embodiments, each of these devices may be composed of multiple devices connected together and occupy a large amount of silicon area. FIG3C shows a conventional word line driver that includes transistors P1 and N1, level shifters 322 and 324, and additional circuitry to support the application of a wider range of positive voltages to the word line via p-channel MOS device P3. Additional circuitry also includes p-channel MOS device P2, n-channel MOS device N2, and level shifters 333 and 335 that receive input from a low-voltage column control margin mode block 336. Conventional word line driver 330 includes more devices than embodiment word line driver 320. In various embodiments of the present invention, embodiment word line drivers are physically smaller than conventional word line drivers used in voltage-mode device characterization. Figures 3D and 3E show level shifter circuits 332 and 334, respectively, which can be used to implement negative level shifter circuit 322 and positive level shifter circuit 324 of word line driver 320 shown in Figure 3B. Figure 3D shows negative level shifter 332, which is configured to convert a low-level logic signal (e.g., 0V to 1V) into a high-level logic signal having a signal swing between a negative power supply and a positive power supply (e.g., -3V to 0 / 1V). In various embodiments, the voltage range at the output of negative level shifter circuit 332 is sufficient to drive the gate of n-channel MOS transistor N1 (Figure 3B), which functions as a high-side switching transistor. Negative level shifter 332 includes a cross-coupled latch including p-channel MOS transistors P4 and P5, n-channel MOS transistors N4 and N5, and input p-channel MOS transistors P6 and P7, which function as input transistors. During operation, a low-level logic input, InLV, is applied to the gate of p-channel MOS transistor P6, and an inverted low-level logic input, InbLV, is applied to the gate of p-channel MOS transistor P7. The resulting currents provided by transistors P6 and P7 cause the cross-coupled latch circuit to provide a high-level logic signal and an inverted high-level logic signal, OutBHV, at the output node OutHV. Referring to FIG. 3E , as shown, a positive level shifter 334 is configured to convert a low-level logic signal (e.g., 0V to 1V) into a high-level logic signal having a signal swing between a negative power supply and a positive power supply (e.g., 0 / 1V to 4V). In various embodiments, the voltage range at the output of the positive level shifter circuit 334 is sufficient to drive the gate of p-channel MOS transistor P1 ( FIG. 3B ), which serves as a low-side switching transistor. Positive level shifter 334 includes a cross-coupled latch comprising p-channel MOS transistors P4 and P5, n-channel MOS transistors N4 and N5, and input n-channel MOS transistors N8 and N9 serving as input transistors. During operation, a low-level logic input In LV is applied to the gate of N-channel MOS transistor N8, and an inverted low-level logic input Inb LV is applied to the gate of N-channel MOS transistor N9. The resulting current provided by transistors N8 and N9 causes the cross-coupled latch circuit to provide a high-level logic signal at the output node Out HV and an inverted high-level logic signal OutB HV. 3D and 3E are two examples of many possible level shifter circuits that may be used to implement the level shifting functionality of word line driver 320. In alternative embodiments of the present invention, other level shifter circuits known in the art may be used. FIG3F illustrates a CDAC circuit 360 that can be used to implement the reference current generator 108 shown in FIG1A . As shown, CDAC circuit 360 is configured to provide an output current Iout based on an n-bit digital input word CDAC[n:1]. In one embodiment of the present invention, CDAC 360 is an 8-bit CDAC; however, other embodiments may utilize other bit resolutions depending on the specific embodiment and its specifications. As shown, CDAC circuit 360 is implemented as a binary-weighted circuit having n binary-weighted output branches and a bias branch. The bias branch includes p-channel MOS transistors 362, 364, and 366 and a resistor RC1. Current source Iin provides a bias voltage P0_BIAS to transistor 366 in the input branch and transistors 372, 378, and 384 in the output branch. The output of resistor RC1 provides a bias voltage P1_BIAS to transistor 364 in the input branch and transistors 370, 376, and 382 in the output branch, and transistor 362 is used to match the on-resistance of selected transistors 368, 374, and 380 in the output branch. As shown, transistors 362, 364, and 366 each have a relative size of one unit cell and are configured to receive DC bias current Iin. The first output branch includes a stacked transistor 372, a current source transistor 370, and a select transistor 368. Select transistor 368 is activated when the LSB of the digital input word CDAC[n:1] is asserted. As shown, transistors 368, 370, and 372 have the same dimensions as transistors 362, 364, and 366 of the bias branch, resulting in the first branch generating a current of 1*Iin when that branch is active. The second output branch includes a stacked transistor 378, a current source transistor 376, and a select transistor 374. Select transistor 374 is activated when the second least significant bit of the digital input word CDAC[n:1] is asserted. As shown, transistors 374, 376, and 378 have twice the dimensions of transistors 362, 364, and 366 of the bias branch, resulting in the second branch generating a current of 2*Iin when that branch is active. The nth output branch includes a stacked transistor 384, a current source transistor 382, ​​and a select transistor 380. The select transistor 380 is activated when the MSB of the digital input word CDAC[n:1] is asserted. As shown in the figure, the sizes of transistors 380, 382, ​​and 384 are n times the sizes of transistors 362, 364, and 366 of the bias branch, so that the nth branch generates 2 n-1 *Iin current. If applicable, use a weighting of 4 to 2 n-2 Additional binary-weighted branches are provided between the CDAC circuit 360 and the CDAC circuit 360, but are not shown for simplicity of illustration. In some embodiments, the CDAC circuit 360 may be implemented using equally-weighted segments or a combination of equally-weighted and binary-weighted segments, depending on the specifications of the particular embodiment. In further alternative embodiments, other CDAC circuits and architectures known in the art may also be used. FIG4 shows a timing diagram illustrating the states of column address lines RADDR and data lines DATA coupled to I / O logic 114 of FIG1A during an embodiment memory cell characterization process while the memory array 104 is being read. Also depicted are clock signal CLK, representing the system clock of the memory system, and signal R_VALID, a control signal asserted when an initial column address is written to the test memory system. At time t1, when R_VALID is asserted, initial column address A1 is written to column address line RADDR. This causes the first measurement result, represented by data word D1, to appear on data line DATA at time t2, where the length of each word corresponds to the width of the measured column or selected row. For example, in embodiments in which 128 sense amplifiers are coupled to a selected row and / or in embodiments in which 128 sense amplifiers coupled to 128-bit-wide columns are used, the width of data words D1, D2, D3, and D4 will each be 128 bits. After five clock cycles, the initial column address A1 is incremented to A2 and applied to the column decoder 102, and the corresponding data word D2 appears on the data line DATA at time t3. This process is repeated until the memory array 104 is completely read. In embodiments where a row decoder (such as the row decoder 110 shown in FIG1A) is utilized, a separate read is performed for each selected row until the entire row is read before the column address RADDR is incremented. The timing scheme shown in FIG4 is highly advantageous because it can output a large number of measurement results in a small number of clock cycles. This increases the speed of characterization testing and reduces the cost of testing each device. In contrast, conventional embodiments require a significant delay between measurements of each row of the memory array to allow the on-board charge pump to charge and discharge the word lines. Additionally, embodiments that provide measurement data via a wide external data bus are more efficient because the measurement data can be rapidly output in parallel, which is faster than using narrower output buses or narrower special-purpose buses (such as narrow test buses or control buses). It should be understood that the timing diagram of FIG. 4 is only one example of possible signal timing relationships in the embodiment characterization system. In alternative embodiments, different timing relationships may be implemented. For example, in alternative embodiments, the data line DATA may be updated every n clock cycles, where n is less than or greater than 5. Figures 5A, 5B, and 5C illustrate example memory cells that may be used to implement memory cells 105 of nonvolatile memory array 104 according to embodiments of the present invention. For example, Figure 5A illustrates an embodiment of a transistor (1T) SONOS memory cell comprising an N-type SONOS transistor having gate, drain, and source terminals (see Figure 5C). The gate of the SONOS transistor is coupled to receive a SONOS word line (WLS) voltage, the drain is coupled to receive a bit line (BL) voltage, and the source is coupled to receive a source line (SL) voltage. As shown in the cross-section of Figure 5C, the substrate or well of the SONOS transistor is coupled to receive a well bias voltage (P-WELL). Exemplary voltages for reading, erasing, and programming the 1T SONOS memory cell are shown in Figure 5D and discussed in more detail below. Figure 5B shows an embodiment of a 2T SONOS memory cell, which includes an N-type SONOS transistor and an N-type pass device (FNPASS), which is included to minimize leakage current during read operations. The SONOS gate is coupled to receive the SONOS word line (WLS) voltage, and the drain is coupled to receive the bit line (BL) voltage. The source of the SONOS transistor is coupled to the drain of the FNPASS device. The gate of the FNPASS device is coupled to receive the word line (WL) voltage, and the source is coupled to receive the source line (SL) voltage. The SONOS and FNPASS devices can share a common substrate connection. As with the 1T cell, a well bias (P-WELL) is provided to the substrates of the SONOS and FNPASS devices to facilitate read, erase, and program operations. Example voltages for reading, erasing, and programming a 2T SONOS memory cell are shown in Figure 5D and will be discussed in more detail below. FIG5C is a cross-sectional view illustrating an embodiment of an N-type SONOS transistor. Although FIG5A through FIG5C illustrate N-type devices, the memory architecture described herein is not limited thereto and may include P-type devices in other embodiments. Those skilled in the art will appreciate how to modify the memory architecture to accommodate such devices. As shown in Figure 5C, the gate of the SONOS transistor is separated from the channel by a dielectric layer stack. The dielectric stack (often referred to as the "ONO stack") can include a thin tunneling layer (usually an oxide) above the channel, a charge trapping layer (usually a nitride) above the tunneling layer, and a blocking layer (usually an oxide) located between the charge trapping layer and the gate. The charge trapping layer of the SONOS transistor is the storage node of the 1T and 2T memory cells shown in Figures 5A and 5B, for example. The charge trapping layer can be "charged" to change the threshold voltage (Vt) of the SONOS transistor and change the value of the bit stored in the 1T or 2T memory cell (for example, to "0" or "1"). The threshold voltage (Vt) is defined as the critical gate-source voltage at which current flows through the SONOS transistor. A SONOS memory cell according to an embodiment of the present invention can be programmed or erased by applying a voltage of appropriate polarity, amplitude, and duration between the gate terminal and the source / drain / substrate terminals of the SONOS transistor. This voltage is referred to as the gate-to-channel voltage. For example, a SONOS memory cell can be programmed by raising the gate-to-channel voltage of the SONOS transistor to a relatively high positive value (typically between 7V and 12V). This causes electrons to tunnel from the channel into the ONO stack and be trapped in the charge-trapping nitride layer. The trapped charge creates an energy barrier between the transistor's drain and source, thereby raising the threshold voltage (Vt) of the SONOS transistor. In one embodiment, a "1" bit can be stored in the memory cell by raising the threshold voltage of the programmed SONOS transistor to a substantially positive Vt. By applying a negative gate-to-channel voltage (typically between -7V and -12V) to the SONOS transistor, electrons trapped within the nitride layer can be removed, thereby lowering the threshold voltage of the SONOS transistor and erasing the contents of the memory cell. In one embodiment, an erased SONOS transistor with a substantially negative Vt can be used to store a "0" bit within the memory cell. Once programmed or erased, the contents of the SONOS memory cell can be read by applying nominal voltages to a specific combination of word lines, bit lines, and source lines and sensing whether current flows on the corresponding bit lines. FIG5D shows an exemplary bias voltage scheme for reading, erasing, and programming 1T and 2T SONOS memory cells. Some bias voltages shown in FIG5D include two entries separated by a slash ( / ). If two entries are included, the first entry corresponds to a "select bias" and the second entry corresponds to a "de-select bias." In some embodiments, the non-volatile memory array 104 can be divided into multiple "blocks" and / or multiple "sectors." In an embodiment, if a block or sector architecture is used, the select bias and deselect bias shown in FIG5D can be applied to enabled blocks or sectors. In one embodiment, disabled blocks or sectors can also receive a deselect signal (typically 0V), with the exception of WLs in a 2T cell block architecture (since WLs span multiple blocks, if a WL is connected to an accessed memory cell in an enabled block, the WL may not be disabled). If the memory array is not divided into blocks or sectors, the select bias and deselect bias shown in FIG5D can be applied to the entire memory array. Some of the bias voltages shown in FIG5D are indicated by asterisks (*). These bias voltages are exemplary and may be different in other embodiments of the present invention. For example, the SL can be floated instead of shorting the SL to the BL during programming and erasing. As shown in Figure 5D, 1T and 2T SONOS memory cells can be read by applying a bias voltage (VLIM) to the bit line (BL) while grounding the source line (SL) and SONOS word line (WLS) of the selected memory cell. The word line (WL) of the selected 2T cell can also receive an appropriate voltage bias during the read operation. This enables current to flow (or not flow) on the bit line, depending on the threshold voltage (V) of the SONOS device. As described in more detail below, the bit line current can be sensed or "read" by a sense amplifier. In one embodiment, a current value close to zero can indicate the presence of a "1" bit, while a significantly higher current value can indicate the presence of a "0" bit in the selected cell. In alternative embodiments of the present invention, the opposite may be true. As shown in FIG5D , the bias voltage (VLIM) applied to the selected BL during a read operation is limited to avoid interfering with other cells on the same BL. In one embodiment, a VLIM of approximately 1.2V can be provided. As further shown in FIG5D , a power supply voltage (VPWR) is provided to the WL of the selected 2T cell to enable the N-channel FNPASS device during a read operation. In one embodiment, a power supply voltage of approximately 2V can be supplied to the WL of the selected 2T cell. In other embodiments, the read current can be increased by providing a pumped bias voltage (pumped bias) above the power level to the WL of the selected 2T cell. However, it should be noted that the read bias voltage shown in FIG5D is exemplary and should not be considered as limiting the present invention. In some embodiments, a select bias / deselect bias (e.g., 1.2V / 0V) can be applied to the BL of the 1T and 2T memory cells, as well as the word line (WL) connected to the transfer device (FNPASS) within the 2T cell. A select bias / deselect bias (e.g., 0V / -2V) can also be applied to the WLS line of the 1T cell to select / deselect the cell during a read operation. The select / deselect bias can be used on the WLS line of the 1T cell because it does not have a transfer device. As shown in Figure 5D, the read bias provided to the P-well may be different for the 1T and 2T cells. In one embodiment, 0V can be applied to the substrate of the 2T cell. However, a slight negative bias (e.g., -2V) can be applied to the substrate of the 1T cell. The negative bias applied to the P-well will cause the gate-to-channel voltage of the deselected memory cell to be 0V. However, it is worth noting that the read bias voltages mentioned here are exemplary and may be different in other embodiments of the present invention. As shown in Figure 5D, a 1T SONOS memory cell can be erased by applying a negative voltage (VNEG) to the SONOS word line (WLS) and a positive voltage (VPOS) to the bit line (BL), source line (SL), and substrate (P-Well) of the target or "selected" memory cell. The SONOS word line (WLS) that enables unselected memory cells within a block or sector is biased with VPOS to avoid erasing memory cells on unselected rows. FIG5D shows a similar biasing scheme for erasing a 2T SONOS memory cell. However, the 2T scheme differs from the 1T scheme in that the select / deselect bias is applied to the word lines (WLs) connected to the transfer device (FNPASS) in the 2T cell. In one embodiment, VPWR can be applied to the selected WL, while 0V is applied to all deselected WLs. The select / deselect bias applied to the WLs during erase can be generated, for example, by the word line driver 103. As shown in Figure 5D, a 1T SONOS memory cell can be programmed by applying a positive voltage (VPOS) to the SONOS word line (WLS) and a negative voltage (VNEG) to the bit line (BL), source line (SL), and substrate (P-well) of the selected memory cell. The SONOS word line (WLS) that enables unselected memory cells within a block or sector is biased with VNEG to avoid programming memory cells on unselected columns. In some embodiments, the BL and SL of unselected memory cells can be biased (VBL) to prevent programming of memory cells that are to be maintained in an erased state. As described in more detail below, a VBL bias between 0V and VPWR can be used to inhibit programming of certain cells. In one embodiment, a VBL of approximately 1V can be provided. Figure 5D shows a similar biasing scheme for programming a 2T SONOS memory cell. However, the 2T scheme differs from the 1T scheme in that the 2T scheme applies a VWL bias (typically between 0V and VNEG) to the word lines (WL) of all 2T cells to reduce HV damage to the SONOS device during the programming operation. As further shown in FIG5D , the SONOS memory cell can be programmed and erased by applying a positive voltage (VPOS) and a negative voltage (VNEG) to the gate, drain, source, and substrate terminals of the SONOS transistor. In various embodiments, the SONOS memory cell can be programmed or erased in the manner described above before applying the embodiment characterization method. During the embodiment characterization operation, the selection and biasing of the memory cells are similar to the selection and biasing of the memory cells during the read operation. For example, VPWR can be applied to the WL of the selected 2T cell to enable the FNPASS device, while the ground voltage (0V) is applied to the WLS of the selected 2T cell. For the 1T cell, the ground voltage (0V) is applied to the WLS of the selected 1T cell. Referring now to FIG6 , a block diagram of a processing system 600 is provided in accordance with an embodiment of the present invention. Processing system 600 depicts a general-purpose platform and general components and functionality that may be used to implement portions of the embodiments described herein, such as controller 106, test controller 116, BIST 118, and / or tester 120 described above with reference to FIG1A . For example, processing system 600 may be used to implement some or all of the processes for analyzing memory cell characterization results and determining which reference currents to apply to the memory array being tested. Processing system 600 may also be used to implement portions of the embodiment methods described herein with reference to FIG2A and FIG2B . The processing system 600 may include, for example, a central processing unit (CPU) 602 and a memory 604 connected to a bus 608, and may be configured to execute the processes discussed above according to program instructions stored in the memory 604 or other non-transitory computer-readable media. If desired or necessary, the processing system 600 may also include a display adapter 610 to provide connectivity to a local display 612 and an input / output (I / O) adapter 614 to provide an input / output interface for one or more input / output devices 616, such as a mouse, keyboard, flash drive, or the like. The processing system 600 may also include a network interface 618, which may be implemented using a network adapter for communicating with a network 620, the network adapter being configured to couple to a wired link and / or a wireless / cellular link, such as a network cable, a USB interface, or the like. The network interface 618 may also include a suitable receiver and transmitter for wireless communication. It should be noted that the processing system 600 may include other components. For example, if implemented externally, the processing system 600 may include hardware components such as a power supply, cables, a motherboard, removable storage media, a housing, and the like. Although not shown, these other components are considered part of the processing system 600. In some embodiments, the processing system 600 may be implemented on a single monolithic semiconductor integrated circuit and / or on the same monolithic semiconductor integrated circuit as other disclosed system components. The following summarizes various embodiments of the present invention. Other embodiments can also be understood from the entire specification and claims submitted herein. Example 1. A method for characterizing a non-volatile memory, the method comprising: applying a first voltage to a word line electrically coupled to a non-volatile memory cell; measuring a current flowing through the non-volatile memory cell in response to applying the first voltage, the measuring comprising: using a sense amplifier, comparing the current flowing through the non-volatile memory cell with a plurality of different first currents generated by an adjustable current source when the same first voltage is applied to the word line; and determining the measured current based on the comparison. Example 2. The method of Example 1, further comprising determining whether the measured current falls within a predetermined range. Example 3. The method of Example 1 or 2, further comprising replacing the non-volatile memory cell with a redundant cell when the measured current does not fall within a predetermined range. Example 4. The method of any one of Examples 1 to 3, further comprising setting a memory operating parameter based on the measured current, wherein the memory operating parameter comprises a write duration or a write voltage. Example 5. The method of any one of Examples 1 to 4, wherein the first voltage is a ground voltage. Example 6. The method of any one of Examples 1 to 5, wherein measuring the current flowing through the non-volatile memory cell comprises iteratively adjusting a current generated by the adjustable current source. Example 7. The method of Example 6, wherein iteratively adjusting the current generated by the adjustable current source comprises performing a binary search method. Example 8. The method of Example 6 or 7, wherein iteratively adjusting the current generated by the adjustable current source includes: increasing the current generated by the adjustable current source when the result of the comparison indicates a first comparison result; and decreasing the current generated by the adjustable current source when the result of the comparison indicates a second comparison result opposite to the first comparison result. Example 9. The method of any one of Examples 6 to 8, wherein iteratively adjusting the adjustable current source comprises iteratively adjusting an input word provided to a current digital-to-analog converter. Example 10. The method of any one of Examples 1 to 9, wherein the non-volatile memory includes a plurality of non-volatile memory cells; and the sense amplifier includes a plurality of sense amplifier circuits configured to determine memory states of the plurality of non-volatile memory cells. Example 11. The method of Example 10, further comprising providing outputs of the plurality of sense amplifier circuits to an external data bus. Example 12. The method of Example 10 or 11, wherein the plurality of non-volatile memory cells are arranged in a row in a memory array; and the method further comprises measuring the current flowing through the non-volatile memory cells in at least a portion of the row of the memory array. Example 13. The method of Example 12, wherein measuring the current flowing through the non-volatile memory cells in at least a portion of the column of the memory array comprises selecting the non-volatile memory cells using a row decoder. Example 14. A memory system comprising: an integrated circuit including: a memory array comprising non-volatile memory cells; a plurality of word line drivers coupled to the memory array; a plurality of sense amplifiers coupled to the memory array and to an external data bus; an adjustable current source coupled to the plurality of sense amplifiers; and a first control circuit configured to: set the adjustable current source to a test current and apply a first address to the memory array to select a column of the non-volatile memory cells; and a second control circuit configured to read an output of the sense amplifier and repeatedly update the test current based on the output of the sense amplifier to determine a current flowing through at least one of the non-volatile memory cells in the column. Example 15. The memory system of Example 14, wherein the second control circuit is disposed on the integrated circuit. Example 16. The memory system of Example 15, wherein the second control circuit is external to the bulk circuit. Example 17. The memory system of Example 15 or 16, wherein the second control circuit is configured to read the output of the sense amplifier via the external data bus. Example 18. The method of any one of Examples 14 to 17, wherein each word line driver of the plurality of word line drivers comprises: a first transistor coupled between a word line and a positive power supply node; and a second transistor coupled between the word line and a negative power supply node, wherein the word line is coupled only to the positive power supply node and to the negative power supply node via the first transistor and the second transistor, respectively. Example 19. The memory system of Example 18 further comprises: a first level shifter coupled to the first transistor; and a second level shifter coupled to the second transistor; and wherein the word line driver does not include any additional level shifting circuitry other than the first level shifter and the second level shifter. Example 20. The memory system of any one of Examples 14 to 19, wherein the adjustable current source comprises a current digital-to-analog converter. Example 21. The memory system of any one of Examples 14 to 20, wherein the non-volatile memory cell comprises a silicon-oxygen-nitride-oxygen-silicon (SONOS) memory cell. Example 22. A method of characterizing a non-volatile memory, the method comprising: operating the non-volatile memory in a test mode, the method comprising: performing a test read of the non-volatile memory, the method comprising: applying a column address to the non-volatile memory to select a column of non-volatile memory cells; grounding a word line coupled to the selected column of non-volatile memory cells; measuring a current of at least one non-volatile memory cell in the column of non-volatile memory cells with the grounded word line; and incrementing the column address; and repeatedly performing the test read using the incremented column address. Example 23. The method of Example 22, wherein the method further comprises: applying a row position after applying the column address to select a subset of the selected column of non-volatile memory cells; incrementing the row position after measuring the current and before incrementing the column address; and after incrementing the row position and before incrementing the column address, when the selected column of non-volatile memory cells is not completely read, repeatedly performing the test read using the incremented row position. Example 24. The method of any one of Examples 22 to 23, further comprising: determining a non-functional non-volatile memory cell in the non-volatile memory based on measuring the current; or determining an operating memory parameter based on measuring the current. Example 25. The method of any one of Examples 22 to 24, wherein measuring the current of the at least one non-volatile memory cell comprises: applying a reference current to a sense amplifier coupled to the at least one non-volatile memory cell to generate a sense amplifier output; adjusting the reference current based on the sense amplifier output; and repeatedly applying and adjusting the reference current to estimate the current of the at least one non-volatile memory cell. Example 26. The method of Example 25, wherein repeatedly applying the reference current and adjusting the reference current are performed according to a linear search method or a binary search method. Example 27. The method of any one of Examples 22 to 26, wherein the at least one nonvolatile memory cell in the column of nonvolatile memory cells comprises a nonvolatile memory cell having a maximum or minimum threshold value among the nonvolatile memory cells in the column of nonvolatile memory cells. Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the present invention, will become apparent to those skilled in the art upon reference to this specification. Accordingly, the appended claims are intended to cover any such modifications or embodiments. 100: Integrated Circuit 102: Row Decoder 103: Word Line Driver 104: (Non-Volatile) Memory Array 105: Memory Cell 106: Controller 108: Reference Current Generator 110: Row Decoder 112: Sense Amplifier 114: I / O Logic 116: Test Controller 118: BIST Circuit / BIST 120: Tester 132: When a memory cell is written to a "0" state 134: When a memory cell is written to a "1" state 136: Abnormal value measurement / abnormal memory cell / memory cell / abnormal value 138: Bit / cell 200: Method 202, 204, 206, 208, 210, 212, 213, 214, 216, 218, 220, 232, 234: Step 230: Method 300: Memory sensing system 302: Sense amplifier 320: Word line driver 322: Negative level shifter 324: Positive level shifter 326: Low voltage column control block 360: CDAC circuit / CDAC 362: p-channel MOS transistor 364: p-channel MOS transistor 366: p-channel MOS transistor 368: selected transistor 370: transistor 372: transistor 374: selected transistor 376: transistor 378: transistor 380: selected transistor 382: transistor 384: transistor 600: processing system 602: central processing unit (CPU) 604: memory 608: bus 610: display adapter 612: local display 614: input / output (I / O) adapter 616: input / output device 618: network interface 620: network P1-P7: p-channel MOS devices N1, N2, N4, N5: n-channel MOS transistors For a more complete understanding of the present invention and its advantages, reference will be made to the following description taken in conjunction with the accompanying drawings, in which: FIG. 1A is a block diagram illustrating an embodiment of a memory system; and FIG. 1B is a diagram illustrating an exemplary read current distribution for N memory cells. [FIG. 2A] and [FIG. 2B] are flowcharts showing a method according to an embodiment of the present invention; [FIG. 3A] A block diagram showing the operation of a sense amplifier according to an embodiment; FIG3B is a schematic diagram showing a word line driver according to an embodiment; FIG3C is a schematic diagram showing a conventional word line driver; FIG3D and FIG3E are schematic diagrams showing exemplary level shifters; FIG3F is a schematic diagram showing an embodiment of a reference current generator; [Fig. 4] shows a timing diagram according to an embodiment; [FIG. 5A], [FIG. 5B], and [FIG. 5C] illustrate exemplary memory cells that may be used to implement a non-volatile memory array according to an embodiment of the present invention; FIG5D is a cross-sectional view showing an embodiment of an N-type SONOS transistor; and [FIG. 6] shows a processing system that can be used to implement part of the embodiment system. Unless otherwise indicated, corresponding numerals and symbols in the various figures generally refer to corresponding parts. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale. To more clearly illustrate certain embodiments, letters indicating variations of the same structure, material, or process step may follow a number. 200:Method 202, 204, 206, 208, 210, 212, 213, 214, 216, 218, 220: Steps

Claims

1. A method for characterizing non-volatile memory, the method comprising: A first voltage is applied to the word line, which is electrically coupled to a non-volatile memory cell; And in response to applying the first voltage, measuring the current flowing through the non-volatile memory cell, the measurement comprising: using a sensing amplifier, comparing the current flowing through the non-volatile memory cell with a plurality of different first currents generated by an adjustable current source when the same first voltage is applied to the word line; and determining the measured current based on the comparison, wherein measuring the current flowing through the non-volatile memory cell includes iteratively adjusting the plurality of different first currents generated by the adjustable current source.

2. The method of claim 1, further comprising determining whether the measured current falls within a predetermined range.

3. The method of claim 2, further comprising replacing the non-volatile memory cell with a redundant cell when the measured current does not fall within the predetermined range.

4. The method of claim 1, further comprising setting memory operating parameters based on the measured current, wherein the memory operating parameters include write duration or write voltage.

5. The method as described in claim 1, wherein the first voltage is a ground voltage.

6. The method as described in claim 1, wherein iteratively adjusting the plurality of different first currents generated by the adjustable current source includes performing a binary search method.

7. The method as described in claim 1, wherein iteratively adjusting the plurality of different first currents generated by the adjustable current source comprises: When the comparison result indicates a first comparison result that produces a high logic value for the non-volatile memory cell through which the current flows, the current generated by the adjustable current source is increased; and when the comparison result indicates a second comparison result that produces a low logic value for the non-volatile memory cell through which the current flows, the current generated by the adjustable current source is decreased.

8. The method of claim 1, wherein iteratively adjusting the adjustable current source includes iteratively adjusting the input characters provided to the current digital-to-analog converter.

9. The method as described in request item 1, wherein: The non-volatile memory includes a plurality of non-volatile memory cells; and the sensing amplifier includes a plurality of sensing amplifier circuits configured to determine the memory state of the plurality of non-volatile memory cells.

10. The method of claim 9, further comprising providing the outputs of the plurality of sense amplifier circuits to an external data bus.

11. The method as described in request item 9, wherein: The plurality of non-volatile memory cells are arranged in a column in a memory array; and the method further includes measuring the current flowing through at least a portion of the plurality of non-volatile memory cells in the column of the memory array.

12. The method of claim 11, wherein measuring the current flowing through at least a portion of the plurality of non-volatile memory cells in the column of the memory array includes using a row decoder to select the plurality of non-volatile memory cells.

13. A memory system comprising: An integrated circuit includes: a memory array comprising non-volatile memory cells; a plurality of word line drivers coupled to the memory array; a plurality of sense amplifiers coupled to the memory array and coupled to an external data bus; an adjustable current source coupled to the plurality of sense amplifiers; a first control circuit configured to: set the adjustable current source as a test current and apply a first address to the memory array to select a column of the non-volatile memory cells; and a second control circuit configured to: read the outputs of the plurality of sense amplifiers and iteratively update the test current based on the outputs of the plurality of sense amplifiers to determine the current flowing through at least one non-volatile memory cell in the column of non-volatile memory cells.

14. The memory system as claimed in claim 13, wherein the second control circuit is disposed on the integrated circuit.

15. The memory system as claimed in claim 14, wherein the second control circuit is external to the integrated circuit.

16. The memory system of claim 15, wherein the second control circuitry is configured to read the outputs of the plurality of sense amplifiers via the external data bus.

17. The memory system of claim 13, wherein each of the plurality of word line drivers comprises: The first transistor is coupled between the word line and the positive power node; And a second transistor coupled between the word line and the negative power node, wherein the word line is coupled only to the positive power node and the negative power node via the first transistor and the second transistor, respectively.

18. The memory system as claimed in claim 17, further comprising: A first quasi-displacement device is coupled to the first transistor; and a second quasi-shifter coupled to the second transistor, wherein the word line driver does not include any additional quasi-shifter circuitry other than the first and second quasi-shifters.

19. The memory system of claim 13, wherein the adjustable current source includes a current digital-to-analog converter.

20. The memory system of claim 13, wherein the non-volatile memory cell comprises a silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

21. The memory system of claim 13, wherein the second control circuit is further configured to set memory operating parameters based on the determined current, and wherein the memory operating parameters include write duration or write voltage.

22. A method for characterizing non-volatile memory, the method comprising: Operating the non-volatile memory in test mode includes: performing a test read of the non-volatile memory, which includes: applying a column address to the non-volatile memory to select a column of non-volatile memory cells; grounding a word line coupled to the selected column of non-volatile memory cells; measuring the current of at least one non-volatile memory cell in the column of non-volatile memory cells having the grounded word line; and incrementing the column address; and repeating the test read using the incremented column address.

23. The method as described in claim 22, wherein the method further comprises: After applying the column address, apply the row position to select a subset of the selected column non-volatile memory cells; After measuring the current and before incrementing the column address, increment the row position; and after incrementing the row position and before incrementing the column address, repeat the test read using the incremented row position if the selected column non-volatile memory cell has not been fully read.

24. The method as described in claim 22, further comprising: The non-functional non-volatile memory cells in the non-volatile memory are determined based on the measurement of the current. Alternatively, the operating memory parameters can be determined based on the measurement of the current.

25. The method of claim 22, wherein measuring the current of the at least one non-volatile memory cell comprises: A reference current is applied to a sense amplifier coupled to the at least one non-volatile memory cell to generate a sense amplifier output; The reference current is adjusted based on the output of the sensing amplifier. And repeatedly apply the reference current and adjust the reference current to estimate the current of the at least one non-volatile memory cell.

26. The method of claim 25, wherein the repeated application of the reference current and the adjustment of the reference current are performed according to a linear search method or a binary search method.

27. The method of claim 22, wherein the at least one non-volatile memory cell in the column of non-volatile memory cells includes a non-volatile memory cell having a maximum or minimum threshold value among the non-volatile memory cells in the column of non-volatile memory cells.

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