Method of fabricating semiconductor structure

Abstract

This invention provides a method for manufacturing a semiconductor structure. The method includes forming an epitaxial layer over a semiconductor substrate; forming a first patterned hard mask over the epitaxial layer; performing a first implantation process through the first patterned hard mask to form a first doped region in the epitaxial layer; performing a second implantation process through the first patterned hard mask to form a second doped region in the epitaxial layer, wherein the first doped region and the second doped region at least partially overlap; forming a second patterned hard mask surrounding the first patterned hard mask and covering at least a portion of the first doped region; and performing a third implantation process through the second patterned hard mask to form a third doped region in the epitaxial layer.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor structure, in particular to a method for forming a self-aligned doping region in a semiconductor structure. Prior Art

[0002] Silicon carbide (SiC) material boasts performance several times greater than that of traditional silicon in terms of field strength, band gap, and thermal conductivity. This makes semiconductor structures made of SiC more suitable for high-voltage, high-temperature, and high-frequency environments, meeting the demands of power electronics technology and becoming a preferred choice for high-power converters. Compared to high-power metal oxide semiconductor field-effect transistors (MOSFETs) made of traditional silicon, MOSFETs made of SiC offer higher voltage resistance and high switching speeds not available in silicon-based insulated gate bipolar junction transistors (IGBTs), making them suitable for high-voltage and high-frequency applications. Summary of the Invention

[0003] An embodiment of the present invention provides a method for manufacturing a semiconductor structure, comprising: forming an epitaxial layer above a semiconductor substrate; forming a first patterned hard mask above the epitaxial layer; performing a first implantation process through the first patterned hard mask to form a first doped region in the epitaxial layer; performing a second implantation process through the first patterned hard mask to form a second doped region in the epitaxial layer, the first doped region and the second doped region at least partially overlapping; forming a second patterned hard mask surrounding the first patterned hard mask and covering at least a portion of the first doped region; and performing a third implantation process through the second patterned hard mask to form a third doped region in the epitaxial layer.

[0004] An embodiment of the present invention provides another method for manufacturing a semiconductor structure, comprising: sequentially forming an epitaxial layer and a first patterned hard mask above a semiconductor substrate; performing a first implantation process through the first patterned hard mask to form a first doped region in the epitaxial layer; forming a second patterned hard mask surrounding the first patterned hard mask; performing a second implantation process through the second patterned hard mask to form a second doped region in the epitaxial layer; forming a third patterned hard mask surrounding the second patterned hard mask; and performing a third implantation process through the third patterned hard mask to form a third doped region in the epitaxial layer.

[0005] An embodiment of the present invention provides another method for manufacturing a semiconductor structure, which includes: sequentially forming an epitaxial layer and a first patterned hard mask above a semiconductor substrate; forming a second patterned hard mask surrounding the first patterned hard mask; performing a first implantation process through the second patterned hard mask to form a first doped region in the epitaxial layer; removing the second patterned hard mask; performing a second implantation process through the first patterned hard mask to form a second doped region surrounding the first doped region in the epitaxial layer; removing a portion of the first patterned hard mask to form a third patterned hard mask; and performing a third implantation process through the third patterned hard mask to form a third doped region in the epitaxial layer, the third doped region at least partially overlapping with the second doped region.

[0006] The manufacturing method of the semiconductor structure of the present invention uses a patterned hard mask pattern as a mask layer and forms a doping region or an adjustment region by self-aligned implantation of doping ions, which can accurately locate the doping position and reduce mis-alignment. Simple diagram description

[0007] FIG1 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present invention. FIG. 2 shows a flow chart of a method for manufacturing a semiconductor structure according to some embodiments of the present invention. 3 to 5 are schematic cross-sectional views of various intermediate steps in a process of manufacturing a semiconductor structure according to some embodiments of the present invention. FIG6 is a schematic diagram showing the implantation tilt angle and twist angle according to the present invention. 7 to 12 are schematic cross-sectional views of various intermediate steps in a process of manufacturing a semiconductor structure according to some embodiments of the present invention. FIG. 13 shows a flow chart of a method for fabricating a semiconductor structure according to some embodiments of the present invention. 14 to 17 are schematic cross-sectional views illustrating various intermediate steps in a process of manufacturing a semiconductor structure according to some embodiments of the present invention. FIG. 18 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present invention. FIG. 19 is a flow chart illustrating a method for fabricating a semiconductor structure according to some embodiments of the present invention. 20 to 24 are schematic cross-sectional views illustrating various intermediate steps in a process of manufacturing a semiconductor structure according to some embodiments of the present invention. FIG. 25 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present invention. FIG. 26 shows a flow chart of a method for fabricating a semiconductor structure according to some embodiments of the present invention. 27 to 31 are schematic cross-sectional views illustrating various intermediate steps in a process of manufacturing a semiconductor structure according to some embodiments of the present invention. FIG. 32 shows a flow chart of a method for fabricating a semiconductor structure according to some embodiments of the present invention. 33 to 39 are schematic cross-sectional views illustrating various intermediate steps in a process of manufacturing a semiconductor structure according to some embodiments of the present invention. FIG40 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present invention. FIG. 41 is a flow chart illustrating a method for fabricating a semiconductor structure according to some embodiments of the present invention. 42 to 52 are schematic cross-sectional views illustrating various intermediate steps in a process of manufacturing a semiconductor structure according to some embodiments of the present invention. FIG53 is a schematic cross-sectional view of a semiconductor structure according to some embodiments of the present invention. FIG. 54 shows a flow chart of a method for fabricating a semiconductor structure according to some embodiments of the present invention. 55 to 60 are schematic cross-sectional views illustrating various intermediate steps in a process of manufacturing a semiconductor structure according to some embodiments of the present invention. Implementation Method

[0008] Various aspects of the present disclosure are best understood from the following detailed description accompanied by the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the sizes of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0009] The following disclosure provides many different implementations or examples for achieving different features of the provided subject matter. To simplify the disclosure, specific examples of components and configurations are described below. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, a first feature formed above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, the disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the sake of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0010] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "below," "above," "above," and the like may be used herein to describe one element or component's relationship to another element or component illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted similarly.

[0011] As used herein, terms such as "first," "second," and "third" describe various elements, components, regions, layers, and / or sections, but such elements, components, regions, layers, and / or sections should not be limited by such terms. Such terms are only used to distinguish one element, component, region, layer, or section from another. Terms such as "first," "second," and "third" when used herein do not imply a sequence or order unless clearly indicated by the context.

[0012] The singular forms "a," "an," and "the" may also include plural forms unless the context clearly indicates otherwise. The term "connected," along with its derivatives, may be used herein to describe structural relationships between components. "Connected" may be used to describe two or more elements in direct physical or electrical contact with each other. "Connected" may also be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other (with intervening elements between them), and / or that the two or more elements cooperate or interact with each other.

[0013] FIG1 illustrates a schematic cross-sectional view of a semiconductor structure 100 according to some embodiments of the present invention. Referring to FIG1 , semiconductor structure 100 may be a power metal-oxide-semiconductor field-effect transistor (MOSFET). Semiconductor structure 100 may include a substrate 102, an epitaxial layer 104, a protective layer 106, multiple channel adjustment regions 112, multiple well regions 114, multiple heavily doped regions 116, a gate dielectric layer 122, a gate electrode 124, a source region 126A, a drain region 126B, a metal silicide region 130, and an interconnect structure 140. In some embodiments, channel adjustment regions 112 may also be referred to as first doped regions, well regions 114 may also be referred to as second doped regions, and heavily doped regions 116 may be referred to as third doped regions.

[0014] Substrate 102 is a semiconductor substrate, such as a silicon carbide substrate. An epitaxial layer 104 is disposed above substrate 102. Epitaxial layer 104 can be composed of a single or multiple layers of silicon carbide and can serve as the drift region of a power metal oxide semiconductor field effect transistor. A channel adjustment region 112, a well region 114, a heavily doped region 116, a source region 126A, and a drain region 126B are each disposed within epitaxial layer 104 and can be formed by ion implantation. A gate dielectric layer 122, a gate electrode 124, a metal silicide region 130, and an interconnect structure 140 are each disposed above epitaxial layer 104.

[0015] In some embodiments, the channel adjustment region 112 extends downward from the top surface of the epitaxial layer 104 (away from the surface of the substrate 102) to a first depth D1, the well region 114 extends downward from the top surface of the epitaxial layer 104 to a second depth D2, and the heavily doped region 116 extends downward from the top surface of the epitaxial layer 104 to a third depth D3. The first depth D1 is less than the second depth D2, and the third depth D3 is greater than the first depth D1 and less than the second depth D2. Furthermore, the source region 126A and the drain region 126B may extend downward from the top surface of the epitaxial layer 104 to a depth equal to or slightly less than the third depth D3.

[0016] The well regions 114 in the semiconductor structure 100 are spaced apart from each other in a first direction X, and each heavily doped region 116 is surrounded by a well region 114. The well regions 114 include impurities of a first conductivity type, while the heavily doped regions 116 include impurities of a second conductivity type, which is different from the first conductivity type. In some embodiments, the first conductivity type is P-type and the second conductivity type is N-type. Compared to the well regions 114, the heavily doped regions 116 may have a higher doping concentration.

[0017] The well regions 114 may be spaced apart by a first pitch P1 along the first direction X, and the heavily doped regions 116 may be spaced apart by a second pitch P2 along the first direction X, where the second pitch P2 is greater than the first pitch P1. In some embodiments, the well regions 114 and the heavily doped regions 116 are U-shaped when viewed in a cross-sectional view (in the XZ direction), and the distance from the left edge of the heavily doped region 116 to the left edge of the well region 114 is approximately equal to the distance from the right edge of the heavily doped region 116 to the right edge of the well region 114.

[0018] Each well region 114 also surrounds at least one channel adjustment region 112. The channel adjustment region 112 may extend inward from the edge of the well region 114 into the heavily doped region 116, thereby partially overlapping the well region 114 and the heavily doped region 116. The channel adjustment region 112 may have a rectangular cross-section or a rounded rectangular cross-section (viewed from the XZ direction). In some embodiments, the impurities in the channel adjustment region 112 may be selected from the nitrogen group (e.g., nitrogen, phosphorus, etc.), the boron group (boron, aluminum, etc.), or boron difluoride. The channel adjustment region 112 may have a doping concentration of 1×10 13 cm -2 to 1×10 15 cm -2.

[0019] The protective layer 106 covers the top surface of the epitaxial layer 104. For example, the protective layer 106 is a silicon-containing layer. A gate dielectric layer 122 is disposed between the protective layer 106 and the gate electrode 124. The gate dielectric layer 122 and the gate electrode 124 disposed above the protective layer 106 may extend continuously from approximately the middle of one heavily doped region 116 to approximately the middle of an adjacent heavily doped region 116. The gate dielectric layer 122 may be formed of silicon oxide (Si x O y , such as SiO 2 ), silicon nitride (Si x N y , such as Si 3 N 4 ), silicon oxynitride (SiO x N y ), or other dielectric materials. In some embodiments, the thickness of the gate dielectric layer 122 may range from approximately 10 angstroms (Å) to approximately 1000 Å. The gate electrode 124 may include polysilicon or metal.

[0020] The source region 126A and the drain region 126B are disposed in the epitaxial layer 104 at opposite ends of the gate electrode 124. A fourth spacing P4 is present between the edge of the source region 126A and the edge of the gate dielectric layer 122 or the gate electrode 124. The edge of the drain region 126B is also spaced a fourth spacing P4 from the edge of the gate dielectric layer 122 or the gate electrode 124. The source region 126A may partially overlap with the well region 114 and the heavily doped region 116 located to the left of the gate electrode 124, while the drain region 126B may partially overlap with the well region 114 and the heavily doped region 116 located to the right of the gate electrode 124. In some embodiments, the source region 126A extends outward into the well region 114 and the heavily doped region 116 located on the leftmost side of FIG. 1 and without any overlap with the gate dielectric layer 122 and / or the gate electrode 124, and the drain region 126B extends outward into the well region 114 and the heavily doped region 116 located on the rightmost side of FIG. 1 and without any overlap with the gate dielectric layer 122 and / or the gate electrode 124.

[0021] A metal silicide region 130 may be formed in the protective layer 106 and may contact the source region 126A and the drain region 126B. The metal silicide region 130 is primarily used to reduce the contact resistance between the source region 126A, the drain region 126B, and the interconnect structure 140. In some embodiments, the metal silicide region 130 may be formed in areas of the source region 126A and the drain region 126B that do not overlap with the channel regulating region 112, the well region 114, and the heavily doped region 116. The metal silicide region 130 may include nickel silicide (Ni x Si y), cobalt silicide (Co x Si y), titanium silicide (Ti x Si y), or aluminum silicon carbide (AlSiC). The thickness of the metal silicide region 130 may range from approximately 10 angstroms to approximately 10,000 angstroms.

[0022] The interconnect structure 140 is disposed above the protective layer 106, the gate electrode 124, and the metal silicide region 130 and may include an interlayer dielectric layer 142 and a plurality of conductive features 146. In some embodiments, the interlayer dielectric layer 142 covers the protective layer 106, the metal silicide region 130, and the gate electrode 124. The conductive features 146 may be disposed within or above the interlayer dielectric layer 142 and provide physical and electrical contact with the metal silicide region 130 and the gate electrode 124. The conductive features 146 may have a thickness between approximately 1 micron and approximately 10 microns.

[0023] Conductive feature 146 may include a contact plug 1462 and a conductive line 1464. Contact plug 1462 is located in interlayer dielectric layer 142 and is in physical contact with metal silicide region 130 above source region 126A, metal silicide region 130 above drain region 126B, or gate electrode 124. Conductive line 1464 is disposed above interlayer dielectric layer 142 and contact plug 1462 and is in physical contact with contact plug 1462. The conductive feature 146 contacting gate electrode 124 may be electrically insulated from the conductive feature 146 contacting metal silicide region 130. Although FIG. 1 shows only one interlayer dielectric layer 142 and one conductive feature 146, interconnect structure 140 may include multiple interlayer dielectric layers 142 and multiple conductive features 146.

[0024] In some embodiments, contact plug 1462 and conductive line 1464 may be formed from the same metal material, such as copper, aluminum, or an aluminum-copper alloy. Contact plug 1462 and conductive line 1464 may be integrally formed, for example. For example, a deposition process may be used to form a metal material in and above interlayer dielectric layer 142, followed by a patterning process to pattern the metal material above interlayer dielectric layer 142 to form conductive feature 146. The patterning process may include suitable photolithography and etching processes. Contact plug 1462 and conductive line 1464 may be formed in interlayer dielectric layer 142 using, for example, a dual damascene process.

[0025] In some embodiments, contact plug 1462 and conductive line 1464 are formed of different metal materials; for example, contact plug 1462 can be formed of tungsten, and conductive line 1464 can be formed of copper, aluminum, or an aluminum-copper alloy. Contact plug 1462 can be formed using a single damascene process, while conductive line 1464 can be formed using a deposition process and a patterning process.

[0026] The interconnect structure 140 may optionally include one or more diffusion barrier layers 144 disposed at least between the interlayer dielectric layer 142 and the conductive features 146 to prevent the metal material (e.g., copper) of the conductive features 146 from diffusing into the interlayer dielectric layer 24. The diffusion barrier layer 144 may further be disposed between the metal silicide region 130 and the conductive features 146, and between the gate electrode 124 and the conductive features 146, to completely surround the conductive features 146, thereby reducing manufacturing complexity. In some embodiments, a thin seed layer (not shown) may be formed between the diffusion barrier layer 144 and the conductive features 146. The seed layer may include copper or a copper alloy, and may also include metals such as tungsten, silver, gold, aluminum, and combinations thereof.

[0027] The channel region of the semiconductor structure 100 is formed between the source region 126A and the drain region 126B. The channel adjustment region 112 is provided in the channel region and can be used to adjust the doping concentration distribution in the channel region, thereby changing the channel resistance value of the semiconductor structure 100. Therefore, the semiconductor structure 100 can accurately control the threshold voltage during high-speed, low-power or depletion mode operation.

[0028] FIG2 is a flow chart of a method 200 for fabricating a semiconductor structure 100 according to some embodiments of the present disclosure. Method 200 is merely an example and is not intended to limit the present disclosure beyond the scope expressly recited in the claims. Additional steps may be provided before, during, or after method 200, and some of the steps described may be moved, replaced, or omitted for additional embodiments of method 200. Method 200 is described below in conjunction with other figures, which illustrate schematic cross-sectional views during various intermediate steps of method 200.

[0029] Referring to FIG. 2 and FIG. 3 , method 200 begins at step S210 by forming an epitaxial layer 104 on a semiconductor substrate 102. Substrate 102 may, for example, comprise a semiconductor material. In some embodiments, substrate 102 may be a doped or undoped semiconductor substrate. The semiconductor material of substrate 102 may include silicon, germanium, or a compound semiconductor (e.g., silicon carbide).

[0030] Epitaxial layer 104 is a semiconductor layer. In some embodiments, epitaxial layer 104 may include, for example, silicon carbide. Epitaxial layer 104 can be used to adjust performance; for example, the breakdown voltage can be increased by increasing the channel length using vertical dimensions. Increasing the thickness of epitaxial layer 104 increases the breakdown voltage, while decreasing the thickness of epitaxial layer 104 decreases the breakdown voltage. Epitaxial layer 104 can be formed using, for example, an epitaxial process. For example, epitaxial processes include chemical vapor deposition (CVD), molecular beam epitaxy (MBE), and / or other suitable processes. Epitaxial layer 106 can be a doped or undoped semiconductor layer. When epitaxial layer 106 is a doped semiconductor layer, a blanket implant can be performed to form a lightly doped layer (not shown) in epitaxial layer 104. The lightly doped layer may, for example, have a different conductivity type than the epitaxial layer 106, allowing for adjustment of the epitaxial profile without affecting the conductivity type of the epitaxial layer 104. For example, the epitaxial layer 104 may have an N-type conductivity type, while the lightly doped layer may have a P-type conductivity type. In some embodiments, the substrate 102 may have the same conductivity type as the epitaxial layer 106.

[0031] Next, in step S212, a protective layer 106 and a first hard mask layer 310 are formed over the epitaxial layer 104. The protective layer 106 may be a dielectric layer. The protective layer 106 may be formed of a low-k dielectric material, such as silicon dioxide (SiO2). The protective layer 106 may be deposited on the epitaxial layer 104 using, for example, a spin-on coating process, a chemical vapor deposition process, a plasma-enhanced chemical vapor deposition (PECVD) process, a low-pressure chemical vapor deposition (LPCVD) process, or a thermal oxidation process. Furthermore, the protective layer 106 may be formed of various suitable materials, such as an extremely low-k dielectric (ELK) material, a polymer (e.g., polyimide), or a combination thereof.

[0032] The first hard mask layer 310 is a single-layer structure. In some embodiments, the thickness of the first hard mask layer 310 is not less than 3 microns (µm). The first hard mask layer 310 can be formed of a dielectric material, which may include silicon oxide, silicon nitride, silicon oxynitride, hafnium dioxide (HfO2), zirconium dioxide (ZrO2), or aluminum oxide (Al2O3), but the present disclosure is not limited thereto. In some embodiments, the first hard mask layer 310 may include a semiconductor material, such as silicon. The first hard mask layer 310 can be formed by a suitable process, such as a spin coating process, a chemical vapor deposition process, a sputtering process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, and / or other suitable processes. There is an appropriate etching selectivity ratio between the protection layer 106 and the first hard mask layer 310; therefore, the protection layer 106 can act as an etching stop layer, so that subsequent processes can be well controlled.

[0033] In some embodiments, a photoresist layer (not shown) may be disposed over the first hard mask layer 310. The photoresist layer comprises a photoresist material operable to be patterned by radiation. In some embodiments, the photoresist layer is applied to the surface of the first hard mask layer 310, for example, by spin coating. An exposure process is then performed to expose portions of the photoresist layer to radiation energy, such as ultraviolet (UV), deep ultraviolet (DUV), or extreme ultraviolet (EUV). Because the photoresist layer is sensitive to radiation energy, the portions of the photoresist layer exposed to the radiation energy undergo a chemical change. A development process is then performed to dissolve portions of the photoresist layer exposed to the radiation energy or portions not exposed to the radiation energy (depending on whether a positive-tone or negative-tone photoresist is used in the photoresist layer), thereby forming a patterned photoresist 300 that exposes portions of the first hard mask layer 310.

[0034] Referring to FIG. 2 through FIG. 4 , in step S214 , the patterned photoresist 300 is used as an etching mask to remove the exposed portions of the first hard mask layer 310 , thereby forming a first patterned hard mask 312 . In some embodiments, the first patterned hard mask 312 , which exposes the patterned photoresist layer 300 , is removed by an etching process until the protective layer 106 is reached and exposed. The etching process may include performing a wet etching process, a dry etching process, another suitable etching process, or any combination thereof. Subsequently, the patterned photoresist 300 is removed, for example, by an ashing or stripping process.

[0035] Referring to Figures 2 and 5, in step S216, a first implantation process is performed through the first patterned hard mask 312 to form a plurality of channel adjustment regions 112 in the epitaxial layer 104. The first implantation process can be performed one or more times to implant impurities into the epitaxial layer 104, thereby forming a plurality of channel adjustment regions 112 spaced apart from one another in the first direction X. The first implantation process uses the first patterned hard mask 312 as an implantation mask to implant specific impurity atoms into designated regions of the epitaxial layer 104 through ion acceleration, thereby altering the conductive properties of the designated regions and thereby adjusting the performance of the semiconductor structure 100. In this embodiment, the channel adjustment regions 112 can be formed in the epitaxial layer 104 on both sides of the bottom of the first patterned hard mask 312 and can be used to modulate the resistance of the channel of the semiconductor structure 100. The specific impurity atoms can be selected from the nitrogen group (e.g., nitrogen, phosphorus, etc.), the boron group (e.g., boron, aluminum, etc.), or boron difluoride.

[0036] The first implantation process can be performed at room temperature (e.g., approximately 25 degrees Celsius), or it can be a hot implantation process. Using a hot implantation process to implant impurities helps reduce damage to the epitaxial layer 104 caused by the implanted ions. Precise positioning of the dopant impurities is crucial for ensuring optimal operation of the semiconductor structure 100. In some embodiments, the impurity implantation is performed by tilting the ion beam B relative to the epitaxial layer 104, and this can be repeated by rotating the substrate 102 and epitaxial layer 104.

[0037] Referring to Figure 6 , the first implantation process includes at least one implantation tilt angle θ. For example, an ion beam B is generated by an ion implanter (not shown) and implants impurity atoms into appropriate locations within the epitaxial layer 104 at a specific angle relative to the normal to the wafer processing surface (e.g., the top surface of the epitaxial layer 104) (i.e., the z-axis in this embodiment). The implantation tilt angle θ is the angle formed by the normal and the ion beam B. Varying the implantation tilt angle θ will cause the ion implantation depth to vary, thereby affecting the electrical parameters of the semiconductor structure. In some embodiments, the implantation tilt angle θ can range from 0 degrees to about 45 degrees.

[0038] In some embodiments, the first implantation process further includes a twist angle δ. For example, the position of the ion beam implanted into the epitaxial layer 104 is adjusted by using a line connecting the initial position of the alignment mark AM and the centerline of the semiconductor wafer C as a reference line and rotating the wafer about the centerline of the semiconductor wafer C. The twist angle δ is the angle formed by the aforementioned reference line and the projection line (indicated by a dashed line) of the ion beam B on the semiconductor wafer C. The twist angle δ can range from 0 degrees to 360 degrees, and the semiconductor wafer C can be rotated clockwise or counterclockwise. Controlling the implantation tilt angle θ and the twist angle δ allows for implanting a sufficient dose of impurities into appropriate locations in the epitaxial layer 104.

[0039] Referring to FIG. 2 and FIG. 7 , in step S218, a second implantation process is performed using the first patterned hard mask 312 as a mask layer to form a plurality of well regions 114 in the epitaxial layer 106. In some embodiments, the plurality of well regions 114 are spaced apart from one another in the first direction X, the channel adjustment region 112 is located above the well regions 114, and each well region 114 at least partially overlaps with two channel adjustment regions 112. In some embodiments, each well region 114 surrounds two channel adjustment regions 112. The second implantation process may implant impurities having a first conductivity type into the epitaxial layer 104 at an implantation tilt angle θ of approximately 0 degrees. In some embodiments, the first conductivity type is P-type.

[0040] Referring to FIG. 2 and FIG. 8 , in step S220, a second hard mask layer 314 is formed over the protective layer 106 and the first patterned hard mask layer 312. The thickness of the second hard mask layer 314 is less than that of the first patterned hard mask layer 312, and the second hard mask layer 314 substantially conforms to the shapes of the protective layer 106 and the first patterned hard mask layer 312. The term "conformal," as used herein, means that the horizontal portion of the second hard mask layer 314 (i.e., the portion extending in the first direction X) is substantially parallel to the top surfaces of the protective layer 106 and the first patterned hard mask layer 312, and the vertical portion of the second hard mask layer 314 (i.e., the portion extending in the second direction Y) is substantially parallel to the side surfaces of the first patterned hard mask 312. The first patterned hard mask 312 and the second hard mask layer 314 have different material compositions, and an appropriate etching selectivity is achieved between the first patterned hard mask 312 and the second hard mask layer 314. The second hard mask layer 312 can be formed from a dielectric material or a semiconductor material, for example, through a chemical vapor deposition process. The dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, hafnium dioxide, zirconium dioxide, aluminum oxide, etc., while the semiconductor material may be, for example, silicon. The protective layer 106 and the second hard mask layer 314 have an appropriate etch selectivity; therefore, the protective layer 106 can serve as an etch stop layer, ensuring good control of subsequent processes.

[0041] 2 and 9 , in step S222, the second hard mask layer 314 is anisotropically etched to form a second patterned hard mask 316 surrounding the first patterned hard mask 312. The anisotropic etching can remove the second hard mask layer 314 disposed on the top surface of the protective layer 106 and the top surface of the first patterned hard mask 312 (i.e., the horizontal portion of the second hard mask layer 314), leaving the second hard mask layer 314 on the side surfaces of the first patterned hard mask 312 (i.e., the vertical portion of the second hard mask layer 314) as the second patterned hard mask 316. In some embodiments, the second patterned hard mask 316 has a shape that tapers from one end; for example, the width of the lower portion of the second patterned hard mask 316 contacting the protective layer 106 is greater than the width of the upper portion of the second patterned hard mask 316 away from the protective layer 106.

[0042] Next, in step S224, a third implantation process is performed using the first patterned hard mask 312 and the second patterned hard mask 316 as mask layers to form a heavily doped region 116 in the epitaxial layer 104. The third implantation process is used to implant impurities having a second conductivity type into the well region 114, thereby forming the heavily doped region 116 surrounded by the well region 114 and partially overlapping the channel adjustment region 112. The second conductivity type is different from the first conductivity type and may be, for example, an N-type. In some embodiments, the third implantation process implants the impurities into the epitaxial layer 104 at an implantation tilt angle θ of approximately 0 degrees.

[0043] Next, in step S226, the first patterned hard mask 312 and the second patterned hard mask 316 are removed. In some embodiments, the first patterned hard mask 312 and the second patterned hard mask 316 are removed using a suitable process, such as multiple wet etching processes. Because the protective layer 106 has a sufficient etching selectivity relative to the first patterned hard mask 312 and the second patterned hard mask 316, the protective layer 106 can serve as an etch stop layer; that is, when the first patterned hard mask 312 and the second patterned hard mask 316 are removed using an etching process, the protective layer 106 is not removed.

[0044] Next, a dielectric layer (not shown) is deposited over the protective layer 106 by, for example, chemical vapor deposition or spin coating, and a conductive layer (not shown) is formed over the dielectric layer by, for example, chemical vapor deposition or sputtering. The dielectric layer substantially covers the entire surface of the protective layer 106, and the conductive layer substantially covers the entire surface of the dielectric layer. The dielectric layer can be formed of silicon oxide, silicon nitride, silicon oxynitride, or other dielectric materials, and the conductive layer can be formed of polysilicon or a metal material.

[0045] Then, the dielectric layer and the conductive layer are patterned to form the gate structure 120 shown in FIG. 10 , wherein the gate structure 120 includes a gate dielectric layer 122 and a gate electrode 124 sequentially formed on the protective layer 106 (step S228 ). In some embodiments, the gate structure 120 can be formed by performing an etching process on the dielectric layer and the conductive layer using a soft mask (e.g., patterned photoresist) formed by a lithography process or a hard mask formed of a dielectric material (e.g., silicon nitride) as an etching mask. The gate structure 120 can extend continuously from the protective layer 106 approximately above the center of one heavily doped region 116 to the protective layer 106 approximately above the center of an adjacent heavily doped region 116 .

[0046] Referring to FIG. 2 and FIG. 11 , in step S230 , a source region 126A and a drain region 126B are formed in the epitaxial layer 114 . In some embodiments, one or more ion implantations can be performed using a patterned photoresist as an implantation mask to introduce dopants into the epitaxial layer 114 to form the source region 126A and the drain region 126B. The source region 126A and the drain region 126 are located on opposite sides of the gate structure 120 and can be spaced apart from the gate structure 120 by a distance d. The source region 126A and the drain region 126 can extend into the heavily doped region 116 , at least partially overlapping the gate structure 120 .

[0047] Next, in step S232, a metal silicide region 130 is formed in the protective layer 106 above the source region 126A and the drain region 126B. The metal silicide region 130 extends through the protective layer 106 and terminates at the top surface of the epitaxial layer 104. In some embodiments, one or more thin metal layers (not shown) can be deposited at specific locations on the protective layer 106 (e.g., locations where the source region 126A and the drain region 126B do not overlap with the channel regulating region 112, the well region 114, and the heavily doped region) and then annealed to allow the thin metal layers to react with the silicon in the protective layer 106, thereby forming the metal silicide region 130 in the protective layer 106. The thin metal layer includes a barrier metal layer such as nickel (Ni), cobalt (Co), titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), and combinations thereof. The thin metal layer can also include a metal carbide such as aluminum carbide (AlC). The protection layer 106 is mainly used to form the metal silicide region 130 . Therefore, in some embodiments, after the metal silicide region 130 is formed, an etching process may be performed to remove the residual (unreacted) protection layer 106 .

[0048] Referring to FIG. 2 , the method continues to step S234 where an interconnect structure 140 is formed on the gate electrode 124 , the source region 126A, and the drain region 126B. Referring now to FIG. 12 , after forming the metal silicide region 130 , an interlayer dielectric layer 142 is formed over the protective layer 106 , the gate electrode 124 , and the metal silicide region 130 using, for example, a chemical vapor deposition process or another suitable process (e.g., a spin-on coating process). The interlayer dielectric layer 142 includes a dielectric material such as silicon dioxide, silicon nitride, a low-K dielectric material, or a combination thereof. A chemical-mechanical planarization (CMP) process may then be performed to planarize the surface of the interlayer dielectric layer 142 . The interlayer dielectric layer 142 may have a thickness between approximately 50 angstroms and approximately 30,000 angstroms.

[0049] Next, a contact hole 143 is formed in the interlayer dielectric layer 142. Forming the contact hole 143 involves etching the interlayer dielectric layer 142 so that the gate electrode 124 and the metal silicide region 130 are exposed through the contact hole 143. The contact hole 143 can be aligned with the metal silicide region 130. In some embodiments, the contact hole 143 has a profile that is wider at the top and narrower at the bottom. The etching process can include one or more etching steps designed to selectively etch the interlayer dielectric layer 142, such as wet etching, dry etching, or a combination thereof.

[0050] Referring back to FIG. 1 , a diffusion barrier layer 144 is deposited on the top surface of the interlayer dielectric layer 142 and in the contact hole 143 using, for example, an atomic layer deposition process or a physical vapor deposition process. The diffusion barrier layer 144 has a substantially uniform thickness such that the diffusion barrier layer 144 substantially conforms to the shapes of the interlayer dielectric layer 142, the metal silicide region 130, and the gate electrode 124. The diffusion barrier layer 144 may include titanium, cobalt, nickel, titanium nitride, tantalum nitride, and the like, and combinations thereof. The diffusion barrier layer 144 may have a thickness between approximately 50 angstroms and approximately 5000 angstroms. In some embodiments, the diffusion barrier layer 144 may not be formed over the gate electrode 124. In these embodiments, a portion of the diffusion barrier layer 144 may be removed by performing a patterning process to expose the gate electrode 124, or a mask layer may be used to shield the gate electrode 124 before depositing the diffusion barrier layer 144, and then the mask layer and the diffusion barrier layer 144 deposited above the mask layer may be removed to expose the gate electrode 124.

[0051] After the formation of the diffusion barrier layer 144 is completed, a conductive material is deposited to fill the contact hole 143. The deposition of the conductive material includes filling the remaining portion of the contact hole 143 using, for example, electroplating, electroless plating, chemical vapor deposition, etc. A planarization process, such as a chemical mechanical polishing process or a mechanical polishing process, may be performed to remove excess conductive material, or a lithography and etching process may be performed to pattern the conductive material and the diffusion barrier layer 144 and expose a portion of the interlayer dielectric layer 142, thereby forming the conductive features 144 and the semiconductor structure 100 shown in FIG. FIG. 1 and FIG. 12 only illustrate the method for manufacturing one layer of the interconnect structure 140, and the methods for manufacturing the other layers of the interconnect structure 140 are similar.

[0052] In the present invention, the order of forming the channel adjustment region 112, the well region 114, and the heavily doped region 116 can be changed. For example, the heavily doped region 116 can be formed first using the first patterned hard mask 312 and the second patterned hard mask 316 as mask layers, and then the channel adjustment region 112 and the well region 114 can be formed using the first patterned hard mask 312 as a mask layer. Even in this manner, the function of the semiconductor structure 100 is not affected.

[0053] FIG13 is a flow chart of a method 400 for fabricating a semiconductor structure 100 according to some embodiments of the present disclosure. Method 400 is merely an example and is not intended to limit the present disclosure beyond the scope expressly recited in the claims. Additional steps may be provided before, during, or after method 400, and some of the steps described may be moved, replaced, or omitted for additional embodiments of method 400. Method 400 is described below in conjunction with other figures, which illustrate schematic cross-sectional views during various intermediate steps of method 400.

[0054] Referring to FIG. 13 , method 400 begins at step S410 , where an epitaxial layer is formed over a semiconductor substrate. Method 400 proceeds to step S412 , where a protective layer and a first hard mask layer are formed over the epitaxial layer. Method 400 proceeds to step S414 , where the first hard mask layer is patterned to form a first patterned hard mask that exposes portions of the protective layer. Method 400 proceeds to step S416 , where a second hard mask layer is formed over the protective layer and the first patterned hard mask. Method 400 proceeds to step S418 , where the second hard mask layer is anisotropically etched to form a second patterned hard mask surrounding the first patterned hard mask. Method 400 proceeds to step S420 , where a first implantation process is performed through the second patterned hard mask to heavily dope regions in the epitaxial layer. Method 400 proceeds to step S422 , where the second patterned hard mask is removed. Method 400 continues with step S424, where a second implantation process is performed through the first patterned hard mask to form a well region surrounding the heavily doped region in the epitaxial layer. Method 400 continues with step S426, where a third implantation process is performed through the first patterned hard mask to form a channel adjustment region in the epitaxial layer that partially overlaps the heavily doped region and the well region. Method 400 will be described below with reference to other figures, which illustrate schematic cross-sectional views of semiconductor structure 100 during intermediate steps of method 400.

[0055] Steps S410, S412, and S414 in Figure 13 are respectively the same as steps S210, S212, and S214 in Figure 2, and the specific implementation can be described in conjunction with Figures 3 to 4, respectively, and will not be repeated here.

[0056] 13 and 14 , the method 400 proceeds to step S416 to form a second hard mask layer 314 over the protective layer 106 and the first patterned hard mask 312. The second hard mask layer 314 has a thickness less than that of the first patterned hard mask 312 and is substantially conformal to the shapes of the protective layer 106 and the first patterned hard mask 312.

[0057] 13 and 15 , in step S418, the second hard mask layer 314 is anisotropically etched to form a second patterned hard mask 316 surrounding the first patterned hard mask 312. The anisotropic etching can remove the second hard mask layer 314 disposed on the top surface of the protection layer 106 and the top surface of the first patterned hard mask 312, leaving the second hard mask layer 314 on the side surfaces of the first patterned hard mask 312 as the second patterned hard mask 316.

[0058] Next, in step S420, a first implantation process is performed using the second patterned hard mask 316 as a mask layer to form a plurality of heavily doped regions 116 in the epitaxial layer 104. The plurality of heavily doped regions 116 are spaced apart from each other in the first direction X. In some embodiments, the first implantation process implants impurities into the epitaxial layer 104 at an implantation tilt angle θ of approximately 0 degrees.

[0059] Method 400 continues to step S422, where the second patterned hard mask 316 is removed. In some embodiments, the second patterned hard mask 316 is removed using a suitable process, such as one or more wet etching processes. Because the protective layer 106 and the first patterned hard mask 312 each have a sufficient etching selectivity relative to the second patterned hard mask 316, the protective layer 106 and the first patterned hard mask 312 can serve as etch stop layers; that is, when the second patterned hard mask 316 is removed using an etching process, the protective layer 106 and the first patterned hard mask 312 are not removed.

[0060] 13 and 16 , in step S424, a second implantation process is performed using the first patterned hard mask 312 as a mask layer to form a plurality of well regions 114 surrounding heavily doped regions 116 in the epitaxial layer 106. In some embodiments, the heavily doped regions 116 are located above the well regions 114. The second implantation process implants P-type impurities into the epitaxial layer 104 at an implantation tilt angle θ of approximately 0 degrees.

[0061] 13 and 17 , in step S426, a third implantation process is performed through the first patterned hard mask 312 to form a channel adjustment region 112 in the epitaxial layer 104. The channel adjustment region 112 may be located above the heavily doped region 116 and the well region 114. In some embodiments, the third implantation process is performed by tilting the ion beam B relative to the epitaxial layer 104 to implant impurities. This process may be repeated by rotating the substrate 102 and the epitaxial layer 104 to form the channel adjustment region 112.

[0062] The first patterned hard mask 312 is removed after forming the channel adjustment region 112. For example, the first patterned hard mask 312 can be removed using an etching process or a planarization process.

[0063] The method 400 may further include steps S228 to S234 shown in FIG. 2 , namely, forming a gate dielectric layer 122 and a gate electrode 124 above the protective layer 106, forming a source region 126A and a drain region 126B in the epitaxial layer 104, forming a metal silicide region 130 in the protective layer 106, and forming an interconnect structure 140 above the metal silicide 130 and the gate electrode 124. The specific implementation process can be referred to the description of S228 to S234 above and will not be repeated here.

[0064] FIG18 illustrates a schematic cross-sectional view of a semiconductor structure 500 according to some embodiments of the present invention. Referring to FIG18 , semiconductor structure 500 may include a substrate 502, an epitaxial layer 504, a protective layer 506, multiple electric field adjustment regions 512, multiple well regions 514, multiple heavily doped regions 516, a gate dielectric layer 522, a gate electrode 524, a source region 526A, a drain region 526B, a metal silicide region 530, and an interconnect structure 540. In some embodiments, the electric field adjustment regions 512 may also be referred to as first doped regions, the well regions 514 may also be referred to as second doped regions, and the heavily doped regions 516 may also be referred to as third doped regions.

[0065] Substrate 502 is a semiconductor substrate, such as a silicon carbide substrate. Epitaxial layer 504 is disposed above substrate 102 and may be composed of a single or multiple layers of silicon carbide. Substrate 502 and epitaxial layer 504 may be doped or undoped. Electric field modulation region 512, well region 514, heavily doped region 516, source region 526A, and drain region 526B are disposed within epitaxial layer 504 and may be formed by ion implantation. Gate dielectric layer 522, gate electrode 524, metal silicide region 530, and interconnect structure 540 are disposed above epitaxial layer 504.

[0066] Multiple well regions 514 in the semiconductor structure 500 are spaced apart from one another in a first direction X, and each heavily doped region 516 is surrounded by a well region 514. The well regions 514 may be spaced apart by a first pitch P1 along the first direction X, and the heavily doped regions 516 may be spaced apart by a second pitch P2 along the first direction X, with the second pitch P2 being greater than the first pitch P1. The well regions 514 extend downward from the top surface of the epitaxial layer 504 (away from the surface of the substrate 502) to a second depth D2, and the heavily doped regions 516 extend downward from the top surface of the epitaxial layer 504 to a third depth D3; the second depth D2 is greater than the third depth D3. The well regions 514 may include P-type impurities, and the heavily doped regions 116 may include N-type impurities. Compared to the well regions 114, the heavily doped regions 116 may have a higher doping concentration. In some embodiments, the well region 514 and the heavily doped region 516 are U-shaped as viewed from the cross-sectional schematic diagram, and the distance from the left edge of the heavily doped region 516 to the left edge of the well region 514 is approximately equal to the distance from the right edge of the heavily doped region 516 to the right edge of the well region 514.

[0067] Multiple electric field adjustment regions 512 in the semiconductor structure 500 are spaced apart from each other in a first direction X. The electric field adjustment regions 512 may, for example, be disposed at corners of the heavily doped regions 516 and may extend into the well region 514. In some embodiments, the electric field adjustment regions 512 extend from a fourth depth D4 below the top surface of the epitaxial layer 504 to a fifth depth D5. The fourth depth D4 is less than the third depth D3, and the fifth depth D5 may be equal to or even slightly greater than the third depth D3. The electric field adjustment regions 512 may have an elliptical cross-section. In some embodiments, a first distance A1 is defined between the top of the electric field adjustment region 512 and the edge of the well region 512, and a second distance A2 is defined between the bottom of the electric field adjustment region 512 and the edge of the well region 512. The first distance A1 may be less than the second distance A2, thereby causing the electric field adjustment regions 512 to be tilted. The electric field adjustment region 512 can be used to reduce the electric field on the surface of the heavily doped region 516 or the PN junction formed between the well region 514 and the heavily doped region 516, thereby preventing the semiconductor structure 500 from being broken down.

[0068] The gate dielectric layer 522 and the gate electrode 524 are stacked on the protective layer 506 and may extend continuously from approximately the middle of one heavily doped region 516 to approximately the middle of an adjacent heavily doped region 516. A source region 526A and a drain region 526B are disposed in the epitaxial layer 504 at opposite ends of the gate electrode 524. The source region 526A and the drain region 526B may extend downward from the top surface of the epitaxial layer 504 to a depth equal to or slightly less than a third depth D3. In some embodiments, the source region 526A may partially overlap with the electric field adjustment region 512, the well region 514, and the heavily doped region 516 located to the left of the gate electrode 524, while the drain region 526B may partially overlap with the electric field adjustment region 512, the well region 514, and the heavily doped region 516 located to the right of the gate electrode 524.

[0069] Metal silicide regions 530 may be formed in protective layer 506 and may contact source region 526A and drain region 526B. In some embodiments, metal silicide regions 530 may be formed in regions of source region 526A and drain region 526B that do not overlap with well region 514 and heavily doped region 516, and may primarily serve to reduce contact resistance between source region 526A, drain region 526B, and interconnect structure 540.

[0070] The interconnect structure 540 is disposed above the protective layer 506, the gate electrode 524, and the metal silicide 530, and may include an interlayer dielectric layer 542 and a plurality of conductive features 546. The conductive features 546 physically and electrically connect the gate electrode 524 and the metal silicide 530. The interlayer dielectric layer 542 covers the protective layer 506, the metal silicide region 530, and the gate electrode 524, and surrounds at least a portion of the conductive features 546.

[0071] FIG19 is a flow chart of a method 600 for fabricating semiconductor structure 500 according to some embodiments of the present disclosure. Method 600 is merely an example and is not intended to limit the present disclosure beyond the scope expressly recited in the claims. Additional steps may be provided before, during, or after method 600, and some of the steps described may be moved, replaced, or omitted for additional embodiments of method 600. Method 600 is described below in conjunction with other figures, which illustrate schematic cross-sectional views during various intermediate steps of method 600.

[0072] Referring to FIG. 19 , method 600 begins at step S610 , where an epitaxial layer is formed over a semiconductor substrate. Method 600 proceeds to step S612 , where a protective layer and a first hard mask layer are formed over the epitaxial layer. Method 600 proceeds to step S614 , where the first hard mask layer is patterned to form a first patterned hard mask that exposes portions of the protective layer. Method 600 proceeds to step S616 , where a second hard mask layer is formed over the protective layer and the first patterned hard mask. Method 600 proceeds to step S618 , where the second hard mask layer is anisotropically etched to form a second patterned hard mask surrounding the first patterned hard mask. Method 600 proceeds to step S620 , where a first implantation process is performed through the second patterned hard mask to form a first doped region in the epitaxial layer. Method 600 proceeds to step S622 , where the second hard mask pattern is removed. Method 600 continues to step S624, where a second implantation process is performed through the first patterned hard mask to form a well region surrounding the heavily doped region in the epitaxial layer. Method 600 continues to step S626, where a third implantation process is performed through the first patterned hard mask to form an electric field modulation region at the corner of the heavily doped region. Method 600 will be described below in conjunction with other figures, which illustrate schematic cross-sectional views of semiconductor structure 500 during intermediate steps of method 600.

[0073] Steps S610, S612, and S614 in Figure 19 are respectively the same as steps S210, S212, and S214 in Figure 2, and the specific implementation can be described in conjunction with Figures 3 to 4, respectively, and will not be repeated here.

[0074] 19 and 20 , the method 600 proceeds to step S616 to form a second hard mask layer 314 over the protective layer 506 and the first patterned hard mask 312. The second hard mask layer 314 has a thickness less than that of the first patterned hard mask 312 and is substantially conformal to the shapes of the protective layer 506 and the first patterned hard mask 312.

[0075] 19 and 21 , in step S618, the second hard mask layer 314 is anisotropically etched to form a second patterned hard mask 316 surrounding the first patterned hard mask 312. The anisotropic etching can remove the second hard mask layer 314 disposed on the top surface of the protection layer 506 and the top surface of the first patterned hard mask 312, and leave the second hard mask layer 314 on the side surfaces of the first patterned hard mask 312 as the second patterned hard mask 316.

[0076] 19 and 22 , in step S620, N-type impurities are implanted into the epitaxial layer 504 using the first patterned hard mask 312 and the second patterned hard mask 316 as mask layers, thereby forming a plurality of heavily doped regions 516. In some embodiments, the implantation tilt angle θ of the first implantation process is approximately 0 degrees, so that the impurities are implanted substantially vertically into the epitaxial layer 504.

[0077] The method 600 continues to step S622 by removing the second patterned hard mask 316. In some embodiments, the second patterned hard mask 316 is removed using a suitable process such as one or more wet etching processes.

[0078] Referring to Figures 19 and 23, in step S624, a second implantation process is performed using the first patterned hard mask 320 as a mask layer to implant P-type impurities into the epitaxial layer 506, thereby forming a plurality of well regions 514. Each well region 514 may surround a heavily doped region 516. In some embodiments, the heavily doped region 516 is located above the well region 514, and the heavily doped region 516 and the well region 514 each contact the protective layer 506. In some embodiments, the second conductivity type is P-type. In some embodiments, the second implantation process implants the impurities substantially vertically into the epitaxial layer 504.

[0079] Referring to Figures 18 and 24, in step S626, a third implantation process is performed using the first patterned hard mask 320 as a mask layer to form electric field adjustment regions 512 at the corners of the heavily doped regions 516. In some embodiments, impurity implantation can be performed by tilting the ion beam B relative to the epitaxial layer 104, and this process can be repeated by rotating the substrate 102 and epitaxial layer 104 to form multiple electric field adjustment regions 512 spaced apart from each other in the first direction X. This modifies the electric field distribution of the semiconductor structure 500, thereby improving the breakdown performance of the semiconductor structure 500. The implantation dose of the third implantation process can be from approximately 1×10 13 cm -2 to approximately 1×10 15 cm -2. In some embodiments, the impurity atoms can be selected from the nitrogen group, the boron group, or boron difluoride. The third implantation process can be performed at room temperature, or the third implantation process can be a thermal implantation process.

[0080] Subsequently, the first patterned hard mask 312 is removed. Method 600 may further include steps S228 to S234 shown in FIG. 2 , which may be used to form the gate dielectric layer 522, gate electrode 524, source region 526A, drain region 526B, metal silicide region 530, and interconnect structure 540 shown in FIG. 18 . The specific implementation process can be found in the description of S228 to S234 above and will not be repeated here.

[0081] FIG25 illustrates a schematic cross-sectional view of a semiconductor structure 700 according to some embodiments of the present invention. Referring to FIG25 , semiconductor structure 700 may include a substrate 702, an epitaxial layer 704, a protective layer 706, multiple hot carrier regulation regions 712, multiple well regions 714, multiple heavily doped regions 716, a gate dielectric layer 722, a gate electrode 724, a source region 726A, a drain region 726B, a metal silicide region 730, and an interconnect structure 740. In some embodiments, the heavily doped regions 716 may also be referred to as first doped regions, the well regions 714 may also be referred to as second doped regions, and the hot carrier regulation regions 712 may also be referred to as third doped regions.

[0082] Substrate 702 is a semiconductor substrate, and epitaxial layer 704 is disposed above substrate 702. Substrate 702 and epitaxial layer 704 may comprise silicon carbide. A hot carrier regulation region 712, a well region 714, a heavily doped region 716, a source region 726A, and a drain region 726B are disposed within epitaxial layer 704. A protective layer 706, a gate dielectric layer 722, a gate electrode 724, a metal silicide region 730, and an interconnect structure 740 are disposed above epitaxial layer 704.

[0083] Multiple well regions 714 in the semiconductor structure 700 are spaced apart from each other in the first direction X, and each heavily doped region 716 is surrounded by a well region 714. The well regions 714 may include P-type impurities, and the heavily doped regions 716 may include N-type impurities. Compared to the well regions 114, the heavily doped regions 116 may have a higher doping concentration.

[0084] The well region 714 extends downward from the top surface of the epitaxial layer 704 (the surface away from the substrate 702) to a second depth D2, and the heavily doped region 716 extends downward from the top surface of the epitaxial layer 704 to a third depth D3. The second depth D2 may be greater than the third depth D3. The hot carrier regulation region 712 may, for example, be disposed on the sidewalls of the well region 516 and extend beyond the undoped portion of the epitaxial layer 704. As shown in FIG. 25 , the hot carrier regulation region 712 does not extend into the heavily doped region 716. The hot carrier regulation region 712 may extend downward from the top surface of the epitaxial layer 504 to the second depth D2, or it may be slightly less than the second depth D2 (but not less than the third depth D3), such that substantially the entire sidewalls of the well region 714 are covered by the hot carrier regulation region 712.

[0085] The well region 714 and heavily doped region 716 are U-shaped when viewed in a cross-section (from the XZ direction). The hot carrier regulation region 712 may have an elliptical cross-section, with the long side of the elliptical cross-section extending substantially along the edge of the well region 714. This increases the length of the well region 714 sidewalls covered by the hot carrier regulation region 712, thereby reducing hot carrier injection. In some embodiments, the hot carrier regulation region 712 positioned to the right of the well region 714 may be tilted from the upper right to the lower left, while the hot carrier regulation region 712 positioned to the left of the well region 714 may be tilted from the upper left to the lower right.

[0086] The gate dielectric layer 722 and the gate electrode 724 are stacked on the protective layer 706 and may extend continuously from approximately the middle of one heavily doped region 716 to approximately the middle of an adjacent heavily doped region 716. A source region 726A and a drain region 726B are disposed in the epitaxial layer 704 at opposite ends of the gate electrode 724. In some embodiments, the source region 726A may partially overlap with the hot carrier regulation region 712, the well region 714, and the heavily doped region 716 located to the left of the gate electrode 724, while the drain region 726B may partially overlap with the hot carrier regulation region 712, the well region 714, and the heavily doped region 716 located to the right of the gate electrode 724.

[0087] A metal silicide region 730 may be formed in the protective layer 706 and may contact the source region 726A and the drain region 726B. In some embodiments, the metal silicide region 730 may be formed in regions of the source region 726A and the drain region 726B that do not overlap with the hot carrier regulation region 712, the well region 714, and the heavily doped region 716, and may be used to reduce the contact resistance between the source region 726A and the drain region 726B and the interconnect structure 740.

[0088] The interconnect structure 740 is disposed above the protective layer 706, the gate electrode 724, and the metal silicide 730, and may include an interlayer dielectric layer 742 and a plurality of conductive features 746. The conductive features 746 physically and electrically connect the gate electrode 724 and the metal silicide 730. The interlayer dielectric layer 742 covers the protective layer 706, the metal silicide region 730, and the gate electrode 724, and surrounds at least the lower portion of the conductive features 746.

[0089] FIG26 is a flow chart of a method 800 for fabricating semiconductor structure 700 according to some embodiments of the present disclosure. Method 800 is merely an example and is not intended to limit the present disclosure beyond the scope expressly recited in the claims. Additional steps may be provided before, during, or after method 800, and some of the steps described may be moved, replaced, or omitted for additional embodiments of method 800. Method 800 is described below in conjunction with other figures, which illustrate schematic cross-sectional views during various intermediate steps of method 800.

[0090] Steps S810, S812, and S814 in Figure 26 are respectively the same as steps S210, S212, and S214 in Figure 2, and the specific implementation can be described in conjunction with Figures 3 to 4, respectively, and will not be repeated here.

[0091] 26 and 27 , the method 800 proceeds to step S816 to form a second hard mask layer 314 over the protective layer 706 and the first patterned hard mask 312. The second hard mask layer 314 has a substantially uniform thickness and can conform to the shapes of the protective layer 706 and the first patterned hard mask 312.

[0092] 26 and 28 , in step S818, the second hard mask layer 314 is anisotropically etched to form a second patterned hard mask 316 surrounding the first patterned hard mask 312. The anisotropic etching can remove horizontal portions of the second hard mask layer 314 and leave vertical portions of the second hard mask layer 314 surrounding the sides of the first patterned hard mask 312.

[0093] Next, method 800 proceeds to step S820, where a first implantation process is performed using the first patterned hard mask 312 and the second patterned hard mask 316 as mask layers to implant N-type impurities into the epitaxial layer 704 to form a plurality of heavily doped regions 716 spaced apart and arranged in parallel at predetermined intervals. After the first implantation process is completed, the second patterned hard mask 342 can be removed by one or more etching processes (step S822).

[0094] Referring to Figures 26 and 29, in step S824, a second implantation process is performed using the first patterned hard mask 330 as a mask layer to form a plurality of well regions 714 in the epitaxial layer 706. In some embodiments, the heavily doped regions 716 are located above the well regions 714. The well regions 714 and the heavily doped regions 716 may each contact the protective layer 706. The second implantation process is used to implant P-type impurities into the epitaxial layer 706, thereby forming a P-type well region surrounding the heavily doped regions 716. In some embodiments, the first implantation process and the second implantation process each implant the impurities into the epitaxial layer 104 in a direction substantially perpendicular to the top surface of the epitaxial layer 104.

[0095] 26 and 30 , in step S826, a portion of the first patterned hard mask is removed to form a third patterned hard mask 332. A trimming process may be performed to reduce the width and height of the first patterned hard mask 312, thereby forming the third patterned hard mask 332. In some embodiments, the trimming process may include a dry etching process or a wet etching process.

[0096] Referring to Figures 26 and 31, in step S828, a third implantation process is performed using the third patterned hard mask 332 as a mask layer to form a hot carrier regulation region 712 in the epitaxial layer 704 that at least partially overlaps the sidewalls of the well region 714. In some embodiments, impurity implantation can be performed by tilting the ion beam B relative to the epitaxial layer 104, and this process can be repeated by rotating the substrate 102 and epitaxial layer 104 to form multiple hot carrier regulation regions 712 spaced apart from each other in the first direction X, thereby improving the hot carrier injection problem of the semiconductor structure 500. The implantation dose of the third implantation process can be from approximately 1×10 13 cm -2 to approximately 1×10 15 cm -2. In some embodiments, the impurity atoms can be selected from the nitrogen group, the boron group, or boron difluoride. The third implantation process can be performed at room temperature, or the third implantation process can be a thermal implantation process.

[0097] Afterwards, the third patterned hard mask 332 is removed. In some embodiments, the third patterned hard mask 330 is removed by, for example, a wet etching process or a planarization process. Method 800 may further include steps S228 to S234 shown in FIG. 2 . These steps may be used to form the gate dielectric layer 722, gate electrode 724, source region 726A, drain region 726B, metal silicide region 730, and interconnect structure 740 shown in FIG. 25 . The specific implementation process can be referred to the description of S228 to S234 above and will not be repeated here.

[0098] FIG32 is a flow chart of a method 1000 for fabricating a semiconductor structure 700 according to some embodiments of the present disclosure. Method 1000 is merely an example and is not intended to limit the present disclosure beyond the scope expressly recited in the claims. Additional steps may be provided before, during, or after method 1000, and some of the steps described may be moved, replaced, or omitted for additional embodiments of method 1000. Method 1000 is described below in conjunction with other figures, which illustrate schematic cross-sectional views during various intermediate steps of method 1000.

[0099] Steps S1010, S1012, and S1014 in Figure 32 are respectively the same as steps S210, S212, and S214 in Figure 2, and the specific implementation can be described in conjunction with Figures 3 to 4, respectively, and will not be repeated here.

[0100] Referring to Figures 32 and 33, in step S1016, a first implantation process is performed using the first patterned hard mask 312 as a mask layer to form a plurality of hot carrier modulation regions 712 in the epitaxial layer 704. The first implantation process is used to implant specific impurity atoms into locations on both sides of the bottom of the first patterned hard mask 312 using ion acceleration. In some embodiments, the impurity atoms can be selected from the nitrogen group, the boron group, or boron difluoride. The first implantation process can be performed at room temperature, or the first implantation process can be a thermal implantation process.

[0101] 32 and 34 , the method 1000 proceeds to step S1018, where a second hard mask layer 314 is formed over the protective layer 706 and the first patterned hard mask 312. The second hard mask layer 314 has a thickness less than that of the first hard mask layer 312, and the second hard mask layer 314 is substantially conformal to the shapes of the protective layer 706 and the first patterned hard mask 312.

[0102] 32 and 35 , in step S1020, the second hard mask layer 314 is anisotropically etched to form a second patterned hard mask 316 surrounding the first patterned hard mask 312. The anisotropic etching can remove the second hard mask layer 314 disposed on the top surface of the protection layer 706 and the top surface of the first patterned hard mask 312, and leave the second hard mask layer 314 on the side surfaces of the first patterned hard mask 312 as the second patterned hard mask 316.

[0103] 32 and 36 , in step S1022, a second implantation process is performed using the first patterned hard mask 312 and the second patterned hard mask 316 as mask layers to form a well region 714 in the epitaxial layer 704. The second implantation process implants P-type impurities into the epitaxial layer 704, thereby forming the P-type well region 714. In some embodiments, the second implantation process implants the impurities into the epitaxial layer 704 at an implantation tilt angle θ of approximately 0 degrees.

[0104] 32 and 37 , the method 1000 proceeds to step S1024, where a third hard mask layer 320 is formed over the protective layer 706, the first patterned hard mask 312, and the second patterned hard mask 316. The thickness of the third hard mask layer 320 is less than that of the first patterned hard mask layer 310, and the third hard mask layer 320 is substantially conformal to the shapes of the protective layer 706, the first patterned hard mask 310, and the second patterned hard mask 314.

[0105] 32 and 38 , in step S1026, the third hard mask layer 320 is anisotropically etched to form a third patterned hard mask 322 surrounding the second patterned hard mask 316. The anisotropic etching can remove the third hard mask layer 320 disposed on the top surface of the protective layer 706, the top surface of the first patterned hard mask 312, and the top surface of the second patterned hard mask 316, leaving the third hard mask layer 320 on the side surfaces of the second patterned hard mask 316 as the third patterned hard mask 322.

[0106] 32 and 39 , in step S1028, a third implantation process is performed using the first patterned hard mask 312, the second patterned hard mask 316, and the third patterned hard mask 322 to form a heavily doped region 716 in the well region 714. The third implantation process can be used to implant N-type impurities into the epitaxial layer 704, thereby forming the N-type heavily doped region 716. The heavily doped region 716 may partially overlap with the well region 714. In some embodiments, the third implantation process is performed by directing the ion beam B approximately perpendicular to the top surface of the epitaxial layer 704 to implant the impurities.

[0107] Thereafter, the first patterned hard mask 312, the second patterned hard mask 316, and the third patterned hard mask 332 are removed. In some embodiments, the first patterned hard mask 312, the second patterned hard mask 316, and the third patterned hard mask 332 are removed by, for example, a wet etching process or a planarization process. Method 1000 may further include steps S228 to S234 shown in FIG. 2 , which may be used to form the gate dielectric layer 722, the gate electrode 724, the source region 726A, the drain region 726B, the metal silicide region 730, and the interconnect structure 740 shown in FIG. The specific implementation process can be referred to the description of S228 to S234 above and will not be repeated here.

[0108] FIG40 illustrates a schematic cross-sectional view of a semiconductor structure 1100 according to some embodiments of the present invention. Referring to FIG40 , semiconductor structure 1100 may include a substrate 1102, an epitaxial layer 1104, a protective layer 1106, a buried oxide (BOX) layer 1110, multiple hot carrier regulation regions 1112, multiple well regions 1114, multiple heavily doped regions 1116, a gate dielectric layer 1122, a gate electrode 1124, a source region 1126A, a drain region 1126B, a metal silicide region 1130, and an interconnect structure 1140. In some embodiments, the heavily doped regions 1116 may also be referred to as first doped regions, the well regions 1114 may also be referred to as second doped regions, and the hot carrier regulation regions 1112 may also be referred to as third doped regions.

[0109] Substrate 1102 is a semiconductor substrate, and epitaxial layer 1104 is disposed above substrate 1102. Substrate 1102 and epitaxial layer 1104 may comprise silicon carbide. Hot carrier regulation region 1112, well region 1114, heavily doped region 1116, source region 1126A, and drain region 1126B are disposed within epitaxial layer 1104. Protective layer 1106, buried oxide layer 1110, gate dielectric layer 1122, gate electrode 1124, metal silicide region 1130, and interconnect structure 1140 are disposed above epitaxial layer 1104.

[0110] Multiple well regions 1114 in the semiconductor structure 1100 are spaced apart from each other in a first direction X, and each heavily doped region 1116 is surrounded by a well region 1114. The well regions 1114 may include P-type impurities, and the heavily doped regions 1116 may include N-type impurities. The hot carrier regulation region 1112 may, for example, extend along the sidewalls of the well regions 1114, with a portion of the hot carrier regulation region 1112 overlapping with an undoped portion of the epitaxial layer 1104.

[0111] A gate dielectric layer 1122 and a gate electrode 1124 are sequentially disposed on the protective layer 1106 and may extend continuously from approximately the middle of one heavily doped region 1116 to approximately the middle of an adjacent heavily doped region 1116. A buried oxide layer 1110 penetrates the gate dielectric layer 1122 and contacts the protective layer 1106. In some embodiments, the buried oxide layer 1110 is disposed above a portion of the epitaxial layer 1104 that does not include the well region 1114. The buried oxide layer 1110 may extend into the gate electrode 1124. The buried oxide layer 1110 may have a thickness ranging from approximately 10 angstroms to approximately 20,000 angstroms, and a width ranging from approximately 500 angstroms to approximately 4,000 angstroms.

[0112] Source region 1126A and drain region 1126B are disposed in epitaxial layer 1104 at opposite ends of gate electrode 1124. In some embodiments, source region 1126A may partially overlap with hot carrier regulation region 1112, well region 1114, and heavily doped region 1116 located to the left of gate electrode 1124, while drain region 1126B may partially overlap with hot carrier regulation region 1112, well region 1114, and heavily doped region 1116 located to the right of gate electrode 1124. A metal silicide region 1130 may be formed in protective layer 1106 and may contact source region 1126A and drain region 1126B.

[0113] The interconnect structure 1140 is disposed above the protective layer 1106, the gate electrode 1124, and the metal silicide 1130, and may include an interlayer dielectric layer 1142 and a plurality of conductive features 1146. The conductive features 1146 physically and electrically connect the gate electrode 1124 and the metal silicide 1130. The interlayer dielectric layer 1142 covers the protective layer 1106, the metal silicide region 1130, and the gate electrode 1124, and surrounds at least the lower portion of the conductive features 1146.

[0114] FIG41 is a flow chart of a method 1200 for fabricating semiconductor structure 1100 according to some embodiments of the present disclosure. Method 1200 is merely an example and is not intended to limit the present disclosure beyond the scope expressly recited in the claims. Additional steps may be provided before, during, or after method 1200, and some of the steps described may be moved, replaced, or omitted for additional embodiments of method 1200. Method 1200 is described below in conjunction with other figures, which illustrate schematic cross-sectional views during various intermediate steps of method 1200.

[0115] 41 and 42 , in step S1210, an epitaxial layer 1104 is formed on a semiconductor substrate 1102. The substrate 1102 and the epitaxial layer 1104 may comprise a semiconductor material, such as silicon carbide. The epitaxial layer 1104 may be formed using a suitable process.

[0116] Next, in step S1214, a protective layer 1106, a first dielectric layer 1510, a semiconductor layer 1520, and a second dielectric layer 1530 are formed over the epitaxial layer 1104. The protective layer 1106 can be a dielectric layer. The protective layer 1106 can be formed of a low-k dielectric material, and the semiconductor layer 1520 can include polycrystalline silicon. The melting point of the first dielectric layer 1510 is higher than that of the second dielectric layer 1530. In some embodiments, the first dielectric layer 1510 can include a high-temperature resistant dielectric material such as silicon nitride, hafnium dioxide, zirconium dioxide, or aluminum oxide. The second dielectric layer 1530 includes silicon dioxide. The thickness of the first dielectric layer 1510, the semiconductor layer 1520, and the second dielectric layer 1530 is each between approximately 500 angstroms and approximately 30,000 angstroms.

[0117] Thereafter, a patterned photoresist layer 300 is formed over the second dielectric layer 1530 ; the patterned photoresist layer 300 is used to expose portions of the second dielectric layer 1530 .

[0118] 41 to 43 , in step S1214, an etching process is performed using the patterned photoresist layer 300 as an etching mask to remove portions of the first dielectric layer 1510, the semiconductor layer 1520, and the second dielectric layer 1530 not covered by the patterned photoresist layer 300, thereby forming a first patterned hard mask 1500. The first patterned hard mask 1500 is composed of the remaining portions of the first dielectric layer 1512, the remaining portions of the semiconductor layer 1522, and the remaining portions of the second dielectric layer 1532 after the etching process. In some embodiments, one or more etching processes are performed to sequentially remove the second dielectric layer 1530, the semiconductor layer 1520, and the first dielectric layer 1510, exposing the patterned photoresist layer 300, until the protective layer 1106 is reached and exposed. The etching process may include performing a wet etching process, a dry etching process, another suitable etching process, or any combination of the aforementioned processes. Subsequently, the patterned photoresist layer 300 is removed, for example, in an ashing or stripping process.

[0119] Referring to Figures 41 and 44, in step S1216, a first implantation process is performed using the first patterned hard mask 1500 as a mask layer to form a plurality of hot carrier modulation regions 1112 in the epitaxial layer 1104. The first implantation process is used to implant specific impurity atoms into locations on both sides of the bottom of the first patterned hard mask 1110 using ion acceleration. In some embodiments, the impurity atoms can be selected from the nitrogen group, the boron group, or boron difluoride. The first implantation process can be performed at room temperature, or the first implantation process can be a thermal implantation process.

[0120] 41 and 45 , in step S1218, a second hard mask layer 1540 is formed over the protective layer 1106 and the first patterned hard mask 1110. The second hard mask layer 1540 has a thickness less than that of the first patterned hard mask 1500 and is substantially conformal to the shapes of the protective layer 1106 and the first patterned hard mask 1500.

[0121] 41 and 46 , in step S1220, the second hard mask layer 1540 is anisotropically etched to form a second patterned hard mask 1542 surrounding the first patterned hard mask 1500. The anisotropic etching can remove the second hard mask layer 1540 disposed on the top surface of the protective layer 1106 and the top surface of the first patterned hard mask 1500, leaving the second hard mask layer 1540 on the side surfaces of the first patterned hard mask 1500 as the second patterned hard mask 1542. In some embodiments, the width of the second patterned hard mask 1542 is between approximately 500 angstroms and approximately 10,000 angstroms.

[0122] 41 and 47 , in step S1222, a second implantation process is performed using the first patterned hard mask 1500 and the second patterned hard mask 1540 as mask layers to form a well region 1114 in the epitaxial layer 1104. The second implantation process implants P-type impurities into the epitaxial layer 1104, thereby forming the P-type well region 1114. In some embodiments, the second implantation process implants the impurities into the epitaxial layer 1104 at an implantation tilt angle θ of approximately 0 degrees.

[0123] 41 and 48 , in step S1224, a third hard mask layer 1550 is formed over the protective layer 1106, the first patterned hard mask 1500, and the second patterned hard mask 1540. The third hard mask layer 1550 has substantially the same thickness as the first patterned hard mask 1500, and the thickness of the third hard mask layer 1550 is less than the thickness of the first patterned hard mask 1500. In some embodiments, the third hard mask layer 1550 is substantially conformal to the shapes of the protective layer 1106, the first patterned hard mask 1500, and the second patterned hard mask 1540.

[0124] 41 and 49 , in step S1226, the third hard mask layer 1550 is anisotropically etched to form a third patterned hard mask 1552 surrounding the second patterned hard mask 1542. The anisotropic etching can remove the third hard mask layer 1550 disposed on the top surface of the protective layer 1106, the top surface of the first patterned hard mask 1500, and the top surface of the second patterned hard mask 1542, leaving the third hard mask layer 1550 on the side surfaces of the second patterned hard mask 1542 as the third patterned hard mask 1552.

[0125] 41 and 50 , in step S1228, a third implantation process is performed using the first patterned hard mask 1500, the second patterned hard mask 1540, and the third patterned hard mask 1552 to form a heavily doped region 1116 in the well region 1114. In some embodiments, the third implantation process can be used to implant N-type impurities into the epitaxial layer 704. The heavily doped region 1116 can partially overlap with the well region 1114. In some embodiments, the third implantation process is performed by directing the ion beam B approximately perpendicular to the top surface of the epitaxial layer 1104 to implant the impurities.

[0126] 41 and 51 , in step S1230, the third patterned hard mask 1552, the second patterned hard mask 1542, the remaining portion of the second dielectric layer 1532, and the remaining portion of the semiconductor layer 1522 are removed. In some embodiments, the third patterned hard mask 1552, the second patterned hard mask 1542, the remaining portion of the second dielectric layer 1532, and the remaining portion of the semiconductor layer 1522 can be removed by using an etching process or a planarization process, thereby exposing the remaining portion of the first dielectric layer 1512.

[0127] 41 and 52 , in step S1232, a trimming process is performed to reduce the width and height of the remaining portion of the first dielectric layer 1512, thereby forming a buried oxide layer 1110. In some embodiments, the trimming process may include a dry etching process or a wet etching process.

[0128] FIG53 illustrates a schematic cross-sectional view of a semiconductor structure 1300 according to some embodiments of the present invention. Referring to FIG53 , semiconductor structure 1300 may include a substrate 1302, an epitaxial layer 1304, a well region 1314, a heavily doped region 1316, a gate dielectric layer 1322, a gate electrode 1324, a source region 1326A, a drain region 1326B, a metal silicide region 1330, an interconnect structure 1340, and a buried oxide layer 1350. In some embodiments, well region 1314 may also be referred to as a first doped region, and heavily doped region 1316 may also be referred to as a second doped region.

[0129] Substrate 1302 is a semiconductor substrate, and epitaxial layer 1304 is disposed above substrate 1302. Substrate 1302 and epitaxial layer 1304 may comprise silicon carbide. Source region 1326A and drain region 1326B are respectively disposed in epitaxial layer 1304. Gate dielectric layer 1322, gate electrode 1324, metal silicide region 1330, interconnect structure 1340, and buried oxide layer 1350 are respectively disposed above epitaxial layer 1304.

[0130] Multiple well regions 1314 in the semiconductor structure 1300 are spaced apart from each other in a first direction X, and each heavily doped region 1316 is surrounded by a well region 1314. The well regions 1314 may include P-type impurities, and the heavily doped regions 1316 may include N-type impurities. A buried oxide layer 1350 is disposed on the epitaxial layer 1304 where the well regions 1314 are not disposed. A gate dielectric layer 1322 is disposed on the epitaxial layer 1304 and may extend continuously from approximately the middle of the heavily doped regions 1316 on either side of the buried oxide layer 1350 to the sidewalls of the buried oxide layer 1350. A gate electrode 1324 covers the buried oxide layer 1350 and the gate dielectric layer 1322. In some embodiments, the gate electrode 1324 extends continuously from approximately the middle of one heavily doped region 1316 to approximately the middle of an adjacent heavily doped region 1316. The buried oxide layer 1350 may have a width ranging from about 500 angstroms to about 4000 angstroms.

[0131] Source region 1326A and drain region 1326B are disposed in epitaxial layer 1304 at opposite ends of gate electrode 1324. In some embodiments, source region 1326A may partially overlap with well region 1314 and heavily doped region 1316 located to the left of gate electrode 1324, while drain region 1326B may partially overlap with well region 1314 and heavily doped region 1316 located to the right of gate electrode 1324. Metal silicide region 1330 is formed above locations where source region 1126A and drain region 1126B do not overlap with well region 1314 and heavily doped region 1316.

[0132] The interconnect structure 1340 is disposed above the epitaxial layer 1304, the gate electrode 1324, and the metal silicide region 1330, and may include an interlayer dielectric layer 1342 and a plurality of conductive features 1346. The conductive features 1346 physically and electrically connect the gate electrode 1324 and the metal silicide region 1330. The interlayer dielectric layer 1342 covers the epitaxial layer 1304, the metal silicide region 1330, and the gate electrode 1324, and surrounds at least the lower portion of the conductive features 1346.

[0133] FIG54 is a flow chart of a method 1400 for fabricating semiconductor structure 1300 according to some embodiments of the present disclosure. Method 1400 is merely an example and is not intended to limit the present disclosure beyond the scope expressly recited in the claims. Additional steps may be provided before, during, or after method 1400, and some of the steps described may be moved, replaced, or omitted for additional embodiments of method 1400. Method 1400 is described below in conjunction with other figures, which illustrate schematic cross-sectional views of the method during various intermediate steps of method 1400.

[0134] Steps S1410, S1412, and S1414 of Figure 54 are respectively the same as steps S210, S212, and S214 of Figure 2, and the specific implementation can be described in conjunction with Figures 3 to 4, respectively, and will not be repeated here.

[0135] 54 and 55 , in step S1416, a first implantation process is performed using the first patterned hard mask 312 as a mask layer to form a first doped region 1314 in the epitaxial layer 1304. The first implantation process may, for example, implant P-type impurities into the epitaxial layer 1304 substantially perpendicular to the top surface of the epitaxial layer 1304.

[0136] 54 and 56 , in step S1418, a second hard mask layer 314 is formed over the protective layer 1306 and the first patterned hard mask 312. In some embodiments, the second hard mask layer 314 is formed along the topography of the protective layer 1306 and the first patterned hard mask 312 and may have a substantially uniform thickness. The second hard mask layer 314 is substantially conformal to the shape of the protective layer 1306 and the first patterned hard mask 312.

[0137] 54 and 57 , in step S1420, the second hard mask layer 314 is anisotropically etched to form a second patterned hard mask 316 surrounding the first patterned hard mask 312. The anisotropic etching can remove the horizontal portion of the second hard mask layer 314 (i.e., the second hard mask layer 314 disposed on the top surface of the protection layer 1306 and the top surface of the first patterned hard mask 312), while leaving the vertical portion of the second hard mask layer 314 (i.e., the second hard mask layer 314 disposed on the side surfaces of the first patterned hard mask 312) as the second patterned hard mask 316.

[0138] 54 and 58 , in step S1422, a second implantation process is performed using the second patterned hard mask 316 as a mask layer to form heavily doped regions 1316 in the epitaxial layer 1304. The second implantation process may, for example, be used to implant N-type impurities substantially vertically into the epitaxial layer 1304. In some embodiments, the heavily doped regions 1306 have a higher doping concentration than the well regions 1304.

[0139] 54 and 59 , in step S1424, the second patterned hard mask 316 and a portion of the first patterned hard mask 312 are removed. In some embodiments, the second patterned hard mask 316 and a majority of the first patterned hard mask 312 may be removed by one or more etching processes to form a third patterned hard mask 318.

[0140] 54 and 60 , in step S1426 , the third patterned hard mask 318 is used as an etching mask to remove the exposed portion of the protective layer 1306 ; the remaining protective layer 1307 and the third patterned hard mask 318 cooperate to form a buried oxide layer 1350 .

[0141] Method 1400 may further include steps S228 to S234 shown in Figure 2, which can be used to form the gate dielectric layer 1322, gate electrode 1324, source region 1326A, drain region 1326B, metal silicide region 1330 and interconnect structure 1340 shown in Figure 53; the specific implementation process can refer to the above description of S228 to S234 and will not be repeated here.

[0142] The foregoing summarizes the structures of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use this disclosure as a basis for designing or modifying other manufacturing processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

[0143] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, or modifications may be made herein without departing from the technology of the present disclosure as defined by the appended claims. For example, many of the procedures discussed above may be implemented using different methodologies and may be replaced by other procedures, or combinations thereof.

[0144] Furthermore, the scope of this application is not intended to be limited to the particular embodiments of the processes, machines, articles, compositions of matter, means, methods, and steps described in this specification. As will be readily understood by those skilled in the art from the disclosure of this invention, processes, machines, articles, compositions of matter, means, methods, or steps now existing or later developed that perform substantially the same function or achieve substantially the same results as the corresponding embodiments described herein may be used in accordance with the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, and steps.

[0145] 100:Semiconductor structure 102:Substrate 104: epitaxial layer 106: Protective layer 112: Channel regulation region 114: Well region 116:Heavily doped region 120: Gate structure 122: Gate dielectric layer 124: Gate electrode 126A: Source region 126B: Drain region 130: Metal silicide region 140: Interconnection structure 142: interlayer dielectric layer 143: Contact hole 144: Diffusion barrier layer 146: Conductive characteristics 1462: Contact plug 1464: Wire 200:Method 300: Patterned photoresist 310: First hard mask layer 312: First patterned hard mask 314: Second hard mask layer 316: Second patterned hard mask 318: Third patterned hard mask 320: Third hard mask layer 322: Third patterned hard mask 332: Third patterned hard mask 400:Method 500:Semiconductor Structure 502:Substrate 504: epitaxial layer 506: Protective layer 512: Electric field adjustment area 514: Well region 516:Heavily doped region 522: Gate dielectric layer 524: Gate electrode 526A: Source region 526B: Drain region 530: Metal silicide region 540: Interconnection structure 542: interlayer dielectric layer 546: Conductive characteristics 600:Method 700:Semiconductor Structure 702:Substrate 704: epitaxial layer 706: Protective layer 712: Hot carrier regulation area 714: Well region 716:Heavily doped region 722: Gate dielectric layer 724: Gate electrode 726A: Source region 726B: Drain region 730: Metal silicide region 740: Interconnection structure 742: Interlayer dielectric layer 746: Conductive characteristics 800:Method 1000:Method 1100:Semiconductor Structure 1102:Substrate 1104: epitaxial layer 1106: Protective layer 1110: buried oxide layer 1112: Hot carrier regulation area 1114: Well region 1116:Heavily doped region 1122: Gate dielectric layer 1124: Gate electrode 1126A: Source region 1126B: Drain region 1130: Metal silicide region 1140: Interconnection structure 1142: interlayer dielectric layer 1146: Conductive characteristics 1200: Method 1300:Semiconductor structure 1302:Substrate 1304: epitaxial layer 1306: Protective layer 1307: Remaining protective layer 1314: Well region 1316:Heavily doped region 1322: Gate dielectric layer 1324: Gate electrode 1326A: Source region 1326B: Drain area 1330: Metal silicide region 1340: Interconnection structure 1342: Interlayer dielectric layer 1346: Conductive characteristics 1350: buried oxide layer 1400: Method 1500: First patterned hard mask 1510: first dielectric layer 1512: Remaining portion of the first dielectric layer 1520: semiconductor layer 1522: Remaining semiconductor layer 1530: Second dielectric layer 1532: Remaining portion of the second dielectric layer 1540: Second hard mask layer 1542: Second patterned hard mask 1550: Third hard mask layer 1552: Third patterned hard mask AM: Alignment Mark A1: First distance A2: Second distance B: Ion beam C: semiconductor wafer d: distance D1: First depth D2: Second Depth D3: Third Depth D4: Fourth Depth D5: Fifth Depth P1: First spacing P2: Second spacing P4: The fourth pitch S210-S234: Steps S410-S426: Steps S610-S626: Steps S810-S828: Steps S1010-S1028: Steps S1210-S1232: Steps S1410-S1426: Steps X: first direction Y: Second direction θ: implant tilt angle δ: torsion angle

Claims

1. A method for manufacturing a semiconductor structure, comprising: An epitaxial layer is formed on a semiconductor substrate; A first patterned hard mask is formed above the epitaxial layer; A first implantation process is performed using the first patterned hard mask to form a plurality of first doped regions in the epitaxial layer; a second implantation process is performed using the first patterned hard mask to form a second doped region in the epitaxial layer, wherein the first doped regions at least partially overlap with the second doped region; a second patterned hard mask is formed surrounding the first patterned hard mask and covering at least a portion of the first doped regions; and a third implantation process is performed using the first patterned hard mask and the second patterned hard mask to form a third doped region in the epitaxial layer, wherein the second doped region surrounds the third doped region and contacts the first doped regions, wherein the first doped regions were formed in the epitaxial layer prior to the second implantation process and the third implantation process.

2. The manufacturing method as claimed in claim 1, wherein the first doped regions are disposed at the corner of the third doped region.

3. The manufacturing method as claimed in claim 1, wherein the epitaxial layer includes a first surface and a second surface opposite to the first surface, the first surface contacting the semiconductor substrate, and the first doped regions contacting the second surface.

4. The manufacturing method as described in claim 3, wherein the first doped regions partially overlap with the third doped region.

5. The manufacturing method as claimed in claim 1, wherein the third doped region is located within and surrounded by the second doped region.

6. The manufacturing method as described in any one of claims 1 to 5, wherein the first implantation process implants the epitaxial layer at an implantation angle of less than or equal to 45 degrees.

7. The manufacturing method as described in any one of claims 1 to 5, wherein the first implantation process is performed at room temperature or is a thermal implantation process.

8. The manufacturing method as described in any one of claims 1 to 5, wherein the second doped region has a first conductivity type, the third doped region has a second conductivity type different from the first conductivity type, and the doping concentration of the second doped region is lower than the doping concentration of the third doped region.

9. The manufacturing method as described in any one of claims 1 to 5, wherein the implantation dose in the first implantation process is from about 1 × 10¹³ cm⁻² to about 1 × 10¹⁵ cm⁻².

10. A method for manufacturing a semiconductor structure, comprising: An epitaxial layer and a first patterned hard mask are sequentially formed on a semiconductor substrate; A first implantation process is performed using the first patterned hard mask to form a plurality of spaced-apart first doped regions in the epitaxial layer; a second patterned hard mask is formed around the first patterned hard mask; a second implantation process is performed using the first and second patterned hard masks to form a second doped region in the epitaxial layer, wherein the first and second doped regions at least partially overlap; a third patterned hard mask is formed around the second patterned hard mask; and a third implantation process is performed using the first, second, and third patterned hard masks to form a third doped region in the epitaxial layer.

11. The manufacturing method as claimed in claim 10, wherein the first doped regions are disposed on the sidewall of the second doped region.

12. The manufacturing method as claimed in claim 10, wherein the third doped region is located within and surrounded by the second doped region.

13. The manufacturing method as described in any one of claims 10 to 12, wherein the first implantation process implants the epitaxial layer at an implantation angle of less than or equal to 45 degrees, and the first implantation process is performed at room temperature or is a thermal implantation process.

14. The manufacturing method as described in any one of claims 10 to 12, wherein forming the first patterned hard mask comprises: A protective layer is formed on the epitaxial layer; a first dielectric layer is formed on the protective layer; A semiconductor layer is formed on the first dielectric layer; A second dielectric layer is formed on the semiconductor layer, wherein the melting point of the first dielectric layer is higher than the melting point of the second dielectric layer; and the second dielectric layer, the semiconductor layer and the first dielectric layer are patterned to form the first patterned hard mask, wherein the first patterned hard mask exposes a portion of the protective layer.

15. The manufacturing method as claimed in claim 14, wherein the first dielectric layer is selected from silicon nitride (Si3N4), hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), and the second dielectric layer comprises silicon dioxide (SiO2).

16. The manufacturing method as claimed in claim 14, wherein the thicknesses of the first dielectric layer, the semiconductor layer, and the second dielectric layer are each between about 500 angstroms and about 30,000 angstroms, and the width of the second patterned hard mask is between about 500 angstroms and about 10,000 angstroms.

17. The manufacturing method as described in claim 14 further includes: Remove the third patterned hard mask, the second patterned hard mask, the second dielectric layer, the semiconductor layer, a portion of the first dielectric layer, and a portion of the protective layer, wherein the remaining portion of the first dielectric layer and the remaining portion of the protective layer form a buried oxide layer, and the first doped region, the second doped region, and the third doped region are not covered by the buried oxide layer.

18. The manufacturing method as described in claim 17, wherein the width of the buried oxide layer is between about 10 angstroms and about 20,000 angstroms, and the thickness of the buried oxide layer is between about 500 angstroms and about 4,000 angstroms.

19. A method for manufacturing a semiconductor structure, comprising: An epitaxial layer and a first patterned hard mask are sequentially formed over a semiconductor substrate; a second patterned hard mask is formed surrounding the first patterned hard mask; a first implantation process is performed using the first and second patterned hard masks to form a first doped region in the epitaxial layer; the second patterned hard mask is removed; a second implantation process is performed using the first patterned hard mask to form a second doped region surrounding the first doped region in the epitaxial layer; a portion of the first patterned hard mask is removed to form a third patterned hard mask; and a third implantation process is performed using the third patterned hard mask to form a third doped region in the epitaxial layer, the third doped region at least partially overlapping the second doped region, wherein the first and second doped regions have different conductive morphologies.

20. The manufacturing method as described in claim 19, wherein the third doped region is disposed on the sidewall of the second doped region.

21. The manufacturing method as described in claim 19 or 20, wherein the first implantation process implants the epitaxial layer at an implantation angle of less than or equal to 45 degrees, and the first implantation process is performed at room temperature or is a thermal implantation process.

22. The manufacturing method as described in claim 19 or 20, wherein the thickness of the first patterned hard mask is greater than or equal to about 3 micrometers.

23. A method for manufacturing a semiconductor structure, comprising: An epitaxial layer, a protective layer and a first patterned hard mask are sequentially formed on a semiconductor substrate. A first implantation process is performed using the first patterned hard mask to form a first doped region in the epitaxial layer; a second patterned hard mask is formed around the first patterned hard mask; a second implantation process is performed using the first patterned hard mask and the second patterned hard mask to form a second doped region in the epitaxial layer; and the second patterned hard mask, a portion of the first patterned hard mask, and a portion of the protective layer are removed, wherein the remaining portion of the first patterned hard mask and the remaining portion of the protective layer form a buried oxide layer, and neither the first doped region nor the second doped region is covered by the buried oxide layer.

24. The manufacturing method as claimed in claim 23, wherein the first patterned hard mask includes forming a first dielectric layer on the protective layer, forming a semiconductor layer on the first dielectric layer, and forming a second dielectric layer on the semiconductor layer, wherein the melting point of the first dielectric layer is higher than the melting point of the second dielectric layer.

25. The manufacturing method as claimed in claim 24, wherein removing a portion of the first patterned hard mask includes removing the second dielectric layer, the semiconductor layer, and a portion of the first dielectric layer, such that the buried oxide layer includes a residual portion of the first dielectric layer and a residual portion of the protective layer.

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