Semiconductor structure and method for forming the same

Abstract

The method includes providing a workpiece comprising a stack of semiconductor layers, the stack of semiconductor layers including interleaved first and second semiconductor layers; forming a dummy gate structure to surround a channel region of the stack of semiconductor layers; performing a first etching process to selectively recess a second semiconductor layer; forming a gate spacer layer over the dummy gate structure and the stack of semiconductor layers; recessing a source / drain region of the stack of semiconductor layers to form a source / drain opening; performing a second etching process to selectively recess the second semiconductor layer from the source / drain opening to form an internal spacer wall notch; forming an internal spacer wall in the internal spacer wall notch; forming a source / drain component in the source / drain opening; and replacing the dummy gate structure and the second semiconductor layer with a gate structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor technology, and more particularly to semiconductor structures and methods of forming the same. Prior Art

[0002] The integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous one. Over the history of IC development, functional density (i.e., the number of interconnected devices per chip area) has increased while geometry (i.e., the smallest component or circuit produced during the manufacturing process) has shrunk. This process of device miniaturization provides the benefits of increased production efficiency and reduced associated costs. This device miniaturization has also increased the complexity of processing and manufacturing ICs.

[0003] For example, the advancement of integrated circuit (IC) technology toward smaller technology nodes has introduced multi-gate metal-oxide-semiconductor field effect transistors (multi-gate MOSFETs or multi-gate devices) to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCEs). Multi-gate devices generally refer to devices having a gate structure or a portion of a gate structure disposed on more than one side of a channel region. Gate-all-around (GAA) transistors have become an example of a popular and promising candidate multi-gate device for high-performance and low-leakage applications. A gate-all-around transistor has a gate structure that can extend to partially or completely surround the channel region to provide access to the channel region on two or more sides. Since the gate structure of a fully wound gate transistor surrounds the channel region, the fully wound gate transistor can also be called a surrounding gate transistor (SGT) or a multi-bridge-channel (MBC) transistor.

[0004] In a fully wound gate transistor, the source / drain components may be separated from the channel region by the presence of various gate spacers. The gate spacers may vary in thickness at different locations, which may affect the protection of the source / drain components by the gate spacers during the manufacturing process and / or mitigate electrical shorts between the gate structure and the source / drain features. This may affect the overall performance of the fully wound gate transistor. While conventional fully wound gate transistors are generally adequate for their intended purpose, these fully wound gate transistors are not satisfactory in all respects. Summary of the invention

[0005] In some embodiments, a method for forming a semiconductor structure is provided, the method comprising providing a workpiece, the workpiece comprising a stack of a plurality of semiconductor layers extending longitudinally along a first direction, wherein the stack of the plurality of semiconductor layers comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers that are staggered; forming a dummy gate structure to surround a channel region of the stack of the plurality of semiconductor layers, and the dummy gate structure extends longitudinally along a second direction perpendicular to the first direction; after forming the dummy gate structure, performing a first etching process to selectively recess the plurality of second semiconductor layers; after the first etching process, A gate spacer layer is formed above the gate structure and the stack of multiple semiconductor layers; the source / drain region of the stack of multiple semiconductor layers is recessed to form a source / drain opening that exposes the sidewalls of the stack of multiple semiconductor layers; after the source / drain region is recessed, a second etching process is performed to selectively recess multiple second semiconductor layers from the source / drain opening to form an internal spacer recess; an internal spacer is formed in the internal spacer recess; a source / drain component is formed in the source / drain opening; and a dummy gate structure and multiple second semiconductor layers are replaced with a metal gate structure.

[0006] In some embodiments, a method for forming a semiconductor structure is provided, the method comprising providing a workpiece, comprising: a first channel layer and a second channel layer, extending longitudinally along a first direction; and a sacrificial layer, disposed between the first channel layer and the second channel layer; forming a dummy gate structure above the first channel layer, the second channel layer, and the sacrificial layer, wherein the dummy gate structure extends longitudinally along a second direction perpendicular to the first direction; performing an etching process to selectively and partially recess the sacrificial layer from a first sidewall of the sacrificial layer parallel to the first direction; depositing a gate spacer layer above the dummy gate structure, the first channel layer, the second channel layer, and the sacrificial layer; recessing source / drain regions of the first channel layer, the second channel layer, and the sacrificial layer to form a source / drain opening; and forming a source / drain component in the source / drain opening, wherein after the source / drain component is formed, a portion of the gate spacer layer is located between the first channel layer and the second channel layer.

[0007] In some other embodiments, a semiconductor structure is provided, which includes a channel stack, including a first channel element and a second channel element; a gate structure, which is arranged around the first channel element and the second channel element and extends longitudinally along a first direction; an internal spacer, which is arranged between the first channel element and the second channel element; and a gate spacer, which is arranged on the gate structure and connected to the internal spacer, wherein in a horizontal plane between the first channel element and the second channel element, the gate spacer includes a portion protruding into the gate structure along a second direction perpendicular to the first direction. Simple diagram description

[0008] The embodiments of the present invention can be better understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, the various features shown in the drawings are not necessarily drawn to scale. In fact, the sizes of various features may be arbitrarily enlarged or reduced to make the description clear. FIG. 1 is a flow chart showing a method for forming a semiconductor structure according to one or more aspects of an embodiment of the present invention. 2 and 3 show partial perspective views of an exemplary workpiece during various stages of fabrication of the method of FIG. 1 according to aspects of embodiments of the present invention. FIG. 4 shows a partial top view of an exemplary workpiece during various manufacturing stages of the method of FIG. 1 according to various aspects of embodiments of the present invention. Figures 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, and 13A show partial cross-sectional schematic diagrams of an exemplary workpiece during a manufacturing process according to the method of Figure 1 along line AA of Figure 3 and area B of Figure 4 according to one or more aspects of embodiments of the present invention. Figures 6B, 7B, 11B, 11C, 13B, and 13C respectively show enlarged views of portion B1 of Figures 6A, 7A, 11A, 11A, 13A, and 13A according to one or more aspects of embodiments of the present invention. FIGS. 5B, 6C, 7C, and 8B respectively show partial cross-sectional schematic views of an exemplary workpiece during a manufacturing process according to the method of FIG. 1 along lines CC of FIGS. 5A, 6A, 7A, and 8A, according to one or more aspects of embodiments of the present invention. Figures 5C, 6D, 7D, 8C, 9B, 10B, 11D, 12B, 13D, and 13E respectively show partial cross-sectional schematic diagrams of an exemplary workpiece during a manufacturing process according to the method of Figure 1 along line DD of Figures 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, and 13A according to one or more aspects of an embodiment of the present invention. Figures 6E, 7E, 8D, 13F, and 13G respectively show partial cross-sectional schematic diagrams of an exemplary workpiece during the manufacturing process according to the method of Figure 1 along line EE of Figures 6A, 7A, 8A, 13B, and 13C according to one or more aspects of an embodiment of the present invention. Implementation

[0009] It is to be understood that the following content provides many different embodiments or examples to implement different components of the subject provided. The following describes specific examples of each component and its arrangement in order to simplify the description of the content. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, the size of the component is not limited to the range or value of one embodiment of the present disclosure, but may depend on the processing conditions and / or required properties of the component. In addition, in the subsequent description, the first component formed above or on the second component includes an embodiment in which the first and second components are formed in direct contact, and may also include an embodiment in which an additional component can be formed between the first and second components so that the first and second components may not be in direct contact. In addition, different examples in the content may use repeated reference symbols and / or words. These repeated symbols or words are for the purpose of simplicity and clarity, and are not used to define the relationship between the various embodiments and / or the described appearance structures.

[0010] To facilitate description of the relationship between one element or component and another (plural) element or (plural) component in the drawings, spatially relative terms, such as "under", "below", "lower", "above", "upper" and similar terms, may be used. In addition to the orientations depicted in the drawings, spatially relative terms also encompass different orientations of the device in use or operation. The device may also be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the description of the spatially relative terms used should be interpreted accordingly.

[0011] Furthermore, when "about," "approximately," and similar terms are used to describe a number or a range of numbers, such terms are intended to encompass a reasonable range of the described number, which is a reasonable range that takes into account the inherent variations that occur during the manufacturing process as understood by those of ordinary skill in the art. For example, a number or range of numbers encompasses a reasonable range that includes the described number (e.g., within + / - 10% of the described number) based on known manufacturing tolerances associated with manufacturing components having the features associated with the number. For example, a material layer having a thickness of "about 5 nm" may encompass a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with depositing material layers is known to those of ordinary skill in the art to be + / - 15%.

[0012] Embodiments of the present invention generally relate to fully wound gate transistors and methods of manufacturing, and more particularly to gate spacers having protrusions extending into metal gate structures.

[0013] As described above, a fully wound gate transistor may also be referred to as a wrap-around gate transistor, a multi-bridge channel transistor, a nanosheet transistor, or a nanowire transistor. A fully wound gate transistor may be n-type or p-type. A fully wound gate transistor according to an embodiment of the present invention may have a channel region disposed in a nanowire channel element, a rod-shaped channel element, a nanosheet channel element, a nanostructure channel element, a bridge-shaped channel element, and / or other suitable channel shapes. A gate spacer and / or an internal spacer component may be used to isolate a gate structure (or a sacrificial layer before gate replacement) from a source / drain component. However, in some existing examples, the spacer component may not provide sufficient isolation between the source / drain component and the sacrificial layer or gate structure. For example, when the sacrificial layer is removed during the channel release process, a portion of the internal spacer may be removed, which reduces the thickness of the internal spacer and may increase the possibility of damaging the source / drain component.

[0014] Embodiments of a fully wrapped gate structure are provided herein, wherein a sacrificial layer is selectively etched prior to forming a gate spacer. In the method herein, a dummy gate stack is formed over a stack of semiconductor layers including an alternating channel layer and a sacrificial layer. A first etching process is performed to form a recess having a portion directly below the dummy gate structure. Next, a gate spacer is deposited over the dummy gate stack, the semiconductor layer stack, and in the recess. Since the gate spacer is also filled in the recess, the gate spacer formed by the gate spacer has an increased thickness at the interface with the sacrificial layer. Next, a source / drain recess is formed in the source / drain region of the semiconductor layer stack. Next, a second selective etching process is performed on the sacrificial layer to form an inner spacer recess, the inner spacer being formed in the inner spacer recess. After forming a source / drain feature in the source / drain recess, the dummy gate stack and the sacrificial layer are replaced with a metal gate structure. After the gate replacement process, the gate spacer has an increased thickness at the interface with the sacrificial layer, thereby reducing the possibility of etching through the gate spacer and / or the inner spacer, which can reduce damage to the source / drain components. In addition, the thickened gate spacer can also reduce electrical shorts between the metal gate structure and the source / drain components.

[0015] Various aspects of embodiments of the present invention will be described in more detail with reference to the drawings. In this regard, FIG. 1 shows a flow chart of a method 10 for forming a semiconductor structure from a workpiece according to an embodiment of the present invention. Method 10 is merely an example and is not intended to limit embodiments of the present invention to what is explicitly described in method 10. For additional embodiments of the method, additional steps may be provided before, during, and / or after method 10, and some of the steps described may be replaced, eliminated, or moved. For the sake of brevity, not all steps are described in detail herein. Method 10 is described below in conjunction with FIGS. 2 to 13G, which are partial perspective, top, or cross-sectional schematic views of a workpiece 200 at different stages of manufacture according to an embodiment of method 10 of FIG. 1. Since workpiece 200 is to be manufactured as a semiconductor structure, workpiece 200 herein may be referred to as a semiconductor structure as the context requires. For the avoidance of doubt, the X, Y, and Z directions in FIGS. 2 to 13G are perpendicular to each other. In addition, similar reference symbols may be used herein to label similar components.

[0016] 1 and 2, the method 10 includes a block 12, wherein a workpiece 200 is provided. The workpiece 200 includes a substrate 202 and a fin structure 212 extending vertically from the substrate 202 along the Z direction. The fin structure 212 extends longitudinally along the X direction. The fin structure 212 includes a base 204 and a semiconductor layer stack 210 above the base 204. The number of fin structures 212 shown in FIG. 2 is for illustration purposes only and should not be construed as limiting the scope of embodiments of the present invention.

[0017] As shown in FIG. 2 , the workpiece 200 includes a substrate 202. In some embodiments, the substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. The substrate 202 may include various doping configurations depending on design requirements known in the art. In embodiments where the semiconductor structure is p-type, an n-type doping profile (i.e., an n-type well) may be formed on the substrate 202. In some embodiments, the n-type dopant used to form the n-type well may include phosphorus (P) or arsenic (As). In embodiments where the semiconductor structure is n-type, a p-type doping profile (i.e., a p-type well) may be formed on the substrate 202. In some embodiments, the p-type dopant used to form the p-type well may include boron (B) or gallium (Ga). Suitable doping may include ion implantation and / or diffusion processes of dopants. The substrate 202 may also include other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate 202 may include a compound semiconductor and / or an alloy semiconductor. Furthermore, the substrate 202 may selectively include an epitaxial layer (epi-layer) that can be strained to enhance performance, may include a silicon-on-insulator (SOI) or a germanium-on-insulator (GeOI) structure and / or may have other suitable enhancement components.

[0018] In some embodiments, the semiconductor layer stack 210 includes a first semiconductor layer (also referred to as a channel layer 208) of a first semiconductor composition and a second semiconductor layer (also referred to as a sacrificial layer 206) of a second semiconductor composition that are alternating. The first and second semiconductor compositions may be different. In some embodiments, the channel layer 208 includes silicon (Si) and the sacrificial layer 206 includes silicon germanium (SiGe). It should be noted that FIG. 2 shows three layers of sacrificial layers 206 and three layers of channel layers 208 arranged alternately, which is only for illustrative purposes, but is not intended to limit beyond what is specifically described in the claims. It is understood that any number of semiconductor layers may be formed in the semiconductor layer stack 210, the number of which depends on the number of channel elements desired for the workpiece 200. In some embodiments, the number of channel layers 208 is between 2 and 10.

[0019] In some embodiments, all sacrificial layers 206 may have a substantially uniform first thickness, and all channel layers 208 may have a substantially uniform second thickness. The first thickness and the second thickness may be the same or different. As described in more detail below, the channel layer 208 or a portion of the channel layer 208 may be used as a channel element of a subsequently formed multi-gate device, and the thickness of each channel layer 208 may be selected based on device performance considerations. The sacrificial layer 206 in the channel region may be eventually removed, and the sacrificial layer 206 is used to define the vertical distance (along the Z direction) between the channel regions of adjacent subsequently formed multi-gate devices, and the thickness of each sacrificial layer 206 may be selected based on device performance considerations.

[0020] The layers in the semiconductor layer stack 210 may be deposited using a molecular beam epitaxy (MBE) process, a vapor phase deposition (VPE) process, and / or other suitable epitaxial growth processes. As described above, in at least one example, the sacrificial layer 206 includes an epitaxially grown silicon germanium (SiGe) layer, and the channel layer 208 includes an epitaxially grown silicon (Si) layer. In some embodiments, the sacrificial layer 206 and the channel layer 208 are substantially free of dopants (i.e., the extrinsic doping concentration is between about 0 cm-3 and about 1×10 17 cm-3), where, for example, no doping is intended during the epitaxial growth process for the semiconductor layer stack 210.

[0021] The fin structure 212 may be formed from the deposited layers of the semiconductor layer stack 210 and the substrate 202. A hard mask layer may be deposited over the deposited layers of the semiconductor layer stack 210 to form an etching mask. The hard mask layer may be a single layer or multiple layers. For example, the hard mask layer may include a pad oxide layer and a pad nitride layer over the pad oxide layer. The fin structure 212 may be patterned from the deposited layers of the semiconductor layer stack 210 and the substrate 202 by using a lithography process and an etching process. The lithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., reactive ion etching (RIE)), wet etching, and / or other etching methods. The etching process forms a trench extending through the semiconductor layer stack 210 and a portion of the substrate 202 to form the base 204. The trench defines a fin structure 212. In some embodiments, a double patterning or multiple patterning process may be used to define the fin structure, for example, the fin structure has a pattern with a smaller pitch than can be obtained using a single direct photolithography process. For example, in one embodiment, a material layer is formed above the substrate and patterned using a photolithography process. Spacers are formed next to the patterned material layer using a self-aligned process. The material layer is then removed, and the fin structure 212 may then be patterned by etching the deposited layers of the semiconductor layer stack 210 using the remaining spacers or mandrels. As shown in FIG. 2, the fin structure 212, as well as the sacrificial layer 206 and the channel layer 208, extend vertically in the Z direction and longitudinally in the X direction.

[0022] The workpiece 200 may include an isolation feature 214 adjacent to the fin structure 212. In some embodiments, the isolation feature 214 may be formed in a trench to isolate the fin structure 212 from an adjacent active region. The isolation feature 214 may also be referred to as a shallow trench isolation (STI) feature. For example, in some embodiments, a dielectric layer is first deposited over the substrate 202, and the dielectric layer fills the trench. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, a combination thereof, and / or other suitable materials. In various examples, the dielectric layer may be deposited by a chemical vapor deposition (CVD) process, a subatmospheric CVD (SACVD) process, a flowable CVD (FCVD) process, a spin coating process, and / or other suitable processes. Next, the deposited dielectric material is thinned and planarized, for example, by a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed or pulled back by a dry etching process, a wet etching process, and / or a combination thereof to form the isolation feature 214. After the recessing step, the fin structure 212 protrudes above the isolation feature 214.

[0023] Referring to FIGS. 1 and 3 to 5C, method 10 includes block 14, wherein a dummy gate stack 220 is formed above a channel region 212C of a fin structure 212. FIGS. 3 and 4 show a partial perspective view and a partial top view, respectively, of a workpiece 200 at block 14, according to aspects of embodiments of the present invention. FIG. 5A shows a partial cross-sectional schematic view of the workpiece 200 along line AA of FIG. 3 and in region B of FIG. 4. FIGS. 5B and 5C show a partial cross-sectional schematic view of the workpiece 200 along line CC and line DD of FIG. 5A, respectively. The number of dummy gate stacks 220 shown in FIGS. 3 and 4 is for illustration purposes only and should not be construed as limiting the scope of embodiments of the present invention.

[0024] In some embodiments, a gate replacement process (or gate-last process) is used, wherein the dummy gate stack 220 is used as a standoff to undergo various processes and will be removed and replaced by a functional metal gate structure. Other processes and configurations are possible. In some embodiments, the dummy gate stack 220 is formed above the fin structure 212, and the fin structure 212 can be divided into a channel region 212C below the dummy gate stack 220 and a source / drain region 212SD not below the dummy gate stack 220. The channel region 212C is adjacent to the source / drain region 212SD. As shown in FIG. 5C, the channel region 212C is disposed between two source / drain regions 212SD along the X direction. As shown in FIGS. 5A-5C, the sacrificial layer 206 and the channel layer 208 in the channel region 212C overlap vertically and have the same shape and size in different horizontal planes.

[0025] The formation of the dummy gate stack 220 may include forming layers in the dummy gate stack 220 and patterning the layers. Referring to FIG. 3 , the dummy dielectric layer 216 , the dummy electrode layer 218 , and the gate top hard mask layer 222 may be blanket deposited over the workpiece 200 . In the illustrated embodiment, the dummy dielectric layer 216 is formed as a blanket layer over the top surface and sidewall surfaces of the semiconductor layer stack 210 , but is not formed on the top surface of the isolation member 214 . In an alternative embodiment, the dummy dielectric layer 216 is formed over the top surface and sidewall surfaces of the semiconductor layer stack 210 and over the top surface of the isolation member 214 . The dummy dielectric layer 216 may provide protection for the semiconductor layer stack 210 . The dummy dielectric layer 216 may be formed by various methods, such as chemical oxidation of silicon, thermal oxidation of silicon, ozone oxidation of silicon, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable methods. The dummy dielectric layer 216 may include silicon oxide.

[0026] Thereafter, the dummy electrode layer 218 may be deposited on the dummy dielectric layer 216 using a chemical vapor deposition process, an atomic layer deposition process, or other suitable process. In some examples, the dummy electrode layer 218 may include polysilicon. For patterning purposes, the gate top hard mask layer 222 may be deposited on the dummy electrode layer 218 using a chemical vapor deposition process, an atomic layer deposition process, or other suitable process. Next, the gate top hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216 may be patterned to form a dummy gate stack 220, as shown in FIG. 3. For example, the patterning process may include a lithography process (e.g., photolithography or electron beam lithography), and the lithography process may further include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., reactive ion etching), wet etching, and / or other etching methods. In some embodiments, the gate top hard mask layer 222 may include a silicon oxide layer 223 and a silicon nitride layer 224 above the silicon oxide layer 223. As shown in FIG. 5C , no dummy gate stack 220 is disposed above the source / drain region 212SD of the fin structure 212.

[0027] Referring to FIGS. 1 and 6A-6E, the method 10 includes a block 16, wherein a portion of the sacrificial layer 206 is recessed to form a first notch 225. FIG. 6A shows a partial cross-sectional schematic diagram of the workpiece 200 at block 16 along line AA of FIG. 3 and area B of FIG. 4. FIG. 6B shows an enlarged view of portion B1 of FIG. 6A. FIGS. 6C, 6D, and 6E show partial cross-sectional schematic diagrams of the workpiece 200 along lines CC, DD, and EE of FIG. 6A, respectively. As shown in FIGS. 6A and 6B, line EE extends along the Y direction, close to the edge 219 of the dummy electrode layer 218, and crosses the dummy dielectric layer 216, the dummy electrode layer 218, and a portion 225a of the first notch 225.

[0028] In some embodiments, the step of recessing the sacrificial layer 206 includes performing a first etching process to selectively and partially recess the sacrificial layer 206. In some embodiments, the selective recessing may be a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the degree of recessing the sacrificial layer 206 is controlled by the duration of the etching process. The selective dry etching process may include using one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. The selective wet etching process may include using a first solution including hydrogen fluoride (HF), hydrogen peroxide (H2O2), hydrochloric acid (HCl), or a combination thereof. In some embodiments, the first etching process may include a wet etching process. In some embodiments, during the selective recessing of the sacrificial layer 206, the dummy dielectric layer 216 is not significantly etched.

[0029] Referring to FIGS. 6A and 6B , in some embodiments, the first recess 225 has a rod shape extending longitudinally along the X direction and having two half-rounded ends. In some embodiments, the first recess 225 includes a portion 225a disposed between the dummy gate stack 220 and the sacrificial layer 206 along the Y direction. The portion 225a extends into the sacrificial layer 206 and may have any suitable shape, such as a triangle, a triangle with rounded edges, or a fan. In some embodiments, the first recess 225 has a depth D1 along the Y direction of about 1 nm to about 3 nm. The portion 225a of the first recess 225 may have a depth D1 along the Y direction and a depth D2 along the X direction. The depth D2 may be about 1 nm to about 4 nm. If the depth D1 and / or the depth D2 is less than the lower limit of the above range, the advantages of the embodiments of the present invention may not exist. If the depth D1 and / or the depth D2 is greater than the upper limit of the above range, the connection between the dummy dielectric layer 216 and the sacrificial layer 206 may be too small, which may cause the dummy gate stack 220 to collapse. The ratio of the depth D2 to the width D3 of the dummy electrode layer 218 along the X direction is about 0.05 to about 0.3. If this ratio is less than the lower limit of the above range, the advantages of the embodiment of the present invention may not exist. If this ratio is greater than the upper limit of the above range, the connection between the dummy dielectric layer 216 and the sacrificial layer 206 may be too small, which may cause the dummy gate stack 220 to collapse.

[0030] Referring to FIG. 6C , in some embodiments, the first recesses 225 are each disposed between the channel layer 208 and the adjacent channel layer 208 (or the base 204 ). In the cross-sectional view along line CC, the sidewall of the sacrificial layer 206 is recessed from the sidewall of the channel layer 208 (or the base 204 ) by about a depth D1. Therefore, the fin structure 212 has a wavy profile, as shown in FIG. 6C . Since the dummy dielectric layer 216 is not etched during the selective recessing of the sacrificial layer 206 , the cross-sectional view of FIG. 6D remains substantially the same as FIG. 5C .

[0031] 6E, in some embodiments, the portion 225a of the first recess 225 is directly below the dummy electrode layer 218. In some embodiments, the portions 225a are each disposed between the channel layer 208 and an adjacent channel layer 208 (or the pedestal 204). Since the dummy dielectric layer 216 is not etched during the selective recessing of the sacrificial layer 206, the dummy dielectric layer 216 surrounds the semiconductor layer stack 210, the portion 225a of the first recess 225, and the top of the sidewall of the pedestal 204.

[0032] Referring to FIGS. 1 and 7A-7E, method 10 includes block 18, wherein a portion of dummy dielectric layer 216 is recessed to form second notch 227. FIG. 7A shows a partial cross-sectional schematic diagram of workpiece 200 at block 18 along line AA of FIG. 3 and area B of FIG. 4. FIG. 7B shows an enlarged view of portion B1 of FIG. 7A. FIG. 7C, 7D, and 7E show partial cross-sectional schematic diagrams of workpiece 200 along lines CC, DD, and EE of FIG. 7A, respectively. As shown in FIGS. 7A and 7B, line EE extends along the Y direction, close to edge 219 of dummy electrode layer 218, and crosses dummy electrode layer 218, second notch 227, and portion 225a of first notch 225. The operation of block 18 is optional and may be omitted. In some embodiments, the operation of block 18 is performed before the operation of block 16. In some embodiments, the operations of blocks 16 and 18 are combined.

[0033] In some embodiments, the step of recessing the dummy dielectric layer 216 includes performing a second etching process. The second etching process may selectively and partially recess the dummy dielectric layer 216. In some embodiments, the selective recessing may be a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the degree of recessing the dummy dielectric layer 216 is controlled by the duration of the etching process. The selective dry etching process may include using one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. The selective wet etching process may include using a second solution including hydrogen fluoride (HF), hydrogen peroxide (H 2O 2), hydrochloric acid (HCl), or a combination thereof. The second solution may be different from the first solution (e.g., different in composition or concentration of the composition). In some embodiments, the second etching process may include a wet etching process. In some other embodiments, the first etching process and the second etching process are combined into one etching process using the same etching liquid, and the etching liquid includes hydrogen fluoride (HF), hydrogen peroxide (H 2O 2), hydrochloric acid (HCl), or a combination thereof.

[0034] Referring to FIG. 7B , the depth D4 of the second recess 227 along the X direction may be between about 0.5 nm and about 2 nm. If the depth D4 is less than the lower limit of the above range, the advantage of the block 18 may be too little. If the depth D4 is greater than the upper limit of the above range, the connection between the dummy electrode layer 218 and the semiconductor layer stack 210 may be too small, which may cause the dummy gate stack 220 to collapse. The depth D4 may be equal to, greater than, or less than the depth D2. In some embodiments, the depth D4 is less than the depth D2. The width D5 of the second recess 227 along the Y direction may be approximately the same as the thickness of the dummy dielectric layer 216 and may be between about 0.5 nm and about 2.5 nm. The second recess 227 may be merged with the first recess 225, as shown, and may be collectively referred to as a recess 229. The recess 229 may be a stepped profile with rounded edges, as shown in FIG. 7B . The width D5′ of the recess 229 along the Y direction may be the sum of the width D5 and the depth D1.

[0035] In the illustrated embodiment, the dummy dielectric layer 216 is not disposed above the fin structure 212 in the source / drain region 212SD. Therefore, the cross-sectional view along line CC shown in FIG. 7C may be significantly the same as FIG. 6C. Referring to FIG. 7D, the difference from FIG. 6D includes that the dummy dielectric layer 216 below the dummy electrode layer 218 is recessed by a depth D4 along the X direction (not shown in FIG. 7D). The second notch 227 may be disposed between the dummy electrode layer 218 and the fin structure 212.

[0036] Referring to FIG. 7E , each second notch 227 may be continuous and surround the top surface and sidewalls of the fin structure 212. In some embodiments, the second notch 227 is directly below the dummy electrode layer 218. Each second notch 227 may be merged with a portion 225a of the first notch 225 below the same dummy electrode layer 218. The second notch 227 may have a width D5 along the Y direction and / or the Z direction, as shown.

[0037] For the sake of brevity, unless explicitly described, the following figures show the subsequent process after the operation of block 16 when the operation of block 18 is omitted. However, it should be understood that when the operation of block 18 is not omitted, after the operation of block 18, the workpiece 200 undergoes similar subsequent processes, as described below.

[0038] Referring to FIGS. 1 and 8A-8C, the method 10 includes a block 20, wherein a gate spacer layer 226 is deposited over the dummy gate stack 220 and the source / drain region 212SD of the fin structure 212. FIG. 8A shows a partial cross-sectional schematic diagram of the workpiece 200 at block 20 along line AA of FIG. 3 and area B of FIG. 4. FIGS. 8B, 8C, and 8D show partial cross-sectional schematic diagrams of the workpiece 200 along lines CC, DD, and EE of FIG. 8A, respectively.

[0039] In some embodiments, the gate spacer 226 is deposited over the workpiece 200, for example, over the top surface and sidewalls of the dummy gate stack 220 and over the source / drain region 212SD of the fin structure 212. In the illustrated embodiment, the gate spacer 226 fills the first recess 225. In some other embodiments, the gate spacer 226 fills the first recess 225 and the second recess 227. Thus, the inner surface 231 of the gate spacer 226 conforms to the shape of the first recess 225 and / or the second recess 227. Since the depth D1 of the first recess 225 is smaller than the thickness of the gate spacer 226, the outer surface 233 of the gate spacer 226 can be significantly smooth (e.g., does not reflect the shape of the corresponding inner surface 231), as shown in FIGS. 8A and 8B. A portion of the gate spacer 226 can be disposed between the channel layer 208 and an adjacent channel layer 208 or the pedestal 204, as shown in FIGS. 8B and 8D. In some embodiments, a portion of the gate spacer 226 is disposed directly below the dummy gate stack 220, as shown in FIG. 8D. The gate spacer 226 may be a single layer or multiple layers. The gate spacer 226 may be a single layer or multiple layers. The gate spacer 226 may include silicon carbide nitride, silicon oxycarbide, silicon oxycarbon nitride, or silicon nitride. In some embodiments, the gate spacer 226 may be deposited on the dummy gate stack 220 using a process such as a chemical vapor deposition process, a sub-atmospheric pressure chemical vapor deposition (SACVD) process, an atomic layer deposition process, or other suitable processes.

[0040] 1 and 9A-9B, the method 10 includes a block 22, wherein the source / drain region 212SD of the fin structure 212 is recessed to form a source / drain trench 228. FIG. 9A shows a partial cross-sectional view of the workpiece 200 at block 22 along line AA of FIG. 3 and area B of FIG. 4. FIG. 9B shows a partial cross-sectional view of the workpiece 200 along line DD of FIG. 9A.

[0041] As shown in FIG. 9B , the recessing step of block 22 can remove a portion of the top surface of the gate spacer 226 to form a gate spacer 2260 disposed along the sidewall of the dummy gate stack 220. In some embodiments, the source / drain region 212SD not covered by the dummy gate stack 220 is etched by dry etching or a suitable etching process to form a source / drain trench 228. For example, the dry etching process can use an oxygen-containing gas, a fluorine-containing gas (e.g., CF 4, SF 6, CH 2F 2, CHF 3 and / or C 2F 6), a chlorine-containing gas (e.g., Cl 2, CHCl 3, CCl 4 and / or BCl 3), a bromine-containing gas (e.g., HBr and / or CHBr 3), an iodine-containing gas, other suitable gases and / or plasma and / or a combination thereof. In some embodiments presented in FIGS. 9A and 9B , the source / drain region 212SD of the fin structure 212 is recessed to expose the sidewalls of the sacrificial layer 206 and the channel layer 208. In some embodiments, the source / drain trench 228 extends below the semiconductor layer stack 210 and into the base 204. As shown in FIGS. 9A and 9B , the sacrificial layer 206 and the channel layer 208 in the source / drain region 212SD are removed at block 22 to expose the base 204 and the sidewalls of the sacrificial layer 206 and the channel layer 208.

[0042] Referring to FIGS. 1 and 10A-10B, method 10 includes block 24, wherein sacrificial layer 206 is selectively and partially recessed to form inner spacer recess 230. FIG. 10A shows a partial cross-sectional view of workpiece 200 at block 24 along line AA of FIG. 3 and area B of FIG. 4. FIG. 10B shows a partial cross-sectional view of workpiece 200 along line DD of FIG. 10A.

[0043] The sacrificial layer 206 is selectively and partially recessed to expose the source / drain trenches 228 to form the inner spacer recess 230, while the gate spacer 2260, the exposed portion of the pedestal 204, and the channel layer 208 are substantially unetched. For example, the dashed rectangle 237 in FIG. 10A shows the top view location of the channel layer 208. In embodiments where the channel layer 208 is primarily composed of silicon (Si) and the sacrificial layer 206 is primarily composed of silicon germanium (SiGe), the selective recessing of the sacrificial layer 206 may be performed using a selective wet etch or a selective dry etch process. The selective and partial recessing of the sacrificial layer 206 may include a SiGe oxidation process followed by SiGe oxide removal. In these embodiments, the SiGe oxidation process may include the use of ozone. In some other embodiments, the selective dry etch process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. The selective wet etching process may include an ammonia hydroxide-hydrogen peroxide-water mixture (APM) etching.

[0044] Referring to FIGS. 1 and 11A-11D, method 10 includes block 26, wherein an inner spacer 234 is formed in the inner spacer recess 230. FIG. 11A shows a partial cross-sectional view of the workpiece 200 at block 26 along line AA of FIG. 3 and area B of FIG. 4. FIGS. 11B and 11C show enlarged views of portion B1 of FIG. 11A according to various aspects of embodiments of the present invention. FIG. 11D shows a partial cross-sectional view of the workpiece 200 along line DD of FIG. 11A.

[0045] Although not explicitly shown, the operation of block 26 may include depositing an inner spacer material over the workpiece 200, and etching back the inner spacer material to form an inner spacer 234 in the inner spacer recess 230. In some embodiments, after forming the inner spacer recess 230, the inner spacer material is deposited over the workpiece 200, including being deposited over the inner spacer recess 230. The inner spacer material may include a metal oxide, silicon oxide, silicon oxycarbonitride, silicon nitride, silicon oxynitride, carbon-rich silicon nitride carbonitride, or a low-k dielectric material. The metal oxide may include aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide, or other suitable metal oxides. Although not explicitly shown, the inner spacer material may be a single layer or multiple layers. In some embodiments, the inner spacer material may be deposited using chemical vapor deposition, plasma-assisted chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, atomic layer deposition, or other suitable methods. The inner spacer material is deposited in the inner spacer recess 230 and also deposited on the sidewalls of the channel layer 208 exposed to the source / drain trench 228. Next, the deposited inner spacer material is etched back to remove the inner spacer material from the sidewalls of the channel layer 208 to form an inner spacer 234 in the inner spacer recess 230. At block 26, the inner spacer material may also be removed from the top surface and / or sidewalls of the gate top hard mask layer 222 and the gate spacer 2260. In some embodiments, the etch back process performed at block 26 may include using hydrogen fluoride (HF), fluorine (F2), hydrogen (H2), ammonia (NH3), nitrogen trifluoride (NF3), or other fluorine-based etchants.

[0046] As shown in FIGS. 11A and 11D , each inner spacer 234 directly contacts the recessed sacrificial layer 206 and is disposed between two adjacent channel layers 208. That is, the inner spacer 234 is staggered with the channel layer 208. In some embodiments, referring to FIG. 11B , the operation of block 18 is omitted, and the gate spacer 2260 includes a protrusion 2260a, and the protrusion 2260a fills a portion 225a of the first recess 225 in FIG. 6B . That is, the protrusion 2260a conforms to the shape and size of the portion 225a. For example, the protrusion 2260a may have a triangle, a triangle with rounded edges, or a fan shape, as shown in FIG. 11B . In these embodiments, the protrusion 2260a extends into the sacrificial layer 206 and directly contacts the dummy dielectric layer 216. The thickness D6 of the gate spacer 2260 adjacent to the sacrificial layer 206 and the inner spacer 234 is greater than the thickness D7 of the gate spacer 2260 extending along the dummy electrode layer 218. The thicknesses D6 and D7 extend along the X direction. The thickness D6 may be about 1 nm to about 4 nm greater than the thickness D7. In some embodiments, referring to FIG. 11C, without omitting the operation of block 18, the gate spacer 2260 includes a protrusion 2260a, and the protrusion 2260a fills a portion of the recess 229 in FIG. 7B. Therefore, the protrusion 2260a conforms to the shape and size of a portion of the recess 229. In these embodiments, the protrusion 2260a extends into the sacrificial layer 206 and directly contacts the dummy dielectric layer 216 and the dummy electrode layer 218. The protrusion 2260a may be a stepped profile with rounded edges, as shown in FIG. 11C. The thicknesses D6 and D7 may be the same as described above with reference to FIG. 11B.

[0047] 1 and 12A-12B, the method 10 includes a block 28, wherein a source / drain feature 242 is formed in the source / drain trench 228. FIG. 12A shows a partial cross-sectional view of the workpiece 200 at block 28 along line AA of FIG. 3 and area B of FIG. 4. FIG. 12B shows a partial cross-sectional view of the workpiece 200 along line DD of FIG. 12A.

[0048] In some embodiments, the source / drain components 242 may be formed using an epitaxial growth process, such as vapor phase deposition (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. The epitaxial growth process may use gaseous and / or liquid precursors that react with the composition of the base 204 and the channel layer 208. The source / drain components 242 may be doped with n-type dopants and / or p-type dopants. Exemplary n-type source / drain components 242 may include Si, GaAs, GaAsP, SiP, or other suitable materials, and may be in-situ doped during the epitaxial growth process by introducing n-type dopants, such as phosphorus (P), arsenic (As), or both. When the source / drain component 242 is not in-situ doped with an n-type dopant, an implantation process (i.e., a junction implantation process) may be performed to dope the source / drain component 242 with an n-type dopant. Exemplary p-type source / drain components 242 may include Si, Ge, AlGaAs, SiGe, boron-doped SiGe, or other suitable materials, and may be in-situ doped by introducing a p-type dopant during the epitaxy process. When the source / drain component 242 is not in-situ doped with a p-type dopant, an implantation process (i.e., a junction implantation process) may be performed to dope the source / drain component 242 with a p-type dopant. In some embodiments, the source / drain component 242 includes more than one epitaxial semiconductor layer, wherein the epitaxial semiconductor layers may include the same or different materials and / or the same or different dopant concentrations.

[0049] Referring to FIGS. 1 and 13A-13G, method 10 includes block 30, wherein dummy gate stack 220 and sacrificial layer 206 are replaced with gate structure 252 (sometimes also referred to as metal gate structure). FIG. 13A shows a partial cross-sectional view of workpiece 200 at block 30 along line AA of FIG. 3 and area B of FIG. 4. FIGS. 13B and 13C show enlarged views of portion B1 of FIG. 13A according to various aspects of embodiments of the present invention. FIGS. 13D and 13F show partial cross-sectional views of workpiece 200 along line DD of FIG. 13A and line EE of FIG. 13B, respectively, according to some aspects of embodiments of the present invention. Line EE of FIG. 13B is similar to line EE of FIG. 6B. FIGS. 13E and 13G show partial cross-sectional views of workpiece 200 along line DD of FIG. 13A and line EE of FIG. 13C, respectively, according to some other aspects of embodiments of the present invention. The position of line EE in FIG. 13C is similar to that of line EE in FIG. 7B .

[0050] The operations of block 30 may include depositing a contact etch stop layer (CESL) 244 over the workpiece 200, depositing an interlayer dielectric (ILD) layer 246 over the CESL 244, removing the dummy gate stack 220, selectively removing the sacrificial layer 206 between the channel layers 208 in the channel region 212C, and forming a gate structure 252.

[0051] In some embodiments, the contact etch stop layer 244 is deposited before the interlayer dielectric layer 246 is deposited. In some examples, the contact etch stop layer 244 includes silicon nitride, silicon oxynitride, and / or other known materials. The contact etch stop layer 244 can be formed by atomic layer deposition, plasma assisted chemical vapor deposition (PECVD) process, and / or any suitable deposition process. Then, the interlayer dielectric layer 246 is deposited over the contact etch stop layer 244. In some embodiments, the interlayer dielectric layer 246 includes a material such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials. The interlayer dielectric layer 246 may be deposited by a plasma-assisted chemical vapor deposition process or any suitable deposition technique. In some embodiments, after forming the interlayer dielectric layer 246, the workpiece 200 may be annealed to improve the integrity of the interlayer dielectric layer 246. As shown in FIGS. 13A, 13D, and 13E, the contact etch stop layer 244 may be disposed directly above the top surface and the side surface of the source / drain component 242.

[0052] After depositing the contact etch stop layer 244 and the interlayer dielectric layer 246, the workpiece 200 may be planarized by a planarization process to expose the dummy gate stack 220. For example, the planarization process may include a chemical mechanical planarization (CMP) process. Exposing the dummy gate stack 220 may allow the dummy gate stack 220 to be removed. In some embodiments, the removal of the dummy gate stack 220 results in the formation of a gate trench above the channel region 212C. The removal of the dummy gate stack 220 may include one or more etching processes that are selective to the material of the dummy gate stack 220. For example, the removal of the dummy gate stack 220 may be performed by using a selective wet etch, a selective dry etch, or a combination thereof that is selective to the dummy gate stack 220. After removing the dummy gate stack 220, the sidewalls of the channel layer 208 and the sacrificial layer 206 in the channel region 212C are exposed in the gate trench.

[0053] After removing the dummy gate stack 220 to form the gate trench, the method 10 selectively removes the sacrificial layer 206 between the channel layers 208 in the channel region 212C. The selective removal of the sacrificial layer 206 releases the channel layer 208 and may be referred to as a channel release process. The selective removal of the sacrificial layer 206 also leaves space between adjacent channel layers 208. The selective removal of the sacrificial layer 206 may be performed by selective dry etching, selective wet etching, or other selective etching processes. An exemplary selective dry etching process may include using one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. The selective wet etching process may include ammonium hydroxide-hydrogen peroxide-water mixture (APM) etching.

[0054] Because the gate spacer 2260 has an increased thickness (e.g., thickness D6 in FIGS. 11B and 11C ) adjacent to the sacrificial layer 206 along the X direction and connected to the inner spacer 234, during the selective removal of the sacrificial layer 206 of block 30, the thickened gate spacer 2260 can eliminate the path between the sacrificial layer 206 and the source / drain component 242 and provide more protection to the adjacent source / drain component 242, thereby avoiding or reducing damage to the source / drain component 242 (e.g., by the etching solution of the selective etching process). In addition, due to the protection provided by the thickened gate spacer 2260, the selective etching process for removing the sacrificial layer 206 can be performed more thoroughly, thereby reducing the amount of the sacrificial layer 206 remaining after the selective etching process. Therefore, defects in the workpiece 200 can be reduced. The thickened gate spacer 2260 also provides additional electrical isolation between the source / drain component 242 and an adjacent gate structure 252 (described below), thereby reducing electrical shorts between the source / drain component 242 and the adjacent gate structure 252.

[0055] In some embodiments, a gate structure 252 is formed. The method 10 may include further operations to form a gate structure 252 to surround each channel layer 208. In some embodiments, the gate structure 252 is formed in the gate trench and in the space left by the removal of the sacrificial layer 206. The gate structure 252 includes a gate dielectric layer 254 and a gate electrode layer 256 above the gate dielectric layer 254. In some embodiments, although not explicitly shown in the drawings, the gate dielectric layer 254 includes an interfacial layer disposed on the channel layer 208 and a high-k gate dielectric layer above the interfacial layer. The high-k dielectric materials used and described herein include dielectric materials having a high dielectric constant, such as a dielectric constant greater than that of thermal silicon oxide (~3.9). The interfacial layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k gate dielectric layer may include hafnium oxide. Alternatively, the high-k gate dielectric layer may include other high-k dielectric materials, such as titanium oxide (TiO 2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta 2O 5), hafnium silicon oxide (HfSiO 4), zirconium oxide (ZrO 2), zirconium oxide silicon (ZrSiO 2), lanthanum oxide (La 2O 3), aluminum oxide (Al 2O 3), zirconium oxide (ZrO), yttrium oxide (Y 2O 3), SrTiO 3 (STO), BaTiO 3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO 3 (BST), silicon nitride (SiN), Silicon oxynitride (SiON), combinations thereof, or other suitable materials. The high-k gate dielectric layer may be formed by atomic layer deposition, physical vapor deposition (PVD), chemical vapor deposition, oxidation, and / or other suitable methods.

[0056] The gate electrode layer 256 of the gate structure 252 may include a single layer or a multi-layer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a liner layer, a wetting layer, an adhesion layer, a metal alloy or various combinations of metal silicides. For example, the gate electrode layer 256 may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbide nitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, other suitable metal materials or combinations thereof. In various embodiments, the gate electrode layer 256 may be formed by using atomic layer deposition, physical vapor deposition, chemical vapor deposition, electron beam evaporation or other suitable processes. In various embodiments, a chemical mechanical polishing process is performed to remove excess metal to provide a substantially planar top surface of the gate structure 252 .

[0057] After the operation of block 30 is completed, a fully wound gate transistor 260 is substantially formed. As described above, the fully wound gate transistor 260 can be of n-type or p-type. In some embodiments, the gate spacer 2260 includes a protrusion 2260a extending into the gate structure 252. The gate structure 252 conforms to the shape of the dummy gate stack 220 and the sacrificial layer 206 removed in block 30. Therefore, as shown in FIG. 13A, the gate structure 252 includes a first portion between the two smooth sidewalls of the gate spacer 2260 (e.g., in the dashed line rounded rectangle B2), a second portion between the two protrusions 2260a of the gate spacer 2260 (e.g., in the dashed line rounded rectangle B3), and a third portion disposed between the two inner spacers 234 (e.g., in the dashed line rounded rectangle B4). The first portion can be disposed in the gate trench formed after the dummy gate stack 220 is removed. The second portion and the third portion may be disposed in the space left by removing the sacrificial layer 206. In an operation without omitting block 18, a portion of the second portion may also be disposed in the space left by removing the dummy dielectric layer 216. The first portion has a width D3 along the X direction, the second portion has a width D8 along the X direction, and the third portion has a width D9 along the X direction. In some embodiments, the width D8 is smaller than the width D3 by about 2 nm to about 6 nm. In some embodiments, the width D8 is smaller than the width D9 by about 2 nm to about 8 nm. Therefore, the second portion is also referred to as a bottleneck portion.

[0058] Please refer to FIGS. 13A, 13B, 13D and 13F. In these embodiments, the operation of block 18 is omitted. Each channel layer 208 is surrounded by the gate structure 252. The channel layer 208 extends between the two source / drain components 242 along the X direction. As described above, the dotted rectangle 237 in FIG. 13A shows the top view position of the channel layer 208. The interface 235 between the gate spacer 2260 and the inner spacer 234 is located in the dotted rectangle 237, so that the interface 235 is disposed between the channel layer 208 and the adjacent channel layer 208 or the base 204. Please refer to FIG. 13B, each protrusion 2260a is buried in the gate structure 252. The protrusion 2260a has a width D1 as shown in FIG. 6B, and the width D1 is the same as the length of the bottleneck of the gate structure 252 along the Y direction. Referring to FIG. 13D , the gate structure 252 conforms to the shape of the dummy gate stack 220 in FIG. 6D . Referring to FIG. 13F , the protrusion 2260 a is directly below the gate structure 252 . Each protrusion 2260 a is located between the channel layer 208 and the adjacent channel layer 208 or the base 204 .

[0059] Please refer to FIGS. 13C, 13E and 13G. In these embodiments, the operation of block 18 is not omitted. The difference from the embodiments described above with reference to FIGS. 13B, 13D and 13F is that the embodiments of FIGS. 13C, 13E and 13G include the protrusion 2260a having a width D5' as shown in FIG. 7B, and the width D5' is the same as the length of the bottleneck portion of the gate structure 252 along the Y direction. The width D5' is greater than the width D1 because the width D5' is approximately the sum of the width D5 and the width D1. The bottleneck portion of the gate structure 252 can be a stepped profile with rounded edges, as shown in FIG. 13C. Please refer to FIG. 13E, the gate structure 252 conforms to the shape of the dummy gate stack 220 in FIG. 7D. Therefore, the gate structure 252 includes a top portion having a width D9 and a bottom portion having a width D10 along the X direction. In some embodiments, the width D10 is smaller than the width D9 by about 2 times the depth D4. Therefore, the adjacent gate spacer 2260 includes a bottom portion having a first thickness along the X direction and a top portion having a second thickness along the X direction. The first thickness is greater than the second thickness. Since the protrusion 2260a fills and conforms to the notch 229 of FIG. 7E, please refer to FIG. 13G, the protrusion 2260a is interlaced with the channel layer 208 and surrounds the top surface and sidewalls of the fin structure 212.

[0060] Referring to FIG. 1 , method 10 includes block 32 , wherein further processing is performed to complete the fabrication of workpiece 200 . For example, subsequent processing may form contact openings, contact metals, and various contacts / vias / conductors and multi-layer interconnect structures (e.g., metal layers and inter-layer dielectric layers) configured to connect various components to form functional circuits that may include one or more multi-gate devices. Various conductive materials may be used for various interconnect components, including copper, tungsten, and / or silicide. In one example, a damascene and / or dual damascene process is used to form a copper-related multi-layer interconnect structure.

[0061] Although not intended to be limiting, one or more embodiments of the present invention provide many advantages to semiconductor structures and methods of forming the same. For example, embodiments of the present invention provide methods of manufacturing semiconductor structures. By recessing a sacrificial layer prior to forming a gate spacer, the gate spacer formed thereafter includes a protrusion extending into an adjacent gate structure. The protrusion of the gate spacer provides more protection for the source / drain components during the channel release process, thereby avoiding and / or reducing source / drain damage, and more completely removing the sacrificial layer during the channel release process. The thickened gate spacer can also reduce electrical shorts between the source / drain components and the gate structure.

[0062] In an exemplary aspect, an embodiment of the present invention relates to a method, which includes providing a workpiece, the workpiece including a stack of multiple semiconductor layers extending longitudinally along a first direction; forming a dummy gate structure to surround a channel region of the stack of multiple semiconductor layers, and the dummy gate structure extends longitudinally along a second direction perpendicular to the first direction; after forming the dummy gate structure, performing a first etching process to selectively recess the multiple second semiconductor layers; after the first etching process, forming a square on the dummy gate structure and the stack of multiple semiconductor layers The invention relates to a method for forming a gate spacer layer; recessing the source / drain region of the stack of multiple semiconductor layers to form a source / drain opening that exposes the sidewalls of the stack of multiple semiconductor layers; after recessing the source / drain region, performing a second etching process to selectively recess multiple second semiconductor layers from the source / drain opening to form an internal spacer recess; forming an internal spacer in the internal spacer recess; forming a source / drain component in the source / drain opening; and replacing the dummy gate structure and the multiple second semiconductor layers with a metal gate structure. The stack of multiple semiconductor layers includes a plurality of first semiconductor layers and a plurality of second semiconductor layers that are interlaced.

[0063] In some embodiments, after performing the first etching process, in a horizontal plane of a layer across the plurality of second semiconductor layers, the layer has a first width along the first direction and is adjacent to the dummy gate structure, and the dummy gate structure has a second width along the first direction, and the second width is greater than the first width. In some embodiments, performing the first etching process forms a plurality of first recesses directly below the dummy gate structure, and the step of forming the gate spacer layer includes depositing the gate spacer layer in the plurality of first recesses. In some embodiments, the presence of the plurality of first recesses makes the stack of the plurality of semiconductor layers have a wavy profile when the stack of the plurality of semiconductor layers is viewed along the first direction. In some embodiments, performing the first etching process includes using a solution including hydrogen fluoride (HF), hydrogen peroxide (H 2O 2), hydrochloric acid (HCl), or a combination thereof. In some embodiments, after performing the first etching process, in a cross-sectional schematic diagram perpendicular to the first direction, the plurality of first semiconductor layers have a first width along the second direction, and the plurality of second semiconductor layers have a second width along the second direction, and the second width is less than the first width. In some embodiments, the first etching process performed is isotropic. In some embodiments, the step of forming a dummy gate structure includes: forming a dielectric layer above a stack of a plurality of semiconductor layers; depositing a polysilicon layer above the dielectric layer; and removing the dielectric layer and the polysilicon layer above the source / drain region of the stack of a plurality of semiconductor layers; the step of performing the first etching process includes: a first step of selectively recessing a plurality of second semiconductor layers; and a second step of selectively recessing the dielectric layer. In some embodiments, the second step forms a second recess between the stack of a plurality of semiconductor layers and the dummy gate structure. In some embodiments, the step of forming a gate spacer includes depositing a gate spacer in the second recess.

[0064] In another exemplary aspect, an embodiment of the present invention relates to a method, the method comprising providing a workpiece, comprising: a first channel layer and a second channel layer, extending longitudinally along a first direction; and a sacrificial layer, disposed between the first channel layer and the second channel layer. The method further comprises forming a dummy gate structure above the first channel layer, the second channel layer, and the sacrificial layer; performing an etching process to selectively and partially recess the sacrificial layer from a first sidewall of the sacrificial layer parallel to the first direction; depositing a gate spacer layer above the dummy gate structure, the first channel layer, the second channel layer, and the sacrificial layer; recessing the source / drain regions of the first channel layer, the second channel layer, and the sacrificial layer to form a source / drain opening; and forming a source / drain component in the source / drain opening. The dummy gate structure extends longitudinally along a second direction perpendicular to the first direction. After forming the source / drain component, a portion of the gate spacer layer is located between the first channel layer and the second channel layer.

[0065] In some embodiments, after the etching process, in a horizontal plane across the sacrificial layer, the sacrificial layer has a first width along the first direction and is adjacent to the dummy gate structure, and the dummy gate structure has a second width along the first direction, and the first width is smaller than the second width. In some embodiments, after the etching process, in a cross-sectional schematic diagram perpendicular to the first direction, the second sidewall of the sacrificial layer is recessed from the sidewalls of the first channel layer and the second channel layer. In some embodiments, the step of performing the etching process includes a wet etching process using a solution including hydrogen fluoride (HF), hydrogen peroxide (H 2O 2), hydrochloric acid (HCl), or a combination thereof. In some embodiments, performing the etching process forms a recess directly below the dummy gate structure. In some embodiments, the step of depositing a gate spacer includes depositing a gate spacer in the recess.

[0066] In another exemplary aspect, an embodiment of the present invention relates to a semiconductor structure, the semiconductor structure comprising a channel stack, comprising a first channel element and a second channel element; a gate structure disposed around the first channel element and the second channel element and extending longitudinally along a first direction; an internal spacer disposed between the first channel element and the second channel element; and a gate spacer disposed on the gate structure and connected to the internal spacer. In a horizontal plane between the first channel element and the second channel element, the gate spacer includes a portion protruding into the gate structure along a second direction perpendicular to the first direction.

[0067] In some embodiments, the portion of the gate spacer is disposed between the first channel element and the second channel element. In some embodiments, the interface between the inner spacer and the gate spacer is disposed between the first channel element and the second channel element. In some embodiments, in a horizontal plane, the gate structure has a narrower section adjacent to the portion of the gate spacer.

[0068] The foregoing text summarizes the features of many embodiments, so that those with ordinary knowledge in the art can better understand the embodiments of the present invention from various aspects. Those with ordinary knowledge in the art should understand and can easily design or modify other processes and structures based on the embodiments of the present invention, and thereby achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those with ordinary knowledge in the art should also understand that these equivalent structures do not deviate from the spirit and scope of the invention of the embodiments of the present invention. Various changes, substitutions or modifications can be made to the embodiments of the present invention without departing from the spirit and scope of the invention of the embodiments of the present invention.

[0069] 10: Methods 12,14,16,18,20,22,24,26,28,30,32: Blocks 200:Workpiece 202: Base 204: Base 206: Sacrificial layer 208: Channel layer 210: Semiconductor layer stack 212: Fin structure 212C: Channel area 212SD: Source / Drain Region 214: Isolation components 216: dummy dielectric layer 218: dummy electrode layer 219: Edge 220: dummy gate stack 222: Gate top hard mask layer 223: Silicon oxide layer 224: Silicon nitride layer 225: First notch 225a,B1:Partial 226: Gate spacer layer 227: Second notch 228: Source / Drain Trench 229: Notch 230: Internal spacer notch 231: Inner surface 233: Outer surface 234: Internal gap wall 235: Interface 237: Dashed rectangle 242: Source / drain component 244: Contact etching stop layer 246: Interlayer dielectric layer 252: Gate structure 254: Gate dielectric layer 256: Gate electrode layer 260: Fully wound gate transistor 2260: Gate spacer 2260a: protrusion B: Area B2: Dashed rounded rectangle B3: Dashed circle B4: Dashed Line Rounded Rectangle D1,D2,D4: Depth D3,D5,D5',D8,D9,D10: Width D6,D7:Thickness

Claims

1. A method of forming a semiconductor structure, comprising: providing a workpiece including a stack of a plurality of semiconductor layers extending longitudinally along a first direction, wherein the stack of the plurality of semiconductor layers includes an interleaved plurality of first semiconductor layers and a plurality of second semiconductor layers; forming a dummy gate structure to surround a channel region of the stack of the plurality of semiconductor layers, and the dummy gate structure extending longitudinally along a second direction perpendicular to the first direction; after forming the dummy gate structure, performing a first etching process to selectively recess the plurality of second semiconductor layers; after the first etching process, forming a gate spacer layer over the dummy gate structure and the stack of the plurality of semiconductor layers; recessing a source / drain region of the stack of the plurality of semiconductor layers to form a source / drain opening exposing a sidewall of the stack of the plurality of semiconductor layers; After the source / drain region is recessed, a second etching process is performed to selectively recess the plurality of second semiconductor layers from the source / drain opening to form an internal spacer wall notch; an internal spacer wall is formed in the internal spacer wall notch; a source / drain component is formed in the source / drain opening; and a metal gate structure is used to replace the dummy gate structure and the plurality of second semiconductor layers.

2. The method of forming a semiconductor structure as claimed in claim 1, wherein after the first etching process, in a horizontal plane of a layer spanning the plurality of second semiconductor layers, the layer has a first width along the first direction and is adjacent to the dummy gate structure, and the dummy gate structure has a second width along the first direction, the second width being greater than the first width.

3. The method for forming a semiconductor structure as claimed in claim 1, wherein the first etching process forms a plurality of first notches directly below the dummy gate structure, and wherein the step of forming the gate spacer layer includes depositing the gate spacer layer in the plurality of first notches.

4. A method for forming a semiconductor structure as claimed in any one of claims 1 to 3, wherein the step of forming the dummy gate structure includes: forming a dielectric layer over the stack of the plurality of semiconductor layers; depositing a polysilicon layer over the dielectric layer; and removing the dielectric layer and the polysilicon layer over the source / drain region of the stack of the plurality of semiconductor layers; wherein the step of performing the first etching process includes: a first step of selectively recessing the plurality of second semiconductor layers; and a second step of selectively recessing the dielectric layer.

5. The method for forming a semiconductor structure as claimed in claim 4, wherein the second step forms a second notch between the stack of the plurality of semiconductor layers and the dummy gate structure, and wherein the step of forming the gate spacer layer includes depositing the gate spacer layer in the second notch.

6. A method of forming a semiconductor structure, comprising: providing a workpiece, including: a first channel layer and a second channel layer extending longitudinally along a first direction; and a sacrificial layer disposed between the first channel layer and the second channel layer; forming a dummy gate structure over the first channel layer, the second channel layer and the sacrificial layer, wherein the dummy gate structure extends longitudinally along a second direction perpendicular to the first direction; performing an etching process to selectively and partially recess the sacrificial layer from a first sidewall parallel to the first direction; depositing a gate spacer layer over the dummy gate structure, the first channel layer, the second channel layer and the sacrificial layer; recessing a source / drain region of the first channel layer, the second channel layer and the sacrificial layer to form a source / drain opening; and forming a source / drain component in the source / drain opening, wherein after forming the source / drain component, a portion of the gate spacer layer is located between the first channel layer and the second channel layer.

7. A semiconductor structure comprising: a channel stack including a first channel element and a second channel element; a gate structure disposed around the first channel element and the second channel element and extending longitudinally along a first direction; an internal spacer wall disposed between the first channel element and the second channel element; and a gate spacer wall disposed on the gate structure and in contact with the internal spacer wall, wherein in a horizontal plane between the first channel element and the second channel element, the gate spacer wall includes a portion protruding into the gate structure along a second direction perpendicular to the first direction.

8. The semiconductor structure of claim 7, wherein the portion of the gate spacer layer is disposed between the first channel element and the second channel element.

9. The semiconductor structure of claim 7 or 8, wherein an interface between the internal spacer wall and the gate spacer layer is disposed between the first channel element and the second channel element.

10. The semiconductor structure of claim 7 or 8, wherein in the horizontal plane, the gate structure has a narrower section adjacent to the portion of the gate gap wall.

Images