Semiconductor cell architecture including backside power rails

Abstract

The present invention provides a semiconductor cell architecture comprising multiple cells, multiple back power rails and multiple metal lines, wherein, in a plan view, the back power rails extend along the length direction of the cell, and at least one back power rail vertically overlaps with the internal region of at least one cell but not vertically overlaps with the lower or upper boundary of at least one cell.

Description

Semiconductor unit architecture including back power rails Devices and methods consistent with example embodiments of the present disclosure relate to standard cells for semiconductor devices. One or more semiconductor cells provided for implementing a logic circuit when designing an integrated circuit have a predetermined architecture and can be stored in a cell library. This semiconductor cell can be a standard cell and can also be referred to herein as a cell. A standard cell can include a plurality of active regions and gate structures forming one or more transistors, and the one or more transistors are configured to perform logic functions such as AND, OR, NOR, NAND, XOR, multiplexer, etc. When designing an integrated circuit, one or more cells are retrieved from the cell library and placed in desired positions on the integrated circuit layout. Then, wiring interconnects or metal lines (collectively referred to hereinafter as "metal lines") are performed for the component connections within and between the cells to form a semiconductor cell architecture for the semiconductor device. Each cell can have a predetermined size in terms of cell width, cell height, cell length, etc. The device performance and design / manufacturing efficiency of an integrated circuit can be determined according to the configuration or layout of the semiconductor cells and the metal lines, and the metal lines connect the active regions and gate structures forming one or more transistors in each cell to each other or to other circuit components or power rails. For example, a long signal wiring path formed by one or more metal lines can cause signal attenuation, delay or interference, an increase in IR drop, connection resistance and / or capacitance, thereby reducing device performance. In addition, the metal lines forming a long signal wiring path make the design and manufacturing work difficult and complex. The information disclosed in this background section was known to the inventors before achieving the embodiments of this application or was technical information obtained during the process of achieving the embodiments described herein. Therefore, the information may contain information that does not form prior art known to the public. Various example embodiments provide a semiconductor cell architecture in which a plurality of back power rails are formed at a predetermined pitch. According to an embodiment, a semiconductor cell architecture is provided, which can include a plurality of cells, a plurality of back power rails, and a plurality of metal lines. In a plan view, the back power rails extend in the cell length direction, and at least one back power rail vertically overlaps an internal region of at least one cell without vertically overlapping a lower boundary or an upper boundary of at least one cell. In a plan view, at least one back power rail can vertically overlap an upper boundary or a lower boundary of another at least one cell. According to an embodiment, a semiconductor cell structure is provided, which may include a plurality of cells, a plurality of back power rails, and a plurality of metal lines, wherein the cells have an equal cell height, the back power rails extend in the cell length direction, and at least two adjacent cells in the cell length direction do not share a complete side boundary of the cell length. According to an embodiment, a semiconductor cell structure is provided, which may include a plurality of cells, a plurality of back metal lines, and a plurality of metal lines, wherein in a plan view, the back metal lines extend in the cell length direction, the metal lines include a plurality of first metal lines extending in the cell length direction in a first metal layer and a plurality of second metal lines extending in the cell height direction in a second metal layer, and the first metal lines are placed in at least one column defined by two adjacent back metal lines. The embodiments described herein are exemplary embodiments, and thus, the present disclosure is not limited thereto and can be implemented in various other forms. Each of the embodiments provided herein does not exclude being associated with one or more features of another example or another embodiment provided herein or not provided herein but consistent with the present disclosure. For example, even if the materials described in a specific example or embodiment are not described in another different example or embodiment, unless otherwise mentioned in its description, the materials can still be understood as being related to or combined with different examples or embodiments. Additionally, it should be understood that all descriptions of the principles, aspects, examples, and embodiments of the present disclosure are intended to cover their structural and functional equivalents. Additionally, these equivalents should be understood to include not only currently well-known equivalents but also equivalents to be developed in the future, that is, all devices invented to perform the same function, regardless of their structure. It should be understood that when an element, component, layer, pattern, structure, region, etc. (hereinafter collectively referred to as "element") of a semiconductor device is referred to as "over", "above", "on", "below", "under", "beneath", "connected to", or "coupled to" another element of the semiconductor device, it may be directly "over", "above", "on", "below", "under", "beneath", "connected to", or "coupled to" the other element, or there may be one or more intervening elements. In contrast, when an element of a semiconductor device is referred to as "directly over", "directly above", "directly on", "directly below", "directly under", "directly beneath", "directly connected to", or "directly coupled to" another element, there are no intervening elements. Throughout the present disclosure, the same reference numerals refer to the same elements. For ease of description, spatial relative terms such as "above", "over", "on", "upper", "below", "beneath", "under", "lower", "left", "right", "lower-left", "lower-right", "upper-left", "upper-right", "central", "middle", and the like may be used herein to describe the relationship of one element to another as shown in the drawings. It should be understood that, in addition to the orientation depicted in the drawings, the spatial relative terms are intended to encompass different orientations of the semiconductor device during use or operation. For example, if the semiconductor device in the drawings is flipped, an element described as "under" or "beneath" other elements will be oriented "above" the other elements. Thus, the term "beneath" can encompass both orientations of above and beneath. The semiconductor device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. As another example, when an element referred to as a "lower" element and an "upper" element can be a "upper" element and a "lower" element, different orientations include devices or structures that include these elements. Thus, in the following description, the "lower" element and the "upper" element may also be referred to as the "first" element or the "second" element, respectively, as long as their structural relationship is clearly understood in the context of the description. Similarly, the terms "left" element and "right" element may be referred to as the "first" element and the "second" element, respectively, with the necessary description to distinguish the two elements. It should be understood that although the terms "first", "second", "third", "fourth", "fifth", "sixth", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, without departing from the teachings of the present disclosure, a first element described in one embodiment herein may be referred to as a second element in another embodiment or claims of the present disclosure. As used herein, a phrase such as "at least one of" when preceding a list of elements modifies the entire list of elements and not individual elements in the list. For example, the phrase "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. In the present disclosure, when the term "same" is used to compare the sizes of two or more than two elements, the term may encompass "substantially the same" sizes. It should be understood that the various elements illustrated in the drawings are schematic illustrations not drawn to scale. Additionally, for ease of explanation, one or more elements of the type commonly used to form semiconductor devices may not be explicitly illustrated in the drawings, but this does not mean that these elements are omitted from the actual semiconductor device. Furthermore, it should be understood that the embodiments described herein are not limited to the specific materials, features, and manufacturing steps or operations illustrated or described herein. Thus, the description provided herein with respect to semiconductor manufacturing steps is not intended to include all steps that may be required to form an actual semiconductor device. For example, common steps such as planarization, cleaning, or annealing steps may not be described herein for the sake of brevity. It should also be understood that even if a step or operation is described later than another step or operation, the step or operation may be performed later than the other step or operation, unless the other step or operation is described as being performed after the step or operation. Many embodiments are described herein with reference to cross-sectional views that are schematic illustrations as examples. Accordingly, shape variations due to, for example, manufacturing techniques and / or tolerances are expected. Thus, embodiments should not be construed as limited to the specific shapes of the elements shown herein, but will include shape deviations due to, for example, manufacturing. The various elements shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the elements of a semiconductor device, and are not intended to limit the scope of the present disclosure. Additionally, when conventional elements of a semiconductor device are not relevant to the novel features of an embodiment or are unnecessary in depicting the features, these elements and their functions, materials, and shapes may not be described. Hereinafter, various embodiments of the present disclosure will be described with reference to FIGS. 1 to 4. FIG. 1 is a plan view of a semiconductor cell structure including a plurality of cells on which a positive power rail is formed according to an embodiment. Referring to FIG. 1, the semiconductor cell structure 10 may include a plurality of cells C1, C2, and C3 disposed in the first column in the first direction D1, and another plurality of cells C4, C5, and C6 disposed in the second column in the first direction D1. The first direction D1 and the second direction D2 respectively indicate the cell length direction and the cell height direction, and may intersect horizontally with each other. Each of the cells CL1 to CL6 may have a fixed cell length CL and a fixed cell height CH. Each of the cells C1 to C6 may include one or more active regions and gate structures to form one or more transistors. The active region may include source / drain regions and channel structures of one or more transistors formed in the semiconductor cell structure 10. Units C1 to C3 may have respective upper boundaries coplanar in the first direction D1 to form a combined upper boundary B1 of units C1 to C3. Units C1 to C3 may also have respective lower boundaries coplanar in the first direction D1 to form a combined lower boundary B2 of units C1 to C3. The lower boundary B2 of units C1 to C3 may also be the combined upper boundary of units C4 to C6. Units C4 to C6 may also have respective lower boundaries coplanar in the first direction D1 to form a combined lower boundary B3 of units C4 to C6. According to an embodiment, the boundaries B1 to B3 and each unit boundary may be implemented by an isolation or insulation structure such as a shallow trench isolation (STI) structure, a gate cut structure, a fin cut structure, etc., and the isolation or insulation structure may be formed of a dielectric material such as silicon oxide or silicon nitride, but is not limited thereto. The semiconductor unit structure 10 may include three power rails 110, 120, and 130 located on the front surfaces of units C1 to C6. The power rail 110 may be placed on the combined upper boundary B1 of units C1 to C3, and the power rail 120 may be placed on the combined lower boundary B2 of units C1 to C3 that is also the combined upper boundary of units C4 to C6. The power rail 130 may be placed on the combined lower boundary B3 of units C4 to C6. These power rails 110 to 130 may vertically overlap the respective unit boundaries B1 to B3 in a third direction D3 intersecting the first direction D1 and the second direction D2. Accordingly, the power rails 110 to 130 may be arranged at a front power rail pitch FP in the second direction D2, and the pitch may be equal to a fixed unit height CH. The power rail 110 and the power rail 130 may each provide a first voltage to the semiconductor unit structure 10, and the power rail 120 may provide a second voltage lower than the first voltage to the semiconductor unit structure 10. For example, the second voltage may be a ground voltage or a negative voltage. Based on the positions of power rails 110 to 130 at boundaries B1 to B3, multiple metal lines M11 to M18 and multiple metal lines M21 to M23 can be placed in units C1 to C6 to connect the active region and the gate structure to other circuit elements and power rails 110 to 130, respectively. Metal lines M11 to M18 and power rails 110 to 130 can be placed and extended in a first direction D1 in a first metal layer, and the first metal layer is vertically above the active region and the gate structure in a third direction D3. Metal lines M21 to M23 can be placed and extended in a second direction D2 in a second metal layer, and the second metal layer is vertically above the first metal layer in the D3 direction. In the plan view shown in FIG. 1, power rails 110 to 130 and metal lines M11 to M18 can be arranged in the second direction D2 with a first metal pitch MP1, and metal lines M21 to M23 can be arranged in the first direction D1 with a second metal pitch MP2. For example, when the semiconductor cell structure 10 is designed to implement a flip-flop circuit, metal line M13 can be placed as an input node in unit C2 to receive an input signal for the master latch, and metal line M14 can be placed as an output node in unit C3 to receive the output signal of the master latch as an input signal for the slave latch. In addition, metal line M11 can be placed as another output node in unit C1 to receive the output signal of the master latch as a feedback signal to the master latch. Here, these metal lines M11, M13, and M14 can be placed in respective units C1, C2, and C3 based on the fixed sizes, configurations, and positions of units C1 to C6 relative to each other and the fixed positions of power rails 110 to 130 at respective boundaries B1, B2, and B3 in the semiconductor cell structure 10. Therefore, the placement positions of metal lines M11, M13, and M14 can be highly restricted, such that output node metal line M11 and output node metal line M14 can be far from input node metal line M13, thereby forming a long signal routing path in the semiconductor cell structure 10. For example, output node metal line M11 and output node metal line M14 can be two metal line pitches away from input node metal line M13 and four metal line pitches apart in the second direction D2. As described earlier, the long signal routing path formed by metal lines in the semiconductor cell structure can lead to manufacturing difficulties and reduced device performance. In addition, as shown in FIG. 1, when the wire M23 in the unit C5 can be the input node of the output inverter circuit of the flip-flop circuit, for example, the risk of short circuit or signal interference can increase. This is because the wire M23 configured to receive the output signal of the controlled latch is placed too close to the wire M22 configured to receive the input signal of the master latch. For example, the distance "d" between the two wires M22 and the wire M23 can even be much lower than a first wire pitch in the second direction D2. Although FIG. 1 shows that the semiconductor cell structure 10 includes three cells at each of two columns and three power rails 110 to 130, 11 wires M11 to M18 and wires M21 to M23 at two metal layers, and three power rails 110 to 130. However, there may be more or less than three cells at each column, more or less than 11 wires at more or less than two metal layers, and more or less than three power rails may be formed in the semiconductor cell structure 10. To solve the long signal routing path and signal interference in the semiconductor cell structure 10 shown in FIG. 1, repositioning the cells C1 to C6 can be considered. FIG. 2 is a plan view of a semiconductor cell structure in which a plurality of cells in the semiconductor cell structure of FIG. 1 are repositioned according to an embodiment. Referring to FIG. 2, the semiconductor cell structure 20 may include the same cells C1 to C6, power rails 110 to 130, and wires M11 to M18 and wires M21 to M23 as those included in the semiconductor cell structure 10. Therefore, its repeated description can be omitted. However, according to an embodiment, compared with the semiconductor cell structure 10 shown in FIG. 1, the semiconductor cell structure 20 may have different configurations of the cells C3, C5, and C6. The cells C3 and C6 adjacent to each other in the second direction D2 can be moved up by one cell height, thereby reducing the distance between the input node wire M13 and the output node wire M14 in the second direction D2 by at least two wire pitches. In addition, the cell C5 including the interfering wire M23 can be moved down by one cell height, thereby removing or reducing the risk of short circuit and signal interference with respect to the wire M22 in the cell C2. However, as shown in FIG. 2, the entire occupied area of the semiconductor unit structure 10 can be increased by at least two unit heights in the second direction D2. This is because the unit configuration and placement of the metal lines on the front side of the semiconductor unit structure 10 or the semiconductor unit structure 20 depend on the positions of the power rails 110, 1120, and 130 at the respective unit boundaries B1, B2, and B2 and the fixed unit length CL and fixed unit height CH on the same front side of the semiconductor unit structure 10 or the semiconductor unit structure 20. Therefore, when moving in the second direction D2, each of the units C1 to C6 in the semiconductor unit structure 10 and the semiconductor unit structure 20 has to move at least one or more unit heights. Therefore, to solve the increase in the size of the semiconductor unit structure 20 and the long signal wiring path and signal interference in the semiconductor unit structure 10, as shown in the example of FIG. 3, the following embodiments provide a semiconductor unit structure in which the placement of the metal lines is flexibly adjusted based on a backside power distribution network (BSPDN). A BSPDN structure is introduced to solve the wiring complexity at the front side of the semiconductor device during the back-end-of-line (BEOL) process of manufacturing the semiconductor device. The BSPDN structure can include, for example, a back contact structure formed on the bottom surface of the source / drain region of the transistor; and back metal lines, which can be signal path metal lines or power rails connecting the back contact structure to a voltage source from the back side of the semiconductor device. The BSPDN structure can be formed in the substrate on which the active region and the gate structure are formed, or in a back isolation structure that replaces at least a part of the substrate at the back side of the semiconductor device. Since the BSPDN structure is formed at the back side of the semiconductor device, the semiconductor device can achieve area gain, prevent excessive IR drop at its front side, and reduce the manufacturing complexity at its front side. FIG. 3 is a plan view of a semiconductor unit structure on which a BSPDN structure is formed according to an embodiment. Referring to FIG. 3, the semiconductor unit structure 30 can include the same units C1 to C6 as those included in the semiconductor unit structure 10, and metal lines M11 to M18 and metal lines M21 to M23. Therefore, its repeated description can be omitted. However, according to an embodiment, the semiconductor cell structure 30 may include a plurality of back power rails BPR1 to BPR8 located on the back surface of the semiconductor cell structure 30 instead of the front power rails 110 to 130 illustrated in FIGS. 1 and 2. According to an embodiment, the back power rails BPR1 to BPR8 may extend parallel in the first direction D1 and be arranged at a back power rail pitch BP in the second direction D2, and the pitch may be less than the cell height CH and greater than the first metal line pitch MP1 of the semiconductor cell structures 10 and 20. The back power rail pitch BP may also be a back metal line pitch because any one of the back power rails BPR1 to BPR8 may be replaced by a back metal line that is not a power rail. When a back metal line is formed at the position of any one of the back power rails BPR1 to BPR8, the back metal line may not be as long as the back power rail and, instead, may be sized according to its connection purpose. According to an embodiment, the back power rails BPR1 to BPR8 illustrated in FIG. 3 may all be back metal lines, and a selected one of the back metal lines may be used as a back power rail. According to an embodiment, the back power rail pitch BP may be an integer multiple of the first metal line pitch MP1. For example, the back power rail pitch BP may be twice the first metal line pitch MP1 as illustrated in FIG. 3. However, the cell height CH and the first metal line pitch MP1 in the semiconductor cell structure 30 may be equal to the cell height and the first metal line pitch in the semiconductor cell structures 10 and 20. According to an embodiment, unlike the upper and lower boundaries of the cells C1 to C6 of the semiconductor cell structures 10 and 20, the upper and lower boundaries of the cells C1 to C6 of the semiconductor cell structure 30 may not be coplanar in the first direction D1. Therefore, two adjacent cells C1 and C2 may not share the side boundaries of their entire lengths in the second direction D2 while their cell heights are equal to each other. As illustrated in FIG. 3, only two back power rail pitches overlap between the right side boundary and the left side boundary of the cell C1. This configuration is possible because, compared with the embodiments of FIGS. 1 and 2 where the cell height CH is equal to the front power rail pitch, the cell height CH is greater than the BPR pitch, for example, an integer multiple of the BPR pitch. Therefore, according to an embodiment, the positions of the back power rails BPR1 to BPR8 in the semiconductor cell structure 30 may not be limited to the upper or lower boundaries of the cells C1 to C6. For example, the back power rail BPR2 may cross the internal regions of each of the cells C1 and C3 without vertically overlapping the upper or upper and lower boundaries of these cells, while it may vertically overlap the upper boundary of the cell C2. Also, however, according to an embodiment, each of the lower and upper boundaries of each of units C1 to C6 may overlap with any one of back power rails BPR1 to BPR8. According to an embodiment, due to the freedom of power rail placement at the back side of the semiconductor unit structure 30, the position of each of units C1 to C6 can be changed more freely in the second direction. For example, as illustrated in FIG. 3, unit C1 can be moved upward relative to unit C2 by two first metal line pitches (e.g., one BPR pitch) to place the output node metal line M11 coplanar with the input node metal line M13 in the first direction D1, such that these two metal lines can be close enough to reduce the length of the signal routing path. According to an embodiment, when unit C1 moves, unit C4, which is vertically adjacent to unit C1, can also be moved upward relative to unit C2 by two first metal line pitches. As another example, as illustrated in FIG. 3, unit C3 can be moved upward relative to unit C2 by four first metal line pitches to place the output node metal line M14 coplanar with the input node metal line M13 in the first direction D1, such that these two metal lines can also be close enough to reduce the length of the signal routing path. According to an embodiment, when unit C3 moves, unit C6, which is vertically adjacent to unit C1, can also be moved upward relative to unit C2 by four first metal line pitches. As yet another example, as illustrated in FIG. 3, unit C4 can be moved downward relative to unit C2 by two first metal line pitches to space the metal line M23 apart from the metal line M22 such that the signals transmitted by these two metal lines may not interfere with each other, and / or to reduce the risk of short circuit due to being closely adjacent. According to an embodiment, the back power rails BPR1 to BPR8 extending in the first direction D1 may not vertically (in the third direction D3) overlap with the metal lines M11 to M18 also extending in the first direction D1 in the first metal layer, so as to at least minimize signal interference therebetween and wiring convenience at the back of the semiconductor cell structure 30, because the power rails 110 to 130 at the front of the semiconductor cell structure 10 and the semiconductor cell structure 20 do not overlap with the metal lines M11 to M18. For example, each of the metal lines M11 to M18 may be placed in a column defined by two adjacent back power rails. However, the present disclosure is not limited thereto. According to an embodiment, two or more metal lines spaced apart in the second direction D2 at the first metal layer may be placed in a column defined by two adjacent back power rails. In addition, according to an embodiment, one or more metal lines at the first metal layer may vertically overlap with one or more of the back power rails in the semiconductor cell structure 30. This vertical overlap between the back power rails and the metal lines at the first metal layer extending in the same direction can be achieved because the back power rails are formed at the back of the active regions and gate structures in the semiconductor cell structure 30, while the metal lines are formed at the opposite front of the active regions and gate structures. Since the cell positions can be freely adjusted without being limited to the front power rails, the semiconductor cell structure 30 can still have a minimum increase in occupied area even when the length of the signal wiring path is significantly reduced and the risk of short circuit or signal interference between adjacent metal lines is also reduced. According to an embodiment, the back power rails BPR1, BPR3, BPR5, and BPR7 may each provide a first voltage, and the alternately arranged back power rails BPR2, BRP4, BRP6, and BPR8 may each provide a second voltage that may be lower than the first voltage. However, the present disclosure is not limited thereto. Either of two adjacent back power rails may provide the same voltage to the semiconductor cell structure 30 according to an embodiment. Although FIG. 3 shows that the semiconductor cell structure 30 includes eight back power rails, the present disclosure is not limited thereto. According to an embodiment, there may be more or fewer than eight back power rails formed in the semiconductor cell structure 30. In the above embodiments, each of the back power rails BPR1 to BPR6, the metal lines M11 to M18, and the metal lines M21 to M23 may be formed of a metal or metal compound including copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), etc. In the above embodiments, the transistors or transistor structures formed in the semiconductor cell structure 30 may be fin field-effect transistors (FinFETs), nanosheet transistors, or the like, but are not limited thereto. A FinFET has one or more horizontally disposed vertical fin structures as channel structures surrounded by a gate structure on at least three surfaces, and a nanosheet transistor structure is characterized in that one or more nanosheet channel layers are vertically stacked on a substrate as channel structures, and the gate structure surrounds all four surfaces of each of the nanosheet channel layers. Nanosheet transistors are referred to as gate-all-around (GAA) transistors, multi-bridge channel field-effect transistors (MBCFETs). FIG. 4 is a schematic block diagram showing an electronic device manufactured based on the semiconductor cell structure 30 or a part thereof as described above with reference to FIG. 3 according to an embodiment. Referring to FIG. 4, the electronic device 4000 may include at least one application processor 4100, a communication module 4200, a display / touch module 4300, a storage device 4400, and a buffer random access memory (RAM) 4500. According to an embodiment, the electronic device 4000 may be a mobile device such as a smartphone or a tablet computer, but is not limited thereto. The application processor 4100 may control the operation of the electronic device 4000. The communication module 4200 is implemented to perform wireless communication or wired communication with an external device. The display / touch module 4300 is implemented to display data processed by the application processor 4100 and / or receive data via a touch panel. The storage device 4400 is implemented to store user data. The storage device 4400 may be an embedded multimedia card (eMMC), a solid state drive (SSD), a universal flash storage (UFS) device, or the like. The storage device 4400 may perform high-speed access to the mapped data and user data as described above. The buffer RAM 4500 can temporarily store data for processing the operations of the electronic device 4000. For example, the buffer RAM 4500 can be a volatile memory, such as double data rate (DDR) synchronous dynamic random access memory (SDRAM), low power double data rate (LPDDR) SDRAM, graphics double data rate (GDDR) SDRAM, Rambus dynamic random access memory (RDRAM), etc. The electronic device 4000 can further include at least one sensor, such as an image sensor. At least one component in the electronic device 4000 can be manufactured based on the semiconductor unit architecture 30 or a part thereof described above with reference to FIG. 3. The foregoing describes example embodiments and is not to be construed as a limitation of the disclosure. Although some example embodiments have been described above, those of ordinary skill in the art will readily understand that many modifications are possible in the above embodiments without materially departing from the disclosure. 10, 20, 30: Semiconductor unit architecture 110, 120, 130: Power rail 4000: Electronic device 4100: Application processor 4200: Communication module 4300: Display / touch module 4400: Storage device 4500: Buffer random access memory B1, B2, B3: Boundary BP: Backside power rail pitch BPR1, BPR2, BPR3, BPR4, BPR5, BPR6, BPR7, BPR8: Backside power rail C1, C2, C3, C4, C5, C6: Cell CH: Cell height CL: Cell length d: Distance D1: First direction D2: Second direction D3: Third direction FP: Front side power rail pitch M11, M12, M13, M14, M15, M16, M17, M18, M21, M22, M23: Metal line MP1: First metal pitch MP2: Second metal pitch A better understanding of the exemplary embodiments of the present disclosure will be obtained from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. 1 is a plan view of a semiconductor cell structure including a plurality of cells having a front power rail formed thereon according to an embodiment. FIG. 2 is a plan view of a semiconductor cell structure in which a plurality of cells in the semiconductor cell structure of FIG. 1 are repositioned according to an embodiment. FIG. 3 is a plan view of a semiconductor cell structure having a BSPDN structure formed thereon according to an embodiment. FIG. 4 is a schematic block diagram of an electronic device manufactured based on the semiconductor cell structure 30 or a portion thereof as described above with reference to FIG. 3 according to an embodiment. 30: Semiconductor cell structure BP: Back power rail pitch BPR1, BPR2, BPR3, BPR4, BPR5, BPR6, BPR7, BPR8: Back power rails C1, C2, C3, C4, C5, C6: Cells CH: Cell height D1: First direction D2: Second direction D3: Third direction M11, M12, M13, M14, M15, M16, M17, M18, M21, M22, M23: Metal lines MP1: First metal pitch

Claims

1. A semiconductor cell architecture, comprising a plurality of cells, a plurality of back power rails, and a plurality of metal lines, wherein the back power rails extend along the length of the cell, and wherein, In a plan view, at least one rear power rail vertically overlaps with the interior region of at least one unit but not with the lower or upper boundary of the at least one unit, wherein in the plan view, the at least one rear power rail vertically overlaps with the upper or lower boundary of another at least one unit, wherein the center of the at least one unit in the unit height direction is at a different height from the center of the other at least one unit in the unit height direction, the unit height direction being perpendicular to the unit length direction.

2. The semiconductor cell architecture as claimed in claim 1, wherein the other at least one cell is adjacent to the at least one cell in the cell length direction.

3. The semiconductor cell architecture as claimed in claim 1, wherein, in the plan view, each of the upper and lower boundaries of each cell vertically overlaps with each of the rear power rails.

4. The semiconductor cell architecture as described in claim 3, wherein the cells have equal cell heights.

5. The semiconductor cell architecture as claimed in claim 4, wherein at least two adjacent cells in the cell length direction do not share a side boundary of the full cell length.

6. The semiconductor cell architecture as claimed in claim 1, wherein a rear power rail positioned between two power rails in the cell height direction provides a voltage difference with respect to the voltage provided by the two power rails.

7. The semiconductor cell architecture as claimed in claim 1, wherein at least one of the back power rails is configured to connect the corresponding cell to another circuit element that is not a voltage source.

8. The semiconductor cell architecture of claim 1, wherein the back power rail extends in the cell length direction, wherein the plurality of metal lines include a plurality of first metal lines extending in the cell length direction in a first metal layer and a plurality of second metal lines extending in the cell height direction in a second metal layer, and wherein, in the plan view, the first metal lines are positioned in at least one column defined by two adjacent back power rails.

9. The semiconductor cell architecture as claimed in claim 8, wherein the spacing of the back power rails is greater than the spacing of the first metal lines.

10. A semiconductor cell architecture comprising a plurality of cells, a plurality of back power rails, and a plurality of metal lines, wherein the cells have equal cell heights, wherein the back power rails extend in a cell length direction, and wherein at least two adjacent cells in the cell length direction do not share a side boundary of the full cell length, wherein in the plan view, at least one back power rail vertically overlaps with the upper or lower boundary of at least one cell, wherein at least two centers of the at least two adjacent cells that do not share the side boundary of the full cell length are located at different heights in the cell height direction, the cell height direction being perpendicular to the cell length direction.

11. The semiconductor cell architecture as claimed in claim 10, wherein, in a plan view, the at least one rear power rail traverses the interior of at least one other cell.

12. The semiconductor cell architecture of claim 11, wherein, in the plan view, each of the upper and lower boundaries of each cell vertically overlaps with each of the rear power rails.

13. The semiconductor cell architecture of claim 12, wherein the metal lines include a first metal line extending in the cell length direction and a second metal line extending in the cell height direction, and wherein, in the plan view, the first metal line does not vertically overlap with the rear power rail.

14. A semiconductor cell architecture comprising a plurality of cells, a plurality of back metal lines, and a plurality of metal lines, wherein the back metal lines extend in a cell length direction, wherein the metal lines include a plurality of first metal lines extending in the cell length direction in a first metal layer, and a plurality of second metal lines extending in a cell height direction in a second metal layer, and wherein, in a plan view, the first metal lines are positioned in at least one column defined by two adjacent back metal lines, wherein at least one back metal line is at least one back power rail, wherein, in the plan view, the at least one back power rail vertically overlaps with an upper or lower boundary of at least one cell, wherein, in the plan view, the at least one back power rail vertically overlaps with an interior region of another at least one cell but not with a lower or upper boundary of the other at least one cell, wherein the center of the at least one cell in the cell height direction is at a different height from the center of the other at least one cell in the cell height direction, the cell height direction being perpendicular to the cell length direction.

15. The semiconductor cell architecture as described in claim 14, wherein at least two back metal lines are back power rails.

16. The semiconductor cell architecture as claimed in claim 15, wherein the spacing of the back metal lines is greater than the spacing of the first metal lines.

17. The semiconductor cell architecture of claim 14, wherein, in the plan view, each of the upper and lower boundaries of each cell vertically overlaps with each of the rear power rails.

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