Silicon controlled rectifers with field plate and method of fabricating the same

Abstract

This invention relates to semiconductor structures, and more particularly to silicon controlled rectifiers having field plate structures and methods of manufacturing them. The structure includes: a plurality of wells of a first type in a semiconductor substrate; a well of a second type in the semiconductor substrate, the second type well surrounding the plurality of wells of the first type; an isolation structure surrounding the plurality of wells of the first type, the isolation structure isolating the second type well from the plurality of wells of the first type; and a plurality of field plates located on the isolation structure, the plurality of field plates surrounding the plurality of wells of the first type.

Description

Silicon Controlled Rectifier with Field Plate The present invention relates to semiconductor structures, and more particularly to silicon controlled rectifiers with field plate structures and manufacturing methods therefor. In order to make power transmission in power systems such as electric vehicles more efficient, the operating voltage has become higher and higher. With the continuously shrinking integrated circuit size, it has become more sensitive to electrostatic discharge. This high voltage usage and continuous scaling of devices require electrostatic discharge (ESD) protection components to maintain such high voltages with sufficient robustness in a small footprint. Traditionally, the method of stacking low-voltage ESD devices has been used to achieve high-voltage operating capabilities. However, the stacking method multiplies the ESD device footprint by the number of stacks. In addition, using multiple ESD devices results in an increase in on-resistance. In one aspect of the present invention, a structure includes: a plurality of wells of a first type in a semiconductor substrate; a well of a second type in the semiconductor substrate, the well of the second type surrounding the plurality of wells of the first type; an isolation structure surrounding the plurality of wells of the first type, the isolation structure isolating the well of the second type from the plurality of wells of the first type; and a plurality of field plates located on the isolation structure, the plurality of field plates surrounding the plurality of wells of the first type. In one aspect of the present invention, a structure includes: a plurality of P-type wells located in a semiconductor substrate; an N-type well isolating the plurality of P-type wells; an isolation structure surrounding the plurality of P-type wells and isolating the plurality of P-type wells from the N-type well; and a plurality of field plates located on the isolation structure, the field plates forming a ring around the plurality of P-type wells. In one aspect of the present invention, a method includes: forming a plurality of wells of a first type in a semiconductor substrate; forming a well of a second type in the semiconductor substrate, the well of the second type surrounding the plurality of wells of the first type; forming an isolation structure surrounding the plurality of wells of the first type, the isolation structure isolating the well of the second type from the plurality of wells of the first type; and forming a plurality of field plates on the isolation structure, the plurality of field plates surrounding the plurality of wells of the first type. The present invention relates to semiconductor structures, and more specifically to silicon controlled rectifiers with field plates and manufacturing methods therefor. More specifically, a silicon controlled rectifier (SCR) is a bidirectional SCR with field plates surrounding the terminals of the device (such as diffusion regions in P-type wells). In a more specific embodiment, the field plates may include polysilicon material on top of an isolation region, such as a LOCOS or shallow trench isolation structure, which surrounds the P-type wells (such as the terminals of the device). Advantageously, the bidirectional SCR exhibits a highly adjustable breakdown voltage in addition to achieving effective electrostatic discharge (ESD) protection against high fault currents (>30 mA / um) in both the forward and reverse directions. In a more specific embodiment, the bidirectional SCR can be used as an ESD protection device for high voltage applications. The bidirectional SCR can include a polysilicon material on top of an isolation region, such as a field plate. The isolation region can be a LOCOS or shallow trench isolation structure. The field plate can be electrically connected to an N+ diffusion region within an N-type well. The N-type well can be, for example, an annular structure that surrounds and isolates the terminals of the device, such as a P-type well. Moreover, in an embodiment, each terminal of the device can be surrounded by a field plate (e.g., polysilicon material) on top of a LOCOS or shallow trench isolation structure. The N-type well can act as a contact point (Pick-up) for a common floating n-type region. For example, the N-type well is electrically connected to the field plate and does not have any electrical terminals, which makes the N-type well electrically floating. The silicon controlled rectifiers of the present invention can be fabricated in a variety of different ways using a variety of different tools. Generally, however, these methods and tools are used to form structures with micron and nanometer scale dimensions. The methods used to fabricate the silicon controlled rectifiers of the present invention are adopted from integrated circuit (IC) technology, i.e., the technology. For example, these structures are built on a wafer and implemented in a thin film of material patterned through a lithography process on top of the wafer. In particular, the fabrication of the silicon controlled rectifier uses three basic building blocks: (i) depositing a thin film of material on a substrate, (ii) applying a patterned mask on top of the film through lithographic imaging, and (iii) selectively etching the film to the mask. Additionally, a pre-cleaning process can be used to clean any contaminants on the etched surface, as is known in the art. Furthermore, when needed, a rapid thermal annealing process can be used to drive in dopants or material layers, as is known in the art. FIG. 1A shows a top view of a bidirectional SCR, other features, and individual processes according to various aspects of the present invention. FIG. 1B shows a cross-sectional view of the bidirectional SCR of FIG. 1A along line A-A. In an embodiment, the bidirectional SCR 10 can be a symmetric bidirectional SCR device disposed on an epitaxial semiconductor material 14 isolated from a semiconductor substrate 12 by a semiconductor layer 16. In an embodiment, the semiconductor substrate 12 can be a bulk substrate or a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 12 can be composed of any suitable semiconductor material, including but not limited to Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors. In a more specific embodiment, the semiconductor substrate 12 can be a p-type Si substrate having a single crystal orientation, such as a (100), (110), (111), or (001) crystal orientation. The semiconductor layer 16 can be formed in the semiconductor substrate 12. In an embodiment, the semiconductor layer 16 can be a buried N+ layer formed via an ion implantation process. As with any implantation region described herein (e.g., well, diffusion region, etc.), an ion implantation process can be implemented that includes introducing dopant concentrations of different conductivity types in the semiconductor substrate 12 (or N+ semiconductor material 16). For example, a patterned implantation mask can be used to define selected regions exposed for implantation to form the implantation region. The implantation mask can include a photosensitive material layer, such as an organic photoresist, applied via a spin coating process, pre-baked, exposed to light projected through the mask, post-exposure baked, and developed using a chemical developer. Each implantation mask has a thickness and stopping power sufficient to block the masked regions to prevent receipt of a certain dose of implanted ions. The N-type dopant can be, for example, arsenic (As), phosphorus (P), and antimony (Sb), as well as other suitable examples. The P-type dopant can be, for example, boron (B). An annealing process, such as rapid thermal annealing known in the art, can be performed to drive the dopants into the semiconductor substrate 12 (and N+ semiconductor layer 16). The epitaxial semiconductor material 14 can be an n-type semiconductor material epitaxially grown on the N+-type semiconductor layer 16. In a more specific embodiment, the semiconductor material 14 can be an epitaxially grown Si material employing an in-situ N-type doping process known in the art, such that the present invention can be fully understood without further explanation. The semiconductor material 14 can be any suitable semiconductor material, such as Si; although other examples are also contemplated herein. Please refer back to FIGS. 1A and 1B. The N-type wells 18, 18a and the P-type well 20 can be formed in the semiconductor material 14. In an embodiment, the N-type well 18 is an annular structure surrounding the P-type well 20. In another embodiment, the N-type well 18a separates and isolates adjacent P-type wells 20. Additionally, as shown in FIGS. 1A and 1B, for example, the N-type wells 18, 18a can be single wells that form a ring around each of the individual P-type wells 20, thereby electrically isolating each of the P-type wells 20. The distance “X” between the P-type wells 20 can be adjusted according to desired design characteristics (e.g., higher or lower breakdown voltage (BDV)). In an embodiment, the N-type wells 18, 18a are electrically floating N-type regions; while the P-type well 20 is electrically connected to two terminals 22a, 22b of the component, such as terminal 1 and terminal 2. The N wells 18, 18a do not have any terminal connections. Each of the N-type wells 18, 18a includes an N+ diffusion region 24, and each of the P-type wells 20 includes a plurality of N+ diffusion regions 24 and a plurality of P+ diffusion regions 26. As understood by those skilled in the art, the N-type wells 18, 18a, the plurality of P-type wells 20, the plurality of N+ diffusion regions 24, and the plurality of P+ diffusion regions 26 can be formed by an ion implantation process as described herein. In an embodiment, as known in the art, the plurality of N+ diffusion regions 24 and the plurality of P+ diffusion regions 26 within the N-type wells 18, 18a and the P-type wells 20 can be formed with a higher dopant concentration (compared to the wells 18, 18a, 20), such that the present invention can be fully understood without further explanation. The N+ diffusion region 24 and the P+ diffusion region 26 can be isolated by a shallow trench isolation structure 28. For example, in an embodiment, the shallow trench isolation structure 28 can be disposed in the N-type well 18 and the P-type well 20 to isolate the N+ diffusion region 24 and the P+ diffusion region 26. The shallow trench isolation structure 28 can be formed using conventional lithography, etching, and deposition processes. For example, a resist formed over the semiconductor material 14 is exposed to energy (light) and developed to form a pattern (opening). An etching process with a selective chemistry (e.g., reactive ion etching (RIE)) is used to transfer the pattern from the patterned photoresist to the semiconductor material 14 to form one or more trenches (e.g., the N-type well 18 and the P-type well 20) in the semiconductor material 14 through the opening of the resist. After removing the resist through a conventional oxygen ashing process or other known strippers, an insulating material (e.g., oxide) can be deposited through any conventional deposition process, such as a chemical vapor deposition (CVD) process. Any residual material on the surface of the semiconductor material 14 can be removed through a conventional chemical mechanical polishing (CMP) process. Isolation structures 30, 30a can be disposed between the N-type wells 18, 18a and the P-type well 20. In a more specific embodiment, the isolation structure 30a can be respectively disposed between the N+ diffusion region 24 and the P+ diffusion region 26 in the N-type well 18 and the P-type well 20. In addition, the isolation structure 30 can be disposed between the N-type well 18a and the P-type well 20, more specifically, extending between the plurality of N+ diffusion regions 24 of the P-type well and completely covering the N-type well 18a. Thus, the P-type well 20 is surrounded and isolated by the isolation structures 30, 30a. For example, the isolation structures 30, 30a form a ring around the P-type well 20. Those skilled in the art should understand that the isolation structures 30, 30a can be a single annular structure surrounding the individual P-type well 20. In an embodiment, the isolation structures 30, 30a can be LOCOS (local oxidation of silicon) or a shallow trench isolation structure 30b as shown in FIG. 2. In an embodiment, the LOCOS 30, 30a can be a raised oxide region surrounding the diffusion regions 24, 26 (e.g., terminals 22a and 22b) within the P-type well 20. As those skilled in the art will appreciate, the LOCOS process utilizes different silicon oxidation rates and a local mask of silicon nitride. The silicon nitride masks the regions where oxidation should not occur, such that the oxide grows only on the semiconductor material 16. A high resistivity film 32 (e.g., a field plate) can be formed on the isolation structures 30, 30a. In an embodiment, the field plate 32 can be a polysilicon material deposited and patterned on the isolation structures 30, 30a. Thus, the P-type well 20 (e.g., terminals 22a, 22b) can be surrounded by the field plate 32. In this configuration, compared to conventional devices, the field plate 32 provides a high breakdown voltage within a smaller footprint. For example, in an embodiment, the polysilicon field plate 32 will have a higher potential than other structures and will thus reduce the surface electric field. Thus, the device will maintain a higher voltage before breakdown. In an embodiment, the interconnect structure (contact) 34 and the wiring structure 36 electrically connect the field plate 32 (e.g., polysilicon material) on the isolation structure 30a to the N-type well 18, and the N-type well 18 can be biased such that the N-type well 18 serves as a contact point (e.g., is biased) for the common n-type region (e.g., n-type semiconductor material 14). Since no terminal is electrically connected to the N-type wells 18, 18a, this n-type region will also be electrically floating. In addition, the interconnect structure (contact) 34 and the wiring structure 36 are electrically connected to the field plate 32 on the isolation structure 30. Similarly, the interconnect structures 34a and the wiring structures 36a are each formed to the P-type well 20, e.g., the terminals 22a and 22b of the terminals 22a and 22b. In an embodiment, a negative voltage or a positive voltage can be provided to one of the terminals 22a, 22b to provide a bidirectional SCR structure. In an embodiment, the interconnect structures 34, 34a can be formed as silicide contacts on the N+ diffusion region 24 and the P+ diffusion region 26 within the P-type well 20, and on the field plate 32 and the N+ diffusion region 24 within the N-type well 18. Those skilled in the art will appreciate that the silicide process begins by depositing a thin transition metal layer (e.g., nickel, cobalt, or titanium) over a fully formed and patterned semiconductor material (e.g., a doped or ion implanted region). After depositing the material, the structure is heated such that the transition metal reacts with the exposed silicon (or other semiconductor material as described herein) in the active region to form a low resistance transition metal silicide. After the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts in the active regions of the device. The interconnect structures 34, 34a and the wiring structures 36, 36a can be formed using conventional deposition, lithography and etching processes. For example, an interlayer dielectric material 38 can be formed over the semiconductor substrate 12, such as over the N+ diffusion regions 24, P+ diffusion regions 26, shallow trench isolation structures 28, LOCOS 30, 30a and field plates 32. The interlayer dielectric material 38 can comprise a combination of nitride- and / or oxide-based materials, e.g., SiN and SiO deposited using conventional deposition processes such as chemical vapor deposition (CVD). 2 。 Through holes or trenches can be formed in the interlayer dielectric material 38 to expose the N+ diffusion regions 24, P+ diffusion regions 26 and the high resistivity film 32. The through holes or trenches can be formed using conventional lithography and etching processes as described herein, and thus the present invention can be fully understood without further explanation. After silicide formation, contacts 34, 34a can be formed in the through holes or trenches of the interlayer dielectric material 38, connecting to the N+ diffusion regions 24, P+ diffusion regions 26 and the high resistivity film 32. In more specific embodiments, the contacts 34, 34a land on the silicide contacts of the N+ diffusion regions 24, P+ diffusion regions 26 and the high resistivity film 32. The contacts 34, 34a can be tungsten, e.g., lined with TaN or TiN. The contacts 34, 34a can be deposited using conventional deposition processes (such as CVD), followed by a CMP process to remove any excess material on the surface of the interlayer dielectric material 32. The wiring structures 36, 36a can be formed in a similar process. FIG. 2 shows a bidirectional SCR according to additional aspects of the present invention, among other features. In the structure 10a of FIG. 2, a shallow trench isolation structure 30b is used instead of the LOCOS shown in FIGS. 1A and 1B. In this structure, a field plate 32 can be formed on the shallow trench isolation structure 30b. The shallow trench isolation structure 30b and the field plate 32 will effectively form a ring surrounding the P-type well 20. The remaining features of the structure 10a of FIG. 2 are similar to those of the structure 10 of FIG. 1, and thus this embodiment can be fully understood without further explanation. FIG. 3 shows another bidirectional SCR according to aspects of the present invention. In the structure 10b of FIG. 3, the P-type well 20 can be a high voltage P-type well, with an additional P-type well 20a within the P-type well 20. In an embodiment, the P-type well 20a will have a lower doping concentration than the P-type well 20. Additionally, the P-type well 20a can be located below and in electrical and physical contact with the N+ diffusion region 24 within the P-type well 20. The remaining features of the structure 10b of FIG. 3 are similar to those of the structure 10 of FIG. 1, and thus the present invention can be fully understood without further explanation. FIG. 4 shows another bidirectional SCR according to aspects of the present invention. In the structure 10c of FIG. 4, two isolation structures 30c are disposed above and between the N-type well 18a and the adjacent P-type well 20a. The two isolation structures 30 may be LOCOS (or shallow trench isolation structures), which are separated and isolated from each other through the N+ diffusion regions 24a in the N-type well 18a. The remaining features of the structure 10c of FIG. 2 are similar to those of the structure 10b of FIG. 3, and thus the present invention can be fully understood without further explanation. FIG. 5 shows a process flow representative of the current 100 for manufacturing the devices of FIGS. 1A, 1B, and 2-4. In step 105, an N+ semiconductor layer 16 may be formed in the semiconductor substrate 12. As shown with reference to FIGS. 1A and 1B, in an embodiment, the N+ semiconductor layer 16 may be formed using an ion implantation process. In step 110, a semiconductor material 14 is epitaxially grown on the semiconductor substrate 12, for example, above the N+ semiconductor layer 16. Thus, the N+ semiconductor layer 16 is a buried N-type layer. In an embodiment, the epitaxial growth of the semiconductor material 14 may include in-situ doping with an N-type dopant (such as arsenic). In step 115, the diffusion regions 24, 26 and the plurality of wells, such as wells 18, 18a, 20, 20a, may be formed using separate ion implantation processes with different masks as described herein and known in the art, and thus the present invention can be fully understood without further explanation. In these processes, individual patterned implantation masks may be used to define the selected regions to be exposed for implantation. As is known in the art, the implantation mask used to select the exposed region to form a single feature is stripped after the implantation mask and before the implantation mask used to form another feature. In step 120, an isolation structure 28 is formed in the semiconductor material 16. In an embodiment, the isolation structure 28 may be a shallow trench isolation structure formed through conventional lithography, etching and deposition methods as described herein. The isolation structures 30, 30a may also be formed through the LOCOS process as already described. In step 125, a high resistivity film 32 (e.g., polysilicon field plate) may be formed on the insulating structures 30, 30a. In an embodiment, the field plate 32 may be formed through a conventional deposition process (such as CVD), followed by a conventional patterning process (such as lithography and etching processes) as known in the art. In step 130, silicide contacts may be formed on the field plate 32 and the diffusion regions 24, 26. The silicide contacts may be a silicide process as described with respect to FIGS. 1A and 1B. In an embodiment, an interlayer dielectric material (e.g., interlayer dielectric material 38) may first be deposited through a conventional deposition process (e.g., CVD), followed by a conventional patterning process (e.g., lithography and etching processes) as known in the art. The interlayer dielectric material 38 may be a nitride or oxide material layer. The trenches will expose the field plate 32 and the diffusion regions 24, 26, and then a silicide process is performed on them. In step 135, conventional lithography, etching, and deposition processes may be used to form the contacts 34, 34a and the wiring structures 36, 36a. For example, the contact 34 may be fabricated by forming a via hole in the interlayer dielectric material and then depositing a metal material (e.g., tungsten, aluminum, copper, etc.). Then a chemical mechanical polishing (CMP) process is performed. The wiring structures 36, 36a can be formed in a manner similar to a CMOS wiring layer, e.g., conventional deposition, lithography, and etching processes known in the art, so that the present invention can be fully understood without further explanation. Silicon controlled rectifiers can be used in system-on-chip (SoC) technology. Those skilled in the art should understand that an SoC is an integrated circuit (also referred to as a "chip") that integrates all components of an electronic system on a single chip or substrate. Since the components are integrated on a single substrate, the SoC consumes much less power and occupies much less area compared to a multi-chip design with equivalent functionality. Because of this, SoCs are becoming the dominant force in the mobile computing (e.g., smartphones) and edge computing markets. SoCs are also commonly used in embedded systems and the Internet of Things. The above method is for the manufacture of integrated circuit chips. The obtained integrated circuit chips may be distributed by the manufacturer in the form of raw wafers as bare dies (i.e., as a single wafer with multiple unpackaged chips), or in a packaged form. In the latter case, the chip is mounted in a single-chip package (e.g., a plastic carrier, whose leads are fixed to a motherboard or other higher-level carrier), or a multi-chip package (e.g., a ceramic carrier with one or two surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit components, and / or other signal processing devices as part of either (a) an intermediate product, e.g., a motherboard, or (b) a finished product. The finished product can be any product including the integrated circuit chip, ranging from toys and other low-cost applications to advanced computer products with a display, keyboard, or other input devices and a central processing unit. For purposes of illustration, descriptions of various embodiments of the present invention have been presented herein, but are not intended to be exhaustive or limited to the embodiments of the present invention. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are chosen in order to best explain the principles of the embodiments, practical applications, or improvements made to the technology found in the market, or to enable other ordinary skilled in the art to understand the embodiments disclosed herein. 10: Triac 10a: Structure 10b: Structure 10c: Structure 12: Semiconductor substrate 14: Epitaxial semiconductor material 16: Semiconductor layer 18: N-type well 18a: N-type well 20: P-type well 20a: P-type well 22a: Terminal 22b: Terminal 24: N+ diffusion region 26: P+ diffusion region 28: Shallow trench isolation structure 30: Isolation structure 30a: Isolation structure 30b: Isolation structure 30c: Isolation structure 32: High-resistance thin film / polysilicon field plate 34: Contact 34a: Contact 36: Wiring structure 36a: Wiring structure 38: Interlayer dielectric material 100: Process A-A representing the manufacturing process: Line X-X: Line The present invention will be described hereinafter by way of non-limiting examples with reference to the several figures indicated, through exemplary embodiments of the present invention. FIG. 1A shows a top view of a triac (SCR) with a field plate, other features, and individual processes according to aspects of the present invention. FIG. 1B shows a cross-sectional view of the bi-directional SCR of FIG. 1A along line A-A. FIG. 2 shows a bi-directional SCR according to additional aspects of the present invention, among other features. FIG. 3 shows a bi-directional SCR according to further aspects of the present invention, among other features. FIG. 4 shows a bi-directional SCR according to still further additional aspects of the present invention, among other features. FIG. 5 shows a process flow representing the process for manufacturing the bi-directional SCRs of FIGS. 1A, 1B, and 2-4. 10: Triac 22a: Terminal 22b: Terminal 24: N+ diffusion region 26: P+ diffusion region 28: Shallow trench isolation structure 30: Isolation structure 30a: Isolation structure 32: High-resistance thin film / polysilicon field plate 34: Contact 34a: Contact 36: Wiring structure 36a: Wiring structure A-A: Line

Claims

1. A semiconductor structure comprising: a plurality of wells of a first type in a semiconductor substrate; a well of a second type in the semiconductor substrate, the second type well surrounding each of the plurality of wells of the first type such that the second type well is located between adjacent wells in the plurality of wells of the first type; an isolation structure surrounding the plurality of wells of the first type, wherein the isolation structure completely covers the second type well between adjacent wells in the plurality of wells of the first type and extends over adjacent wells in the plurality of wells of the first type, and the second type well is isolated from the plurality of wells of the first type; A plurality of field plates are located on the isolation structure, the plurality of field plates surrounding the plurality of wells of the first type; and an additional well of the first type is located within the plurality of wells of the first type, wherein the additional well of the first type has a lower doping concentration than the plurality of wells of the first type, and a top surface of the additional well of the first type is above a top surface of the plurality of wells of the first type.

2. The structure as claimed in claim 1, wherein the plurality of wells of the first type comprises a plurality of P-type wells connected to individual plurality of terminals, and the well of the second type comprises an N-type well.

3. The structure as described in claim 2, wherein the N-type well is a ring structure surrounding the P-type well.

4. The structure as claimed in claim 2, wherein the isolation structure comprises a LOCOS and the plurality of field plates comprise polycrystalline silicon material on the LOCOS.

5. The structure as claimed in claim 4, wherein the polycrystalline silicon material comprises a ring structure surrounding each of the P-type wells.

6. The structure as claimed in claim 2, wherein the isolation structure comprises a plurality of shallow trench isolation structures, and the plurality of field plates comprise polycrystalline silicon material on the shallow trench isolation structures.

7. The structure as claimed in claim 2, wherein the P-type wells are a plurality of adjacent P-type wells connected to a single terminal, and each of the P-type wells is isolated from each other through the isolation structure.

8. The structure as described in claim 1, wherein the field plates are electrically coupled to the second type of well.

9. The structure as described in claim 8, wherein the second type of trap serves as a contact point of a floating n-type region.

10. The structure as claimed in claim 1, wherein the isolation structure comprises two isolation structures extending between the plurality of wells of the first type and the well of the second type.

11. The structure as described in claim 10 further includes a diffusion region located between the two isolation structures and within the trap of the second type.

12. The structure as described in claim 1, further wherein, compared with the plurality of wells of the first type, the additional well of the first type contains a dopant type.

13. A semiconductor structure comprising: a plurality of P-type wells located in a semiconductor substrate; an N-type well surrounding each of the plurality of P-type wells such that the N-type well is located between adjacent wells in the plurality of P-type wells; an isolation structure surrounding the plurality of P-type wells, wherein the isolation structure completely covers the N-type well between adjacent wells in the plurality of P-type wells and extends over adjacent wells in the plurality of P-type wells, and the plurality of P-type wells are isolated from the N-type wells; a plurality of field plates located on the isolation structure, the field plates forming a ring around the plurality of P-type wells; and a further P-type well located among the plurality of P-type wells, wherein the further P-type well has a lower doping concentration than the plurality of P-type wells, and a top surface of the further P-type well is above a top surface of the plurality of P-type wells.

14. The structure as described in claim 13, wherein the field plates comprise a polycrystalline silicon material and the isolation structure comprises LOCOS.

15. The structure as claimed in claim 13, wherein the field plates comprise a polycrystalline silicon material and the isolation structure comprises a plurality of shallow trench isolation structures.

16. The structure as claimed in claim 13, wherein the isolation structure comprises two isolation structures separated by a diffusion region in the N-type trap.

17. The structure as claimed in claim 13, wherein the plurality of P-type wells are connected to separate plurality of terminals, and the separate terminals are surrounded by both the isolation structure and the field plates.

18. The structure as claimed in claim 13, wherein the P-type wells comprise a plurality of high-voltage P-type wells and the additional P-type wells comprise the same dopant type within the P-type wells.

19. The structure as described in claim 13, wherein the N-type well is electrically coupled to the field plates and has no terminals.

20. A method of manufacturing a semiconductor structure, comprising: forming a plurality of wells of a first type in a semiconductor substrate; forming a well of a second type in the semiconductor substrate, the second type well surrounding each of the plurality of wells of the first type such that the second type well is located between adjacent wells in the plurality of wells of the first type; forming an isolation structure surrounding the plurality of wells of the first type, wherein the isolation structure completely covers the second type well between adjacent wells in the plurality of wells of the first type and extends over adjacent wells in the plurality of wells of the first type, and the second type well is isolated from the plurality of wells of the first type; A plurality of field plates are formed on the isolation structure, the plurality of field plates surrounding the plurality of wells of the first type; and an additional well of the first type is formed, located within the plurality of wells of the first type, wherein the additional well of the first type has a lower doping concentration than the plurality of wells of the first type, and a top surface of the additional well of the first type is above a top surface of the plurality of wells of the first type.

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