Memory chip and semiconductor package including the same

Abstract

This invention provides a memory chip and a semiconductor package including the same. The memory chip includes vertically stacked cell chips and core peripheral chips electrically connected to each other. Each cell chip includes cell regions, each of which contains a memory cell layer. The core peripheral chip includes a core group region and peripheral regions adjacent to each other in a first direction. The core group region includes core regions arranged in rows in a second direction intersecting the first direction. Each core region includes: a core group containing core circuitry; and a neural processing unit (NPU) block containing the NPU.

Description

Memory Chip and Semiconductor Package Comprising the Same [Cross - Reference to Related Applications] This patent application claims the priority of Korean Patent Application No. 10 - 2023 - 0089797, filed on July 11, 2023, with the Korean Intellectual Property Office, the entire content of which is incorporated herein by reference. Embodiments of the present disclosure relate to a memory chip and a semiconductor package comprising the same. The memory chip may include a plurality of circuit regions therein. For example, the memory chip may have a cell region that performs a memory function, and a core region and a peripheral region that form circuits for driving the cell region and inputting / outputting data. At the same time, more circuits should be formed on a limited chip area to improve the integration density of the memory chip. Therefore, various studies are being conducted on memory chips and semiconductor packages comprising the same that can reduce the external dimensions and improve the performance. Embodiments of the present disclosure may provide a memory chip and a semiconductor package comprising the same with improved integration density. Embodiments of the present disclosure may also provide a memory chip and a semiconductor package comprising the same with improved performance. According to an embodiment of the present disclosure, there is provided a memory chip, and the memory chip includes: a cell chip; and a core - peripheral chip, wherein the cell chip and the core - peripheral chip are vertically stacked and electrically connected to each other, wherein the cell chip includes a cell region, each of the cell regions includes a memory cell layer, wherein the core - peripheral chip includes at least one core group region and a peripheral region adjacent to each other in a first direction, wherein at least one core group region includes core regions arranged in rows in a second direction intersecting the first direction, and wherein each of the core regions includes: a core group including a core circuit; and a neural processing unit (NPU) block including an NPU. According to an embodiment of the present disclosure, there is provided a semiconductor package, and the semiconductor package includes: a cell chip; a core - peripheral chip; and through - silicon vias (TSVs) that electrically connect the cell chip and the core - peripheral chip to each other, wherein the cell chip and the core - peripheral chip are alternately stacked, wherein each of the cell chips includes a cell region for storing data, and wherein each of the core - peripheral chips includes a neural processing unit (NPU) block configured to perform data operations. According to an embodiment of the present disclosure, a semiconductor package is provided, and the semiconductor package includes: a plurality of memory chips stacked vertically; and through-silicon vias (TSVs) electrically connecting the plurality of memory chips, wherein each of the plurality of memory chips includes a cell chip and a core-peripheral chip stacked vertically, wherein the cell chip includes: cell regions, each of the cell regions including a memory cell layer, wherein the core-peripheral chip includes at least one core group region and a peripheral region adjacent to each other in a first direction, wherein the at least one core group region includes core regions arranged in rows in a second direction intersecting the first direction, and wherein each of the core regions includes: a core group including core circuits; and a neural processing unit (NPU) block including an NPU. According to an embodiment of the present disclosure, a semiconductor package is provided, and the semiconductor package includes: a package substrate; a main structure located on the package substrate; and a memory structure horizontally spaced apart from and electrically connected to the main structure on the package substrate, wherein the memory structure includes a plurality of memory chips stacked vertically, wherein each of the plurality of memory chips includes a cell chip and a core-peripheral chip stacked vertically and electrically connected to each other, wherein the cell chip includes cell regions, each cell region including a memory cell layer, wherein the core-peripheral chip includes at least one core group region and a peripheral region adjacent to each other in a first direction, wherein the at least one core group region includes core regions arranged in rows in a second direction intersecting the first direction, and wherein each of the core regions includes: a core group including core circuits; and a neural processing unit (NPU) block including an NPU. Embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings. It should be understood that when an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it can be directly on, directly connected to or directly coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element or layer is referred to as being "directly on", "directly connected to" or "directly coupled to" another element or layer, no intervening elements or layers are present. As used herein, the phrase "at least one of" before a list of elements modifies the entire list of elements and not individual elements of the list. For example, the phrase "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. FIG. 1 and FIG. 2 are perspective views showing memory chips according to some embodiments of the present disclosure. Referring to FIGS. 1 and 2, the memory chip 1000 may include core peripheral chips 10 and cell chips 20 stacked in the vertical direction VD. The core peripheral chips 10 and the cell chips 20 may overlap vertically with each other. In some embodiments, as shown in FIG. 1, the cell chips 20 may be stacked on the core peripheral chips 10. In certain embodiments, as shown in FIG. 2, the core peripheral chips 10 may be stacked on the cell chips 20. When viewed in a plan view, the core peripheral chip 10 may include a core region COR and a peripheral region PR. The core region COR and the peripheral region PR may be adjacent to each other in the horizontal direction. Each of the core regions COR may include a core group COB (refer to FIGS. 3 to 9) described below, and the core group COB may include core circuits such as sub-word line drivers, sense amplifiers, column decoders, row decoders, and read / write (R / W) circuits. The peripheral region PR may include peripheral circuits such as timing registers, address registers, data input registers, data output registers, and data input / output terminals. When viewed in a plan view, the cell chip 20 may include a cell region CR. The cell regions CR may be adjacent to each other in the horizontal direction. Each of the cell regions CR may overlap vertically with at least a part of each of the core regions COR. Each of the cell regions CR may include a memory cell layer 210 (refer to FIGS. 15A to 17B) described below, and the memory cell layer 210 may store data. Hereinafter, the planar configuration of the components in the core peripheral chip 10 and the cell chip 20 will be described in more detail. FIGS. 3 to 10 are plan views showing a core peripheral chip of a memory chip according to some embodiments of the present disclosure. Referring to FIGS. 3 to 10, the core peripheral chip 10 may have a first side surface 10a facing a first direction D1, a second side surface 10b opposite to the first side surface 10a, a third side surface 10c facing a second direction D2, and a fourth side surface 10d opposite to the third side surface 10c. The first direction D1 and the second direction D2 may be parallel to the bottom surface of the core peripheral chip 10 and may intersect each other. Each of the core regions COR may include a core group COB and a neural processing unit (NPU) block NB. The NPU block NB may include a neural processing unit (NPU) that performs data operations. For example, one core region COR may include one core group COB and one NPU block NB, and one core group COB and one NPU block NB may be adjacent to each other in the first direction D1 or the second direction D2. Since the core region COR includes the NPU block NB, the memory chip 1000 may serve as a processing in memory (PIM) capable of performing data operations. The peripheral region PR can be located on the central portion of the core-peripheral chip 10. The central portion of the core-peripheral chip 10 can be defined as the region of the core-peripheral chip 10 that is disposed at an equal distance from the first side surface 10a and the second side surface 10b of the core-peripheral chip 10, and is disposed at an equal distance from the third side surface 10c and the fourth side surface 10d of the core-peripheral chip 10. The peripheral region PR can be a region that extends longer in the second direction D2 on the central portion of the core-peripheral chip 10. The core region COR can include core regions COR arranged in a row in the second direction D2. The core regions COR arranged in a row can constitute the core group region COG. The core group region COG can be adjacent to the peripheral region PR in the first direction D1 or in the direction opposite to the first direction D1. Multiple core group regions COG can be provided. The multiple core group regions COG can be sequentially arranged in the first direction D1. In other words, core regions COR arranged in a row can be provided, and core regions COR arranged in another row can be disposed to be spaced apart from the core regions COR arranged in a row in the first direction D1. For example, the core group region COG can include a first group COG1 adjacent to the peripheral region PR in the first direction D1, and a second group COG2 adjacent to the peripheral region PR in the direction opposite to the first direction D1. The first group COG1 and the second group COG2 can be spaced apart from each other by the peripheral region PR inserted therebetween in the first direction D1. The first group COG1 can be located between the peripheral region PR and the first side surface 10a of the core-peripheral chip 10. The second group COG2 can be located between the peripheral region PR and the second side surface 10b of the core-peripheral chip 10. Referring to FIG. 3, the core group COB and the NPU block NB can be symmetrically disposed with respect to the peripheral region PR (i.e., a line perpendicular to the first direction D1). For example, the NPU block NB and the core group COB of the first group COG1 can be sequentially arranged from the peripheral region PR in the first direction D1. The NPU block NB and the core group COB of the second group COG2 can be sequentially arranged from the peripheral region PR in the direction opposite to the first direction D1. In other words, the core group COB and the NPU block NB of the first group COG1 and the core group COB and the NPU block NB of the second group COG2 can be symmetrically disposed with respect to the peripheral region PR. Referring to FIG. 4, the core group COB and the NPU block NB can be symmetrically arranged relative to the peripheral region PR (i.e., a line perpendicular to the first direction D1). For example, the NPU block NB and the core group COB of the first group COG1 can be sequentially arranged from the peripheral region PR in the first direction D1. The core group COB and the NPU block NB of the second group COG2 can be sequentially arranged from the peripheral region PR in the direction opposite to the first direction D1. In other words, the NPU block NB and the core group COB of the first group COG1 and the second group COG2 can be sequentially arranged in the first direction D1. For example, the arrangement order of the NPU block NB and the core group COB in the first group COG1 can be the same as the arrangement order of the NPU block NB and the core group COB in the second group COG2. Referring to FIGS. 5 and 6, the core group COB and the NPU block NB in each of the core regions COR can be adjacent to each other in the second direction D2. In some embodiments, as shown in FIG. 5, a pair of core regions COR can be adjacent to each other in the second direction D2, and the core group COB and the NPU block NB in each of the pair of core regions COR can be sequentially arranged in the second direction D2. In other words, the core group COB and the NPU block NB in the pair of core regions COR can be asymmetrically arranged relative to a line perpendicular to the second direction D2. For example, the pair of core regions COR can have the same arrangement order of the core group COB and the NPU block NB. In certain embodiments, as shown in FIG. 6, the core group COB and the NPU block NB of one of the pair of core regions COR can be sequentially arranged in the second direction D2, and the core group COB and the NPU block NB of the other of the pair of core regions COR can be sequentially arranged in the direction opposite to the second direction D2. In other words, the core group COB and the NPU block NB in the pair of core regions COR can be symmetrically arranged relative to a line perpendicular to the second direction D2. For example, the arrangement order of the core group COB and the NPU block NB in one of the core regions COR in the pair of core regions COR can be opposite to the arrangement order of the core group COB and the NPU block NB in the other core region COR in the pair of core regions COR. Referring to FIGS. 7 to 9, a plurality of core group areas COG can be located between the peripheral area PR and the first side surface 10a of the core peripheral chip 10, and another plurality of core group areas COG can be located between the peripheral area PR and the second side surface 10b of the core peripheral chip 10. For example, as shown in FIGS. 7 to 9, the core group area COG can include a first group COG1, a second group COG2, a third group COG3, and a fourth group COG4. The first group COG1 can be located between the peripheral area PR and the first side surface 10a of the core peripheral chip 10. The second group COG2 can be located between the peripheral area PR and the second side surface 10b of the core peripheral chip 10. The third group COG3 can be located between the first group COG1 and the first side surface 10a of the core peripheral chip 10 and can be adjacent to the first group COG1 in the first direction D1. The fourth group COG4 can be located between the second group COG2 and the second side surface 10b of the core peripheral chip 10 and can be adjacent to the second group COG2 in the first direction D1. However, the embodiments of the present disclosure are not limited thereto, and in some embodiments, the core group area COG can further include additional groups such as a fifth group and a sixth group. Referring to FIG. 7, the core group COB and the NPU block NB can be symmetrically arranged with respect to the peripheral area PR (i.e., the line perpendicular to the first direction D1 and passing through the peripheral area PR). The core group COB and the NPU block NB of the first group COG1 can be sequentially arranged in the first direction D1. The core group COB and the NPU block NB of the second group COG2 can be sequentially arranged in the direction opposite to the first direction D1. Therefore, the second group COG2 and the first group COG1 can be symmetric with respect to the peripheral area PR. The NPU block NB and the core group COB of the third group COG3 can be sequentially arranged in the first direction D1. Therefore, the first group COG1 and the third group COG3 can be symmetrically arranged with respect to the line perpendicular to the first direction D1 and passing through the center between the first group COG1 and the third group COG3. The NPU block NB and the core group COB of the fourth group COG4 can be sequentially arranged in the direction opposite to the first direction D1. Therefore, the second group COG2 and the fourth group COG4 can be symmetrically arranged with respect to the line perpendicular to the first direction D1 and passing through the center between the second group COG2 and the fourth group COG4. In addition, the fourth group COG4 and the third group COG3 can be symmetric with respect to the peripheral area PR. Referring to FIG. 8, similar to FIG. 7, the core group COB and the NPU block NB can be symmetrically arranged with respect to the peripheral region PR (i.e., a line perpendicular to the first direction D1 and passing through the peripheral region PR). However, different from FIG. 7, the NPU blocks NB and the core group COB of the first group COG1 can be sequentially arranged in the first direction D1, and the NPU blocks NB and the core group COB of the second group COG2 can be sequentially arranged in a direction opposite to the first direction D1. Therefore, the first group COG1 and the third group COG3 can be arranged asymmetrically with respect to a line perpendicular to the first direction D1 and passing through the center between the first group COG1 and the third group COG3, and the second group COG2 and the fourth group COG4 can be arranged asymmetrically with respect to a line perpendicular to the first direction D1 and passing through the center between the second group COG2 and the fourth group COG4. For example, the first group COG1 and the third group COG3 can have the same arrangement order of the NPU blocks NB and the core group COB. For example, the second group COG2 and the fourth group COG4 can have the same arrangement order of the NPU blocks NB and the core group COB. Referring to FIG. 9, the core group COB and the NPU block NB can be arranged asymmetrically with respect to the peripheral region PR (i.e., a line perpendicular to the first direction D1 and passing through the peripheral region PR). For example, the NPU blocks NB and the core group COB of each of the first group COG1, the second group COG2, the third group COG3, and the fourth group COG4 can be sequentially arranged in the first direction D1. In other words, the first group COG1, the second group COG2, the third group COG3, and the fourth group COG4 can have the same arrangement order of the NPU blocks NB and the core group COB. The first group COG1 and the third group COG3 can be arranged asymmetrically with respect to a line perpendicular to the first direction D1 and passing through the center between the first group COG1 and the third group COG3, and the second group COG2 and the fourth group COG4 can be arranged asymmetrically with respect to a line perpendicular to the first direction D1 and passing through the center between the second group COG2 and the fourth group COG4. Referring to FIG. 10, the core peripheral chip 10 can further include through-silicon vias (TSVs) 30 located in its central portion. The TSVs 30 can be located in the peripheral region PR. The TSVs 30 can be located between the first group COG1 and the second group COG2. The TSVs 30 can be distributed in a region that extends longer in the second direction D2 on the central portion of the core peripheral chip 10. Each of the TSVs 30 can extend vertically in the core peripheral chip 10, and for example, each of the TSVs 30 can penetrate at least a part of the core peripheral chip 10. The TSVs 30 of the core peripheral chip 10 can be electrically connected to the TSVs 30 of the cell chip 20 (refer to FIG. 14). In other words, the core peripheral chip 10 and the cell chip 20 of the memory chip 1000 can be electrically connected to each other. FIGS. 11 to 14 are plan views of a cell wafer of a memory chip showing some embodiments according to the present disclosure. Referring to FIGS. 11 to 14, the cell wafer 20 may have a first side surface 20a facing a first direction D1, a second side surface 20b opposite to the first side surface 20a, a third side surface 20c facing a second direction D2, and a fourth side surface 20d opposite to the third side surface 20c. Each of the cell regions CR may include a cell block CB. The cell block CB may include a memory cell layer 210 (refer to FIGS. 15A to 17B) to be described in detail below, and the memory cell layer 210 may store data. For example, each of the cell regions CR may vertically overlap at least a part of each of the NPU blocks NB in the core peripheral wafer 10. Therefore, the distance between the cell region CR and the NPU block NB may be reduced compared to the case where the cell regions and the NPU blocks do not overlap with each other. Therefore, the data processing speed of the memory chip 1000 may be improved. In addition, the memory chip 1000 may be driven by low power, and problems such as noise and / or heat generation may be reduced or minimized. The cell regions CR may be arranged in the first direction D1 and the second direction D2. For example, the cell regions CR may include cell regions CR arranged in rows in the second direction D2. The cell regions CR arranged in rows may constitute a cell group region CG. A plurality of cell group regions CG may be provided, and the cell group regions CG may be adjacent to each other in the first direction D1. For example, the cell group region CG may include a first group CG1 adjacent to the central portion of the cell wafer 20 in the first direction D1, and a second group CG2 adjacent to the central portion of the cell wafer 20 in a direction opposite to the first direction D1. The central portion of the cell wafer 20 may be defined as a region of the cell wafer 20 that is disposed at an equal distance from the first side surface 20a and the second side surface 20b of the cell wafer 20, and is disposed at an equal distance from the third side surface 20c and the fourth side surface 20d of the cell wafer 20. The first group CG1 and the second group CG2 may be spaced apart from each other in the first direction D1 by the cell wafer 20 interposed therebetween. The first group CG1 may be located between the first side surface 20a of the cell wafer 20 and the central portion. The second group CG2 may be located between the second side surface 20b of the cell wafer 20 and the central portion. In some embodiments, the cell group region CG may further include additional groups such as a third group and a fourth group. The third group may be located between the first group CG1 and the first side surface 20a of the cell wafer 20, and the fourth group may be located between the second group CG2 and the second side surface 20b of the cell wafer 20. Referring to FIGS. 12 and 13, each of the cell regions CR may further include an NPU buffer NBF. The NPU buffer NBF may include an NPU buffer memory for driving the NPU. The NPU buffer memory may include at least one of a new memory (e.g., a phase-change random access memory (PRAM) device, a spin transfer torque magnetic RAM (STT-MRAM) device, and a ferroelectric RAM (FeRAM) device) and a static RAM (SRAM) device. For example, a cell region CR may include a cell block CB and an NPU buffer NBF. The cell block CB and the NPU buffer NBF may be adjacent to each other in a horizontal direction (e.g., the first direction D1 or the second direction D2). Since the NPU buffer NBF is positioned on the cell region CR, the area of the NPU block NB in the core-peripheral chip 10 can be reduced. Therefore, the integration density in the core-peripheral chip 10 and the cell chip 20 can be appropriately adjusted by the NPU buffer NBF, thereby improving or maximizing the integration density of the memory chip 1000. Referring to FIG. 12, the cell block CB and the NPU buffer NBF may be asymmetrically arranged with respect to the central portion of the cell chip 20 (i.e., the line perpendicular to the first direction D1 and passing through the central portion of the cell chip 20). For example, all the cell regions CR may have the same arrangement order of the cell block CB and the NPU buffer NBF. Referring to FIG. 13, the cell block CB and the NPU buffer NBF may be symmetrically arranged with respect to the central portion of the cell chip 20 (i.e., the line perpendicular to the first direction D1 and passing through the central portion of the cell chip 20). For example, the NPU buffer NBF and the cell block CB of the first group CG1 may be sequentially arranged from the central portion of the cell chip 20 in the first direction D1, and the NPU buffer NBF and the cell block CB of the second group CG2 may be sequentially arranged from the central portion of the cell chip 20 in the direction opposite to the first direction D1. In other words, the NPU buffer NBF and the cell block CB of the first group CG1 and the NPU buffer NBF and the cell block CB of the second group CG2 may be symmetrically arranged with respect to the central portion of the cell chip 20. Referring to FIG. 14, the cell wafer 20 may further include TSVs 30 positioned in its central portion. The TSVs 30 may be positioned between the first group CG1 and the second group CG2. The TSVs 30 may be distributed in a region extending longer in the second direction D2 on the central portion of the cell wafer 20. Each of the TSVs 30 may extend vertically in the cell wafer 20, and for example, each of the TSVs 30 may penetrate at least a portion of the cell wafer 20. The TSVs 30 of the cell wafer 20 may be electrically connected to the TSVs 30 of the core-peripheral wafer 10. The TSVs 30 of the core-peripheral wafer 10 and the cell wafer 20 may be electrically connected to an external device and may be used to transmit electrical signals from the external device to the wafer. FIGS. 15A to 17B are cross-sectional views showing a memory wafer according to some embodiments of the present disclosure. Referring to FIGS. 15A to 17B, the core-peripheral wafer 10 may include a driving layer 11 and a core-peripheral interconnect layer 12. The core-peripheral interconnect layer 12 may be disposed on the driving layer 11. The driving layer 11 may include a core-peripheral semiconductor layer 100 and core-peripheral transistors 110 on the core-peripheral semiconductor layer 100. The core-peripheral semiconductor layer 100 may include a semiconductor material. For some examples, the core-peripheral semiconductor layer 100 may be a semiconductor substrate including a semiconductor material, such as a single-crystal silicon substrate, a silicon-germanium substrate, or an SOI substrate. For certain examples, the core-peripheral semiconductor layer 100 may be a semiconductor epitaxial layer including a semiconductor material. The core-peripheral transistors 110 may be transistors provided in the core circuit, the peripheral circuit, and the NPU. The core-peripheral transistors 110 are shown as planar transistors, but in certain embodiments, transistors having other shapes may be applied to the core-peripheral transistors 110. The core-peripheral interconnect layer 12 may include core-peripheral circuit lines 12a and core-peripheral contact plugs 12b that electrically connect the core-peripheral transistors 110 to the core-peripheral circuit lines 12a. The cell wafer 20 may include a data storage layer 21 and a cell interconnect layer 22. The data storage layer 21 may include a cell semiconductor layer 200 and a memory cell layer 210. The cell semiconductor layer 200 may include a first surface 201 and a second surface 202 that face each other in the vertical direction VD. The first surface 201 of the cell semiconductor layer 200 may be the front surface of the cell semiconductor layer 200, and the memory cell layer 210 may be formed on the front surface of the cell semiconductor layer 200. The second surface 202 of the cell semiconductor layer 200 may be the back surface of the cell semiconductor layer 200. The cell semiconductor layer 200 may include a semiconductor material. For some examples, the cell semiconductor layer 200 may be a semiconductor substrate including a semiconductor material, such as a single-crystalline silicon substrate, a silicon germanium substrate, or a SOI substrate. For certain examples, the cell semiconductor layer 200 may be a semiconductor epitaxial layer including a semiconductor material. The memory cell layer 210 may include at least one of various types of semiconductor memories. In some embodiments, the memory cell layer 210 may include two-dimensional (2D) memory, such as DRAM having a buried channel array transistor (BCAT) structure or a vertical channel transistor (VCT) structure. In certain embodiments, the memory cell layer 210 may include three-dimensional (3D) memory, such as vertically stacked DRAM (VS DRAM), 3D ferroelectric FET (3D FeFET), or 3D monolithic memory. In some embodiments, as illustrated in FIGS. 15A, 16A, and 17A, the memory cell layer 210 may include DRAM having a BCAT structure, the BCAT structure including an active region ACT, a bit line node contact DC, a bit line BL, a storage node contact BC, and a capacitor CAP. Here, a word line may be disposed below a top surface of the active region ACT and may intersect the active region ACT. In certain embodiments, as illustrated in FIGS. 15B, 16B, and 17B, the memory cell layer 210 may include DRAM having a VCT structure, the VCT structure including a bit line BL, a channel pattern CH, a word line WL, and a capacitor CAP. Here, the channel pattern CH may include at least one of single-crystalline silicon, polysilicon, an oxide semiconductor material (e.g., InxGayZnzO, InxGaySizO, InxSnyZnzO, InxZnyO, ZnxO, ZnxSnyO, ZnxOyN, ZrxZnySnzO, SnxO, HfxInyZnzO, GaxZnySnzO, AlxZnySnzO, YbxGayZnzO, InxGayO, etc.) and a two-dimensional material (e.g., graphene, a transition metal dichalcogenide (TMD) including a transition metal element (e.g., Mo, W, V, Nb, Ta, Ti, etc.) and a chalcogen element (e.g., S, Se, Te, etc.)). The cell interconnect layer 22 may include cell circuit lines 22a and cell contact plugs 22b that electrically connect the memory cell layer 210 to the cell circuit lines 22a. Referring to FIGS. 15A and 15B, the data storage layer 21 may be disposed on the core peripheral chip 10, and the cell interconnect layer 22 may be disposed on the data storage layer 21. The data storage layer 21 may be disposed between the core peripheral chip 10 and the cell interconnect layer 22. The memory cell layer 210 and the cell interconnect layer 22 may be sequentially disposed on the first surface 201 of the cell semiconductor layer 200. The core peripheral chip 10 may be disposed on the second surface 202 of the cell semiconductor layer 200. In other words, the cell semiconductor layer 200, the memory cell layer 210, and the cell interconnect layer 22 may be sequentially stacked on the core peripheral chip 10. The chip insulating layer 60 may be disposed between the second surface 202 of the cell semiconductor layer 200 and the core peripheral chip 10. The through-conductive pattern 50 may electrically connect the core peripheral chip 10 to the cell chip 20. The through-conductive pattern 50 may penetrate the cell chip 20 and the chip insulating layer 60 in the vertical direction VD and may extend to the core peripheral chip 10. For example, the through-conductive pattern 50 may be electrically connected to the cell interconnect layer 22 via the data storage layer 21 and may be electrically connected to the driving layer 11 via the core peripheral interconnect layer 12. In some embodiments, when manufacturing the memory chip 1000, the components of the cell chip 20 may be sequentially formed on the core peripheral chip 10. In other words, the cell semiconductor layer 200, the memory cell layer 210, and the cell interconnect layer 22 may be sequentially formed on the core peripheral chip 10. In this case, for example, the cell semiconductor layer 200 may be a semiconductor epitaxial layer. In certain embodiments, when manufacturing the memory chip 1000, the data storage layer 21 may be formed using a separate manufacturing process and then may be bonded to the core peripheral chip 10. In this case, for example, the cell semiconductor layer 200 may be a semiconductor substrate. However, the embodiments of the present disclosure are not limited to the description of the method for manufacturing the memory chip 1000. Referring to FIGS. 16A and 16B, similar to FIGS. 15A and 15B, the data storage layer 21 may be disposed on the core peripheral chip 10, and the cell interconnect layer 22 may be disposed on the data storage layer 21. The data storage layer 21 may be disposed between the core peripheral chip 10 and the cell interconnect layer 22. However, different from FIGS. 15A and 15B, the memory cell layer 210 can be disposed between the first surface 201 of the cell semiconductor layer 200 and the core peripheral chip 10, and the cell interconnect layer 22 can be disposed on the second surface 202 of the cell semiconductor layer 200. In other words, the memory cell layer 210, the cell semiconductor layer 200, and the cell interconnect layer 22 can be stacked on the core peripheral chip 10 in sequence. The chip insulating layer 60 can be positioned on the first surface 201 of the cell semiconductor layer 200 and can be disposed between the memory cell layer 210 and the core peripheral chip 10. The through-conductive pattern 50 can electrically connect the core peripheral chip 10 to the cell chip 20. In some embodiments, when manufacturing the memory chip 1000, the data storage layer 21 can be formed using a manufacturing process different from the process for manufacturing the core peripheral chip 10, and then can be bonded to the core peripheral chip 10. In this case, for example, the cell semiconductor layer 200 can be a semiconductor substrate. For example, the data storage layer 21 can be flipped and bonded to the core peripheral chip 10. However, the embodiments of the present disclosure are not limited to the description of the method for manufacturing the memory chip 1000. Referring to FIGS. 17A and 17B, different from FIGS. 15A to 16B, the cell interconnect layer 22 can be disposed on the core peripheral chip 10, and the data storage layer 21 can be disposed on the cell interconnect layer 22. The cell interconnect layer 22 can be disposed between the data storage layer 21 and the core peripheral chip 10. The memory cell layer 210 can be disposed between the first surface 201 of the cell semiconductor layer 200 and the core peripheral chip 10, and the cell interconnect layer 22 can be disposed between the memory cell layer 210 and the core peripheral chip 10. The cell interconnect layer 22, the memory cell layer 210, and the cell semiconductor layer 200 can be stacked on the core peripheral chip 10 in sequence. The core peripheral interconnect layer 12 can include core peripheral bonding pads 15. The cell interconnect layer 22 can include cell bonding pads 25. The core peripheral bonding pads 15 and the cell bonding pads 25 can be coupled to each other, and thus the core peripheral chip 10 and the cell chip 20 can be electrically connected to each other. For example, each of the core peripheral bonding pads 15 and the cell bonding pads 25 can include copper (Cu), but the embodiments of the present disclosure are not limited thereto. In some embodiments, when manufacturing the memory chip 1000, the cell chip 20 can be formed using a manufacturing process different from the process for manufacturing the core peripheral chip 10, and then can be bonded to the core peripheral chip 10. When manufacturing the core peripheral chip 10, the surface of the core peripheral bonding pad 15 can be exposed to the outside. When manufacturing the cell chip 20, the surface of the cell bonding pad 25 can be exposed to the outside. Through the bonding process, the exposed surface of the core peripheral bonding pad 15 can contact the exposed surface of the cell bonding pad 25, and the core peripheral bonding pad 15 and the cell bonding pad 25 can be coupled to each other. For example, the cell chip 20 can be flipped and bonded to the core peripheral chip 10. However, the embodiments of the present disclosure are not limited to the description of the method for manufacturing the memory chip 1000. FIG. 18 is a cross-sectional view showing multiple memory chips according to some embodiments of the present disclosure. Referring to FIG. 18, multiple memory chips 1000 can be vertically stacked. Each of the memory chips 1000 can be one of the memory chips 1000 described above. Each of the memory chips 1000 can include a core peripheral chip 10 and a cell chip 20 stacked vertically. The core peripheral chip 10 and the cell chip 20 can include TSVs 30. The core peripheral chip 10 and the cell chip 20 can be stacked alternately. Two memory chips 1000 are shown in FIG. 18, but in certain embodiments, three or more than three memory chips 1000 can be stacked. The memory chips 1000 can be electrically connected to each other via the TSVs 30. The TSVs 30 of each of the memory chips 1000 can include the TSVs 30 of the core peripheral chip 10 and the TSVs 30 of the cell chip 20. The TSVs 30 of the core peripheral chip 10 are physically connected to the TSVs 30 of the cell chip 20 in FIG. 18, but in certain embodiments, the TSVs 30 of the core peripheral chip 10 and the TSVs 30 of the cell chip 20 can be connected to each other via additional contact members disposed therebetween. The TSVs 30 of a pair of vertically stacked memory chips 1000 can be electrically connected to each other via a first contact pad CP1 and a second contact pad CP2. The first contact pad CP1 and the second contact pad CP2 can contact each other. The first contact pad CP1 and the second contact pad CP2 can each independently be a conductive pad or a conductive bump. FIG. 19 is a cross-sectional view showing a semiconductor package including a memory chip according to some embodiments of the present disclosure. Referring to FIG. 19, the semiconductor package 2000 may include a base wafer 1100 and a plurality of memory chips 1000 and memory chips 1000' on the base wafer 1100. The base wafer 1100 may be electrically connected to the plurality of memory chips 1000 and memory chips 1000' and may include a main core or a buffer die. The main core may include a processor that performs various operations. The buffer die may receive commands, data, and / or signals transmitted from the outside, and may transmit the received commands, data, and / or signals to the plurality of memory chips 1000 and memory chips 1000'. In other words, the plurality of memory chips 1000 and memory chips 1000' may be connected to the base wafer 1100 and may be used to perform various operations in response to signals received from the base wafer 1100. The plurality of memory chips 1000 and memory chips 1000' may be electrically connected to the base wafer 1100 via the TSVs 30. For example, the base wafer 1100 may include base contact pads CPh disposed at its top end, and the TSVs 30 may be connected to the base wafer 1100 via the base contact pads CPh. For example, the TSVs 30 may not be disposed in the uppermost memory chip 1000', but embodiments of the present disclosure are not limited thereto. FIG. 20 is a cross-sectional view showing a semiconductor package including memory chips according to some embodiments of the present disclosure. Referring to FIG. 20, the semiconductor package 1 may include a package substrate, a memory structure 3000, and a main structure 800. The memory structure 3000 and the main structure 800 may be disposed on the package substrate and may be horizontally spaced apart from each other. The memory structure 3000 and the main structure 800 may be electrically connected to each other via the package substrate. In some embodiments, the package substrate may include a first package substrate 400 and a second package substrate 500. The first package substrate 400 may be positioned on the second package substrate 500, and the memory structure 3000 and the main structure 800 may be positioned on the first package substrate 400. The first package substrate 400 may be an insert, and the second package substrate 500 may be a printed circuit board (PCB). The first connection terminals 440 may electrically connect the first package substrate 400 to the second package substrate 500. The second connection terminals 540 may electrically connect the semiconductor package 1 to an external device (e.g., a motherboard). The memory structure 3000 may include a base wafer 300, a plurality of memory chips 1000 and memory chips 1000' on the base wafer 300, a first molding layer MD1 surrounding the plurality of memory chips 1000 and memory chips 1000', and memory connection terminals 340 between the base wafer 300 and the package substrate (e.g., the first package substrate 400 and the second package substrate 500). The base wafer 300 may correspond to the base wafer 1100 in FIG. 19. The base wafer 300 may include a base layer 310, an upper interconnect layer 330 formed on a surface (e.g., the top surface) of the base layer 310, and a lower base pad 320 exposed at another surface (e.g., the bottom surface) of the base layer 310. The upper interconnect layer 330 may include an upper base pad 332 and a base protection layer 334 surrounding the upper base pad 332. The base wafer 300 may redistribute a plurality of memory wafers 1000 and memory wafers 1000'. The upper base pad 332 and the lower base pad 320 may be electrically connected to each other via circuit lines in the base layer 310 and may together with the circuit lines constitute a redistribution circuit. Memory connection terminals 340 may be positioned between the lower base pad 320 and a package substrate (e.g., a first package substrate 400 and a second package substrate 500). The memory connection terminals 340 may include solder balls or solder bumps. The first molding layer MD1 may include an insulating material. For example, the first molding layer MD1 may include an epoxy molding compound (EMC). The main structure 800 may be a data processing unit. Main connection terminals 840 may be disposed between the main structure 800 and a package substrate (e.g., a first package substrate 400 and a second package substrate 500). The main connection terminals 840 may electrically connect the main structure 800 to the package substrate (e.g., a first package substrate 400 and a second package substrate 500). The second molding layer MD2 may surround the memory structure 3000 and the main structure 800 on the package substrate (e.g., a first package substrate 400 and a second package substrate 500). According to the present disclosure, the core-peripheral wafer 10 and the cell wafer 20 may be vertically stacked, and thus a core region COR and a peripheral region PR may be defined on a plane located at a level different from that of the cell region CR. Therefore, compared with the case where the cell region CR, the core region COR, and the peripheral region PR are defined on the same plane, the integration density in the unit area of the memory wafer 1000 can be improved. In addition, since the core-peripheral wafer 10 includes an NPU block NB, the NPU block NB may be disposed adjacent to the cell region CR. Therefore, the data transfer distance between the NPU block NB and the cell region CR can be minimized, and the data processing speed of the memory wafer 1000 can be improved. In addition, the memory wafer 1000 can be driven by low power, and problems such as noise and / or heat generation can be reduced or minimized. Therefore, the performance of the memory wafer 1000 can be improved. According to an embodiment of the present disclosure, the core-peripheral wafer and the cell wafer may be vertically stacked. Therefore, the integration density in the unit area of the memory wafer and the semiconductor package including the same can be improved. In addition, since the core peripheral chip includes an NPU block, the NPU block can be disposed adjacent to the cell region. Therefore, the data transmission distance between the NPU block and the cell region can be minimized, and the data processing speed of the memory chip can be improved. Accordingly, the performance of the memory chip and the semiconductor package including the same can be improved. Although non-limiting example embodiments of the present disclosure have been specifically illustrated and described, those of ordinary skill in the art will understand that changes in form and detail may be made without departing from the spirit and scope of the present disclosure. 1. 2000: Semiconductor Package 10: Core Peripheral Chip 10a, 20a: First Side Surface 10b, 20b: Second Side Surface 10c, 20c: Third Side Surface 10d, 20d: Fourth Side Surface 11: Driving Layer 12: Core Peripheral Interconnect Layer 12a: Core Peripheral Circuit Line 12b: Core Peripheral Contact Plug 15: Core Peripheral Bonding Pad 20: Cell Chip 21: Data Storage Layer 22: Cell Interconnect Layer 22a: Cell Circuit Line 22b: Cell Contact Plug 25: Cell Bonding Pad 30: Through-Silicon Via 50: Through-Conductive Pattern 60: Chip Insulating Layer 100: Core Peripheral Semiconductor Layer 110: Core Peripheral Transistor 200: Cell Semiconductor Layer 201: First Surface 202: Second Surface 210: Memory Cell Layer 300, 1100: Substrate Chip 310: Substrate Layer 320: Lower Substrate Pad 330: Upper Interconnect Layer 332: Upper Substrate Pad 334: Substrate Protection Layer 340: Memory Connection Terminal 400: First Package Substrate 440: First Connection Terminal 500: Second Package Substrate 540: Second Connection Terminal 800: Main Structure 840: Main Connection Terminal 1000, 1000': Memory Chip 3000: Memory Structure ACT: Active Region BC: Storage Node Contact BL: Bit Line CAP: Capacitor CB: Cell Bank CG: Cell Group Region CG1, COG1: First Group CG2, COG2: Second Group CH: Channel Pattern COB: Core Bank COG: Core Group Region COG3: Third Group COG4: Fourth Group COR: Core Region CP1: First Contact Pad CP2: Second Contact Pad CPh: Substrate Contact Pad CR: Cell Region D1: First Direction D2: Second Direction DC: Bit Line Node Contact MD1: First Molded Layer MD2: Second Molded Layer NB: Neural Processing Unit Block NBF: Neural Processing Unit Buffer PR: Peripheral Region VD: Vertical Direction WL: Word Line FIG. 1 and FIG. 2 are perspective views showing a memory chip according to some embodiments of the present disclosure. FIGS. 3 to 10 are plan views showing a core peripheral chip of a memory chip according to some embodiments of the present disclosure. FIGS. 11 to 14 are plan views showing a cell chip of a memory chip according to some embodiments of the present disclosure. FIGS. 15A to 17B are cross-sectional views showing a memory chip according to some embodiments of the present disclosure. FIG. 18 is a cross-sectional view showing a plurality of memory chips according to some embodiments of the present disclosure. FIG. 19 is a cross-sectional view showing a semiconductor package including a memory chip according to some embodiments of the present disclosure. FIG. 20 is a cross-sectional view showing a semiconductor package including a memory chip according to some embodiments of the present disclosure. 10: Core Peripheral Chip 10a: First Side Surface 10b: Second Side Surface 10c: Third Side Surface 10d: Fourth Side Surface 100: Core Peripheral Semiconductor Layer COG1: First Group COG2: Second Group COB: Core Group COG: Core Group Region COR: Core Region D1: First Direction D2: Second Direction NB: Neural Processing Unit Block PR: Peripheral Region

Claims

1. A memory chip, comprising: Cellular wafers; The core peripheral chip includes a core chip and a peripheral chip, wherein the cellular chip and the core peripheral chip are vertically stacked and electrically connected to each other, wherein the cellular chip includes a cellular region, each of the cellular regions including a memory cellular layer, wherein the core peripheral chip includes at least one core group region and a peripheral region adjacent to each other in a first direction, wherein the peripheral region extends in a second direction intersecting the first direction, the at least one core group region includes a first core group region and a second core group region, the first core group region and the second core group region being spaced apart from each other in the first direction by the peripheral region inserted therebetween, wherein both the first core group region and the second core group region include core regions arranged in a row in the second direction, and wherein each of the core regions includes: a core group including core circuitry; and a neural processing unit (NPU) block including a neural processing unit.

2. The memory chip as claimed in claim 1, wherein the core group and the neural processing unit block of the first core group region and the second core group region are symmetrical with respect to the peripheral region.

3. The memory chip as claimed in claim 1, wherein the core group and the neural processing unit block of the first core group region and the second core group region are asymmetrical relative to the peripheral region.

4. The memory chip of claim 1, wherein the core peripheral chip includes a side surface facing the first direction, and wherein the at least one core group region includes core group regions adjacent to each other in the first direction between the side surface of the core peripheral chip and the peripheral region.

5. The memory chip as claimed in claim 1, wherein each of the cell regions further includes a neural processing unit buffer.

6. The memory chip of claim 5, wherein the neural processing unit buffer comprises at least one of phase-change random access memory (PRAM), spin-transfer torque magnetic RAM (STT-MRAM), ferroelectric RAM (FeRAM), and static RAM (SRAM).

7. The memory chip as claimed in claim 1, wherein the memory cell layer comprises at least one of two-dimensional (2D) memory and three-dimensional (3D) memory.

8. The memory chip as claimed in claim 1, wherein each of the cell regions vertically overlaps at least a portion of one of the neural processing unit blocks.

9. The memory chip of claim 1, wherein each of the cell chip and the core peripheral chip further includes a through-silicon via (TSV), and wherein the TSV of the cell chip is electrically connected to the TSV of the core peripheral chip.

10. The memory chip of claim 1, wherein the cell chip and the core peripheral chip are electrically connected to each other via a through conductive pattern penetrating the cell chip and the core peripheral chip.

11. The memory chip of claim 1, wherein the cell chip further includes cell bonding pads, wherein the core peripheral chip further includes core peripheral bonding pads, and wherein the cell bonding pads and the core peripheral bonding pads are coupled to each other to electrically connect the cell chip and the core peripheral chip.

12. The memory chip as claimed in claim 1, wherein the cell chip further includes a cell semiconductor layer containing semiconductor material, and wherein the cell semiconductor layer is located between the core peripheral chip and the memory cell layer.

13. The memory chip as claimed in claim 1, wherein the cell chip further includes a cell semiconductor layer containing semiconductor material, and wherein the memory cell layer is located between the core peripheral chip and the cell semiconductor layer.

14. A semiconductor package, comprising: Multiple memory chips stacked vertically; And through-silicon vias (TSVs) electrically connecting the plurality of memory chips, each of the plurality of memory chips comprising vertically stacked cell chips and core peripheral chips, wherein the cell chip comprises: cell regions, each of the cell regions comprising a memory cell layer, wherein the core peripheral chip comprises at least one core group region adjacent to each other in a first direction and a peripheral region, wherein the peripheral region extends in a second direction intersecting the first direction, the at least one core group region comprising a first core group region and a second core group region, the first core group region and the second core group region being spaced apart from each other in the first direction by the peripheral region inserted therebetween, wherein both the first core group region and the second core group region comprise core regions arranged in a row in the second direction, and wherein each of the core regions comprises: a core group including core circuitry; and a neural processing unit (NPU) block including a neural processing unit.

15. The semiconductor package as described in claim 14, further comprising: A substrate wafer, including a main core or buffer die, wherein the plurality of memory chips are located on the substrate wafer.

16. The semiconductor package as claimed in claim 14, wherein the silicon through-hole penetrates the central portion of the plurality of memory wafers.

17. A semiconductor package, comprising: Packaging substrate; The main structure is located on the packaging substrate; The package includes a memory structure horizontally spaced from and electrically connected to the main structure on the packaging substrate. The memory structure comprises a plurality of vertically stacked memory chips. Each of the plurality of memory chips includes a vertically stacked and electrically connected cell chip and a core peripheral chip. The cell chip includes a cell region, each cell region including a memory cell layer. The core peripheral chip includes at least one core group region and a peripheral region adjacent to each other in a first direction. The peripheral region extends in a second direction intersecting the first direction. The at least one core group region includes a first core group region and a second core group region, which are spaced apart in the first direction by the peripheral region inserted therebetween. Both the first and second core group regions include core regions arranged in a row in the second direction. Each of the core regions includes: a core group including core circuitry; and a neural processing unit (NPU) block including a neural processing unit.

18. The semiconductor package of claim 17, wherein the memory structure further includes a through-silicon via (TSV) electrically connecting the plurality of memory chips.

19. The semiconductor package of claim 17, wherein the memory structure comprises a plurality of memory structures horizontally spaced apart from each other.

20. The semiconductor package of claim 17, wherein the memory cell layer comprises at least one of two-dimensional (2D) memory and three-dimensional (3D) memory.

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