Semiconductor device and manufacturing method thereof

Abstract

This invention relates to a semiconductor device comprising a substrate, a nonpolar crystal orientation buffer layer, and a first nitride layer, wherein the nonpolar crystal orientation buffer layer is formed on the substrate, and the first nitride layer is formed on the nonpolar crystal orientation buffer layer. This invention also discloses a method for manufacturing such a semiconductor device.

Description

Semiconductor Device and Method for Manufacturing the Same The present invention relates to a semiconductor device, and more particularly to a semiconductor device applicable to light-emitting diodes, laser diodes, power semiconductors, and high electron mobility transistors, and a method for manufacturing the same. Aluminum gallium nitride (AlGaN) is an alloy of aluminum nitride and gallium nitride, which has a direct and continuously adjustable wide bandgap (3.4 eV to 6.2 eV), thermal stability, and chemical stability. AlGaN can be used to manufacture ultraviolet / blue light-emitting diodes, and the ultraviolet wavelength can be as low as 250 nm (far ultraviolet light). In addition, AlGaN can also be used in ultraviolet light-emitting diodes (LEDs), photodetectors, and high electron mobility transistors (HEMTs). Therefore, AlGaN has great application prospects in the semiconductor industry. Currently, in practice, AlGaN lacks a homoepitaxial substrate, which affects the efficiency of the electronic components made therefrom. Currently, the industry uses sapphire as the substrate for AlGaN growth. However, due to the inherent defects of sapphire, such as being extremely hard, non-conductive, low thermal conductivity, and high cost, the development of sapphire substrates for electronic components made of aluminum gallium nitride is limited. Compared with sapphire, silicon substrates have characteristics such as large size, low price, and excellent conductivity, and are substrates that can better realize the performance of electronic components made of AlGaN. Although silicon substrates have the above advantages, compared with sapphire, there are disadvantages such as a large lattice mismatch and thermal mismatch between silicon and aluminum gallium nitride, and Ga is prone to meltback etch with Si. Therefore, AlGaN cannot be directly grown on a silicon substrate. However, the two-step growth method can solve this problem. The so-called "two-step growth method" is to use amorphous aluminum nitride (Amorphous AlN) as a buffer layer between the silicon substrate and AlGaN. Since AlGaN is subjected to strong stress whether on a silicon or sapphire substrate, the epitaxial material AlGaN is extremely prone to cracking. If Amorphous AlN is used to replace the previously used GaN as the buffer layer, in addition to buffering the strong stress that AlGaN receives on the substrate and solving the cracking problem of AlGaN, it can also avoid the above-mentioned meltback etch problem. In addition to the lack of a homogeneous substrate, the polarization electric field of electronic components made of AlGaN is another factor affecting component efficiency. There is a very high piezoelectric polarization and spontaneous polarization electric field inside the nitride grown on the

[0001] crystal plane. For the past light-emitting diode or laser diode component structures, the built-in electric field generates the Quantum-Confined Stark Effect, which will further affect the injection efficiency of their effective carriers, thereby reducing the light emission intensity of the component. On the other hand, for the use of high-power components, such as high electron mobility transistor structures, due to the inherent built-in electric field characteristics, the normally-on components that are still conducting when powered off will face the risk of malfunction. Therefore, the new generation of high-power electronic components must be designed to meet the characteristics of normally-off. Therefore, non-polar nitrides are one of the solutions to solve the problems of the above components such as light-emitting diodes, laser diodes, and high electron mobility transistors. Currently, the general method for growing non-polar a-plane GaN thin films usually requires substrates with special crystal orientations such as sapphire, LiAlO 2 , and SiC, etc. And because the quality of LiAlO 2 is unstable at room temperature and the cost of SiC is relatively high, the current mainstream for growing nonpolar a-plane GaN still mainly uses r-plane sapphire. However, due to the certain technical difficulties and yield problems in the growth and cutting of sapphire, especially it is more difficult to obtain materials with r-plane sapphire, and the cost is also relatively high. In view of this, there is still a need in the market for a substrate that is easy to obtain and has a lower cost to solve the problems of the current use of r-plane sapphire materials. Since semiconductors of the AlGaN type have a very strong polarization built-in electric field, this characteristic is not conducive to applications such as light emission and electronic control. Therefore, by using a non-polar crystal orientation buffer layer to control the crystal structure of the AlGaN sample growth to be non-polar and applying it to LED, photodetector, and HEMT components, the above problems can be effectively improved. To solve the above problems, the main object of the present invention is to provide a semiconductor component, comprising: a substrate; a non-polar crystal orientation buffer layer formed on the substrate; and a first nitride layer formed on the non-polar crystal orientation buffer layer. The semiconductor device as described above further includes a first mask patterning layer formed on the first nitride layer; a second nitride layer formed on the first mask patterning layer and the first nitride layer; a second mask patterning layer formed on the second nitride layer, wherein the second mask patterning layer and the first mask patterning layer are arranged in a vertically staggered manner; and a third nitride layer formed on the second mask patterning layer and the second nitride layer. The semiconductor device as described above, wherein the non-polar crystal orientation buffer layer is a non-polar aluminum nitride buffer layer, a non-polar ternary or quaternary aluminum nitride-based compound buffer layer mainly composed of aluminum nitride, a non-polar zinc oxide buffer layer, or a non-polar ternary or quaternary zinc oxide-based compound buffer layer mainly composed of zinc oxide. The semiconductor device as described above, wherein the substrate includes a silicon substrate, a silicon sapphire substrate, a silicon carbide substrate, a quartz substrate, or a high-temperature resistant substrate, and the high-temperature resistant substrate is a substrate capable of withstanding a high-temperature process of 1000 °C or higher. The semiconductor device as described above, wherein the first nitride layer, the second nitride layer, and the third nitride layer are group III nitrides, and the material of the group III nitrides is selected from one or a combination of the group consisting of GaN and AlGaN. The semiconductor device as described above, wherein the materials of the first mask patterning layer and the second mask patterning layer are selected from one or a combination of the group consisting of silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), or silicon oxynitride (SiO x N y ). Another object of the present invention is to provide a method for manufacturing a semiconductor device, the method comprising the steps of: providing a substrate; forming a non-polar crystal orientation buffer layer on the substrate; and forming a first nitride layer on the non-polar crystal orientation buffer layer. The manufacturing method of the semiconductor device as described above further includes: forming a first mask patterning layer on the first nitride layer, such that a partial region of the first nitride layer is shielded by the first mask patterning layer, and another partial region of the first nitride layer is not shielded by the first mask patterning layer; using the first mask patterning layer as a mask, etching the other partial region of the first nitride layer that is not shielded, to form at least one etching groove and expose the non-polar crystal orientation buffer layer; forming a second nitride layer on the non-polar crystal orientation buffer layer and the first mask patterning layer, wherein the second nitride layer grows from the non-polar crystal orientation buffer layer, such that the second nitride layer fills the etching groove, and forms the second nitride layer on the first mask patterning layer; forming a second mask patterning layer on the second nitride layer, such that a partial region of the second nitride layer is shielded by the second mask patterning layer, and another partial region of the second nitride layer is not shielded by the second mask patterning layer, wherein the second mask patterning layer is disposed corresponding to the etching groove, such that the partial region of the second nitride layer shielded by the second mask patterning layer is disposed corresponding to the etching groove; and forming a third nitride layer on the second nitride layer and the second mask patterning layer, wherein the third nitride layer grows from the second nitride layer, such that the third nitride layer fills the region not shielded by the second mask patterning layer, and forms the third nitride layer on the second mask patterning layer. The manufacturing method of the semiconductor device as described above, wherein the non-polar crystal orientation buffer layer is a non-polar aluminum nitride buffer layer, a non-polar ternary or quaternary aluminum nitride-based compound buffer layer mainly composed of aluminum nitride components, a non-polar zinc oxide buffer layer, or a non-polar ternary or quaternary zinc oxide-based compound buffer layer mainly composed of zinc oxide components. The manufacturing method of the semiconductor device as described above, wherein the substrate includes a silicon substrate, a silicon sapphire substrate, a silicon carbide substrate, a quartz substrate, or a high-temperature resistant substrate, and the high-temperature resistant substrate is a substrate capable of withstanding a high-temperature process above 1000°C. Accordingly, the semiconductor device provided by the present invention utilizes an epitaxial growth technology capable of growing a non-polar crystal orientation buffer layer on any substrate. Since this epitaxial growth method is not limited by the conventional requirement that nonpolar a-plane GaN needs to be grown on a specific substrate crystal plane, such as the r-plane sapphire, the manufacturing cost can be effectively reduced. Through the epitaxial growth method of the present invention, a non-polar crystal orientation buffer layer, such as a non-polar AlN buffer layer, can be grown on any material substrate such as Si, sapphire, or SiC first. Then, a non-polar single crystal thin film, such as an a-plane GaN single crystal thin film, can be grown on this buffer layer. Therefore, the epitaxial growth quality can be optimized by using the technology of the present invention to form a non-polar crystal orientation buffer layer on any substrate. The semiconductor device thus formed can be effectively applied to components such as light-emitting diodes, laser diodes, and high electron mobility transistors. The object of the present invention and its advantages in terms of structure and function will be described with reference to the structure shown in the following drawings and in conjunction with specific embodiments, so that the review committee can have a more in-depth and specific understanding of the present invention. Please refer to FIG. 1. An embodiment of the present invention provides a semiconductor device 1, which includes: a substrate 11, wherein the substrate 11 has a flat surface 111, and no cavities are formed on the flat surface 111; a non-polar crystal orientation buffer layer 12 formed on the flat surface 111 of the substrate 11; and a first nitride layer 13 formed on the non-polar crystal orientation buffer layer 12. In this embodiment, the top surface of the substrate 11 is a flat surface 111, and no cavities are formed on the flat surface 111. However, this is not limited thereto. In other embodiments, concavities and convexities can also be formed on the flat surface 111 to facilitate the application of other different growth conditions. In other words, the present invention does not limit whether the top surface of the substrate 11 is flat or non-flat, such as a patterned-sapphire substrate (PSS). The substrate 11 is a silicon substrate, such as Si. However, this is not limited thereto. Silicon sapphire substrates (sapphire), quartz substrates, silicon carbide substrates (SiC), or other high-temperature resistant substrates can also be applied in the present invention. Here, the high-temperature resistant substrate refers to a substrate that can withstand a high-temperature process of about 1000°C or more. Since metalorganic chemical vapor deposition (MOCVD) is a high-temperature process that requires a temperature of 1000°C or more, a high-temperature resistant substrate such as a ceramic substrate is required to withstand the high-temperature process conditions for chemical reactions. However, since silicon substrates have advantages in terms of raw material acquisition, use, and price, the silicon substrate is used as the substrate 11 in this embodiment. In addition, in this embodiment, the nonpolar crystal orientation buffer layer 12 is a nonpolar aluminum nitride buffer layer (nonpolar AlN buffer layer). However, this is not limiting. Another option is that the nonpolar crystal orientation buffer layer 12 is a nonpolar ternary or quaternary aluminum nitride-based compound buffer layer mainly composed of aluminum nitride components. Among them, the ternary aluminum nitride-based compound buffer layer is, for example, aluminum scandium nitride (AlScN), aluminum indium nitride (AlInN), aluminum gallium nitride (AlGaN), aluminum phosphonitride (AlNP), and the quaternary aluminum nitride-based compound buffer layer is, for example, aluminum scandium indium nitride (AlScInN), aluminum gallium indium nitride (AlGaInN), aluminum scandium gallium nitride (AlScGaN), aluminum scandium phosphonitride (AlScNP), aluminum gallium phosphonitride (AlGaNP), aluminum indium phosphonitride (AlInNP). Another option is that the nonpolar crystal orientation buffer layer 12 is a nonpolar zinc oxide buffer layer (nonpolar ZnO buffer layer), or a nonpolar ternary or quaternary zinc oxide-based compound buffer layer mainly composed of zinc oxide components. Among them, the ternary zinc oxide-based compound buffer layer is, for example, zinc vanadium oxide (ZnVO), zinc chromium oxide (ZnCrO), zinc copper oxide (ZnCuO), zinc iron oxide (ZnFeO), zinc manganese oxide (ZnMnO), zinc nickel oxide (ZnNiO), zinc cobalt oxide (ZnCoO), and the quaternary zinc oxide-based compound buffer layer is, for example, zinc copper cobalt oxide (ZnCuCoO), zinc copper nickel oxide (ZnCuNiO), zinc copper iron oxide (ZnCuFeO), zinc cobalt nickel oxide (ZnCoNiO), zinc cobalt iron oxide (ZnCoFeO), zinc nickel iron oxide (ZnNiFeO). Furthermore, the first nitride layer 13 is a group III nitride, and the material of the group III nitride is selected from one or a combination of the group consisting of GaN and AlGaN. Due to the structure and material characteristics of the semiconductor device 1 of the present invention, it can be applied to light-emitting diodes, laser diodes, or high electron mobility transistors. It is worth mentioning that the non-polar ternary or quaternary aluminum nitride-based compound buffer layer mainly composed of aluminum nitride components used in the present invention, wherein the ternary aluminum nitride-based compound buffer layer is mainly based on the binary non-polar aluminum nitride buffer layer, and part of the original nitrogen atoms or aluminum atoms are replaced or substituted by other elements by means of solid solution or doping. For example, nitrogen atoms can be replaced by group同族 elements such as phosphorus, while aluminum atoms can be replaced by group同族 elements such as gallium or indium or transition elements such as scandium. Such a method can effectively adjust the lattice constant to fully exert the role of the buffer layer. Similarly, the quaternary aluminum nitride-based compound buffer layer is also mainly based on the binary non-polar aluminum nitride buffer layer, except that part of both nitrogen and aluminum atoms or only aluminum atoms will be replaced or substituted by other two elements, rather than just a single element replacing or substituting nitrogen atoms or aluminum atoms. In this way, the fine-tuning effect of the lattice constant can be further improved. Similarly, the non-polar ternary or quaternary zinc oxide-based compound buffer layer mainly composed of zinc oxide components used in the present invention is also similar to the above-mentioned non-polar ternary or quaternary aluminum nitride-based compound buffer layer mainly composed of aluminum nitride components, so it will not be repeated here. In some embodiments, in order to ensure that the dislocation d generated between the non-polar crystal orientation buffer layer 12 and the first nitride layer 13 of the homojunction does not affect the subsequent deposition of the group III nitride. Therefore, referring to FIG. 2, the present invention can then sequentially dispose a first mask patterning layer 14, a second nitride layer 15, a second mask patterning layer 16, and a third nitride layer 17 on the aforementioned semiconductor element 1, wherein the first mask patterning layer 14 is formed on the first nitride layer 13; the second nitride layer 15 is formed on the first mask patterning layer 14 and the first nitride layer 13; the second mask patterning layer 16 is formed on the second nitride layer 15, wherein the second mask patterning layer 16 and the first mask patterning layer 14 are arranged in a vertically staggered manner; and the third nitride layer 17 is formed on the second mask patterning layer 16 and the second nitride layer 15. It can be understood that when the dislocation d extends upward along the thickness direction of the first nitride layer 13, it will first encounter the first mask patterning layer 14. Since the first mask patterning layer 14 is a hard structural material, such as silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), or silicon oxynitride (SiO x N y), so the dislocation d will be blocked by the first mask patterning layer 14 and thus cannot continue to extend upward. The dislocations d not blocked by the first mask patterning layer 14 will continue to extend upward along the thickness direction of the second nitride layer 15. Since the second mask patterning layer 16, like the first mask patterning layer 14, is made of a hard structural material such as silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), or silicon oxynitride (SiO x N y ), and the second mask patterning layer 16 and the first mask patterning layer 14 are arranged in a staggered up-and-down manner, the dislocations d not blocked by the first mask patterning layer 14 will then encounter the second mask patterning layer 16 and be blocked by the second mask patterning layer 16 and thus cannot continue to extend upward. In this way, all the dislocations d are blocked by the first mask patterning layer 14 and the second mask patterning layer 16 and cannot continue to extend upward to the third nitride layer 17. Therefore, the epitaxial layer deposited and coated after the second mask patterning layer 16, such as the third nitride layer 17, has good epitaxial quality and is not easily defective, thereby enabling better light-emitting characteristics to be produced. In some embodiments, another object of the present invention is to provide a method for manufacturing a semiconductor device 2. Please refer to FIGS. 3 and 4A to 4G simultaneously. The method includes the following steps: Step S1: Provide a substrate 11, where the substrate 11 has a flat surface 111, and no cavities are formed on the flat surface 111; Step S2: Form a non-polar crystal orientation buffer layer 12 on the flat surface 111 of the substrate 11; Step S3: Form a first nitride layer 13 on the non-polar crystal orientation buffer layer 12; Step S4: Form a first mask patterning layer 14 on the first nitride layer 13, such that a part of the first nitride layer 13 is shielded by the first mask patterning layer 14, and another part of the first nitride layer 13 is not shielded by the first mask patterning layer 14; Step S5: Using the first mask patterning layer 14 as a mask, etch the other part of the first nitride layer 13 that is not shielded to form at least one etching groove 130 and expose a part of the non-polar crystal orientation buffer layer 12; Step S6: Form a second nitride layer 15 on the non-polar crystal orientation buffer layer 12 and the first mask patterning layer 14, where the second nitride layer 15 grows from the non-polar crystal orientation buffer layer 12, such that the second nitride layer 15 fills the etching groove 130 and forms the second nitride layer 15 on the first mask patterning layer 14; Step S7: Form a second mask patterning layer 16 on the second nitride layer 15, such that a part of the second nitride layer 15 is shielded by the second mask patterning layer 16, and another part of the second nitride layer 15 is not shielded by the second mask patterning layer 16, where the second mask patterning layer 16 is arranged corresponding to the etching groove 130, such that the part of the second nitride layer 15 shielded by the second mask patterning layer 16 also corresponds to the etching groove 130; Step S8: Form a third nitride layer 17 on the second nitride layer 15 and the second mask patterning layer 16, where the third nitride layer 17 grows from the second nitride layer 15, such that the third nitride layer 17 fills the area not shielded by the second mask patterning layer 16 and forms the third nitride layer 17 on the second mask patterning layer 16. It can be understood that when forming the semiconductor element 1 as shown in FIG. 1, the manufacturing method 2 of this semiconductor element only needs to proceed from step S1 to step S3. When forming the semiconductor element 1 as shown in FIG. 2, the manufacturing method 2 of this semiconductor element needs to proceed from step S1 to step S8. In addition, in this embodiment, the epitaxial growth step is mainly carried out by metalorganic chemical vapor deposition (MOCVD), and a nonpolar crystal orientation AlN thin film is deposited on the silicon substrate by radio frequency magnetron sputtering method. Under the deposition parameter conditions such as a temperature of 200 °C, a radio frequency power of 350 W, a chamber pressure of 9 mTorr, and a nitrogen concentration of 50%, the deposition and growth of the nonpolar crystal orientation AlN thin film are carried out. However, it is not limited to this, and other chemical vapor deposition (CVD) or physical vapor deposition (PVD) can also be applied to the present invention. In addition, when the second nitride layer 15 fills the etching groove 130, holes 18 will be generated, that is, the etching groove 130 is not completely filled. Similarly, when the second nitride layer 15 grows on the first mask patterning layer 14, holes 18 will also be formed on the first mask patterning layer 14. The existence of these holes 18 helps to relieve the stress caused by the too large difference in lattice constants between different materials. Similarly, when the third nitride layer 17 grows on the second mask patterning layer 16, holes 18 will also be formed on the second mask patterning layer 16. That is, the first nitride layer 13, the second nitride layer 15, and the third nitride layer 17 of the present invention all contain holes 18, and the positions of these holes 18 correspond to the first mask patterning layer 14 and the second mask patterning layer 16, as shown in FIG. 4G. Furthermore, in this embodiment, since the first nitride layer 13, the second nitride layer 15, and the third nitride layer 17 are all group III nitrides, the problem of stress caused by the too large difference in lattice constants during epitaxial growth can be reduced. In some embodiments, the material of the group III nitride is selected from one or a combination of the groups composed of GaN and AlGaN. In this embodiment, the substrate 11 is a silicon substrate, such as Si. However, it is not limited to this, and silicon sapphire substrate (sapphire), quartz substrate, silicon carbide substrate (SiC), or high-temperature resistant substrate can also be applied to the present invention. In addition, in this embodiment, the nonpolar crystal orientation buffer layer 12 is a nonpolar aluminum nitride buffer layer. However, it is not limited to this. Another option is that the nonpolar crystal orientation buffer layer 12 is a nonpolar ternary or quaternary aluminum nitride-based compound buffer layer mainly composed of aluminum nitride, a nonpolar zinc oxide buffer layer (nonpolar ZnO buffer layer), or a nonpolar ternary or quaternary zinc oxide-based compound buffer layer mainly composed of zinc oxide. Similarly, the top surface of the substrate 11 here is a flat surface 111, and no concavo-convex holes are formed on the flat surface 111. However, this is not limited thereto. In other embodiments, concavo-convex holes may also be formed on the flat surface 111, such as grooves or protrusions of different shapes, to facilitate the application requirements of various different growth conditions. In other words, the present invention does not limit whether the top surface of the substrate 11 is flat or non-flat, and any patterned surface can also be applied in the present invention. The special feature of the present invention is that it is not limited by the fact that nonpolar a-plane GaN needed to grow on special material substrate crystal planes such as r-plane sapphire in the past. Through the growth method of the present invention, a nonpolar crystal orientation aluminum nitride buffer layer (nonpolar AlN buffer layer) can be grown on any material substrate such as Si, sapphire, and SiC first. As shown in FIGS. 1 and 2, then this buffer layer is used to grow a nonpolar a-plane GaN single crystal thin film. For the XRD analysis of this nonpolar crystal orientation aluminum nitride buffer layer, please refer to FIG. 5. The analysis results show that a nonpolar crystal orientation AlN buffer layer is grown on a (100) crystal orientation Si substrate. Through appropriate MOCVD epitaxial growth conditions, a nonpolar a-plane GaN thin film with a crystal orientation of (110) can be further grown as shown in FIG. 6. The 2 theta angle of (110) GaN is about 57°. In addition, from the XRD analysis results of FIG. 7, it can also be seen that after growing a nonpolar direction AlN buffer layer on c-plane sapphire, through appropriate MOCVD epitaxial condition control, an a-plane GaN thin film with a (110) single crystal orientation can be grown. The above XRD results confirm that the growth technology of the present invention can successfully grow single crystal a-plane GaN thin films on Si(100) and c-plane sapphire. Please refer to FIGS. 8 to 10. Through the above substrate and the nonpolar crystal orientation aluminum nitride buffer layer grown thereon, the epitaxial quality can be further optimized by using the secondary epitaxial technology to respectively selectively form a light-emitting diode 3 as shown in FIG. 8, a laser diode 4 as shown in FIG. 9, and a high electron mobility transistor 5 as shown in FIG. 10. In this way, it can be determined that the present invention is effectively applied to the fabrication of components such as the light-emitting diode 3, the laser diode 4, and the high electron mobility transistor 5. It can be understood that in order to effectively prevent the dislocation d from growing and extending upward, the second mask patterning layer 16 and the first mask patterning layer 14 are arranged in a vertically staggered manner, and the vertical projections of the second mask patterning layer 16 and the first mask patterning layer 14 facing the non-polar crystal orientation buffer layer 12 must cover the entire top surface of the non-polar crystal orientation buffer layer 12. When the first nitride layer 13 is formed on the top surface of the non-polar crystal orientation buffer layer 12, any possible defects or dislocations d will be blocked by the second mask patterning layer 16 and the first mask patterning layer 14, and there will be no space or opportunity for the dislocation d to grow and extend upward. In summary, the semiconductor device provided by the present invention utilizes an epitaxial technology that can grow a non-polar crystal orientation buffer layer on any substrate. Since this epitaxial method is not limited by the need to grow on a substrate crystal plane of a special material in the prior art, the manufacturing cost can be effectively reduced. Through the epitaxial growth method of the present invention, a non-polar crystal orientation buffer layer can be grown on any material substrate such as Si, sapphire, SiC, quartz substrate or high-temperature resistant substrate, and then a non-polar single crystal thin film can be grown by using this non-polar crystal orientation buffer layer. Therefore, the epitaxial quality can be optimized by using the technology of the present invention to form a non-polar crystal orientation buffer layer on any substrate, and the semiconductor device formed in this way can be effectively applied to components such as light-emitting diodes, laser diodes and high electron mobility transistors. However, the above-described illustrations and descriptions are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention; those skilled in the art, according to the characteristic scope of the present invention, any other equivalent changes or modifications should be regarded as not departing from the design scope of the present invention. 1: Semiconductor device 11: Substrate 111: Flat surface 12: Non-polar crystal orientation buffer layer 13: First nitride layer 14: First mask patterning layer 15: Second nitride layer 16: Second mask patterning layer 17: Third nitride layer 18: Hole 2: Manufacturing method of semiconductor device 3: Light-emitting diode 4: Laser diode 5: High electron mobility transistor S1: Provide a substrate, wherein the substrate has a flat surface S2: Form a non-polar crystal orientation buffer layer on the flat surface of the substrate S3: Form a first nitride layer 13 on the non-polar crystal orientation buffer layer S4: Form a first mask patterning layer on the first nitride layer S5: Use the first mask patterning layer as a mask to etch the unshielded other part of the first nitride layer S6: Form a second nitride layer on the non-polar crystal orientation buffer layer and the first mask patterning layer S7: Form a second mask patterning layer on the second nitride layer S8: Form a third nitride layer on the second nitride layer and the second mask patterning layer d: Dislocation FIG. 1 is a schematic cross-sectional structure diagram of a semiconductor device of the present invention; FIG. 2 is a schematic cross-sectional structure diagram of another semiconductor device of the present invention; FIG. 3 is a flowchart block diagram of a manufacturing method of the semiconductor device of the present invention; FIGS. 4A to 4G are schematic cross-sectional structure diagrams in the manufacturing process of the semiconductor device of the present invention; FIG. 5 is an XRD analysis diagram of an aluminum nitride buffer layer of the semiconductor device of the present invention; FIG. 6 is an XRD analysis diagram of a non-polar a-plane GaN thin film grown on a Si substrate of the semiconductor device of the present invention; FIG. 7 is an XRD analysis diagram of a non-polar a-plane GaN thin film grown on a sapphire substrate of the semiconductor device of the present invention; FIG. 8 is a schematic cross-sectional structure diagram of the semiconductor device of the present invention applied to a light-emitting diode; FIG. 9 is a schematic cross-sectional structure diagram of the semiconductor device of the present invention applied to a laser diode; and FIG. 10 is a schematic cross-sectional structure diagram of the semiconductor device of the present invention applied to a high electron mobility transistor. 1: Semiconductor device 11: Substrate 111: Flat surface 12: Non-polar crystal orientation buffer layer 13: First nitride layer d: Dislocation

Claims

1. A semiconductor device comprising: a substrate; a non-polar crystal orientation buffer layer formed on the substrate; a first nitride layer formed on the non-polar crystal orientation buffer layer and having at least one etch trench to expose a portion of the non-polar crystal orientation buffer layer; a first mask patterning layer formed on the first nitride layer; a second nitride layer formed on the first mask patterning layer and the first nitride layer, and filling the etch trench; a second mask patterning layer formed on the second nitride layer, wherein the second mask patterning layer is disposed corresponding to the etch trench and is arranged vertically interleaved with the first mask patterning layer; and a third nitride layer formed on the second mask patterning layer and the second nitride layer. Both the second nitride layer and the third nitride layer contain pores, and the pores in the second nitride layer correspond to those formed by the first mask patterning layer and the second mask patterning layer, while the pores in the third nitride layer correspond to those formed by the second mask patterning layer.

2. The semiconductor device as claimed in claim 1, wherein the nonpolar crystal orientation buffer layer is a nonpolar aluminum nitride buffer layer, a nonpolar ternary or quaternary aluminum nitride-based compound buffer layer with aluminum nitride as the main component, a nonpolar zinc oxide buffer layer, or a nonpolar ternary or quaternary zinc oxide-based compound buffer layer with zinc oxide as the main component.

3. The semiconductor device as claimed in claim 1, wherein the substrate comprises a silicon substrate, a silicon sapphire substrate, a silicon carbide substrate, a quartz substrate, or a high-temperature resistant substrate, wherein the high-temperature resistant substrate is a substrate capable of withstanding high-temperature processes above 1000°C.

4. The semiconductor device as claimed in claim 1, wherein the first nitride layer, the second nitride layer and the third nitride layer are a group 3 nitride, and the material of the group 3 nitride is selected from one or a combination of GaN and AlGaN.

5. The semiconductor device as described in any one of claims 1 to 4, wherein the materials of the first mask patterning layer and the second mask patterning layer are selected from one or a combination of the groups consisting of silicon dioxide (SiO2), silicon nitride (Si3N4), and silicon oxynitride (SiOxNy).

6. A method for manufacturing a semiconductor device, comprising: providing a substrate; forming a non-polar crystal orientation buffer layer on the substrate; forming a first nitride layer on the non-polar crystal orientation buffer layer; forming a first mask patterning layer on the first nitride layer, such that a portion of the first nitride layer is masked by the first mask patterning layer, and another portion of the first nitride layer is not masked by the first mask patterning layer; using the first mask patterning layer as a photomask, etching the other unmasked portion of the first nitride layer to form at least one etch trench and expose a portion of the non-polar crystal orientation buffer layer; forming a second nitride layer on the non-polar crystal orientation buffer layer and the first mask patterning layer, wherein the second nitride layer is grown from the non-polar crystal orientation buffer layer, such that the second nitride layer fills the etch trench, and the second nitride layer is formed on the first mask patterning layer; A second mask patterning layer is formed on the second nitride layer, such that a portion of the second nitride layer is masked by the second mask patterning layer, while another portion of the second nitride layer is not masked by the second mask patterning layer. The second mask patterning layer is disposed corresponding to the etch trench and is arranged vertically and alternately with the first mask patterning layer, such that a portion of the second nitride layer masked by the second mask patterning layer is disposed corresponding to the etch trench. A third nitride layer is formed on the second nitride layer and the second mask patterning layer, wherein the third nitride layer is grown from the second nitride layer, such that the third nitride layer fills the area not masked by the second mask patterning layer, and the third nitride layer is formed on the second mask patterning layer. Both the second nitride layer and the third nitride layer contain pores, and the pores in the second nitride layer correspond to those formed by the first mask patterning layer and the second mask patterning layer, while the pores in the third nitride layer correspond to those formed by the second mask patterning layer.

7. A method for manufacturing a semiconductor device as described in claim 6, wherein the nonpolar crystal orientation buffer layer is a nonpolar aluminum nitride buffer layer, a nonpolar ternary or quaternary aluminum nitride-based compound buffer layer with aluminum nitride as the main component, a nonpolar zinc oxide buffer layer, or a nonpolar ternary or quaternary zinc oxide-based compound buffer layer with zinc oxide as the main component.

8. A method for manufacturing a semiconductor device as described in any one of claims 6 to 7, wherein the substrate comprises a silicon substrate, a silicon sapphire substrate, a silicon carbide substrate, a quartz substrate, or a high-temperature resistant substrate, wherein the high-temperature resistant substrate is a substrate capable of withstanding high-temperature processes above 1000°C.

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