Semiconductor structure and method of forming the same

Abstract

A semiconductor structure includes a substrate, a semiconductor layer on the substrate, a gate structure on the semiconductor layer, a first dielectric layer extending continuously on the gate structure and the semiconductor layer and including a first portion and a second portion, an etch stop layer on at least a first portion of the first dielectric layer, a second dielectric layer on the etch stop layer, and a field plate. The field plate includes a first field plate portion on the second dielectric layer and a second field plate portion on the second portion of the first dielectric layer, wherein the lower surface of the first field plate portion and the lower surface of the second field plate portion are respectively at a first distance and a second distance from the semiconductor layer, the first distance being greater than the second distance; the field plate and the gate structure have a first projection and a second projection on the substrate respectively in a direction perpendicular to the substrate, and the first projection does not cover the second projection.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor structure and a method for forming the same. [Previous Technology]

[0002] Power semiconductor devices continue to evolve and are widely used in applications such as wireless communications, electronic products, and electric vehicles. However, devices capable of withstanding high power require high breakdown voltage, and even better devices need to possess high electron mobility and good thermal stability. Therefore, a new semiconductor structure and its fabrication method are needed to continue the development of this field. [Summary of the Invention]

[0003] This disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a semiconductor layer, a gate structure, a first dielectric layer, an etch stop layer, a second dielectric layer, and a field plate. The semiconductor layer is on the substrate. The gate structure is on the semiconductor layer. The first dielectric layer extends continuously on the gate structure and the semiconductor layer, and the first dielectric layer includes a first portion and a second portion. The etch stop layer is on at least a first portion of the first dielectric layer. The second dielectric layer is on the etch stop layer. The field plate includes a first field plate portion on the second dielectric layer and a second field plate portion on the second portion of the first dielectric layer, wherein the lower surface of the first field plate portion is a first distance from the semiconductor layer, and the lower surface of the second field plate portion is a second distance from the semiconductor layer, the first distance being greater than the second distance; the field plate has a first projection on the substrate in a direction perpendicular to the substrate; the gate structure has a second projection on the substrate in a direction perpendicular to the substrate; and the first projection does not cover the second projection.

[0004] This disclosure also provides a semiconductor structure. The semiconductor structure includes a substrate, a semiconductor layer, a gate structure, a first dielectric layer, an etch stop layer, a second dielectric layer, and a field plate. The semiconductor layer is on the substrate. The gate structure is on the semiconductor layer. The first dielectric layer extends continuously on the gate structure and the semiconductor layer, and includes a first portion, a second portion, and a third portion, the third portion being on the upper surface of the gate structure, and the second portion being closer to the third portion than the first portion. The etch stop layer is on at least a first portion of the first dielectric layer. The second dielectric layer is on the etch stop layer. The field plate includes a first field plate portion on a second dielectric layer and a second field plate portion and a third field plate portion on a second portion and a third portion of the first dielectric layer, respectively. The lower surface of the first field plate portion is a first distance from the semiconductor layer, and the lower surface of the second field plate portion is a second distance from the semiconductor layer. The first distance is greater than the second distance. The field plate has a first projection on the substrate in a direction perpendicular to the substrate. The gate structure has a second projection on the substrate in a direction perpendicular to the substrate. The first projection covers a portion of the second projection and exposes another portion of the second projection.

[0005] This disclosure also provides a method for forming a semiconductor structure. The method includes the following operations: forming a gate structure on a semiconductor layer disposed on a substrate; forming a first dielectric layer on the gate structure and the semiconductor layer; forming an etch stop layer on the first dielectric layer; forming a second dielectric layer on the etch stop layer, wherein the etch stop layer separates the second dielectric layer from the first dielectric layer; etching a portion of the second dielectric layer, such that the etch depth reaches at least to the upper surface of the etch stop layer to form an opening in the remaining portion of the second dielectric layer, wherein the gate structure is located in the opening; forming a field plate on the second dielectric layer and the opening, wherein the field plate has a first projection on the substrate in a direction perpendicular to the substrate, the gate structure has a second projection on the substrate in a direction perpendicular to the substrate, and the first projection either does not cover the second projection or the first projection covers a portion of the second projection and exposes another portion of the second projection.

Implementation Method

[0007] This disclosure provides a semiconductor structure, as shown in Figures 1A to 2C, wherein the semiconductor structure includes a substrate 101, a semiconductor layer 102, a gate structure 103, a first dielectric layer 104, an etch stop layer 105, a second dielectric layer 106, and a field plate 107. The semiconductor layer 102 is on the substrate 101. The gate structure 103 is on the semiconductor layer 102. The first dielectric layer 104 extends continuously on the gate structure 103 and the semiconductor layer 102, wherein the first dielectric layer 104 includes a first portion 104A, a second portion 104B, and a third portion 104C, the third portion 104C being on the upper surface of the gate structure 103, and the second portion 104B being closer to the third portion 104C than the first portion 104A. The etch stop layer 105 is on the first portion 104A of the first dielectric layer 104, and may also be on the second portion 104B and the third portion 104C of the first dielectric layer 104 (or on the remaining portion of the first dielectric layer 104 excluding the first portion 104A, as shown in Figures 1C and 2C). The second dielectric layer 106 is on the etch stop layer 105, wherein, in the direction perpendicular to the substrate 101, the projection of the second dielectric layer 106 onto the substrate 101 overlaps (or substantially completely overlaps) with the projection of the first portion 104A of the first dielectric layer 104 onto the substrate 101, but does not overlap with the projections of the second portion 104B and the third portion 104C of the first dielectric layer 104 (or with the remaining portion of the first dielectric layer 104 excluding the first portion 104A) onto the substrate 101. The field plate 107 includes a first field plate portion 107A on a second dielectric layer 106 on a first portion 104A of a first dielectric layer 104 and a second field plate portion 107B on a second portion 104B of a first dielectric layer 104, wherein the lower surface of the first field plate portion 107A is at a first distance D1 to the upper surface of the semiconductor layer 102, the lower surface of the second field plate portion 107B is at a second distance D2 to the upper surface of the semiconductor layer 102, and the first distance D1 is greater than the second distance D2. In some embodiments, the first distance D1 is preferably 500 Å to 5000 Å (e.g., 500 Å, 750 Å, 1000 Å, 2000 Å, 3000 Å, 4000 Å, or 5000 Å), and the second distance D2 is preferably 200 Å to 5000 Å (e.g., 200 Å, 500 Å, 1000 Å, 1500 Å, 2000 Å, 2500 Å, 3000 Å, or 3500 Å). In some embodiments, the field plate 107 further includes a third field plate portion 107C on the third portion 104C of the first dielectric layer 104, as shown in Figures 2A to 2C. In some embodiments, the lower surface of the third field plate portion 107C is at a third distance D3 to the upper surface of the semiconductor layer 102, and the third distance D3 is greater than the second distance D2.In some embodiments, the third distance D3 is preferably between 1800 Å and 6200 Å (e.g., 1800 Å, 2500 Å, 3000 Å, 4000 Å, 5000 Å, or 6200 Å). The field plate 107 of this disclosure enables the semiconductor structure to have a high breakdown voltage. Furthermore, in a direction perpendicular to the substrate 101, the field plate 107 has a first projection on the substrate 101, and the gate structure 103 has a second projection on the substrate 101. According to one embodiment of the invention, the first projection does not cover the second projection (as shown in Figures 1A to 1C). According to another embodiment of the invention, the first projection covers a portion of the second projection (as shown in Figures 2A to 2C). Therefore, the ratio of the charge between the gate and the source (Q gs) and the charge between the gate and the drain (Q gd) can be adjusted by the field plate 107 (the source and drain are not shown in this disclosure for the sake of simplification, but in fact the semiconductor structure also includes the source structure and drain structure on the semiconductor layer 102, and the gate structure 103 and the field plate 107 are located between the source structure and the drain structure).

[0008] The substrate 101 may be any feasible semiconductor substrate and may include any feasible semiconductor element, compound and / or alloy, such as C, Si, Ge, SiC, BN, AlN, GaN, GaP, GaAs, InP, InAs, InSb, ZnO, SiGe, AlGaAs, InGaAs, InGaP, AlInAs, GaAsP, AlGaN, InGaN, AlGaInP, the like, or combinations thereof. In some embodiments, the substrate 101 may also include any feasible active element (e.g., diode, etc.), passive element (e.g., resistor, capacitor, etc.), wire, the like, or combinations thereof, not shown in the figures.

[0009] Semiconductor layer 102 includes a channel layer 102C and a barrier layer 102B on the channel layer 102C. Channel layer 102C provides a carrier flow channel between the source and drain. Barrier layer 102B facilitates the formation of a carrier flow channel with high concentration, high electron mobility, and low resistance of a two-dimensional electron gas (2DEG) in channel layer 102C. In some embodiments, channel layer 102C comprises epitaxial gallium nitride. In some embodiments, barrier layer 102B comprises AlGaN.

[0010] The gate structure 103 controls the flow of carriers in the channel layer 102C. In some embodiments, the gate structure 103 includes a doped layer 103D and a metal layer 103M on the doped layer 103D. The doped layer 103D may be doped with an N-type dopant (e.g., C, Si, Ge, Sn, or the like) or a P-type dopant (e.g., Be, Mg, Ga, Sr, or the like) as required. For example, in some embodiments, the doped layer 103D includes GaN doped with an N-type dopant or a P-type dopant. The metal layer 103M may be any feasible electrode metal.

[0011] A first dielectric layer 104 extends continuously over the gate structure 103 and the semiconductor layer 102 to provide insulation. For clarity, the first dielectric layer 104 includes a first portion 104A, a second portion 104B, and a third portion 104C. The first portion 104A of the first dielectric layer 104 overlaps with the second dielectric layer 106 in the direction perpendicular to the substrate 101. In some embodiments, the first dielectric layer 104 is in direct contact with the semiconductor layer 102 and the gate structure 103. In some embodiments, the first dielectric layer 104 includes SiO2, Si3N4, SiON, or a combination thereof.

[0012] The etch stop layer 105 is located on the first dielectric layer 104 to act as an etch stop layer during the formation of the semiconductor structure, thereby more effectively controlling the etch depth. For example, etching can be stopped or paused upon contact with the etch stop layer 105 to ensure that the material to be etched away is removed completely and without residue, and to prevent over-etching of the material under the etch stop layer 105. In other words, the etch stop layer 105 helps to prevent unintended residues and / or defects in the semiconductor structure from affecting its operation. In some embodiments, the etch stop layer 105 includes AlN, Al₂O₃, SiN, or combinations thereof. In some embodiments, the thickness of the etch stop layer 105 is preferably from 20 Å to 100 Å, for example, 20 Å, 40 Å, 60 Å, 80 Å, or 100 Å.

[0013] The second dielectric layer 106 is on the first portion 104A of the first dielectric layer 104 but does not cover the second portion 104B and the third portion 104C of the first dielectric layer 104, and is perpendicularly separated from the first dielectric layer 104 by an etch stop layer 105. Since the second dielectric layer 106 does not cover the second portion 104B and the third portion 104C of the first dielectric layer 104, there is a stepped shape between the first dielectric layer 104 and the second dielectric layer 106. Moreover, since there is an etch stop layer 105 between the first dielectric layer 104 and the second dielectric layer 106, when forming the stepped shape of the first dielectric layer 104 and the second dielectric layer 106, the etching of the second dielectric layer 106 can be stopped or paused at the etch stop layer 105, so that the height of the stepped shape can be more in line with expectations (see the method below for details). In some embodiments, the second dielectric layer 106 includes SiO2, Si3N4, SiON or a combination thereof.

[0014] The field plate 107 is formed on the stepped shape of the first dielectric layer 104 and the second dielectric layer 106. The field plate 107 can redistribute the electric field peaks of the 2DEG drift region and the edge of the gate structure 103 located below the first portion 104A and the second portion 104B of the first dielectric layer 104 and in the vertical direction of the substrate 101, thus avoiding excessively high electric field peaks that could cause breakdown voltage (i.e., the semiconductor structure of this disclosure can have a high breakdown voltage). Furthermore, since the field plate 107 has a stepped shape, the electric field distribution at the edge of the gate structure 103 can be gradually redistributed, thereby significantly improving the breakdown voltage of the semiconductor structure. Therefore, this disclosure does not require increasing the distance between the gate structure 103 and the source structure and / or drain structure to increase the breakdown voltage of the semiconductor structure. In some embodiments, the field plate 107 includes TiN, Ti, AlCu, Al, AlSi, or combinations thereof.

[0015] In some embodiments, the field plate 107 extends continuously over the first dielectric layer 104 and the second dielectric layer 106. In some embodiments, the field plate 107 has a substantially uniform thickness, so that the upper and lower surfaces of the field plate 107 have a stepped shape conformal to and / or similar to the stepped shape of the first dielectric layer 104 and the second dielectric layer 106. In some embodiments, the field plate 107 is separated from the gate structure 103 and the semiconductor layer 102 by the first dielectric layer 104. In some embodiments, the lower surface of the first field plate portion 107A is higher than the upper surface of the gate structure 103, and the lower surface of the second field plate portion 107B is lower than the upper surface of the gate structure 103. In some embodiments, the lower surface of the third field plate portion 107C is higher than the upper surface of the gate structure 103. In some embodiments, the upper surface of the second field plate portion 107B is lower than the upper surface of the first field plate portion 107A and, in some embodiments, the upper surface of the third field plate portion 107C. In some embodiments, when the etch stop layer 105, as shown in Figures 1A and 2A, does not cover the remaining portion of the first dielectric layer 104 other than the first portion 104A, the field plate 107 is in direct contact with the remaining portion of the first dielectric layer 104 (including the second portion 104B and the third portion 104C). In some embodiments, the first field plate portion 107A is further away from the gate structure 103 than the second field plate portion 107B and, in some embodiments, the third field plate portion 107C.

[0016] In some embodiments, as shown by the dashed lines in Figures 1A and 2A, the upper surface S2 of the second portion 104B and the third portion 104C of the first dielectric layer 104 may be lower than the upper surface S1 of the first portion 104A of the first dielectric layer 104. Therefore, the height difference between the field plate 107 on the first dielectric layer 104 and the second dielectric layer 106 can be adjusted more precisely, thereby accurately controlling the electric field distribution under the field plate 107. In these embodiments, the etch stop layer 105 only covers the first portion 104A of the first dielectric layer 104.

[0017] In some embodiments, as shown in Figures 1B and 2B, the semiconductor structure may further include a third dielectric layer 108 situated on the first dielectric layer 104 and the second dielectric layer 106, with the field plate 107 described above situated on the third dielectric layer 108. When the semiconductor structure further includes a third dielectric layer 108, the height of the field plate 107 can be adjusted more precisely, thereby allowing for more precise control of the electric field distribution beneath the field plate 107. In some embodiments, the third dielectric layer 108 continuously covers the first dielectric layer 104 and the second dielectric layer 106 to provide a more continuous and flat surface to the field plate 107 situated thereon. In some embodiments, the third dielectric layer 108 has a substantially uniform thickness. In some embodiments, the third dielectric layer 108 is not limited to the number shown in the figures and may include a single or multiple layers. In some embodiments, the third dielectric layer 108 includes a high dielectric constant material (such as HfO2), SiO2, Si3N4, SiON, or a combination thereof.

[0018] This disclosure also provides a method for forming the above-described semiconductor structure. The method includes the following operations: forming a gate structure 103 on a semiconductor layer 102 located on a substrate 101; forming a first dielectric layer 104 on the gate structure 103 and the semiconductor layer 102; forming an etch stop layer 105 on the first dielectric layer 104; forming a second dielectric layer 106 on the etch stop layer 105, wherein the etch stop layer 105 separates the second dielectric layer 106 from the first dielectric layer 104; etching a portion of the second dielectric layer 106, such that the etch depth at least reaches the upper surface of the etch stop layer 105, so as to... An opening 106O is formed in the remaining portion of the second dielectric layer 106, wherein the gate structure 103 is located in the opening 106O; and a field plate 107 is formed on the second dielectric layer 106 and the opening 106O, wherein the field plate 107 has a first projection on the substrate 101 in a direction perpendicular to the substrate 101, the gate structure 103 has a second projection on the substrate 101 in a direction perpendicular to the substrate 101, and the first projection either does not cover the second projection or covers a portion of the second projection and exposes another portion of the second projection.

[0019] First, referring to Figure 3, a gate structure 103 is formed on a semiconductor layer 102 located on a substrate 101, and a first dielectric layer 104, an etch stop layer 105, and a second dielectric layer 106 are subsequently formed sequentially on the gate structure 103 and the semiconductor layer 102. The method for forming the gate structure 103, the first dielectric layer 104, the etch stop layer 105, and the second dielectric layer 106 may include any feasible method, such as chemical vapor deposition. In some embodiments, the method further includes forming a source structure and a drain structure on the semiconductor layer 102 before forming the first dielectric layer 104, the etch stop layer 105, and the second dielectric layer 106.

[0020] Next, a photoresist layer 109 is formed on the second dielectric layer 106, making the photoresist layer 109 serve as the second dielectric layer 106 for masking the etched portion, thus forming the second dielectric layer 106 as shown in Figure 4. By patterning the second dielectric layer 106 with the photoresist layer 109, the first dielectric layer 104 and the patterned second dielectric layer 106 form a stepped shape, thereby forming the field plate 107 on this stepped shape and correspondingly having a stepped shape. In detail, the photoresist layer 109 overlaps with the first portion 104A of the first dielectric layer 104, and the opening 109O of the photoresist layer 109 overlaps with the remaining portion of the first dielectric layer 104 (including the second portion 104B and the third portion 104C) excluding the first portion 104A. The portion of the second dielectric layer 106 exposed by the opening 109O of the photoresist layer 109 can be etched using any feasible etching method, such that the patterned second dielectric layer 106 has an opening 106O exposing the remaining portion of the first dielectric layer 104, excluding the first portion 104A (including the second portion 104B and the third portion 104C). In some embodiments, feasible etching methods include wet etching (e.g., using etchant HF, buffered oxide etchant (BOE), H3PO4, or combinations thereof) or dry etching (e.g., using etching plasma gas Cl2; a combination of HCl and Cl2; a combination of BCl3 and SF6; a combination of S2F2 and C2F6; C3F8; C4F8; C5F8; C4F6, NF3, CHF3, CH2F2, CH3F, SiF4, C3F8, and CCl2F2; or combinations thereof). In some embodiments, the etching depth reaches at least the upper surface of the etch stop layer 105 to ensure that a portion of the exposed second dielectric layer 106 is completely removed. The etch stop layer 105 also prevents the first dielectric layer 104 from being unintentionally over-etched. In some embodiments, etching can continue after contacting the etch stop layer 105 and stopping to remove the etch stop layer 105 in the opening 106O. In some embodiments, after etching the etch stop layer 105 in the opening 106O, etching can continue to the upper portion of the first dielectric layer 104 below the opening 106O, i.e., the remaining portion (e.g., the second portion 104B and the third portion 104C) excluding the first portion 104A, such that the upper surface of the remaining lower portion of the second portion 104B of the first dielectric layer 104 in the opening 106O is lower than the upper surface of the first portion 104A of the first dielectric layer 104 located below the second dielectric layer 106 outside the opening 106O.In some embodiments, the thickness of the upper portion of the second portion 104B prior to etching is preferably 50 Å to 500 Å (e.g., 50 Å, 100 Å, 200 Å, 300 Å, 400 Å, or 500 Å), and the thickness of the remaining lower portion of the second portion 104B after etching is preferably 150 Å to 3400 Å (e.g., 150 Å, 500 Å, 1000 Å, 2000 Å, 3000 Å, or 3400 Å). In some embodiments, etching the etch stop layer 105 is performed by a wet etching process (e.g., using a diluted HF, BOE, or combination thereof etchant), and etching the first dielectric layer 104 is performed by a dry etching process. In some embodiments, etching the etch stop layer 105 and the first dielectric layer 104 is performed by a single, continuous wet etching process (e.g., using a diluted HF, BOE, or combination thereof etchant).

[0021] Next, a field plate 107 is formed on the second dielectric layer 106 and the opening 106O to form a semiconductor structure as shown in Figures 1A, 1C, 2B, or 2C; or in some embodiments, a third dielectric layer 108 is conformally formed on the second dielectric layer 106 and the opening 106O, and then the field plate 107 is formed on the third dielectric layer 108 to form a semiconductor structure as shown in Figures 1B or 2B. In some embodiments, when the implementation includes forming the third dielectric layer 108, the first dielectric layer 104 may not be etched, so the upper surface of the second portion 104B of the first dielectric layer 104 is substantially flush with the upper surface of the first portion 104A of the first dielectric layer 104. In some embodiments, forming the field plate 107 includes depositing a field plate material that extends continuously on the first dielectric layer 104 and the second dielectric layer 106, and etching the edge portions of the field plate material to form the field plate 107. In some embodiments, the field plate material can be patterned to form the field plate 107 as shown in Figures 1A to 2C by using another photoresist layer (not shown) formed on the field plate material as a mask.

[0022] The semiconductor structure disclosed herein and the semiconductor structure formed by the method disclosed herein have high breakdown voltage to reduce leakage current. Furthermore, the semiconductor structure has high electron mobility and good thermal stability. The semiconductor structure disclosed herein can be used not only in high electron mobility transistors (HEMTs) but also in high-power semiconductor devices. The stepped shape of the first and second dielectric layers formed by the etch stop layer located between the first and second dielectric layers makes the height of the stepped shape more consistent with expectations and reduces unwanted etch residues remaining on the stepped shape. The field plate disclosed herein can have a more consistent height difference along the stepped shape to significantly increase the breakdown voltage and precisely adjust the charge distribution. The height difference of the stepped shape can also be further adjusted by adding a third dielectric layer or the upper part of the etched portion of the first dielectric layer. The continuously extending field plates with height differences disclosed herein can be formed by a single patterning process, thus simplifying the process, improving process efficiency, and avoiding damage to the field plates caused by forming field plates of different heights in multiple steps. [Simplified Explanation of the Diagram]

[0006] When reading the drawings of this disclosure, it is recommended to understand the various aspects of this disclosure from the following text. In accordance with industry standard practice, various feature dimensions may not be drawn to scale. Furthermore, to simplify the drawings, conventional structures and components will be shown in a simple schematic manner. Figures 1A to 1C are schematic diagrams of semiconductor structures according to some embodiments of this disclosure. Figures 2A to 2C are schematic diagrams of semiconductor structures according to other embodiments of this disclosure. Figures 3 and 4 are schematic structural diagrams of intermediate processes in a method for forming a semiconductor structure according to some embodiments of this disclosure.

Claims

1. A semiconductor structure, comprising: One substrate; A semiconductor layer is on the substrate; a gate structure is on the semiconductor layer; a first dielectric layer extends continuously on the gate structure and the semiconductor layer, the first dielectric layer including a first portion and a second portion; an etch stop layer is on at least the first portion of the first dielectric layer; a second dielectric layer is on the etch stop layer; a third dielectric layer is on the first dielectric layer and the second dielectric layer; and a field plate is on the third dielectric layer and includes a first field plate portion on the second dielectric layer and a second field plate portion on the second portion of the first dielectric layer, wherein a lower surface of the first field plate portion is a first distance from the semiconductor layer, a lower surface of the second field plate portion is a second distance from the semiconductor layer, the first distance is greater than the second distance, the field plate has a first projection on the substrate in a vertical direction along the substrate, the gate structure has a second projection on the substrate in the vertical direction along the substrate, and the first projection does not cover the second projection.

2. The semiconductor structure as claimed in claim 1, wherein the field plate extends continuously over the first dielectric layer and the second dielectric layer.

3. The semiconductor structure as claimed in claim 1, wherein an upper surface of the second portion of the first dielectric layer is lower than an upper surface of the first portion of the first dielectric layer.

4. A semiconductor structure, comprising: One substrate; A semiconductor layer is on the substrate; A gate structure is on the semiconductor layer; a first dielectric layer extends continuously on the gate structure and the semiconductor layer, the first dielectric layer including a first portion, a second portion and a third portion, the third portion being on an upper surface of the gate structure, and the second portion being closer to the third portion than the first portion; an etch stop layer is on at least the first portion of the first dielectric layer; a second dielectric layer is on the etch stop layer; A field plate includes a first field plate portion on the second dielectric layer and a second field plate portion and a third field plate portion on the second and third portions of the first dielectric layer, respectively. A lower surface of the first field plate portion is a first distance from the semiconductor layer, and a lower surface of the second field plate portion is a second distance from the semiconductor layer. The first distance is greater than the second distance. The field plate has a first projection on the substrate in a vertical direction along the substrate. The gate structure has a second projection on the substrate in the vertical direction along the substrate. The first projection covers a portion of the second projection and exposes another portion of the second projection. A third dielectric layer is on the first and second dielectric layers, and the field plate is on the third dielectric layer.

5. The semiconductor structure as claimed in claim 4, wherein, in the vertical direction along the substrate, a projection of the second dielectric layer on the substrate overlaps with a projection of the first portion of the first dielectric layer on the substrate, and the projection of the second dielectric layer on the substrate does not overlap with a projection of the second portion and the third portion of the first dielectric layer on the substrate.

6. The semiconductor structure as described in any one of claims 4 to 5, wherein a lower surface of the third field plate portion is at a third distance from the semiconductor layer, and the third distance is greater than the second distance.

7. A method for forming a semiconductor structure, comprising: A gate structure is formed on a semiconductor layer located on a substrate; A first dielectric layer is formed on the gate structure and the semiconductor layer; An etch stop layer is formed on the first dielectric layer; a second dielectric layer is formed on the etch stop layer, wherein the etch stop layer separates the second dielectric layer from the first dielectric layer; a portion of the second dielectric layer is etched, and an etch depth is made to at least reach an upper surface of the etch stop layer to form an opening in a remaining portion of the second dielectric layer, wherein the gate structure is located in the opening; The method further includes forming a field plate on the second dielectric layer and the opening, wherein the field plate has a first projection on the substrate in a vertical direction along the substrate, the gate structure has a second projection on the substrate in the vertical direction along the substrate, the first projection does not cover the second projection or the first projection covers a portion of the second projection and exposes another portion of the second projection, and when the first projection covers the portion of the second projection and exposes the other portion of the second projection: the method further includes etching a portion of the first dielectric layer below the opening such that an upper surface of the portion of the first dielectric layer below the opening is lower than an upper surface of the portion of the first dielectric layer located below the second dielectric layer; or the method further includes conformally forming a third dielectric layer on the second dielectric layer and the opening before forming the field plate.

8. The method of claim 7, wherein when the first projection does not cover the second projection, the method further comprises etching a portion of the first dielectric layer below the opening such that an upper surface of the portion of the first dielectric layer below the opening is lower than an upper surface of the portion of the first dielectric layer located below the second dielectric layer.

9. The method as claimed in claim 7, wherein when the first projection does not cover the second projection, the method further includes conformally forming a third dielectric layer on the second dielectric layer and the opening before forming the field plate.

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