Conductive pad on a through-silicon via

Abstract

This invention provides a semiconductor device. The semiconductor device includes a substrate having a front side and a back side opposite the front side. A via extends completely through the substrate. The via includes a protrusion extending beyond the back side of the substrate. A silicon carbide layer is disposed on the back side of the substrate along the sidewall of the protrusion of the via. An oxide layer is disposed on the back side of the substrate and at least partially surrounds the protrusion of the via. A conductive pad is disposed at a coupling surface of the via and at least partially extends through the oxide layer. Therefore, a reliable and cost-effective semiconductor device can be assembled.

Description

Technical Field

[0001] The present invention relates broadly to semiconductor device assemblies, and more specifically to a conductive pad on a through-silicon via (TSV). Prior Technology

[0002] Microelectronic devices generally have a die (e.g., a chip) containing integrated circuitry with a high density of extremely small components. Typically, the die includes an array of bonding pads electrically coupled to the integrated circuitry. The bonding pads are external electrical contacts through which power supply voltages, signals, etc., are transmitted to and from the integrated circuitry. After die formation, it is "encapsulated" to couple the bonding pads to a larger array of electrical terminals that can be more easily coupled to various power lines, signal lines, and ground lines. Conventional procedures for encapsulating a die include electrically coupling the bonding pads on the die to an array of leads, ball pads, or other types of electrical terminals, and encapsulating the die to protect it from environmental factors (e.g., moisture, particles, static electricity, and physical impacts). Simple diagram description

[0003] Figure 1 shows a simplified schematic cross-sectional view of one of the semiconductor device assemblies.

[0004] Figure 2 illustrates a simplified schematic cross-sectional view of a semiconductor device assembly according to one embodiment of the present technology.

[0005] Figures 3 to 6 illustrate simplified schematic cross-sectional views of a series of steps for manufacturing a semiconductor device assembly according to one embodiment of the present technology.

[0006] Figure 7 illustrates a schematic diagram of a system comprising a semiconductor device assembly configured according to one embodiment of the present technology.

[0007] Figure 8 illustrates a method for manufacturing a semiconductor device assembly according to one embodiment of the present technology. Implementation Method

[0008] Semiconductor devices are integrated into numerous devices to implement memory cells, processor circuits, imaging devices, and other functional features. As more applications for semiconductor devices are discovered, the designer's task is to create improved devices that can perform more operations per second, store larger amounts of data, or operate at a higher level of security. To accomplish this, designers continuously develop new technologies to increase the number of circuit elements on a semiconductor device without simultaneously increasing its size. However, this development may not be sustainable due to the various challenges arising from designing semiconductor devices with high circuit density. Therefore, additional technologies may be needed to continue the growth of semiconductor device capabilities.

[0009] One technique of this technology is to implement multiple circuit components within a single package. For example, stacked semiconductor devices can stack multiple semiconductor dies on top of each other to increase the number of circuit elements within a package without increasing its footprint. In some cases, individual semiconductor dies can be stacked on top of each other to create a vertical stack of semiconductor dies. The semiconductor die may include a through-silicon via (TSV) extending between a front side (e.g., the active side where the circuitry is located) and a back side opposite the front side. Contact pads may be disposed on the back side of the semiconductor die to contact an exposed portion of the TSV so that an additional semiconductor die can be electrically coupled there. Various techniques exist for placing contact pads at the TSV; however, some of these techniques may be too time-consuming or result in semiconductor devices with reliability or cost issues. An exemplary semiconductor device is shown in Figure 1.

[0010] Figure 1 illustrates a semiconductor device assembly 100 including a semiconductor die 102. The semiconductor die 102 can be assembled onto a carrier wafer to enable the semiconductor die 102 to withstand processing. The semiconductor die 102 includes a substrate 104 (e.g., a silicon substrate, an organic substrate, a printed circuit board (PCB) core, etc.), the substrate 104 having a metallization layer 106 (e.g., having connection circuitry, such as traces, lines, and vias) on a front side. A TSV 108 extends completely through the substrate 104 from the front side to a back side opposite the front side. A contact pad 110 can be disposed on a coupling surface 112 of the TSV 108 exposed on the back side of the substrate 104. The contact pad 110 can be disposed within an oxide layer 114 (e.g., high-temperature silicon oxide deposited at a temperature above 300, 400, 500, or 700 degrees Celsius).

[0011] Various techniques can be used to mount the contact pads 110 of the TSV 108. For example, initially, the TSV 108 may protrude beyond the back side of the substrate 104 (e.g., by more than 3 micrometers). A silicon nitride layer 116 (e.g., low-temperature silicon nitride deposited at a temperature below 200, 300, or 400 degrees Celsius) may be mounted on the back side of the substrate, along the sidewalls of the TSV 108, and above the top of the TSV 108. In some cases, the silicon nitride layer is mounted with a thickness greater than 1 micrometer. Next, an oxide layer (not shown) (such as a low-temperature oxide) may be deposited on the back side of the semiconductor die 102 above the silicon nitride layer 116. The oxide layer may be mounted with a thickness of about 0.5 micrometers (e.g., within 0.1 micrometers, within 0.2 micrometers, etc.). The TSV 108 may then be exposed by removing material from the back side of the semiconductor die 102 through chemical mechanical planarization (CMP). For example, the oxide layer can be completely removed, and the silicon nitride layer 116 can be thinned to approximately 1 micrometer (e.g., within 0.1 micrometer, within 0.2 micrometer, within 0.5 micrometer, etc.). In this way, one back side of the semiconductor die 102 can correspond to a planarized silicon nitride layer 116, wherein the coupling surface 112 of the TSV 108 is exposed.

[0012] Next, a silicon carbon nitride layer 118 (e.g., a high-temperature silicon carbon nitride) can be disposed over the silicon nitride layer 116 and the coupling surface 112 of the TSV 108. An oxide layer 114 can be disposed on the back side of the semiconductor die 102 over the silicon carbon nitride layer 118. Next, an additional silicon carbon nitride layer 120 (e.g., high-temperature silicon carbon nitride) can be disposed over the oxide layer 114. The silicon carbon nitride layer 118, oxide layer 114, and silicon carbon nitride layer 120 can be etched (e.g., dry etched) to expose the coupling surface 112 of the TSV 108. Next, a contact pad 110 can be disposed in the opening at the coupling surface 112, such that the contact pad 110 is exposed on the back side of the semiconductor die 102. In this way, an additional semiconductor die can be stacked on the semiconductor die 102 and electrically coupled to the contact pad 110.

[0013] For many reasons, using such techniques to mount a contact pad on a TSV can be suboptimal. As discussed above, the process can involve multiple deposition steps to mount individual layers on the back side of the semiconductor die 102 (e.g., silicon nitride layer 116 or an oxide layer that is later removed). Therefore, implementing the design process can require significant time and material costs. Furthermore, the coupling surface 112 of the TSV 108 can be exposed by CMP, which may result in smearing of conductive material within the TSV 108 across the back side of the semiconductor die 102 or breakage of the semiconductor die 102. In this way, the use of CMP can reduce the reliability or yield of the semiconductor die 102. In another embodiment, the use of CMP in regions containing and excluding the TSV 108 may create morphologies (e.g., height differences of up to 200 nanometers) on the back surface of the semiconductor die 102. The morphology may result from a region containing TSV 108 being more resistant to CMP tendencies than a region without TSV 108. In some cases, this morphology can introduce weaknesses in the semiconductor die 102 or make it difficult to stack additional semiconductor dies on the semiconductor die 102. In some cases, the morphology can reduce the reliability of the metal-metal bonding at the TSV 108 (e.g., due to DC resistance yield). Therefore, designing semiconductor devices using these techniques may result in semiconductor devices with reliability issues or require excessive cost or manufacturing time.

[0014] To address these and other drawbacks, various embodiments of the present technology provide a semiconductor device assembly including a contact pad disposed at a TSV. The semiconductor device includes a substrate having a front side and a back side opposite the front side. A via extends completely through the substrate. The via includes a protrusion extending beyond the back side of the substrate. A silicon carbide nitride layer is disposed on the back side of the substrate and along the sidewall of the protrusion of the via. An oxide layer is disposed on the back side of the substrate and at least partially surrounds the protrusion of the via. A conductive pad is disposed at a coupling surface of the via and at least partially extends through the oxide layer. Therefore, a reliable and cost-effective semiconductor device can be assembled, an example of which is shown in FIG. 2.

[0015] Figure 2 illustrates a semiconductor device assembly 200 including a semiconductor die 202. The semiconductor die 202 can be assembled onto a carrier wafer to enable the semiconductor die 202 to withstand processing. The semiconductor die 202 includes a substrate 204 having a metallization layer 206 (e.g., having connection circuitry, such as traces, lines, and vias) on a front side. A TSV 208 extends completely through the substrate 204 from the front side to a back side opposite the front side. A contact pad 210 can be disposed on a coupling surface 212 of the TSV 208. The contact pad 210 can be disposed within an oxide layer 214 (e.g., a high-temperature silicon oxide) and exposed on the back side of the semiconductor die 202. A silicon carbide layer 216 (e.g., high-temperature silicon carbide) may be disposed on the back side of the substrate 204, and a silicon carbide layer 218 may be disposed opposite to the oxide layer 214.

[0016] Contrary to the semiconductor device assembly 100 shown in Figure 1, the TSV 208 may have a protrusion 220 extending beyond the back side of the substrate 204. For example, the protrusion 220 may extend beyond the back side of the substrate 204 by more than 1 micrometer, more than 2 micrometers, more than 3 micrometers, more than 4 micrometers, or more than 5 micrometers. A silicon carbide layer 216 may be disposed on the back side of the substrate 204, extending along the sidewall 222 of the protrusion 220 of the TSV 208, and extending above a portion of the coupling surface 212. In this way, the silicon carbide layer 216 may conform to the shape of the protrusion 220 of the TSV 208. In some cases, the silicon carbide layer 216 may be about 0.15 micrometers thick (e.g., within 0.01 micrometers, within 0.05 micrometers, within 0.1 micrometers, etc.). As illustrated, the silicon carbide layer 216 may be in direct contact with the substrate 204 (e.g., on the back side). For example, the silicon carbide layer 216 and the substrate 204 may not be separated by another material (e.g., silicon carbide layer 116 of FIG1).

[0017] Contact pad 210 may be disposed on the back side of semiconductor die 202 on a coupling surface 212 of TSV 208. In some cases, contact pad 210 may be smaller than the coupling surface 212 of TSV 208, such that contact pad 210 contacts only a portion of coupling surface 212. For example, the cross-sectional area of ​​contact pad 210 in a plane coplanar with coupling surface 212 may be smaller than the area of ​​coupling surface 212. One surface of contact pad 210 may be disposed on the back side of semiconductor die 202 to allow an additional semiconductor die to be stacked on semiconductor die 202 and electrically coupled to semiconductor die 202 at contact pad 210.

[0018] Although illustrated and described as a semiconductor die, semiconductor die 202 can be replaced by a wafer (e.g., a semiconductor wafer) that implements multiple semiconductor dies. For example, substrate 204 can be replaced by a wafer-level or panel-level substrate for implementing multiple semiconductor dies. Furthermore, although described as a TSV, TSV 208 can generally refer to a substrate via. Thus, TSV 208 can be implemented through a non-silicon substrate (e.g., an organic substrate or other semiconductor substrate). In another embodiment, although described with reference to a particular material, other materials can be used to form the various layers of semiconductor die 202. In this way, oxide layer 214, silicon carbon nitride layer 216, or silicon carbon nitride layer 218 can alternatively contain any other material, such as a different dielectric material (e.g., silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, or the like).

[0019] The present invention now turns to a series of steps for manufacturing a semiconductor device assembly according to embodiments of the present technology. Specifically, Figures 3 to 6 illustrate simplified schematic cross-sectional views of a series of steps for manufacturing a semiconductor device assembly according to one embodiment of the present technology. For ease of description, the steps are illustrated with respect to a particular embodiment. However, these steps may be performed according to other embodiments to manufacture a semiconductor device assembly.

[0020] Starting with Figure 3, at stage 300, a simplified schematic cross-sectional view of a semiconductor device assembly is shown. The semiconductor device assembly includes a semiconductor die 202 assembled onto a carrier substrate. The semiconductor die 202 may be disposed face down and adhered (e.g., via an adhesive or a dielectric material) to the carrier substrate, such that one front side of the semiconductor die 202 faces the carrier substrate. The semiconductor die 202 may be implemented at a substrate 204. A metallization layer 206, including traces, lines, vias, and other interconnect structures, may be disposed on the front side of the semiconductor die 202. A TSV 208 extends completely through the substrate 204 from the metallization layer 206. A protrusion 220 of the TSV 208 extends beyond the back side of the substrate 204. For example, the protrusion 220 of the TSV 208 may extend beyond the back side of the substrate 204 by an amount greater than 1 micrometer, greater than 2 micrometers, greater than 3 micrometers, greater than 4 micrometers, greater than 5 micrometers, etc.

[0021] Figure 4 illustrates a simplified schematic cross-sectional view of stage 400, wherein passivation material is disposed around a protrusion 220 of TSV 208 on the back side of substrate 204. A coupling surface 212 of TSV 208 may be exposed at a distal portion of the protrusion 220 of TSV 208. In this configuration, the protrusion 220 is not planarized down to be substantially coplanar with the back side of substrate 204 (e.g., within 0.5 μm, within 1 μm, within 2 μm, within 5 μm, etc.). Therefore, the back side of substrate 204 may have a morphology of less than 200 nm, less than 100 nm, or less than 50 nm. Instead of planarizing down to the back side of substrate 204, a silicon carbon nitride layer 216 may be deposited on the back side of substrate 204 (e.g., in direct contact with the back side of substrate 204) and around the protrusion 220 of TSV 208. For example, a silicon carbide nitride layer 216 may be disposed on the back side of the substrate 204, along the sidewall 222 of the protrusion 220, and above the coupling surface 212. The silicon carbide nitride layer 216 may comprise a high-temperature silicon carbide nitride deposited at a temperature above 300, 400, 500, or 700 degrees Celsius. The silicon carbide nitride layer 216 may be disposed with a thickness of about 0.15 micrometers (e.g., within 0.01 micrometers, within 0.05 micrometers, within 1 micrometer, etc.).

[0022] An oxide layer 214 (e.g., high-temperature silicon oxide) may be disposed at least partially around the protrusion 220. For example, the oxide layer 214 may be deposited such that it extends more than 1 micrometer above the protrusion 220. The oxide layer 214 may be disposed over a silicon carbon nitride layer 216 such that the silicon carbon nitride layer 216 separates the substrate 204 and the TSV 208 from the oxide layer 214. Subsequently, an additional silicon carbon nitride layer 218 may be disposed over the oxide layer 214 opposite to the silicon carbon nitride layer 216 (e.g., opposite to the substrate 204).

[0023] Figure 5 illustrates a simplified schematic cross-sectional view of a stage 500, in which a contact pad 210 is disposed at the coupling surface 212 of the TSV 208 such that the contact pad 210 is electrically coupled to the TSV 208. Portions of the oxide layer 214, silicon carbide layer 216, and silicon carbide layer 218 can be removed to expose the coupling surface 212 of the TSV 208. For example, the material can be removed by etching. Then, conductive material can be disposed in the opening to implement the contact pad 210. The contact pad 210 can be smaller than the coupling surface 212 of the TSV 208. In this way, the silicon carbide layer 216 can still cover a portion of the coupling surface 212 of the TSV 208. In this example, CMP is not used to expose the coupling surface 212 of the TSV 208. Therefore, the risk of contamination from the TSV 208 or breakage of the semiconductor die 202 can be eliminated. In another embodiment, the TSV 208 is not planarized down to the substrate, allowing for the removal of passivation material deposited on the substrate 204 (e.g., the low-temperature oxide layer removed by CMP during the fabrication of the semiconductor device assembly as described in FIG1) or the planarization step of the TSV 208, thereby simplifying the process and reducing the overall cost of manufacturing the semiconductor device assembly. Next, an additional semiconductor die can be stacked onto the semiconductor die 202, and the stacked semiconductor dies can be packaged into a packaged semiconductor device, an example of which is shown in FIG6.

[0024] Figure 6 illustrates a simplified schematic cross-sectional view of a semiconductor device assembly at stage 600. The semiconductor device assembly 600 includes stacked semiconductor dies 602. One or more of the stacked semiconductor dies 602 may include TSVs having contact pads disposed thereon. Thus, interconnects (e.g., metal-to-metal interconnects) of the electrically coupled semiconductor dies 602 may be formed between the respective contact pads on the respective dies of the stacked semiconductor dies 602. The stacked semiconductor dies 602 may be assembled onto a package-grade substrate 604 via conductive structures 606 (e.g., conductive pillars, solder joints, etc.). For example, a contact pad at the base die of one of the stacked semiconductor dies 602 may be electrically coupled to a contact pad (not shown) on the upper surface of one of the package-grade substrates 604 via conductive structures 606. The package-grade substrate 604 may include internal circuitry (traces, wires, vias, and other connection structures) that connects the contact pads on the upper surface to contact pads (not shown) on the lower surface. Conductive structure 608 may provide external connectivity (e.g., power, ground, input / output (I / O) communication, or the like) to stacked semiconductor die 602 via contact pads disposed on the lower surface. An underfill material 610 (e.g., capillary underfill) may be disposed around conductive structure 606 to electrically insulate such structure and mechanically support semiconductor device assembly 600. An encapsulant 612 (e.g., molding resin) may be disposed at least partially around stacked semiconductor die 602 and package-level substrate 604 to protect semiconductor device assembly 600 and prevent electrical contact therewith.

[0025] Although the semiconductor device assembly has been illustrated and described in the foregoing example embodiments as comprising a specific configuration of semiconductor dies, in other embodiments the assembly may have different configurations of semiconductor dies. For example, with appropriate modifications, the semiconductor device assembly illustrated in any of the foregoing examples may be implemented using a vertically stacked semiconductor die (e.g., according to the High Bandwidth Memory (HBM) protocol), a stack of multiple semiconductor dies, a plurality of semiconductor dies, or a single semiconductor die.

[0026] According to one embodiment of the present invention, the semiconductor device illustrated in the assemblies of Figures 1 to 6 may include memory chips, such as dynamic random access memory (DRAM) chips, not-AND (NAND) memory chips, not-OR (NOR) memory chips, magnetic random access memory (MRAM) chips, phase-change memory (PCM) chips, ferroelectric random access memory (FeRAM) chips, static random access memory (SRAM) chips, or the like. In one embodiment where multiple chips are provided in a single assembly, the semiconductor device may include a memory chip of the same type (e.g., two NAND, two DRAM, etc.) or memory chips of different types (e.g., one DRAM and one NAND, etc.). According to another aspect of the present invention, the semiconductor die of the assembly illustrated and described above may be a logic die (e.g., a controller die, a processor die, etc.), or a combination of logic and memory dies (e.g., a memory controller die and a memory die controlled by it).

[0027] Any of the semiconductor devices and semiconductor device assemblies described above with respect to Figures 1 through 6 can be incorporated into any of a multitude of larger and / or more complex systems, a representative example of which is system 700 schematically shown in Figure 7. System 700 may include a semiconductor device assembly 702 (e.g., a discrete semiconductor device), a power supply 704, a driver 706, a processor 708, and / or other subsystems or components 710. Semiconductor device assembly 702 may include features substantially similar to those of the semiconductor device assemblies described above with respect to Figures 1 through 6. The resulting system 700 can perform any of a variety of functions, such as memory storage, data processing, and / or other suitable functions. Therefore, representative system 700 may include, but is not limited to, handheld devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, vehicles, home appliances, and other products. The components of system 700 may be housed in a single unit or distributed across multiple interconnected units (e.g., via a communication network). The components of system 700 may also include remote devices and any of a variety of computer-readable media.

[0028] Figure 8 illustrates an exemplary method 800 for manufacturing a semiconductor device assembly according to one embodiment of the present technology. Although illustrated in a specific configuration, one or more operations of method 800 may be omitted, repeated, or rearranged. Additionally, method 800 may include other operations not illustrated in Figure 8, such as those detailed in one or more other methods described herein.

[0029] At 802, a substrate is provided. The substrate may include a front side, a back side opposite the front side, and a through-hole extending completely through the substrate and having a protrusion extending beyond the back side of the substrate. At 804, a silicon carbide layer is disposed on the back side of the substrate and surrounds the protrusion of the through-hole. At 806, an oxide layer is disposed on the back side of the substrate and at least partially surrounds the protrusion of the through-hole. At 808, the oxide layer and the silicon carbide layer are etched to expose a coupling surface of the through-hole. At 810, a conductive pad is disposed on the coupling surface of the through-hole and at least partially extends through the oxide layer.

[0030] The foregoing describes specific details of several embodiments of semiconductor devices and associated systems and methods. Depending on the context in which it is used, the term "substrate" may refer to a wafer-level substrate or a single-chip-level substrate. Furthermore, unless the context otherwise indicates, the structures disclosed herein can be formed using known semiconductor manufacturing techniques. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and / or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, CMP, or other suitable techniques.

[0031] The technologies disclosed herein relate to semiconductor devices, systems having semiconductor devices, and related methods for manufacturing semiconductor devices. The term "semiconductor device" generally refers to a solid-state device comprising one or more semiconductor materials. Examples of semiconductor devices include, in particular, logic devices, memory devices, and diodes. Furthermore, the term "semiconductor device" can refer to a finished device or an assembly or other structure at various processing stages prior to becoming a finished device. Depending on its application context, the term "substrate" can refer to a structure supporting electronic components (e.g., a die), such as a PCB or wafer-level substrate, a die-level substrate, or another die used for die stacking or three-dimensional integration (3DI) applications.

[0032] The devices discussed herein (including a memory device) can be formed on a semiconductor substrate or die (such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc.). In some cases, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species (including, but not limited to, phosphorus, boron, or arsenic). Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0033] The functionality described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of this invention and the appended claims. Features implementing the functionality can also be physically located at various locations, including portions distributed such that the functionality is implemented at different physical locations.

[0034] As used herein (and within the scope of the invention claims), the word "or" as used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a conditionally closed set. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the invention. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0035] As used herein, the terms "vertical," "lateral," "up," "down," "above," and "below" may refer to features in a semiconductor device relative to the orientation or position shown in the figures. For example, "up" or "topmost" may refer to a feature positioned closer to the top of a page than another feature. However, these terms should be interpreted broadly to include semiconductor devices with other orientations (such as inverted or tilted orientations), where top / bottom, above / below, above / below, up / down, and left / right may be interchanged depending on the orientation.

[0036] As will be understood from the foregoing, specific embodiments of the invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the invention. Indeed, in the foregoing description, numerous specific details are set forth to provide a thorough and detailed description of one embodiment of the present technology. However, those skilled in the art will recognize that the invention may be practiced without one or more of these specific details. In other instances, well-known structures or operations typically associated with memory systems and devices have not been shown or described in detail to avoid obscuring other aspects of the present technology. Generally, it should be understood that various other devices, systems, and methods, in addition to the specific embodiments disclosed herein, are also within the scope of the present technology.

[0037] 100: Semiconductor device assembly 102: Semiconductor die 104:Substrate 106: Metallization layer 108: Through-Silicone Via (TSV) 110: Contact pad 112: Coupling surface 114: Oxide layer 116: Silicon nitride layer 118: Silicon carbon nitride layer 120: Silicon carbon nitride layer 200: Semiconductor device assembly 202: Semiconductor die 204:Substrate 206: Metallization layer 208: Through-Silicone Via (TSV) 210: Contact pad 212: Coupled Surface 214: Oxide layer 216: Silicon carbon nitride layer 218: Silicon carbon nitride layer 220: Highlighted Part 222: Sidewall 300: Stage 400: Stage 500: Stage 600: Stage / Semiconductor Device Assembly 602: Stacked semiconductor die 604: Packaging-grade substrate 606: Conductive structure 608: Conductive Structure 610: Base adhesive filler material 612: Encapsulation agent 700: System 702: Semiconductor Device Assembly 704: Power Supply 706: Drive 708: Processor 710: Other subsystems or components 800: Method 802: Provide substrate 804: A silicon carbide layer is disposed on the back side of the substrate and surrounds the protruding portion of the via. 806: An oxide layer is disposed on the back side of the substrate and at least partially surrounds the protruding portion of the via. 808: Etch oxide and silicon carbide layers to expose the coupling surface of the via. 810: The conductive pad is placed at the coupling surface of the via and extends at least partially through the oxide layer.

Claims

1. A semiconductor device comprising: A substrate having a front side and a back side opposite to the front side; A through hole that extends completely through the substrate and has a protrusion that extends beyond the back side of the substrate; a silicon carbide layer disposed on the back side of the substrate and extending along the sidewall of the protrusion of the through hole. An oxide layer disposed on the back side of the substrate and at least partially surrounding the protruding portion of the via; a conductive pad disposed on one coupling surface of the via and at least partially extending through the oxide layer; and an additional silicon carbide nitride layer disposed opposite the silicon carbide nitride layer on the oxide layer, wherein the silicon carbide nitride layer extends above a portion of the coupling surface of the via and directly covers that portion of the coupling surface of the via.

2. The semiconductor device of claim 1, wherein the silicon carbon nitride layer is in direct contact with the back side of the substrate.

3. The semiconductor device of claim 1, wherein the surface area of ​​the conductive pad in a plane coplanar with the coupling surface of the via is smaller than the surface area of ​​the coupling surface of the via.

4. The semiconductor device of claim 1, wherein the back side of the substrate has a topography of less than 200 nanometers.

5. The semiconductor device of claim 1, wherein the oxide layer comprises tetraethyl orthosilicate, spin-on-dielectric, or spin-on-glass.

6. A method for manufacturing a semiconductor device, comprising: A substrate is provided, the substrate including a front side, a back side opposite to the front side, and a through-hole extending completely through the substrate and having a protrusion extending beyond the back side of the substrate; a silicon carbide layer is disposed on the back side of the substrate and surrounding the protrusion of the through-hole; an oxide layer is disposed on the back side of the substrate and at least partially surrounds the protrusion of the through-hole; the oxide layer and the silicon carbide layer are etched to expose a coupling surface of the through-hole; a conductive pad is disposed on the coupling surface of the through-hole and at least partially extends through the oxide layer; and the oxide layer and the silicon carbide layer are etched to expose the coupling surface of the through-hole such that a portion of the silicon carbide layer extends over and directly covers a portion of the coupling surface where the conductive pad is not disposed.

7. The method of claim 6 further includes placing the silicon carbon nitride layer in direct contact with the back side of the substrate.

8. The method of claim 6, further comprising placing the silicon carbon nitride layer at a temperature above 700 degrees Celsius.

9. The method of claim 6, further comprising placing an additional silicon carbon nitride layer relative to the silicon carbon nitride layer on the oxide layer.

10. The method of claim 6, further comprising depositing the oxide layer by means of flowable chemical vapor deposition, fluid vapor deposition or spin coating.

11. A semiconductor device comprising: A substrate having a front side and a back side opposite to the front side; A via extending completely through the substrate and having a protrusion extending beyond the back side of the substrate; a silicon carbide layer in direct contact with the back side of the substrate; an oxide layer disposed on the back side of the substrate and above the protrusion of the via; a conductive pad disposed on a coupling surface of the via and extending at least partially through the oxide layer; and an additional silicon carbide layer disposed opposite to the silicon carbide layer on the oxide layer, wherein the silicon carbide layer extends above a portion of the coupling surface of the via and directly covers that portion of the coupling surface of the via.

12. The semiconductor device of claim 11, wherein the silicon carbon nitride layer extends along the sidewall of the protruding portion of the via.

13. The semiconductor device of claim 11, wherein the cross-sectional area of ​​the conductive pad in a plane coplanar with the coupling surface of the via is smaller than the area of ​​the coupling surface of the via.

14. The semiconductor device of claim 11, further comprising: A semiconductor die comprising the substrate and the contact pads; and an additional semiconductor die comprising additional contact pads, wherein the semiconductor die and the additional semiconductor die are coupled at the contact pads to implement a semiconductor die stack according to a high-bandwidth memory protocol.

15. The semiconductor device of claim 11, further comprising: One logic grain; A semiconductor die comprising the substrate and the contact pads, and coupled to the logic die at a first lateral position; an additional semiconductor die comprising additional contact pads, wherein the semiconductor die and the additional semiconductor die are coupled at the contact pads to implement a first semiconductor die stack; and a second semiconductor die stack coupled to the logic die at a second lateral position.

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