Bidirectional switched capacitor converter with current limiting and control circuit and control method thereof

Abstract

A switching capacitor converter for converting a first voltage to a second voltage and vice versa, comprising: a plurality of switches, including at least four switches having a first switch coupled between the first voltage and an inductor switching node; an inductor coupled between the inductor switching node and the second voltage; a flying capacitor coupled to the plurality of switches and configured as a capacitive voltage divider; a current sensing circuit for sensing an inductor current and sampling the inductor current during the conduction of the first switch to generate a sensed current signal; an error amplifier for generating a first amplified signal based on the difference between the sensed current signal and a reference current signal; and a pulse width modulation generator for comparing the first amplified signal with a ramp signal to generate a switching control signal to control the first switching current flowing through the first voltage.

Description

Technical Field

[0001] The present invention relates to a bidirectional switched-capacitor converter, and more particularly to a bidirectional switched-capacitor converter having a current limiting function. The present invention also relates to a control circuit and a control method for controlling the above-mentioned bidirectional switched-capacitor converter. Prior Art

[0002] FIG. 1 shows a prior art switched-capacitor converter 900 having a current limiting function. The input current limiting function in FIG. 1 must connect a sense resistor Rs at the input voltage Vin to sense the input current Iin, and requires a current sense amplifier 90 and a control circuit 91 to control the power stage circuit 92. The control circuit 91 generates a control signal PWM according to the sense signal Ise and the reference current signal Iref to control the power stage circuit 92, thereby limiting the input current Iin.

[0003] Disadvantages of the prior art include significant power loss caused by the sense resistor and the need for a high-voltage current sense amplifier circuit, which results in unnecessary power consumption and higher manufacturing costs.

[0004] In view of the above situation, to overcome the disadvantages in the prior art, the present invention proposes a bidirectional switched-capacitor converter having a current limiting function, which is characterized by performing input current sensing through an output inductor to achieve input current limit control, so that a sense resistor and a high-voltage current sense amplifier circuit are not required. The present invention also has a current limiting and current regulation control function for a power converter to avoid the problem of input power supply shutdown caused by overcurrent protection. Summary of the Invention

[0005] In one aspect, the present invention provides a switched-capacitor converter for converting a first voltage to a second voltage or for converting the second voltage to the first voltage, comprising: a plurality of switches including at least four switches, wherein the at least four switches include a first switch, and the first switch is coupled between the first voltage and a first inductive switching node; a first inductor coupled between the first inductive switching node and the second voltage; a first flying capacitor coupled to the plurality of switches and configured as a capacitive voltage divider to reduce the voltage stress on the plurality of switches; a current sensing circuit coupled to the first inductor for sensing a first inductor current flowing through the first inductor and sampling the first inductor current during the conduction period of the first switch to generate a sensed current signal; a first error amplifier for generating a first amplified signal based on the difference between the sensed current signal and a reference current signal; and a pulse width modulation (PWM) generator for comparing the first amplified signal with a first ramp signal to generate a plurality of switching control signals, wherein the plurality of switching control signals are used to control the plurality of switches, thereby controlling a first switch current flowing into or out of the first voltage.

[0006] In a preferred embodiment, the current sensing circuit includes a sensing resistor and a sensing capacitor coupled to the first inductor, and senses the first inductor current by sensing the voltage across the sensing capacitor, thereby generating the sensed current signal.

[0007] In a preferred embodiment, the current sensing circuit includes a sampling circuit and a low-pass filter for sensing the first inductor current and generating the sensed current signal.

[0008] In a preferred embodiment, the current sensing circuit samples the first inductor current during the conduction period of the first switch, thereby limiting the first switch current flowing into or out of the first voltage.

[0009] In a preferred embodiment, the current sensing circuit further samples the first inductor current during the non-conduction period of the first switch, thereby limiting an output current flowing into or out of the second voltage.

[0010] In a preferred embodiment, the first ramp signal operates at a fixed switching frequency in the switched-capacitor converter.

[0011] In a preferred embodiment, the switched-capacitor converter further includes a second error amplifier for generating a second amplified signal based on the difference between the second voltage and a reference voltage signal, thereby controlling the second voltage.

[0012] In a preferred embodiment, the plurality of switching control signals includes a first switching control signal and a second switching control signal; wherein the pulse width modulation generator includes: a first comparator for comparing the first amplified signal with the first ramp signal to generate the first switching control signal; and a second comparator for comparing the first amplified signal with a second ramp signal to generate the second switching control signal; wherein the plurality of switches are controlled by the first switching control signal and the second switching control signal, thereby controlling the first switch current flowing into or out of the first voltage; wherein a pulse start point of the first switching control signal determines a first valley value of the first inductor current, and a pulse start point of the second switching control signal determines a second valley value of the first inductor current, thereby achieving valley current mode control of the switched capacitor converter; wherein the first ramp signal and the second ramp signal are respectively generated according to a first clock signal and a second clock signal, and are related to the first inductor current.

[0013] In a preferred embodiment, the phase shift between the first ramp signal and the second ramp signal is 180 degrees to ensure balanced control of the switched capacitor converter.

[0014] In a preferred embodiment, the switched capacitor converter further includes: a second switch, a third switch, and a fourth switch, wherein the first switch is coupled between the first voltage and a first capacitor switching node, the first flying capacitor is coupled between the first capacitor switching node and a second capacitor switching node, the second switch is coupled between the first capacitor switching node and the first inductor switching node, the third switch is coupled between the second capacitor switching node and the first inductor switching node, and the fourth switch is coupled between the second capacitor switching node and a ground potential.

[0015] In a preferred embodiment, the switched capacitor converter further includes a second inductor, and the plurality of switches further includes a second switch, a third switch, and a fourth switch, wherein the first flying capacitor is coupled between a first capacitor switching node and the first inductor switching node, the second switch is coupled between the first capacitor switching node and a second inductor switching node, the third switch is coupled between the second inductor switching node and a ground potential, the fourth switch is coupled between the first inductor switching node and the ground potential, and the second inductor is coupled between the second inductor switching node and the second voltage.

[0016] In a preferred embodiment, the switched capacitor converter further includes a second inductor and a second flying capacitor, wherein the plurality of switches, the first inductor, the second inductor, the first flying capacitor, and the second flying capacitor are configured as a cross-coupled switched capacitor converter.

[0017] In another aspect, the present invention provides a control circuit for controlling a switched capacitor converter for converting a first voltage to a second voltage or for converting the second voltage to the first voltage, wherein the switched capacitor converter includes: a plurality of switches including at least four switches, wherein the at least four switches include a first switch, wherein the first switch is coupled between the first voltage and a first inductor switching node; a first inductor coupled between the first inductor switching node and the second voltage; and a first flying capacitor coupled to the plurality of switches and configured as a capacitive voltage divider to reduce the voltage stress on the plurality of switches; wherein the control circuit includes: an inductor sensing circuit coupled to the first inductor for sensing a first inductor current flowing through the first inductor and sampling the first inductor current during the conduction period of the first switch to generate a sensed current signal; a first error amplifier for generating a first amplified signal based on the difference between the sensed current signal and a reference current signal; and a pulse width modulation (PWM) generator for comparing the first amplified signal with a first ramp signal to generate a plurality of switching control signals, wherein the plurality of switching control signals are used to control the plurality of switches, thereby controlling a first switch current flowing into or out of the first voltage.

[0018] In another aspect, the present invention provides a control method for controlling a switched-capacitor converter for converting a first voltage to a second voltage or for converting the second voltage to the first voltage, wherein the switched-capacitor converter includes: a plurality of switches including at least four switches, wherein the at least four switches include a first switch, wherein the first switch is coupled between the first voltage and a first inductive switching node; a first inductor coupled between the first inductive switching node and the second voltage; and a first flying capacitor coupled to the plurality of switches and configured as a capacitive voltage divider to reduce the voltage stress on the plurality of switches; wherein the control method includes: sensing a first inductor current flowing through the first inductor and sampling the first inductor current during the conduction period of the first switch to generate a sensed current signal; generating a first amplified signal based on the difference between the sensed current signal and a reference current signal; and comparing the first amplified signal with a first ramp signal to generate a plurality of switching control signals for controlling the plurality of switches, thereby controlling a first switch current flowing into or out of the first voltage.

[0019] The following will be described in detail by way of specific embodiments to more easily understand the object, technical content, features and achieved effects of the present invention. Brief Description of the Drawings

[0020] FIG. 1 shows a prior art switched-capacitor converter.

[0021] FIG. 2A shows a block diagram of a switched-capacitor converter in an embodiment of the present invention.

[0022] FIG. 2B shows a block diagram of a switched-capacitor converter in another embodiment of the present invention.

[0023] FIG. 3A shows an operational waveform diagram of an embodiment of the switched-capacitor converter corresponding to FIG. 2A of the present invention.

[0024] FIG. 3B shows an operational waveform diagram of another embodiment of the switched-capacitor converter corresponding to FIG. 2A of the present invention.

[0025] FIG. 4 shows a schematic diagram of a switched-capacitor converter in an embodiment of the present invention.

[0026] FIG. 5 shows a schematic diagram of a current signal generator of a current sensing circuit in a switched-capacitor converter in an embodiment of the present invention.

[0027] FIG. 6 shows a schematic diagram of a sampling circuit and a low-pass filter of a current sensing circuit in a switched capacitor converter according to an embodiment of the present invention.

[0028] FIG. 7A shows a schematic diagram of a switched capacitor converter according to an embodiment of the present invention.

[0029] FIG. 7B shows an operational waveform diagram of an embodiment of the switched capacitor converter corresponding to FIG. 7A of the present invention.

[0030] FIG. 8A shows a schematic diagram of a switched capacitor converter according to an embodiment of the present invention.

[0031] FIG. 8B shows an operational waveform diagram of an embodiment of the switched capacitor converter corresponding to FIG. 8A of the present invention.

[0032] FIG. 9A shows a schematic diagram of a switched capacitor converter according to an embodiment of the present invention.

[0033] FIG. 9B shows an operational waveform diagram of an embodiment of the switched capacitor converter corresponding to FIG. 9A of the present invention. Embodiments

[0034] The diagrams in the present invention are all schematic, mainly intended to show the coupling relationship between circuits and the relationship between signal waveforms. As for circuits, signal waveforms and frequencies, they are not drawn to scale. For the sake of clarity, many practical details will be described together in the following description, but this is not intended to limit the scope of the patent application of the present invention.

[0035] FIG. 2A shows a block diagram of a switched capacitor converter according to an embodiment of the present invention. FIG. 2B shows a block diagram of a switched capacitor converter according to another embodiment of the present invention. In one embodiment, as shown in FIG. 2A, the switched capacitor converter 1002A is used to convert the first voltage V1 into the second voltage V2. In another embodiment, as shown in FIG. 2B, the switched capacitor converter 1002B is used to convert the second voltage V2 into the first voltage V1. The following embodiments will be described taking FIG. 2A as an example, and those skilled in the art can infer the operation details of the embodiment of FIG. 2B from the following description.

[0036] In one embodiment, as shown in FIG. 2A, the switched-capacitor converter 1002A includes a plurality of switches, a first inductor L1, a first flying capacitor C1, a current sensing circuit 100, a first error amplifier 210, and a pulse width modulation (PWM) generator 300. In one embodiment, the plurality of switches includes at least four switches. In this embodiment, the plurality of switches includes a first switch Q1, a second switch Q2, a third switch Q3, and a fourth switch Q4. In one embodiment, the first switch Q1 is coupled between a first voltage V1 and a first inductor switching node Nl1. In other words, during at least one period of the switching cycle, the current flowing through the first switch Q1 is equal to the current flowing through the first inductor L1, and the details will be described in detail later. The first inductor L1 is coupled between the first inductor switching node Nl1 and a second voltage V2. The first flying capacitor C1 is coupled to the plurality of switches Q1-Q4 and configured as a capacitive voltage divider to reduce the voltage stress of the plurality of switches Q1-Q4.

[0037] In one embodiment, the current sensing circuit 100 is coupled to the first inductor L1 to sense a first inductor current IL1 flowing through the first inductor L1 and generate a sensed current signal ILf. The first error amplifier 210 is configured to generate a first amplified signal EA1 based on the difference between the sensed current signal ILf and a reference current signal Iref. The PWM generator 300 is configured to compare the first amplified signal EA1 with a first ramp signal Vramp1 to generate switching control signals S1-S4 to control the plurality of switches, thereby limiting the first switch current IQ1 flowing from the first voltage V1 to achieve input current limitation. In this embodiment, the switching control signals S1-S4 are respectively used to control the plurality of switches Q1-Q4. In one embodiment, the current sensing circuit 100 is configured to sample the first inductor current IL1 during the conduction period of the first switch Q1 to generate a sensed current signal ILf. In one embodiment, the first ramp signal Vramp1 operates at a fixed switching frequency in the switched-capacitor converter 1002A.

[0038] FIG. 3A shows an operational waveform diagram of an embodiment of the switched-capacitor converter according to the present invention corresponding to FIG. 2A. In one embodiment, as shown in FIG. 3A, during the switching period Tsw1, the duty cycles of the switching control signal S1 and the switching control signal S2 are both less than 50% (for example, in the case of V2 < V1 / 2). In one embodiment, during the first conduction time Ton1 when the first switch Q1 is in the on state, the first inductor current IL1 is equal to the input current (i.e., the first switch current IQ1). In one embodiment, the current sensing circuit 100 is used to sample the first inductor current IL1 during the first conduction time Ton1, thereby limiting the first switch current IQ1. In another embodiment, the current sensing circuit 100 is further used to sample the first inductor current IL1 when the first switch Q1 is in the off state (i.e., the off time Toff) to limit an output current flowing to the second voltage V2.

[0039] FIG. 3B shows an operational waveform diagram of another embodiment of the switched-capacitor converter according to the present invention corresponding to FIG. 2A. In one embodiment, as shown in FIG. 3B, during the switching period Tsw2, the duty cycles of the switching control signal S1 and the switching control signal S2 are both greater than 50% (for example, in the case of V2 > V1 / 2). For more details about the waveforms, please refer to the description of FIG. 3A.

[0040] FIG. 4 shows a schematic diagram of a switched-capacitor converter in an embodiment of the present invention. Compared with the switched-capacitor converter 1002A shown in FIG. 2A, in one embodiment, the switched-capacitor converter 1004 in FIG. 4 further includes a second error amplifier 220. The current sensing circuit 101 of the switched-capacitor converter 1004 includes a current signal generator 110, a sampling circuit 120, and a low-pass filter 130. In one embodiment, the current signal generator 110 is used to generate an inductor current signal ViL by sensing the first inductor current IL1. The sampling circuit 120 is used to sample the inductor current signal ViL during the first conduction time Ton1 according to the sampling time tsp to generate a sampled current signal ILs. The low-pass filter 130 generates a sensed current signal ILf according to the sampled current signal ILs.

[0041] In a specific embodiment, the first switch Q1 is coupled between the first voltage V1 and the first capacitor switching node Nc1, the first flying capacitor C1 is coupled between the first capacitor switching node Nc1 and the second capacitor switching node Nc2, the second switch Q2 is coupled between the first capacitor switching node Nc1 and the first inductor switching node Nl1, the third switch Q3 is coupled between the second capacitor switching node Nc2 and the first inductor switching node Nl1, and the fourth switch Q4 is coupled between the second capacitor switching node Nc2 and the ground potential.

[0042] In one embodiment, the second error amplifier 220 is configured to generate a second amplified signal EA2 based on the difference between the feedback signal Vfb (related to or equal to the second voltage V2) and the reference voltage signal Vref, thereby controlling the second voltage. In this embodiment, the PWM generator 300 is configured to generate switching control signals S1 to S4 according to the first ramp signal Vramp1 and the third amplified signal Vcomp. The third amplified signal Vcomp is generated based on the lower value of the first amplified signal EA1 and the second amplified signal EA2. For example, as shown in the embodiment of FIG. 4, a diode is used to compare and select the lower value of the first amplified signal EA1 and the second amplified signal EA2 to generate the third amplified signal Vcomp. From another perspective, each loop controlled by the first error amplifier 210 and the second error amplifier 220 determines its respective duty cycle. However, through the comparison and selection mechanism, the loop with the lower duty cycle mainly controls the operation of the switched capacitor converter 1004.

[0043] Please refer to FIGS. 3A, 3B, and 4. In one embodiment, the sampled current signal ILs is generated by sampling the first inductor current IL1 during the first conduction time Ton1 when the first switch Q1 is in the conduction state. Therefore, the sampled current signal ILs is proportional to the input current of the switched capacitor converter 1004 (i.e., the first switch current IQ1). The switched capacitor converter 1004 of the present invention senses its input current through the first inductor current IL1, thereby controlling the input current. Therefore, the present invention does not require an input current sensing resistor and a high-voltage current sensing amplifier circuit in the prior art.

[0044] Please continue to refer to FIG. 4. In one embodiment, when the input current (the first switch current IQ1) of the switched capacitor converter 1004 increases, the sensed current signal ILf also increases. If the sensed current signal ILf is higher than the reference current signal Iref, the first error amplifier 210 will pull down the third amplified signal Vcomp to adjust the switching control signals S1 to S4, thereby controlling the input current below a preset input current level.

[0045] FIG. 5 shows a schematic diagram of a current signal generator of a current sensing circuit in a switched capacitor converter according to an embodiment of the present invention. The current signal generator 111 shown in FIG. 5 is a specific embodiment of the direct current resistance (DCR) sensing of the current signal generator 110 shown in FIG. 4. In one embodiment, the first inductor L1 includes a direct current resistance Dcr1. The current signal generator 111 includes a sensing resistor Rx and a sensing capacitor Cx. The sensing resistor Rx and the sensing capacitor Cx are connected in series and coupled to the first inductor L1. When the time constants of the first inductor L1, the direct current resistance Dcr1, the sensing resistor Rx, and the sensing capacitor Cx match, the first inductor current IL1 can be sensed by the voltage across the sensing capacitor Cx. The inductor current signal ViL is generated according to the voltage across the sensing capacitor Cx. The remaining details of the current signal generator 111 are well known to those skilled in the art and will not be described in detail.

[0046] It should be noted that the advantage of the above DCR sensing method is to reduce the power loss of the current sensing resistor. The generation method of the inductor current signal ViL in FIG. 4 is not limited to the DCR sensing method. The inductor current signal ViL can also be generated by at least one of a physical current sensing resistor, a current sensing transformer, a Hall Effect sensing device, a first flying capacitor C1, or a plurality of switches Q1 to Q4 connected in series with the first inductor L1.

[0047] FIG. 6 shows a schematic diagram of a sampling circuit and a low-pass filter of a current sensing circuit in a switched capacitor converter according to an embodiment of the present invention. The sampling circuit 121 and the low-pass filter 131 shown in FIG. 6 are specific embodiments of the sampling circuit 120 and the low-pass filter 130 shown in FIG. 4, respectively. In one embodiment, the sampling switch SW1 of the sampling circuit 121 is controlled by a sampling control signal having a sampling time tsp. The sampling control signal can be a switching control signal S1 or a fixed voltage (such as the supply voltage Vcc). In one embodiment, when the sampling control signal is the switching control signal S1, the sampling current signal ILs is proportional to the input current flowing through the first switch Q1 (i.e., the first switch current IQ1). In another embodiment, when the sampling control signal is the supply voltage Vcc, the sampling current signal ILs is proportional to the output current corresponding to the second voltage V2.

[0048] In one embodiment, the low-pass filter 131 includes a filtering resistor Rf and a filtering capacitor Cf. The low-pass filter 131 is used to generate a sensing current signal ILf according to the sampling current signal ILs.

[0049] Please refer to FIGS. 7A and 7B. FIG. 7A shows a schematic diagram of a switched-capacitor converter in an embodiment of the present invention. FIG. 7B shows an operating waveform diagram of a switched-capacitor converter corresponding to FIG. 7A in the present invention. The switched-capacitor converter 1007 shown in FIG. 7A is a specific embodiment of the switched-capacitor converter 1004 shown in FIG. 4. In an embodiment, as shown in FIG. 7A, the PWM generator 301 of the switched-capacitor converter 1007 includes a first comparator 310 and a second comparator 320. In an embodiment, the first comparator 310 is used to compare the third amplified signal Vcomp with the first ramp signal Vramp1 to generate a trigger signal Str1, thereby simultaneously cooperating with the flip-flop FF1 to generate switching control signals S1 and S4 according to the clock signal clk1. The second comparator 320 is used to compare the third amplified signal Vcomp with the second ramp signal Vramp2 to generate a trigger signal Str2, thereby simultaneously cooperating with the flip-flop FF2 to generate switching control signals S2 and S3 according to the clock signal clk2. It should be noted that the third amplified signal Vcomp is equivalent to the aforementioned first amplified signal EA1 or second amplified signal EA2. In addition, the first ramp signal Vramp1 and the second ramp signal Vramp2 are respectively generated according to the clock signals clk1 and clk2, and are related to the inductor current signal ViL.

[0050] As shown in FIG. 7A, in an embodiment, the first comparator 310 and the second comparator 320 are used to generate switching control signals S1 to S4 to control a plurality of switches Q1 to Q4, so as to control the first switching current IQ1 flowing from the first voltage V1, so that the first inductive switching node Nl1 (i.e., the switching node voltage VNl1) switches between two of the k voltage levels, thereby adjusting the first voltage V1 or the second voltage V2 to a preset target level, and adjusting and balancing the voltage on the first flying capacitor C1 to one (k - 1)th of the first voltage V1.

[0051] It should be noted that the above k is an integer greater than or equal to 3 (in the embodiment shown in FIG. 7A, k is equal to 3), and the k voltage levels include the first voltage V1, the ground potential, and at least one divided voltage of the first voltage V1. As shown in FIG. 7B, in this embodiment, the switching node voltage VNl1 switches between V1 / 2 (i.e., V1 - VC or VC, where VC is the voltage across the two ends of the first flying capacitor C1, and its steady state is V1 / 2) and the ground potential. Tsw is the switching period in this embodiment. It should also be noted that in other embodiments, the switching node voltage VNl1 can switch between V1 and V1 / 2.

[0052] Please continue to refer to FIG. 7B. In one embodiment, the start point of the pulse of the first control signal (e.g., t1) determines the first valley value of the first inductor current IL1 (by determining the first valley value of the inductor current signal ViL), and the start point of the pulse of the second control signal (e.g., t3) determines the second valley value of the first inductor current IL1 (by determining the second valley value of the inductor current signal ViL), thereby achieving valley current mode control. It should also be noted that, in order to ensure the balanced control of the switched-capacitor converter 1007, the phase shift between the first ramp signal Vramp1 and the second ramp signal Vramp2 is 180 degrees.

[0053] FIG. 8A shows a schematic diagram of a switched-capacitor converter in an embodiment of the present invention. In one embodiment, the switched-capacitor converter 1008A further includes a second inductor L2, and the second inductor L2 has a second inductor current IL2. In one embodiment, the power stage circuit of the switched-capacitor converter 1008A is configured as a series capacitor buck (SCB) converter, including a first flying capacitor C1, a first inductor L1, a second inductor L2, and a plurality of switches Q1 to Q4. In a specific embodiment, as shown in FIG. 8A, the first flying capacitor C1 is coupled between the first capacitor switching node Nc1 and the first inductor switching node Nl1, the second switch Q2 is coupled between the first capacitor switching node Nc1 and the second inductor switching node Nl2, the third switch Q3 is coupled between the second inductor switching node Nl2 and the ground potential, the fourth switch Q4 is coupled between the first inductor switching node Nl1 and the ground potential, and the second inductor L2 is coupled between the second inductor switching node Nl2 and the second voltage V2.

[0054] FIG. 8B shows an operating waveform diagram of an embodiment of the switched-capacitor converter corresponding to FIG. 8A of the present invention. In one embodiment, during the switching period Tsw3, the duty cycles of the switching control signal S1 and the switching control signal S2 are both less than 50%. In this embodiment, the current sensing circuit 100 is used to sample the first inductor current IL1 during the first conduction time Ton1 when the first switch Q1 is in the conduction state to limit the first switch current IQ1. Those skilled in the art can infer the details of the operating waveforms in FIG. 8B from FIG. 8A and the foregoing description.

[0055] FIG. 9A shows a schematic diagram of a switched capacitor converter in an embodiment of the present invention. Compared with the switched capacitor converter 1002A shown in FIG. 2A, in one embodiment, the switched capacitor converter 1009A further includes a second inductor L2 and a second flying capacitor C2. The current sensing circuits in FIG. 9 include current sensing circuits 1091 and 1092, which are respectively used to sense the first inductor current IL1 and the second inductor current IL2 to generate a first sensed current signal ILf1 and a second sensed current signal ILf2 respectively. In one embodiment, as shown in FIG. 9, the plurality of switches further includes a fifth switch Q5 and a sixth switch Q6, which are respectively controlled by switching control signals S5 and S6.

[0056] In the embodiment shown in FIG. 9A, the plurality of switches Q1~Q6, the first inductor L1, the second inductor L2, the first flying capacitor C1, and the second flying capacitor C2 are configured as a cross-coupled switched capacitor converter, which is used to convert the first voltage V1 into the second voltage V2, or convert the second voltage V2 into the first voltage V1.

[0057] Please refer to FIGS. 9A and 9B. FIG. 9B shows an operating waveform diagram of an embodiment of the switched capacitor converter corresponding to FIG. 9A of the present invention. In one embodiment, during the switching period Tsw4, the duty cycles of the switching control signal S1 and the switching control signal S2 are both less than 50%. In one embodiment, as shown in FIG. 9B, during the time period t0~t1, the first inductor current IL1 is magnetized according to the charging current IC1_ch of the first flying capacitor C1 and the discharging current IC2_disch of the second flying capacitor C2. During the time period t2~t3, the second inductor current IL2 is magnetized according to the discharging current IC1_disch of the first flying capacitor C1 and the charging current IC2_ch of the second flying capacitor C2. In the steady state, due to charge balance, the charging current and discharging current of the first flying capacitor C1 and the second flying capacitor C2 are equal. Therefore, the average input current value Iina of the input current Iin can be sampled from the first inductor current IL1 when the switching control signal S1 is at a high level, and sampled from the second inductor current IL2 when the switching control signal S2 is at a high level. The average input current value Iina can be calculated by the following equation.

[0058] ILS1 = IC1_ch + IC2_disch

[0059] ILS2 = IC1_disch + IC2_ch

[0060] Iina = (ILS1 + ILS2) / 2

[0061] In the above equation, ILS1 is the current value of the first inductor current IL1 when the switching control signal S1 is at a high level, and ILS2 is the current value of the second inductor current IL2 when the switching control signal S2 is at a high level.

[0062] In addition, if the component parameters between the first flying capacitor C1 and the second flying capacitor C2, and between the first inductor L1 and the second inductor L2 match, the average input current value Iina can be sampled from the first inductor current IL1 during the period when the switching control signal S1 is at a high level, or sampled from the second inductor current IL2 during the period when the switching control signal S2 is at a high level.

[0063] The present invention has been described with respect to the preferred embodiments. However, the above description is only for the convenience of those skilled in the art to understand the content of the present invention, and is not used to limit the scope of the rights of the present invention. The described embodiments are not limited to being applied alone, and can also be combined. For example, two or more embodiments can be combined, and some components in one embodiment can also be used to replace the corresponding components in another embodiment. In addition, in the same spirit of the present invention, those skilled in the art can conceive various equivalent changes and various combinations. For example, the so-called "processing or operating or generating a certain output result according to a certain signal" in the present invention is not limited to the signal itself, but also includes, when necessary, performing voltage-current conversion, current-voltage conversion, and / or ratio conversion on the signal, and then processing or operating according to the converted signal to generate a certain output result. It can be seen that in the same spirit of the present invention, those skilled in the art can conceive various equivalent changes and various combinations, and there are many combination methods, which are not listed one by one here. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

[0064] 100, 101, 1091, 1092: Current sensing circuit 1002A, 1002B, 1004, 1007, 1008A: Switching capacitor converter 110, 111: Current signal generator 120, 121: Sampling circuit 130, 131: Low-pass filter 210: First error amplifier 220: Second error amplifier 300, 301: Pulse width modulation generator 310: First comparator 320: Second comparator 90: Current sensing amplifier 900: Switched capacitor converter 91: Control circuit 92: Power stage circuit C1: First flying capacitor C2: Second flying capacitor Cf: Filter capacitor clk1: Clock signal Cx: Sensing capacitor Dcr1: DC resistance EA1: First amplified signal EA2: Second amplified signal FF1, FF2: Flip-flop IC1_ch, IC2_ch: Charging current IC1_disch, IC2_disch: Discharging current Iin: Input current Iina: Average input current value IL1: First inductor current IL2: Second inductor current ILf: Sensing current signal ILf1: First sensing current signal ILf2: Second sensing current signal ILs: Sampling current signal ILS1: Current value of the first inductor current ILS2: Current value of the second inductor current IQ1: First switching current Iref: Reference current signal Iref: Reference current signal Ise: Sensing signal L1: First inductor L2: Second inductor Nc1: First capacitor switching node Nc2: Second capacitor switching node Nl1: First inductor switching node Nl2: Second inductor switching node PWM: Control signal Q1~Q6: Switch Rf: Filter resistance Rs: Sensing resistance Rx: Sensing resistor S1~S6: Switching control signals Str1,Str2: Trigger signals SW1: Sampling switch Toff: Turn-off time Ton1: First conduction time tsp: Sampling time Tsw,Tsw1,Tsw2,Tsw3,Tsw4: Switching periods V1: First voltage V2: Second voltage VC: Voltage across the first flying capacitor Vcc: Supply voltage Vcomp: Third amplified signal Vfb: Feedback signal ViL: Inductor current signal Vin: Input voltage VNl1: Switching node voltage Vramp1: First ramp signal Vramp2: Second ramp signal Vref: Reference voltage signal

Claims

1. A switching capacitor converter for converting an input voltage into an output voltage, comprising: a plurality of switches including at least four switches, wherein the at least four switches include a first switch, wherein a first terminal of the first switch is coupled to the input voltage; a first inductor having a first terminal coupled to the output voltage; a first flying capacitor coupled between a second terminal of the first switch and a second terminal of the first inductor, and configured as a capacitive voltage divider to reduce voltage stress on the plurality of switches, wherein in at least one switching state of the plurality of switches, the first switch is turned on, thereby the first flying capacitor and the first inductor are connected in series between the input voltage and the output voltage through the first switch; a current sensing circuit coupled to the first inductor for sensing and sampling a first inductor current flowing through the first inductor during the turn-on period of the first switch to generate a sense current signal, thereby sensing a first switch current flowing through the first switch; A first error amplifier for generating a first amplified signal based on the difference between the sensed current signal and a reference current signal; a second error amplifier for generating a second amplified signal based on the difference between the output voltage and a reference voltage signal; a comparator selection circuit for comparing the levels of the first amplified signal and the second amplified signal to select the one with the lower corresponding duty cycle to generate a third amplified signal; and a pulse width modulation (PWM) generator for comparing the third amplified signal with a first ramp signal to generate a complex switching control signal, wherein the complex switching control signal controls the complex switches, thereby controlling the first switching current based on the first inductor current when the third amplified signal corresponds to the first amplified signal to limit an input current related to the input voltage, and controlling the output voltage based on the difference between the output voltage and the reference voltage signal when the third amplified signal corresponds to the second amplified signal.

2. The switching capacitor converter as claimed in claim 1, wherein the current sensing circuit includes a sensing resistor and a sensing capacitor coupled to the first inductor, and generates the sensing current signal by sensing the voltage across the sensing capacitor to sense the current in the first inductor.

3. The switching capacitor converter as claimed in claim 1, wherein the current sensing circuit includes a sampling circuit and a low-pass filter for sensing the first inductor current and generating the sensed current signal.

4. The switching capacitor converter as described in claim 1, wherein the first ramp signal operates at a fixed switching frequency in the switching capacitor converter.

5. The switching capacitor converter as claimed in claim 1, wherein the comparison selection circuit includes a first diode and a second diode coupled to each other for comparing and selecting the lower of the first amplified signal and the second amplified signal to generate the third amplified signal.

6. The switching capacitor converter as described in claim 1, wherein the complex switching control signal includes a first switching control signal and a second switching control signal; wherein the pulse width modulation generator includes: A first comparator and a second comparator are provided, wherein when the third amplified signal corresponds to the first amplified signal, the first comparator compares the third amplified signal with the first ramp signal to generate the first switching control signal, and when the third amplified signal corresponds to the second amplified signal, the second comparator compares the third amplified signal with a second ramp signal to generate the second switching control signal; wherein the multiple switches are controlled by the first switching control signal and the second switching control signal, thereby controlling the first switching current; wherein the pulse start time of the first switching control signal determines a first valley value of the first inductor current, and the pulse start time of the second switching control signal determines a second valley value of the first inductor current, thereby achieving valley current mode control of the switching capacitor converter; wherein the first ramp signal and the second ramp signal are generated based on a first clock signal and a second clock signal, respectively, and are related to the first inductor current.

7. The switching capacitor converter as described in claim 6, wherein the phase offset between the first ramp signal and the second ramp signal is 180 degrees to ensure balanced control of the switching capacitor converter.

8. The switching capacitor converter as described in claim 1, wherein the plurality of switches further comprises: A second switch, a third switch, and a fourth switch, wherein the first switch is coupled between the input voltage and a first capacitor switching node, the first flying capacitor is coupled between the first capacitor switching node and a second capacitor switching node, the second switch is coupled between the first capacitor switching node and a first inductor switching node, the third switch is coupled between the second capacitor switching node and the first inductor switching node, and the fourth switch is coupled between the second capacitor switching node and a ground potential.

9. The switching capacitor converter as claimed in claim 1 further includes a second inductor, and the plurality of switches further includes a second switch, a third switch, and a fourth switch, wherein the first switch is coupled between the input voltage and a first capacitor switching node, the first flying capacitor is coupled between the first capacitor switching node and a first inductor switching node, the second switch is coupled between the first capacitor switching node and a second inductor switching node, the third switch is coupled between the second inductor switching node and a ground potential, the fourth switch is coupled between the first inductor switching node and the ground potential, the first inductor is coupled between the first inductor switching node and the output voltage, and the second inductor is coupled between the second inductor switching node and the output voltage.

10. The switching capacitor converter as claimed in claim 1 further includes a second inductor and a second flying capacitor, wherein the plurality of switches, the first inductor, the second inductor, the first flying capacitor and the second flying capacitor are configured as a cross-coupled switched capacitor converter.

11. A control circuit for controlling a switching capacitor converter for converting an input voltage into an output voltage, wherein the switching capacitor converter comprises: A complex switch includes at least four switches, wherein the at least four switches include a first switch, wherein a first terminal of the first switch is coupled to the input voltage; a first inductor, wherein a first terminal of the first inductor is coupled to the output voltage; and a first flying capacitor, coupled between a second terminal of the first switch and a second terminal of the first inductor, and configured as a capacitive voltage divider to reduce the voltage pressure on the complex switch, wherein in at least one switching state of the complex switch, the first switch is turned on, thereby the first flying capacitor and the first inductor are connected in series between the input voltage and the output voltage through the first switch; wherein the control circuit includes: a current sensing circuit coupled to the first inductor, for sensing and sampling a first inductor current flowing through the first inductor during the turn-on period of the first switch to generate a sense current signal, thereby sensing a first switch current flowing through the first switch; and a first error amplifier for generating a first amplified signal based on the difference between the sensed current signal and a reference current signal; A second error amplifier for generating a second amplified signal based on the difference between the output voltage and a reference voltage signal; a comparator selection circuit for comparing the levels of the first amplified signal and the second amplified signal to select the one with the lower corresponding duty cycle to generate a third amplified signal; and a pulse width modulation (PWM) generator for comparing the third amplified signal with a first ramp signal to generate a complex switching control signal, wherein the complex switching control signal controls the complex switching, thereby controlling the first switching current based on the first inductor current when the third amplified signal corresponds to the first amplified signal to limit an input current related to the input voltage, and controlling the output voltage based on the difference between the output voltage and the reference voltage signal when the third amplified signal corresponds to the second amplified signal.

12. The control circuit as claimed in claim 11, wherein the current sensing circuit includes a sensing resistor and a sensing capacitor coupled to the first inductor, and generates the sensing current signal by sensing the voltage across the sensing capacitor to sense the current in the first inductor.

13. The control circuit as claimed in claim 11, wherein the current sensing circuit includes a sampling circuit and a low-pass filter for sensing the first inductor current and generating the sensed current signal.

14. The control circuit as claimed in claim 11, wherein the first ramp signal operates at a fixed switching frequency on the switching capacitor converter.

15. The control circuit as claimed in claim 11, wherein the comparison selection circuit includes a first diode and a second diode coupled to each other for comparing and selecting the lower of the first amplified signal and the second amplified signal to generate the third amplified signal.

16. The control circuit as claimed in claim 11, wherein the complex switching control signal includes a first switching control signal and a second switching control signal; wherein the pulse width modulation generator includes: A first comparator and a second comparator are provided, wherein when the third amplified signal corresponds to the first amplified signal, the first comparator compares the third amplified signal with the first ramp signal to generate the first switching control signal, and when the third amplified signal corresponds to the second amplified signal, the second comparator compares the third amplified signal with a second ramp signal to generate the second switching control signal; wherein the multiple switches are controlled by the first switching control signal and the second switching control signal, thereby controlling the first switching current; wherein the pulse start time of the first switching control signal determines a first valley value of the first inductor current, and the pulse start time of the second switching control signal determines a second valley value of the first inductor current, thereby achieving valley current mode control of the switching capacitor converter; wherein the first ramp signal and the second ramp signal are generated based on a first clock signal and a second clock signal, respectively, and are related to the first inductor current.

17. The control circuit as claimed in claim 16, wherein the phase offset between the first ramp signal and the second ramp signal is 180 degrees to ensure balanced control of the switching capacitor converter.

18. A control method for controlling a switching capacitor converter for converting an input voltage into an output voltage, wherein the switching capacitor converter comprises: A complex switch includes at least four switches, wherein the at least four switches include a first switch, wherein a first terminal of the first switch is coupled to the input voltage; a first inductor, wherein a first terminal of the first inductor is coupled to the output voltage; and a first flying capacitor, coupled between a second terminal of the first switch and a second terminal of the first inductor, and configured as a capacitive voltage divider to reduce the voltage pressure on the complex switch; wherein the control method includes: controlling the first switch to be turned on in at least one switching state of the complex switch, such that the first flying capacitor and the first inductor are connected in series between the input voltage and the output voltage through the first switch; during the on period of the first switch, sensing and sampling a first inductor current flowing through the first inductor to generate a sense current signal, thereby sensing a first switch current flowing through the first switch; generating a first amplified signal based on the difference between the sensed current signal and a reference current signal; and generating a second amplified signal based on the difference between the output voltage and a reference voltage signal. The levels of the first amplified signal and the second amplified signal are compared to select the one with the lower duty cycle to generate a third amplified signal; and the third amplified signal is compared with a first ramp signal to generate a multiple switching control signal to control the multiple switches, thereby controlling the first switching current according to the first inductor current when the third amplified signal corresponds to the first amplified signal to limit an input current related to the input voltage, and controlling the output voltage according to the difference between the output voltage and the reference voltage signal when the third amplified signal corresponds to the second amplified signal.

19. The control method as described in claim 18, wherein the step of generating the sensed current signal further includes: The current of the first inductor is sampled to generate a sampled current signal; And the sampled current signal is averaged to generate the sensed current signal.

20. The control method as described in claim 18, wherein the first ramp signal operates at a fixed switching frequency on the switching capacitor converter.

21. The control method as described in claim 18, wherein the step of generating the third amplified signal includes: Provides a first diode and a second diode that are coupled to each other; And by comparing the first diode with the second diode and selecting the lower of the first amplified signal and the second amplified signal, the third amplified signal is generated.

22. The control method as described in claim 18, wherein the plurality of switching control signals includes a first switching control signal and a second switching control signal, wherein the step of generating the plurality of switching control signals includes: The first ramp signal and the second ramp signal are generated based on the first inductor current, and based on a first clock signal and a second clock signal, respectively. When the third amplified signal corresponds to the first amplified signal, the third amplified signal is compared with the first ramp signal to generate the first switching control signal; when the third amplified signal corresponds to the second amplified signal, the third amplified signal is compared with the second ramp signal to generate the second switching control signal; the multiple switches are controlled by the first switching control signal and the second switching control signal to control the first switching current; and a first valley value of the first inductor current is determined by the pulse start time of the first switching control signal, and a second valley value of the first inductor current is determined by the pulse start time of the second switching control signal, thereby achieving valley current mode control of the switching capacitor converter.

23. The control method as described in claim 22, wherein the phase offset between the first ramp signal and the second ramp signal is 180 degrees to ensure balanced control of the switching capacitor converter.

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